drc: split disassembly to separate pass
[picodrive.git] / cpu / sh2 / mame / sh2pico.c
CommitLineData
41397701 1#include "../sh2.h"
00faec9c 2#ifdef DRC_CMP
3#include "../compiler.c"
4#endif
eaa10a6e 5
6// MAME types
00faec9c 7#ifndef INT8
eaa10a6e 8typedef signed char INT8;
9typedef signed short INT16;
10typedef signed int INT32;
11typedef unsigned int UINT32;
12typedef unsigned short UINT16;
13typedef unsigned char UINT8;
00faec9c 14#endif
eaa10a6e 15
f4c0720c 16#define RB(sh2, a) p32x_sh2_read8(a,sh2)
17#define RW(sh2, a) p32x_sh2_read16(a,sh2)
18#define RL(sh2, a) p32x_sh2_read32(a,sh2)
19#define WB(sh2, a, d) p32x_sh2_write8(a,d,sh2)
20#define WW(sh2, a, d) p32x_sh2_write16(a,d,sh2)
21#define WL(sh2, a, d) p32x_sh2_write32(a,d,sh2)
eaa10a6e 22
23// some stuff from sh2comn.h
24#define T 0x00000001
25#define S 0x00000002
26#define I 0x000000f0
27#define Q 0x00000100
28#define M 0x00000200
29
30#define AM 0xc7ffffff
31
32#define FLAGS (M|Q|I|S|T)
33
34#define Rn ((opcode>>8)&15)
35#define Rm ((opcode>>4)&15)
36
f4c0720c 37#define sh2_state SH2
38
39extern void lprintf(const char *fmt, ...);
40#define logerror lprintf
1d7a28a7 41
71f68165 42#ifdef SH2_STATS
43static SH2 sh2_stats;
44static unsigned int op_refs[0x10000];
45# define LRN 1
46# define LRM 2
47# define LRNM (LRN|LRM)
48# define rlog(rnm) { \
49 int op = opcode; \
50 if ((rnm) & LRN) { \
51 op &= ~0x0f00; \
52 sh2_stats.r[Rn]++; \
53 } \
54 if ((rnm) & LRM) { \
55 op &= ~0x00f0; \
56 sh2_stats.r[Rm]++; \
57 } \
58 op_refs[op]++; \
59}
60# define rlog1(x) sh2_stats.r[x]++
61# define rlog2(x1,x2) sh2_stats.r[x1]++; sh2_stats.r[x2]++
62#else
63# define rlog(x)
64# define rlog1(...)
65# define rlog2(...)
66#endif
67
41397701 68#include "sh2.c"
1d7a28a7 69
f0d7b1fa 70#ifndef DRC_SH2
679af8a3 71
f4c0720c 72int sh2_execute(SH2 *sh2, int cycles)
eaa10a6e 73{
00faec9c 74#ifdef DRC_CMP
75 unsigned int base_pc = 0, end_pc = 0;
e1553677 76 unsigned char op_flags[BLOCK_INSN_LIMIT];
00faec9c 77#endif
78 UINT32 opcode;
79
ed4402a7 80 sh2->icount = cycles;
41397701 81
82 if (sh2->icount <= 0)
ed4402a7 83 return cycles;
84
85 sh2->cycles_timeslice = cycles;
eaa10a6e 86
87 do
88 {
00faec9c 89#ifdef DRC_CMP
90 if (!sh2->delay) {
bf092a36 91 if (sh2->pc < base_pc || sh2->pc >= end_pc) {
00faec9c 92 base_pc = sh2->pc;
93 scan_block(base_pc, sh2->is_slave,
bf092a36 94 op_flags, &end_pc, NULL);
00faec9c 95 }
bf092a36 96 if ((op_flags[(sh2->pc - base_pc) / 2]
97 & OF_BTARGET) || sh2->pc == base_pc)
98 {
00faec9c 99 if (sh2->icount < 0)
100 break;
101 }
102
103 do_sh2_trace(sh2, sh2->icount);
104 }
105#endif
eaa10a6e 106
3cf9570b 107 if (sh2->delay)
108 {
a44737c1 109 sh2->ppc = sh2->delay;
f4c0720c 110 opcode = RW(sh2, sh2->delay);
3cf9570b 111 sh2->pc -= 2;
112 }
113 else
a44737c1 114 {
115 sh2->ppc = sh2->pc;
f4c0720c 116 opcode = RW(sh2, sh2->pc);
a44737c1 117 }
eaa10a6e 118
119 sh2->delay = 0;
120 sh2->pc += 2;
eaa10a6e 121
122 switch (opcode & ( 15 << 12))
123 {
f4c0720c 124 case 0<<12: op0000(sh2, opcode); break;
125 case 1<<12: op0001(sh2, opcode); break;
126 case 2<<12: op0010(sh2, opcode); break;
127 case 3<<12: op0011(sh2, opcode); break;
128 case 4<<12: op0100(sh2, opcode); break;
129 case 5<<12: op0101(sh2, opcode); break;
130 case 6<<12: op0110(sh2, opcode); break;
131 case 7<<12: op0111(sh2, opcode); break;
132 case 8<<12: op1000(sh2, opcode); break;
133 case 9<<12: op1001(sh2, opcode); break;
134 case 10<<12: op1010(sh2, opcode); break;
135 case 11<<12: op1011(sh2, opcode); break;
136 case 12<<12: op1100(sh2, opcode); break;
137 case 13<<12: op1101(sh2, opcode); break;
138 case 14<<12: op1110(sh2, opcode); break;
139 default: op1111(sh2, opcode); break;
eaa10a6e 140 }
141
41397701 142 sh2->icount--;
1f1ff763 143
144 if (sh2->test_irq && !sh2->delay && sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
145 {
146 int level = sh2->pending_level;
147 int vector = sh2->irq_callback(sh2, level);
148 sh2_do_irq(sh2, level, vector);
149 sh2->test_irq = 0;
150 }
151
eaa10a6e 152 }
00faec9c 153#ifndef DRC_CMP
41397701 154 while (sh2->icount > 0 || sh2->delay); /* can't interrupt before delay */
553c3eaa 155#else
00faec9c 156 while (1);
553c3eaa 157#endif
158
00faec9c 159 return sh2->cycles_timeslice - sh2->icount;
679af8a3 160}
161
00faec9c 162#endif // DRC_SH2
679af8a3 163
71f68165 164#ifdef SH2_STATS
165#include <stdio.h>
166#include <string.h>
167#include "sh2dasm.h"
168
169void sh2_dump_stats(void)
170{
171 static const char *rnames[] = {
172 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
173 "R8", "R9", "R10", "R11", "R12", "R13", "R14", "SP",
174 "PC", "", "PR", "SR", "GBR", "VBR", "MACH", "MACL"
175 };
176 long long total;
177 char buff[64];
178 int u, i;
179
180 // dump reg usage
181 total = 0;
182 for (i = 0; i < 24; i++)
183 total += sh2_stats.r[i];
184
185 for (i = 0; i < 24; i++) {
186 if (i == 16 || i == 17 || i == 19)
187 continue;
188 printf("r %6.3f%% %-4s %9d\n", (double)sh2_stats.r[i] * 100.0 / total,
189 rnames[i], sh2_stats.r[i]);
190 }
191
192 memset(&sh2_stats, 0, sizeof(sh2_stats));
193
194 // dump ops
195 printf("\n");
196 total = 0;
197 for (i = 0; i < 0x10000; i++)
198 total += op_refs[i];
199
200 for (u = 0; u < 16; u++) {
201 int max = 0, op = 0;
202 for (i = 0; i < 0x10000; i++) {
203 if (op_refs[i] > max) {
204 max = op_refs[i];
205 op = i;
206 }
207 }
208 DasmSH2(buff, 0, op);
209 printf("i %6.3f%% %9d %s\n", (double)op_refs[op] * 100.0 / total,
210 op_refs[op], buff);
211 op_refs[op] = 0;
212 }
213 memset(op_refs, 0, sizeof(op_refs));
214}
215#endif
216