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ef79bbde P |
1 | /*************************************************************************** |
2 | * Copyright (C) 2010 by Blade_Arma * | |
3 | * * | |
4 | * This program is free software; you can redistribute it and/or modify * | |
5 | * it under the terms of the GNU General Public License as published by * | |
6 | * the Free Software Foundation; either version 2 of the License, or * | |
7 | * (at your option) any later version. * | |
8 | * * | |
9 | * This program is distributed in the hope that it will be useful, * | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
12 | * GNU General Public License for more details. * | |
13 | * * | |
14 | * You should have received a copy of the GNU General Public License * | |
15 | * along with this program; if not, write to the * | |
16 | * Free Software Foundation, Inc., * | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * | |
18 | ***************************************************************************/ | |
19 | ||
20 | /* | |
21 | * Internal PSX counters. | |
22 | */ | |
23 | ||
24 | #include "psxcounters.h" | |
fc8145b7 | 25 | #include "debug.h" |
ef79bbde P |
26 | |
27 | /******************************************************************************/ | |
28 | ||
ef79bbde P |
29 | enum |
30 | { | |
31 | Rc0Gate = 0x0001, // 0 not implemented | |
32 | Rc1Gate = 0x0001, // 0 not implemented | |
33 | Rc2Disable = 0x0001, // 0 partially implemented | |
34 | RcUnknown1 = 0x0002, // 1 ? | |
35 | RcUnknown2 = 0x0004, // 2 ? | |
36 | RcCountToTarget = 0x0008, // 3 | |
37 | RcIrqOnTarget = 0x0010, // 4 | |
38 | RcIrqOnOverflow = 0x0020, // 5 | |
39 | RcIrqRegenerate = 0x0040, // 6 | |
40 | RcUnknown7 = 0x0080, // 7 ? | |
41 | Rc0PixelClock = 0x0100, // 8 fake implementation | |
42 | Rc1HSyncClock = 0x0100, // 8 | |
43 | Rc2Unknown8 = 0x0100, // 8 ? | |
44 | Rc0Unknown9 = 0x0200, // 9 ? | |
45 | Rc1Unknown9 = 0x0200, // 9 ? | |
46 | Rc2OneEighthClock = 0x0200, // 9 | |
47 | RcUnknown10 = 0x0400, // 10 ? | |
48 | RcCountEqTarget = 0x0800, // 11 | |
49 | RcOverflow = 0x1000, // 12 | |
50 | RcUnknown13 = 0x2000, // 13 ? (always zero) | |
51 | RcUnknown14 = 0x4000, // 14 ? (always zero) | |
52 | RcUnknown15 = 0x8000, // 15 ? (always zero) | |
53 | }; | |
54 | ||
55 | #define CounterQuantity ( 4 ) | |
56 | //static const u32 CounterQuantity = 4; | |
57 | ||
58 | static const u32 CountToOverflow = 0; | |
59 | static const u32 CountToTarget = 1; | |
60 | ||
61 | static const u32 FrameRate[] = { 60, 50 }; | |
62 | static const u32 VBlankStart[] = { 240, 256 }; | |
aecf98c5 | 63 | static const u32 HSyncTotal[] = { 263, 313 }; |
554a2220 | 64 | static const u32 SpuUpdInterval[] = { 32, 32 }; |
ef79bbde | 65 | |
9f7ee52e | 66 | #define VERBOSE_LEVEL 0 |
67 | static const s32 VerboseLevel = VERBOSE_LEVEL; | |
ef79bbde P |
68 | |
69 | /******************************************************************************/ | |
70 | ||
b1be1eee | 71 | Rcnt rcnts[ CounterQuantity ]; |
ef79bbde P |
72 | |
73 | static u32 hSyncCount = 0; | |
74 | static u32 spuSyncCount = 0; | |
61ef5cf4 | 75 | static u32 hsync_steps = 0; |
76 | static u32 gpu_wants_hcnt = 0; | |
ef79bbde P |
77 | |
78 | u32 psxNextCounter = 0, psxNextsCounter = 0; | |
79 | ||
80 | /******************************************************************************/ | |
81 | ||
82 | static inline | |
83 | void setIrq( u32 irq ) | |
84 | { | |
85 | psxHu32ref(0x1070) |= SWAPu32(irq); | |
86 | } | |
87 | ||
88 | static | |
9f7ee52e | 89 | void verboseLog( u32 level, const char *str, ... ) |
ef79bbde | 90 | { |
9f7ee52e | 91 | #if VERBOSE_LEVEL > 0 |
ef79bbde P |
92 | if( level <= VerboseLevel ) |
93 | { | |
94 | va_list va; | |
95 | char buf[ 4096 ]; | |
96 | ||
97 | va_start( va, str ); | |
98 | vsprintf( buf, str, va ); | |
99 | va_end( va ); | |
100 | ||
ab948f7e | 101 | printf( "%s", buf ); |
ef79bbde P |
102 | fflush( stdout ); |
103 | } | |
9f7ee52e | 104 | #endif |
ef79bbde P |
105 | } |
106 | ||
107 | /******************************************************************************/ | |
108 | ||
109 | static inline | |
110 | void _psxRcntWcount( u32 index, u32 value ) | |
111 | { | |
112 | if( value > 0xffff ) | |
113 | { | |
114 | verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value ); | |
115 | value &= 0xffff; | |
116 | } | |
117 | ||
118 | rcnts[index].cycleStart = psxRegs.cycle; | |
119 | rcnts[index].cycleStart -= value * rcnts[index].rate; | |
120 | ||
121 | // TODO: <=. | |
122 | if( value < rcnts[index].target ) | |
123 | { | |
124 | rcnts[index].cycle = rcnts[index].target * rcnts[index].rate; | |
125 | rcnts[index].counterState = CountToTarget; | |
126 | } | |
127 | else | |
128 | { | |
129 | rcnts[index].cycle = 0xffff * rcnts[index].rate; | |
130 | rcnts[index].counterState = CountToOverflow; | |
131 | } | |
132 | } | |
133 | ||
134 | static inline | |
135 | u32 _psxRcntRcount( u32 index ) | |
136 | { | |
137 | u32 count; | |
138 | ||
139 | count = psxRegs.cycle; | |
140 | count -= rcnts[index].cycleStart; | |
61ef5cf4 | 141 | if (rcnts[index].rate > 1) |
142 | count /= rcnts[index].rate; | |
ef79bbde P |
143 | |
144 | if( count > 0xffff ) | |
145 | { | |
146 | verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count ); | |
147 | count &= 0xffff; | |
148 | } | |
149 | ||
150 | return count; | |
151 | } | |
152 | ||
153 | /******************************************************************************/ | |
154 | ||
155 | static | |
156 | void psxRcntSet() | |
157 | { | |
158 | s32 countToUpdate; | |
159 | u32 i; | |
160 | ||
161 | psxNextsCounter = psxRegs.cycle; | |
162 | psxNextCounter = 0x7fffffff; | |
163 | ||
164 | for( i = 0; i < CounterQuantity; ++i ) | |
165 | { | |
166 | countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart); | |
167 | ||
168 | if( countToUpdate < 0 ) | |
169 | { | |
170 | psxNextCounter = 0; | |
171 | break; | |
172 | } | |
173 | ||
174 | if( countToUpdate < (s32)psxNextCounter ) | |
175 | { | |
176 | psxNextCounter = countToUpdate; | |
177 | } | |
178 | } | |
179 | } | |
180 | ||
181 | /******************************************************************************/ | |
182 | ||
183 | static | |
184 | void psxRcntReset( u32 index ) | |
185 | { | |
186 | u32 count; | |
187 | ||
188 | if( rcnts[index].counterState == CountToTarget ) | |
189 | { | |
190 | if( rcnts[index].mode & RcCountToTarget ) | |
191 | { | |
192 | count = psxRegs.cycle; | |
193 | count -= rcnts[index].cycleStart; | |
61ef5cf4 | 194 | if (rcnts[index].rate > 1) |
195 | count /= rcnts[index].rate; | |
ef79bbde P |
196 | count -= rcnts[index].target; |
197 | } | |
198 | else | |
199 | { | |
200 | count = _psxRcntRcount( index ); | |
201 | } | |
202 | ||
203 | _psxRcntWcount( index, count ); | |
204 | ||
205 | if( rcnts[index].mode & RcIrqOnTarget ) | |
206 | { | |
207 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) | |
208 | { | |
209 | verboseLog( 3, "[RCNT %i] irq: %x\n", index, count ); | |
210 | setIrq( rcnts[index].irq ); | |
211 | rcnts[index].irqState = 1; | |
212 | } | |
213 | } | |
214 | ||
215 | rcnts[index].mode |= RcCountEqTarget; | |
216 | } | |
217 | else if( rcnts[index].counterState == CountToOverflow ) | |
218 | { | |
219 | count = psxRegs.cycle; | |
220 | count -= rcnts[index].cycleStart; | |
61ef5cf4 | 221 | if (rcnts[index].rate > 1) |
222 | count /= rcnts[index].rate; | |
ef79bbde P |
223 | count -= 0xffff; |
224 | ||
225 | _psxRcntWcount( index, count ); | |
226 | ||
227 | if( rcnts[index].mode & RcIrqOnOverflow ) | |
228 | { | |
229 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) | |
230 | { | |
231 | verboseLog( 3, "[RCNT %i] irq: %x\n", index, count ); | |
232 | setIrq( rcnts[index].irq ); | |
233 | rcnts[index].irqState = 1; | |
234 | } | |
235 | } | |
236 | ||
237 | rcnts[index].mode |= RcOverflow; | |
238 | } | |
239 | ||
240 | rcnts[index].mode |= RcUnknown10; | |
241 | ||
242 | psxRcntSet(); | |
243 | } | |
244 | ||
245 | void psxRcntUpdate() | |
246 | { | |
247 | u32 cycle; | |
248 | ||
249 | cycle = psxRegs.cycle; | |
250 | ||
251 | // rcnt 0. | |
252 | if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle ) | |
253 | { | |
254 | psxRcntReset( 0 ); | |
255 | } | |
256 | ||
257 | // rcnt 1. | |
258 | if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle ) | |
259 | { | |
260 | psxRcntReset( 1 ); | |
261 | } | |
262 | ||
263 | // rcnt 2. | |
264 | if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle ) | |
265 | { | |
266 | psxRcntReset( 2 ); | |
267 | } | |
268 | ||
269 | // rcnt base. | |
270 | if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle ) | |
271 | { | |
61ef5cf4 | 272 | u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle; |
273 | u32 next_vsync, next_lace; | |
ef79bbde | 274 | |
61ef5cf4 | 275 | spuSyncCount += hsync_steps; |
276 | hSyncCount += hsync_steps; | |
ef79bbde P |
277 | |
278 | // Update spu. | |
279 | if( spuSyncCount >= SpuUpdInterval[Config.PsxType] ) | |
280 | { | |
281 | spuSyncCount = 0; | |
282 | ||
283 | if( SPU_async ) | |
284 | { | |
285 | SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target ); | |
286 | } | |
287 | } | |
288 | ||
289 | // VSync irq. | |
290 | if( hSyncCount == VBlankStart[Config.PsxType] ) | |
291 | { | |
61ef5cf4 | 292 | GPU_vBlank( 1, &hSyncCount, &gpu_wants_hcnt ); |
ef79bbde P |
293 | |
294 | // For the best times. :D | |
295 | //setIrq( 0x01 ); | |
296 | } | |
297 | ||
298 | // Update lace. (with InuYasha fix) | |
299 | if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) ) | |
300 | { | |
301 | hSyncCount = 0; | |
302 | ||
61ef5cf4 | 303 | GPU_vBlank( 0, &hSyncCount, &gpu_wants_hcnt ); |
ef79bbde P |
304 | setIrq( 0x01 ); |
305 | ||
ef79bbde | 306 | EmuUpdate(); |
cefe86b7 | 307 | GPU_updateLace(); |
ef79bbde | 308 | } |
61ef5cf4 | 309 | |
310 | // Schedule next call, in hsyncs | |
311 | hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount; | |
312 | next_vsync = VBlankStart[Config.PsxType] - hSyncCount; // ok to overflow | |
313 | next_lace = HSyncTotal[Config.PsxType] - hSyncCount; | |
314 | if( next_vsync && next_vsync < hsync_steps ) | |
315 | hsync_steps = next_vsync; | |
316 | if( next_lace && next_lace < hsync_steps ) | |
317 | hsync_steps = next_lace; | |
318 | if( gpu_wants_hcnt ) | |
319 | hsync_steps = 1; | |
320 | ||
321 | rcnts[3].cycleStart = cycle - leftover_cycles; | |
322 | rcnts[3].cycle = hsync_steps * rcnts[3].target; | |
323 | psxRcntSet(); | |
ef79bbde P |
324 | } |
325 | ||
61ef5cf4 | 326 | #ifndef NDEBUG |
ef79bbde | 327 | DebugVSync(); |
61ef5cf4 | 328 | #endif |
ef79bbde P |
329 | } |
330 | ||
331 | /******************************************************************************/ | |
332 | ||
333 | void psxRcntWcount( u32 index, u32 value ) | |
334 | { | |
335 | verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value ); | |
336 | ||
ef79bbde P |
337 | _psxRcntWcount( index, value ); |
338 | psxRcntSet(); | |
339 | } | |
340 | ||
341 | void psxRcntWmode( u32 index, u32 value ) | |
342 | { | |
343 | verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value ); | |
344 | ||
ef79bbde P |
345 | rcnts[index].mode = value; |
346 | rcnts[index].irqState = 0; | |
347 | ||
348 | switch( index ) | |
349 | { | |
350 | case 0: | |
351 | if( value & Rc0PixelClock ) | |
352 | { | |
353 | rcnts[index].rate = 5; | |
354 | } | |
355 | else | |
356 | { | |
357 | rcnts[index].rate = 1; | |
358 | } | |
359 | break; | |
360 | case 1: | |
361 | if( value & Rc1HSyncClock ) | |
362 | { | |
363 | rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); | |
364 | } | |
365 | else | |
366 | { | |
367 | rcnts[index].rate = 1; | |
368 | } | |
369 | break; | |
370 | case 2: | |
371 | if( value & Rc2OneEighthClock ) | |
372 | { | |
373 | rcnts[index].rate = 8; | |
374 | } | |
375 | else | |
376 | { | |
377 | rcnts[index].rate = 1; | |
378 | } | |
379 | ||
380 | // TODO: wcount must work. | |
381 | if( value & Rc2Disable ) | |
382 | { | |
383 | rcnts[index].rate = 0xffffffff; | |
384 | } | |
385 | break; | |
386 | } | |
387 | ||
388 | _psxRcntWcount( index, 0 ); | |
389 | psxRcntSet(); | |
390 | } | |
391 | ||
392 | void psxRcntWtarget( u32 index, u32 value ) | |
393 | { | |
394 | verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value ); | |
395 | ||
ef79bbde P |
396 | rcnts[index].target = value; |
397 | ||
398 | _psxRcntWcount( index, _psxRcntRcount( index ) ); | |
399 | psxRcntSet(); | |
400 | } | |
401 | ||
402 | /******************************************************************************/ | |
403 | ||
404 | u32 psxRcntRcount( u32 index ) | |
405 | { | |
406 | u32 count; | |
407 | ||
ef79bbde P |
408 | count = _psxRcntRcount( index ); |
409 | ||
410 | // Parasite Eve 2 fix. | |
411 | if( Config.RCntFix ) | |
412 | { | |
413 | if( index == 2 ) | |
414 | { | |
415 | if( rcnts[index].counterState == CountToTarget ) | |
416 | { | |
417 | count /= BIAS; | |
418 | } | |
419 | } | |
420 | } | |
421 | ||
422 | verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count ); | |
423 | ||
424 | return count; | |
425 | } | |
426 | ||
427 | u32 psxRcntRmode( u32 index ) | |
428 | { | |
429 | u16 mode; | |
430 | ||
ef79bbde P |
431 | mode = rcnts[index].mode; |
432 | rcnts[index].mode &= 0xe7ff; | |
433 | ||
434 | verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode ); | |
435 | ||
436 | return mode; | |
437 | } | |
438 | ||
439 | u32 psxRcntRtarget( u32 index ) | |
440 | { | |
441 | verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target ); | |
442 | ||
443 | return rcnts[index].target; | |
444 | } | |
445 | ||
446 | /******************************************************************************/ | |
447 | ||
448 | void psxRcntInit() | |
449 | { | |
450 | s32 i; | |
451 | ||
452 | // rcnt 0. | |
453 | rcnts[0].rate = 1; | |
454 | rcnts[0].irq = 0x10; | |
455 | ||
456 | // rcnt 1. | |
457 | rcnts[1].rate = 1; | |
458 | rcnts[1].irq = 0x20; | |
459 | ||
460 | // rcnt 2. | |
461 | rcnts[2].rate = 1; | |
462 | rcnts[2].irq = 0x40; | |
463 | ||
464 | // rcnt base. | |
465 | rcnts[3].rate = 1; | |
466 | rcnts[3].mode = RcCountToTarget; | |
467 | rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); | |
468 | ||
469 | for( i = 0; i < CounterQuantity; ++i ) | |
470 | { | |
471 | _psxRcntWcount( i, 0 ); | |
472 | } | |
473 | ||
c62b43c9 | 474 | hSyncCount = 0; |
475 | spuSyncCount = 0; | |
61ef5cf4 | 476 | hsync_steps = 1; |
c62b43c9 | 477 | |
ef79bbde P |
478 | psxRcntSet(); |
479 | } | |
480 | ||
481 | /******************************************************************************/ | |
482 | ||
483 | s32 psxRcntFreeze( gzFile f, s32 Mode ) | |
484 | { | |
485 | gzfreeze( &rcnts, sizeof(rcnts) ); | |
486 | gzfreeze( &hSyncCount, sizeof(hSyncCount) ); | |
487 | gzfreeze( &spuSyncCount, sizeof(spuSyncCount) ); | |
488 | gzfreeze( &psxNextCounter, sizeof(psxNextCounter) ); | |
489 | gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) ); | |
490 | ||
61ef5cf4 | 491 | if (Mode == 0) |
492 | hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target; | |
493 | ||
ef79bbde P |
494 | return 0; |
495 | } | |
496 | ||
497 | /******************************************************************************/ |