045a4c52 |
1 | /* |
2 | * SH2 peripherals/"system on chip" |
3 | * (C) notaz, 2013 |
4 | * |
5 | * This work is licensed under the terms of MAME license. |
6 | * See COPYING file in the top-level directory. |
7 | * |
8 | * rough fffffe00-ffffffff map: |
9 | * e00-e05 SCI serial communication interface |
10 | * e10-e1a FRT free-running timer |
11 | * e60-e68 VCRx irq vectors |
12 | * e71-e72 DRCR dma selection |
13 | * e80-e83 WDT watchdog timer |
14 | * e91 SBYCR standby control |
15 | * e92 CCR cache control |
16 | * ee0 ICR irq control |
17 | * ee2 IPRA irq priorities |
18 | * ee4 VCRWDT WDT irq vectors |
19 | * f00-f17 DIVU |
20 | * f40-f7b UBC user break controller |
21 | * f80-fb3 DMAC |
22 | * fe0-ffb BSC bus state controller |
23 | */ |
24 | |
25 | #include "../pico_int.h" |
26 | #include "../memory.h" |
27 | |
28 | // DMAC handling |
29 | struct dma_chan { |
30 | unsigned int sar, dar; // src, dst addr |
31 | unsigned int tcr; // transfer count |
32 | unsigned int chcr; // chan ctl |
33 | // -- dm dm sm sm ts ts ar am al ds dl tb ta ie te de |
34 | // ts - transfer size: 1, 2, 4, 16 bytes |
35 | // ar - auto request if 1, else dreq signal |
36 | // ie - irq enable |
37 | // te - transfer end |
38 | // de - dma enable |
39 | #define DMA_AR (1 << 9) |
40 | #define DMA_IE (1 << 2) |
41 | #define DMA_TE (1 << 1) |
42 | #define DMA_DE (1 << 0) |
43 | }; |
44 | |
45 | struct dmac { |
46 | struct dma_chan chan[2]; |
47 | unsigned int vcrdma0; |
48 | unsigned int unknown0; |
49 | unsigned int vcrdma1; |
50 | unsigned int unknown1; |
51 | unsigned int dmaor; |
52 | // -- pr ae nmif dme |
53 | // pr - priority: chan0 > chan1 or round-robin |
54 | // ae - address error |
55 | // nmif - nmi occurred |
56 | // dme - DMA master enable |
57 | #define DMA_DME (1 << 0) |
58 | }; |
59 | |
60 | static void dmac_te_irq(SH2 *sh2, struct dma_chan *chan) |
61 | { |
f81107f5 |
62 | char *regs = (void *)sh2->peri_regs; |
045a4c52 |
63 | struct dmac *dmac = (void *)(regs + 0x180); |
64 | int level = PREG8(regs, 0xe2) & 0x0f; // IPRA |
65 | int vector = (chan == &dmac->chan[0]) ? |
66 | dmac->vcrdma0 : dmac->vcrdma1; |
67 | |
68 | elprintf(EL_32XP, "dmac irq %d %d", level, vector); |
69 | sh2_internal_irq(sh2, level, vector & 0x7f); |
70 | } |
71 | |
72 | static void dmac_transfer_complete(SH2 *sh2, struct dma_chan *chan) |
73 | { |
74 | chan->chcr |= DMA_TE; // DMA has ended normally |
75 | |
76 | p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDoneT()); |
77 | if (chan->chcr & DMA_IE) |
78 | dmac_te_irq(sh2, chan); |
79 | } |
80 | |
81 | static void dmac_transfer_one(SH2 *sh2, struct dma_chan *chan) |
82 | { |
83 | u32 size, d; |
84 | |
85 | size = (chan->chcr >> 10) & 3; |
86 | switch (size) { |
87 | case 0: |
88 | d = p32x_sh2_read8(chan->sar, sh2); |
89 | p32x_sh2_write8(chan->dar, d, sh2); |
90 | case 1: |
91 | d = p32x_sh2_read16(chan->sar, sh2); |
92 | p32x_sh2_write16(chan->dar, d, sh2); |
93 | break; |
94 | case 2: |
95 | d = p32x_sh2_read32(chan->sar, sh2); |
96 | p32x_sh2_write32(chan->dar, d, sh2); |
97 | break; |
98 | case 3: |
99 | d = p32x_sh2_read32(chan->sar + 0x00, sh2); |
100 | p32x_sh2_write32(chan->dar + 0x00, d, sh2); |
101 | d = p32x_sh2_read32(chan->sar + 0x04, sh2); |
102 | p32x_sh2_write32(chan->dar + 0x04, d, sh2); |
103 | d = p32x_sh2_read32(chan->sar + 0x08, sh2); |
104 | p32x_sh2_write32(chan->dar + 0x08, d, sh2); |
105 | d = p32x_sh2_read32(chan->sar + 0x0c, sh2); |
106 | p32x_sh2_write32(chan->dar + 0x0c, d, sh2); |
107 | chan->sar += 16; // always? |
108 | if (chan->chcr & (1 << 15)) |
109 | chan->dar -= 16; |
110 | if (chan->chcr & (1 << 14)) |
111 | chan->dar += 16; |
112 | chan->tcr -= 4; |
113 | return; |
114 | } |
115 | chan->tcr--; |
116 | |
117 | size = 1 << size; |
118 | if (chan->chcr & (1 << 15)) |
119 | chan->dar -= size; |
120 | if (chan->chcr & (1 << 14)) |
121 | chan->dar += size; |
122 | if (chan->chcr & (1 << 13)) |
123 | chan->sar -= size; |
124 | if (chan->chcr & (1 << 12)) |
125 | chan->sar += size; |
126 | } |
127 | |
128 | // DMA trigger by SH2 register write |
129 | static void dmac_trigger(SH2 *sh2, struct dma_chan *chan) |
130 | { |
131 | elprintf(EL_32XP, "sh2 DMA %08x->%08x, cnt %d, chcr %04x @%06x", |
132 | chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc); |
133 | chan->tcr &= 0xffffff; |
134 | |
135 | if (chan->chcr & DMA_AR) { |
136 | // auto-request transfer |
137 | while ((int)chan->tcr > 0) |
138 | dmac_transfer_one(sh2, chan); |
139 | dmac_transfer_complete(sh2, chan); |
140 | return; |
141 | } |
142 | |
143 | // DREQ0 is only sent after first 4 words are written. |
144 | // we do multiple of 4 words to avoid messing up alignment |
145 | if (chan->sar == 0x20004012) { |
146 | if (Pico32x.dmac0_fifo_ptr && (Pico32x.dmac0_fifo_ptr & 3) == 0) { |
147 | elprintf(EL_32XP, "68k -> sh2 DMA"); |
148 | p32x_dreq0_trigger(); |
149 | } |
150 | return; |
151 | } |
152 | |
153 | elprintf(EL_32XP|EL_ANOMALY, "unhandled DMA: " |
154 | "%08x->%08x, cnt %d, chcr %04x @%06x", |
155 | chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc); |
156 | } |
157 | |
158 | // timer state - FIXME |
159 | static int timer_cycles[2]; |
160 | static int timer_tick_cycles[2]; |
161 | |
162 | // timers |
163 | void p32x_timers_recalc(void) |
164 | { |
165 | int cycles; |
166 | int tmp, i; |
167 | |
168 | // SH2 timer step |
169 | for (i = 0; i < 2; i++) { |
f81107f5 |
170 | tmp = PREG8(sh2s[i].peri_regs, 0x80) & 7; |
045a4c52 |
171 | // Sclk cycles per timer tick |
172 | if (tmp) |
173 | cycles = 0x20 << tmp; |
174 | else |
175 | cycles = 2; |
176 | timer_tick_cycles[i] = cycles; |
177 | timer_cycles[i] = 0; |
178 | elprintf(EL_32XP, "WDT cycles[%d] = %d", i, cycles); |
179 | } |
180 | } |
181 | |
182 | void p32x_timers_do(unsigned int m68k_slice) |
183 | { |
184 | unsigned int cycles = m68k_slice * 3; |
185 | int cnt, i; |
186 | |
187 | // WDT timers |
188 | for (i = 0; i < 2; i++) { |
f81107f5 |
189 | void *pregs = sh2s[i].peri_regs; |
045a4c52 |
190 | if (PREG8(pregs, 0x80) & 0x20) { // TME |
191 | timer_cycles[i] += cycles; |
192 | cnt = PREG8(pregs, 0x81); |
193 | while (timer_cycles[i] >= timer_tick_cycles[i]) { |
194 | timer_cycles[i] -= timer_tick_cycles[i]; |
195 | cnt++; |
196 | } |
197 | if (cnt >= 0x100) { |
198 | int level = PREG8(pregs, 0xe3) >> 4; |
199 | int vector = PREG8(pregs, 0xe4) & 0x7f; |
200 | elprintf(EL_32XP, "%csh2 WDT irq (%d, %d)", |
201 | i ? 's' : 'm', level, vector); |
202 | sh2_internal_irq(&sh2s[i], level, vector); |
203 | cnt &= 0xff; |
204 | } |
205 | PREG8(pregs, 0x81) = cnt; |
206 | } |
207 | } |
208 | } |
209 | |
cd0ace28 |
210 | void sh2_peripheral_reset(SH2 *sh2) |
211 | { |
212 | memset(sh2->peri_regs, 0, sizeof(sh2->peri_regs)); // ? |
213 | PREG8(sh2->peri_regs, 4) = 0x84; // SCI SSR |
214 | } |
215 | |
045a4c52 |
216 | // ------------------------------------------------------------------ |
217 | // SH2 internal peripheral memhandlers |
218 | // we keep them in little endian format |
219 | |
f81107f5 |
220 | u32 sh2_peripheral_read8(u32 a, SH2 *sh2) |
045a4c52 |
221 | { |
f81107f5 |
222 | u8 *r = (void *)sh2->peri_regs; |
045a4c52 |
223 | u32 d; |
224 | |
225 | a &= 0x1ff; |
226 | d = PREG8(r, a); |
227 | |
f81107f5 |
228 | elprintf(EL_32XP, "%csh2 peri r8 [%08x] %02x @%06x", |
229 | sh2->is_slave ? 's' : 'm', a | ~0x1ff, d, sh2_pc(sh2)); |
045a4c52 |
230 | return d; |
231 | } |
232 | |
f81107f5 |
233 | u32 sh2_peripheral_read16(u32 a, SH2 *sh2) |
045a4c52 |
234 | { |
f81107f5 |
235 | u16 *r = (void *)sh2->peri_regs; |
045a4c52 |
236 | u32 d; |
237 | |
238 | a &= 0x1ff; |
239 | d = r[(a / 2) ^ 1]; |
240 | |
f81107f5 |
241 | elprintf(EL_32XP, "%csh2 peri r16 [%08x] %04x @%06x", |
242 | sh2->is_slave ? 's' : 'm', a | ~0x1ff, d, sh2_pc(sh2)); |
045a4c52 |
243 | return d; |
244 | } |
245 | |
f81107f5 |
246 | u32 sh2_peripheral_read32(u32 a, SH2 *sh2) |
045a4c52 |
247 | { |
248 | u32 d; |
249 | a &= 0x1fc; |
f81107f5 |
250 | d = sh2->peri_regs[a / 4]; |
045a4c52 |
251 | |
f81107f5 |
252 | elprintf(EL_32XP, "%csh2 peri r32 [%08x] %08x @%06x", |
253 | sh2->is_slave ? 's' : 'm', a | ~0x1ff, d, sh2_pc(sh2)); |
045a4c52 |
254 | return d; |
255 | } |
256 | |
f81107f5 |
257 | void REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, SH2 *sh2) |
045a4c52 |
258 | { |
f81107f5 |
259 | u8 *r = (void *)sh2->peri_regs; |
260 | elprintf(EL_32XP, "%csh2 peri w8 [%08x] %02x @%06x", |
261 | sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2)); |
045a4c52 |
262 | |
263 | a &= 0x1ff; |
264 | PREG8(r, a) = d; |
265 | |
266 | // X-men SCI hack |
267 | if ((a == 2 && (d & 0x20)) || // transmiter enabled |
268 | (a == 4 && !(d & 0x80))) { // valid data in TDR |
f81107f5 |
269 | void *oregs = sh2->other_sh2->peri_regs; |
045a4c52 |
270 | if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled |
271 | int level = PREG8(oregs, 0x60) >> 4; |
272 | int vector = PREG8(oregs, 0x63) & 0x7f; |
f81107f5 |
273 | elprintf(EL_32XP, "%csh2 SCI recv irq (%d, %d)", |
274 | (sh2->is_slave ^ 1) ? 's' : 'm', level, vector); |
275 | sh2_internal_irq(sh2->other_sh2, level, vector); |
276 | return; |
045a4c52 |
277 | } |
278 | } |
045a4c52 |
279 | } |
280 | |
f81107f5 |
281 | void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2) |
045a4c52 |
282 | { |
f81107f5 |
283 | u16 *r = (void *)sh2->peri_regs; |
284 | elprintf(EL_32XP, "%csh2 peri w16 [%08x] %04x @%06x", |
285 | sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2)); |
045a4c52 |
286 | |
287 | a &= 0x1ff; |
288 | |
289 | // evil WDT |
290 | if (a == 0x80) { |
291 | if ((d & 0xff00) == 0xa500) { // WTCSR |
292 | PREG8(r, 0x80) = d; |
293 | p32x_timers_recalc(); |
294 | } |
295 | if ((d & 0xff00) == 0x5a00) // WTCNT |
296 | PREG8(r, 0x81) = d; |
f81107f5 |
297 | return; |
045a4c52 |
298 | } |
299 | |
300 | r[(a / 2) ^ 1] = d; |
045a4c52 |
301 | } |
302 | |
f81107f5 |
303 | void sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2) |
045a4c52 |
304 | { |
f81107f5 |
305 | u32 *r = sh2->peri_regs; |
306 | elprintf(EL_32XP, "%csh2 peri w32 [%08x] %08x @%06x", |
307 | sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2)); |
045a4c52 |
308 | |
309 | a &= 0x1fc; |
310 | r[a / 4] = d; |
311 | |
312 | switch (a) { |
313 | // division unit (TODO: verify): |
314 | case 0x104: // DVDNT: divident L, starts divide |
f81107f5 |
315 | elprintf(EL_32XP, "%csh2 divide %08x / %08x", |
316 | sh2->is_slave ? 's' : 'm', d, r[0x100 / 4]); |
045a4c52 |
317 | if (r[0x100 / 4]) { |
318 | signed int divisor = r[0x100 / 4]; |
319 | r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor; |
320 | r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor; |
321 | } |
322 | else |
323 | r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ? |
324 | break; |
325 | case 0x114: |
326 | elprintf(EL_32XP, "%csh2 divide %08x%08x / %08x @%08x", |
f81107f5 |
327 | sh2->is_slave ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(sh2)); |
045a4c52 |
328 | if (r[0x100 / 4]) { |
329 | signed long long divident = (signed long long)r[0x110 / 4] << 32 | d; |
330 | signed int divisor = r[0x100 / 4]; |
331 | // XXX: undocumented mirroring to 0x118,0x11c? |
332 | r[0x118 / 4] = r[0x110 / 4] = divident % divisor; |
333 | divident /= divisor; |
334 | r[0x11c / 4] = r[0x114 / 4] = divident; |
335 | divident >>= 31; |
336 | if ((unsigned long long)divident + 1 > 1) { |
f81107f5 |
337 | //elprintf(EL_32XP, "%csh2 divide overflow! @%08x", |
338 | // sh2->is_slave ? 's' : 'm', sh2_pc(sh2)); |
045a4c52 |
339 | r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow |
340 | } |
341 | } |
342 | else |
343 | r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ? |
344 | break; |
345 | } |
346 | |
347 | // perhaps starting a DMA? |
348 | if (a == 0x1b0 || a == 0x18c || a == 0x19c) { |
f81107f5 |
349 | struct dmac *dmac = (void *)&sh2->peri_regs[0x180 / 4]; |
045a4c52 |
350 | if (!(dmac->dmaor & DMA_DME)) |
351 | return; |
352 | |
353 | if ((dmac->chan[0].chcr & (DMA_TE|DMA_DE)) == DMA_DE) |
f81107f5 |
354 | dmac_trigger(sh2, &dmac->chan[0]); |
045a4c52 |
355 | if ((dmac->chan[1].chcr & (DMA_TE|DMA_DE)) == DMA_DE) |
f81107f5 |
356 | dmac_trigger(sh2, &dmac->chan[1]); |
045a4c52 |
357 | } |
358 | } |
359 | |
360 | /* 32X specific */ |
361 | static void dreq0_do(SH2 *sh2, struct dma_chan *chan) |
362 | { |
363 | unsigned short *dreqlen = &Pico32x.regs[0x10 / 2]; |
364 | int i; |
365 | |
366 | // debug/sanity checks |
367 | if (chan->tcr != *dreqlen) |
368 | elprintf(EL_32XP|EL_ANOMALY, "dreq0: tcr0 and len differ: %d != %d", |
369 | chan->tcr, *dreqlen); |
370 | // note: DACK is not connected, single addr mode should not be used |
371 | if ((chan->chcr & 0x3f08) != 0x0400) |
372 | elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad control: %04x", chan->chcr); |
373 | if (chan->sar != 0x20004012) |
374 | elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad sar?: %08x\n", chan->sar); |
375 | |
376 | // HACK: assume bus is busy and SH2 is halted |
377 | sh2->state |= SH2_STATE_SLEEP; |
378 | |
379 | for (i = 0; i < Pico32x.dmac0_fifo_ptr && chan->tcr > 0; i++) { |
380 | elprintf(EL_32XP, "dmaw [%08x] %04x, left %d", |
381 | chan->dar, Pico32x.dmac_fifo[i], *dreqlen); |
382 | p32x_sh2_write16(chan->dar, Pico32x.dmac_fifo[i], sh2); |
383 | chan->dar += 2; |
384 | chan->tcr--; |
385 | (*dreqlen)--; |
386 | } |
387 | |
388 | if (Pico32x.dmac0_fifo_ptr != i) |
389 | memmove(Pico32x.dmac_fifo, &Pico32x.dmac_fifo[i], |
390 | (Pico32x.dmac0_fifo_ptr - i) * 2); |
391 | Pico32x.dmac0_fifo_ptr -= i; |
392 | |
393 | Pico32x.regs[6 / 2] &= ~P32XS_FULL; |
394 | if (*dreqlen == 0) |
395 | Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete |
396 | if (chan->tcr == 0) |
397 | dmac_transfer_complete(sh2, chan); |
398 | else |
399 | sh2_end_run(sh2, 16); |
400 | } |
401 | |
402 | static void dreq1_do(SH2 *sh2, struct dma_chan *chan) |
403 | { |
404 | // debug/sanity checks |
405 | if ((chan->chcr & 0xc308) != 0x0000) |
406 | elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad control: %04x", chan->chcr); |
407 | if ((chan->dar & ~0xf) != 0x20004030) |
408 | elprintf(EL_32XP|EL_ANOMALY, "dreq1: bad dar?: %08x\n", chan->dar); |
409 | |
410 | dmac_transfer_one(sh2, chan); |
411 | if (chan->tcr == 0) |
412 | dmac_transfer_complete(sh2, chan); |
413 | } |
414 | |
415 | void p32x_dreq0_trigger(void) |
416 | { |
f81107f5 |
417 | struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4]; |
418 | struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4]; |
045a4c52 |
419 | |
420 | elprintf(EL_32XP, "dreq0_trigger"); |
421 | if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[0].chcr & 3) == DMA_DE) { |
422 | dreq0_do(&msh2, &mdmac->chan[0]); |
423 | } |
424 | if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[0].chcr & 3) == DMA_DE) { |
425 | dreq0_do(&ssh2, &sdmac->chan[0]); |
426 | } |
427 | } |
428 | |
429 | void p32x_dreq1_trigger(void) |
430 | { |
f81107f5 |
431 | struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4]; |
432 | struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4]; |
045a4c52 |
433 | int hit = 0; |
434 | |
435 | elprintf(EL_32XP, "dreq1_trigger"); |
436 | if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[1].chcr & 3) == DMA_DE) { |
437 | dreq1_do(&msh2, &mdmac->chan[1]); |
438 | hit = 1; |
439 | } |
440 | if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[1].chcr & 3) == DMA_DE) { |
441 | dreq1_do(&ssh2, &sdmac->chan[1]); |
442 | hit = 1; |
443 | } |
444 | |
445 | if (!hit) |
446 | elprintf(EL_32XP|EL_ANOMALY, "dreq1: nobody cared"); |
447 | } |
448 | |
449 | // vim:shiftwidth=2:ts=2:expandtab |