cff531af |
1 | /* |
2 | * PicoDrive |
3 | * (C) notaz, 2009,2010 |
4 | * |
5 | * This work is licensed under the terms of MAME license. |
6 | * See COPYING file in the top-level directory. |
7 | */ |
c5c73e2f |
8 | /* |
9 | * <random_info=mem_map> |
10 | * 00000000-029fffff linux (42MB) |
11 | * 02a00000-02dfffff fb (4MB, 153600B really used) |
12 | * 02e00000-02ffffff sound dma (2MB) |
13 | * 03000000-03ffffff MPEGDEC (?, 16MB) |
14 | * </random_info> |
15 | */ |
ee2a3bdf |
16 | #include <stdio.h> |
17 | #include <stdlib.h> |
18 | #include <string.h> |
19 | #include <math.h> |
20 | #include <sys/types.h> |
21 | #include <sys/stat.h> |
22 | #include <fcntl.h> |
23 | #include <sys/mman.h> |
24 | #include <unistd.h> |
25 | #include <sys/ioctl.h> |
26 | #include <linux/fb.h> |
27 | |
28 | #include "soc.h" |
29 | #include "plat_gp2x.h" |
30 | #include "../common/emu.h" |
f4750ee0 |
31 | #include "../common/plat.h" |
ee2a3bdf |
32 | #include "../common/arm_utils.h" |
33 | #include "pollux_set.h" |
34 | |
35 | static volatile unsigned short *memregs; |
f4750ee0 |
36 | static volatile unsigned int *memregl; |
ee2a3bdf |
37 | static int memdev = -1; |
61753a67 |
38 | static int battdev = -1; |
ee2a3bdf |
39 | |
40 | extern void *gp2x_screens[4]; |
41 | |
42 | #define fb_buf_count 4 |
43 | static unsigned int fb_paddr[fb_buf_count]; |
44 | static int fb_work_buf; |
45 | static int fbdev = -1; |
46 | |
2275c676 |
47 | static char cpuclk_was_changed = 0; |
48 | static unsigned short memtimex_old[2]; |
9f6a4e90 |
49 | static unsigned int pllsetreg0_old; |
50 | static unsigned int timer_drift; // count per real second |
cc41eb4f |
51 | static int last_pal_setting = 0; |
2275c676 |
52 | |
ee2a3bdf |
53 | |
7b436906 |
54 | /* misc */ |
55 | static void pollux_set_fromenv(const char *env_var) |
56 | { |
57 | const char *set_string; |
58 | set_string = getenv(env_var); |
59 | if (set_string) |
60 | pollux_set(memregs, set_string); |
61 | else |
62 | printf("env var %s not defined.\n", env_var); |
63 | } |
64 | |
ee2a3bdf |
65 | /* video stuff */ |
66 | static void pollux_video_flip(int buf_count) |
67 | { |
68 | memregl[0x406C>>2] = fb_paddr[fb_work_buf]; |
69 | memregl[0x4058>>2] |= 0x10; |
70 | fb_work_buf++; |
71 | if (fb_work_buf >= buf_count) |
72 | fb_work_buf = 0; |
73 | g_screen_ptr = gp2x_screens[fb_work_buf]; |
74 | } |
75 | |
76 | static void gp2x_video_flip_(void) |
77 | { |
78 | pollux_video_flip(fb_buf_count); |
79 | } |
80 | |
81 | /* doulblebuffered flip */ |
82 | static void gp2x_video_flip2_(void) |
83 | { |
84 | pollux_video_flip(2); |
85 | } |
86 | |
87 | static void gp2x_video_changemode_ll_(int bpp) |
88 | { |
cc41eb4f |
89 | static int prev_bpp = 0; |
ee2a3bdf |
90 | int code = 0, bytes = 2; |
cc41eb4f |
91 | int rot_cmd[2] = { 0, 0 }; |
ee2a3bdf |
92 | unsigned int r; |
7b436906 |
93 | char buff[32]; |
cc41eb4f |
94 | int ret; |
95 | |
96 | if (bpp == prev_bpp) |
97 | return; |
98 | prev_bpp = bpp; |
99 | |
100 | printf("changemode: %dbpp rot=%d\n", abs(bpp), bpp < 0); |
101 | |
102 | /* negative bpp means rotated mode */ |
103 | rot_cmd[0] = (bpp < 0) ? 6 : 5; |
104 | ret = ioctl(fbdev, _IOW('D', 90, int[2]), rot_cmd); |
105 | if (ret < 0) |
106 | perror("rot ioctl failed"); |
107 | memregl[0x4004>>2] = (bpp < 0) ? 0x013f00ef : 0x00ef013f; |
108 | memregl[0x4000>>2] |= 1 << 3; |
109 | |
110 | /* the above ioctl resets LCD timings, so set them here */ |
7b436906 |
111 | snprintf(buff, sizeof(buff), "POLLUX_LCD_TIMINGS_%s", last_pal_setting ? "PAL" : "NTSC"); |
112 | pollux_set_fromenv(buff); |
cc41eb4f |
113 | |
114 | switch (abs(bpp)) |
ee2a3bdf |
115 | { |
116 | case 8: |
117 | code = 0x443a; |
118 | bytes = 1; |
119 | break; |
120 | |
121 | case 15: |
122 | case 16: |
123 | code = 0x4432; |
124 | bytes = 2; |
125 | break; |
126 | |
127 | default: |
cc41eb4f |
128 | printf("unhandled bpp request: %d\n", abs(bpp)); |
ee2a3bdf |
129 | return; |
130 | } |
131 | |
132 | memregl[0x405c>>2] = bytes; |
cc41eb4f |
133 | memregl[0x4060>>2] = bytes * (bpp < 0 ? 240 : 320); |
ee2a3bdf |
134 | |
135 | r = memregl[0x4058>>2]; |
136 | r = (r & 0xffff) | (code << 16) | 0x10; |
137 | memregl[0x4058>>2] = r; |
138 | } |
139 | |
140 | static void gp2x_video_setpalette_(int *pal, int len) |
141 | { |
142 | /* pollux palette is 16bpp only.. */ |
143 | int i; |
144 | for (i = 0; i < len; i++) |
145 | { |
146 | int c = pal[i]; |
147 | c = ((c >> 8) & 0xf800) | ((c >> 5) & 0x07c0) | ((c >> 3) & 0x001f); |
148 | memregl[0x4070>>2] = (i << 24) | c; |
149 | } |
150 | } |
151 | |
152 | static void gp2x_video_RGB_setscaling_(int ln_offs, int W, int H) |
153 | { |
154 | /* maybe a job for 3d hardware? */ |
155 | } |
156 | |
157 | static void gp2x_video_wait_vsync_(void) |
158 | { |
8340e7c9 |
159 | while (!(memregl[0x308c>>2] & (1 << 10))) |
ee2a3bdf |
160 | spend_cycles(128); |
161 | memregl[0x308c>>2] |= 1 << 10; |
162 | } |
163 | |
164 | /* CPU clock */ |
165 | static void gp2x_set_cpuclk_(unsigned int mhz) |
166 | { |
167 | char buff[24]; |
168 | snprintf(buff, sizeof(buff), "cpuclk=%u", mhz); |
169 | pollux_set(memregs, buff); |
2275c676 |
170 | |
171 | cpuclk_was_changed = 1; |
ee2a3bdf |
172 | } |
173 | |
ee2a3bdf |
174 | /* RAM timings */ |
ee2a3bdf |
175 | static void set_ram_timings_(void) |
176 | { |
177 | pollux_set_fromenv("POLLUX_RAM_TIMINGS"); |
178 | } |
179 | |
180 | static void unset_ram_timings_(void) |
181 | { |
182 | int i; |
183 | |
2275c676 |
184 | memregs[0x14802>>1] = memtimex_old[0]; |
185 | memregs[0x14804>>1] = memtimex_old[1] | 0x8000; |
ee2a3bdf |
186 | |
187 | for (i = 0; i < 0x100000; i++) |
188 | if (!(memregs[0x14804>>1] & 0x8000)) |
189 | break; |
190 | |
191 | printf("RAM timings reset to startup values.\n"); |
192 | } |
193 | |
194 | /* LCD refresh */ |
195 | static void set_lcd_custom_rate_(int is_pal) |
196 | { |
7b436906 |
197 | /* just remember PAL/NTSC. We always set timings in _changemode_ll() */ |
cc41eb4f |
198 | last_pal_setting = is_pal; |
ee2a3bdf |
199 | } |
200 | |
201 | static void unset_lcd_custom_rate_(void) |
202 | { |
203 | } |
204 | |
205 | static void set_lcd_gamma_(int g100, int A_SNs_curve) |
206 | { |
207 | /* hm, the LCD possibly can do it (but not POLLUX) */ |
208 | } |
42171343 |
209 | |
61753a67 |
210 | static int gp2x_read_battery_(void) |
211 | { |
212 | unsigned short magic_val = 0; |
213 | |
214 | if (battdev < 0) |
215 | return -1; |
216 | if (read(battdev, &magic_val, sizeof(magic_val)) != sizeof(magic_val)) |
217 | return -1; |
218 | switch (magic_val) { |
219 | default: |
220 | case 1: return 100; |
221 | case 2: return 66; |
222 | case 3: return 40; |
223 | case 4: return 0; |
224 | } |
225 | } |
226 | |
b24e0f6c |
227 | #define TIMER_BASE3 0x1980 |
228 | #define TIMER_REG(x) memregl[(TIMER_BASE3 + x) >> 2] |
229 | |
9f6a4e90 |
230 | static unsigned int gp2x_get_ticks_us_(void) |
b24e0f6c |
231 | { |
232 | TIMER_REG(0x08) = 0x4b; /* run timer, latch value */ |
233 | return TIMER_REG(0); |
234 | } |
235 | |
9f6a4e90 |
236 | static unsigned int gp2x_get_ticks_ms_(void) |
b24e0f6c |
237 | { |
3328d53b |
238 | /* approximate /= 1000 */ |
b24e0f6c |
239 | unsigned long long v64; |
3328d53b |
240 | v64 = (unsigned long long)gp2x_get_ticks_us_() * 4294968; |
241 | return v64 >> 32; |
b24e0f6c |
242 | } |
243 | |
244 | static void timer_cleanup(void) |
245 | { |
246 | TIMER_REG(0x40) = 0x0c; /* be sure clocks are on */ |
247 | TIMER_REG(0x08) = 0x23; /* stop the timer, clear irq in case it's pending */ |
248 | TIMER_REG(0x00) = 0; /* clear counter */ |
249 | TIMER_REG(0x40) = 0; /* clocks off */ |
250 | TIMER_REG(0x44) = 0; /* dividers back to default */ |
251 | } |
252 | |
f4750ee0 |
253 | /* note: both PLLs are programmed the same way, |
254 | * the databook incorrectly states that PLL1 differs */ |
255 | static int decode_pll(unsigned int reg) |
256 | { |
257 | long long v; |
258 | int p, m, s; |
259 | |
260 | p = (reg >> 18) & 0x3f; |
261 | m = (reg >> 8) & 0x3ff; |
262 | s = reg & 0xff; |
263 | |
264 | if (p == 0) |
265 | p = 1; |
266 | |
267 | v = 27000000; // master clock |
268 | v = v * m / (p << s); |
269 | return v; |
270 | } |
271 | |
9f6a4e90 |
272 | int pollux_get_real_snd_rate(int req_rate) |
273 | { |
274 | int clk0_src, clk1_src, rate, div; |
275 | |
276 | clk0_src = (memregl[0xdbc4>>2] >> 1) & 7; |
277 | clk1_src = (memregl[0xdbc8>>2] >> 1) & 7; |
278 | if (clk0_src > 1 || clk1_src != 7) { |
279 | fprintf(stderr, "get_real_snd_rate: bad clk sources: %d %d\n", clk0_src, clk1_src); |
280 | return req_rate; |
281 | } |
282 | |
283 | rate = decode_pll(clk0_src ? memregl[0xf008>>2] : memregl[0xf004>>2]); |
284 | |
285 | // apply divisors |
1889fe87 |
286 | div = ((memregl[0xdbc4>>2] >> 4) & 0x3f) + 1; |
9f6a4e90 |
287 | rate /= div; |
1889fe87 |
288 | div = ((memregl[0xdbc8>>2] >> 4) & 0x3f) + 1; |
9f6a4e90 |
289 | rate /= div; |
290 | rate /= 64; |
291 | |
292 | //printf("rate %d\n", rate); |
293 | rate -= rate * timer_drift / 1000000; |
294 | printf("adjusted rate: %d\n", rate); |
295 | |
296 | if (rate < 8000-1000 || rate > 44100+1000) { |
297 | fprintf(stderr, "get_real_snd_rate: got bad rate: %d\n", rate); |
298 | return req_rate; |
299 | } |
300 | |
301 | return rate; |
302 | } |
303 | |
42171343 |
304 | void pollux_init(void) |
305 | { |
ee2a3bdf |
306 | struct fb_fix_screeninfo fbfix; |
9f6a4e90 |
307 | int i, ret, rate, timer_div; |
ee2a3bdf |
308 | |
309 | memdev = open("/dev/mem", O_RDWR); |
310 | if (memdev == -1) { |
311 | perror("open(/dev/mem) failed"); |
312 | exit(1); |
313 | } |
314 | |
315 | memregs = mmap(0, 0x20000, PROT_READ|PROT_WRITE, MAP_SHARED, memdev, 0xc0000000); |
316 | if (memregs == MAP_FAILED) { |
317 | perror("mmap(memregs) failed"); |
318 | exit(1); |
319 | } |
320 | memregl = (volatile void *)memregs; |
321 | |
322 | fbdev = open("/dev/fb0", O_RDWR); |
323 | if (fbdev < 0) { |
324 | perror("can't open fbdev"); |
325 | exit(1); |
326 | } |
327 | |
328 | ret = ioctl(fbdev, FBIOGET_FSCREENINFO, &fbfix); |
329 | if (ret == -1) { |
330 | perror("ioctl(fbdev) failed"); |
331 | exit(1); |
332 | } |
333 | |
334 | printf("framebuffer: \"%s\" @ %08lx\n", fbfix.id, fbfix.smem_start); |
335 | fb_paddr[0] = fbfix.smem_start; |
336 | |
337 | gp2x_screens[0] = mmap(0, 320*240*2*fb_buf_count, PROT_READ|PROT_WRITE, |
338 | MAP_SHARED, memdev, fb_paddr[0]); |
339 | if (gp2x_screens[0] == MAP_FAILED) |
340 | { |
341 | perror("mmap(gp2x_screens) failed"); |
342 | exit(1); |
343 | } |
344 | memset(gp2x_screens[0], 0, 320*240*2*fb_buf_count); |
345 | |
346 | printf(" %p -> %08x\n", gp2x_screens[0], fb_paddr[0]); |
347 | for (i = 1; i < fb_buf_count; i++) |
348 | { |
349 | fb_paddr[i] = fb_paddr[i-1] + 320*240*2; |
350 | gp2x_screens[i] = (char *)gp2x_screens[i-1] + 320*240*2; |
351 | printf(" %p -> %08x\n", gp2x_screens[i], fb_paddr[i]); |
352 | } |
353 | fb_work_buf = 0; |
354 | g_screen_ptr = gp2x_screens[0]; |
355 | |
61753a67 |
356 | battdev = open("/dev/pollux_batt", O_RDONLY); |
357 | if (battdev < 0) |
358 | perror("Warning: could't open pollux_batt"); |
359 | |
f4750ee0 |
360 | /* find what PLL1 runs at, for the timer */ |
361 | rate = decode_pll(memregl[0xf008>>2]); |
362 | printf("PLL1 @ %dHz\n", rate); |
f4750ee0 |
363 | |
b24e0f6c |
364 | /* setup timer */ |
9f6a4e90 |
365 | timer_div = (rate + 500000) / 1000000; |
366 | if (1 <= timer_div && timer_div <= 256) { |
367 | timer_drift = (rate - (timer_div * 1000000)) / timer_div; |
368 | |
f4750ee0 |
369 | if (TIMER_REG(0x08) & 8) { |
370 | fprintf(stderr, "warning: timer in use, overriding!\n"); |
371 | timer_cleanup(); |
372 | } |
373 | |
9f6a4e90 |
374 | TIMER_REG(0x44) = ((timer_div - 1) << 4) | 2; /* using PLL1, divide by it's rate */ |
f4750ee0 |
375 | TIMER_REG(0x40) = 0x0c; /* clocks on */ |
376 | TIMER_REG(0x08) = 0x6b; /* run timer, clear irq, latch value */ |
377 | |
378 | gp2x_get_ticks_ms = gp2x_get_ticks_ms_; |
379 | gp2x_get_ticks_us = gp2x_get_ticks_us_; |
380 | } |
381 | else { |
382 | fprintf(stderr, "warning: could not make use of timer\n"); |
b24e0f6c |
383 | |
f4750ee0 |
384 | // those functions are actually not good at all on Wiz kernel |
385 | gp2x_get_ticks_ms = plat_get_ticks_ms_good; |
386 | gp2x_get_ticks_us = plat_get_ticks_us_good; |
387 | } |
b24e0f6c |
388 | |
9f6a4e90 |
389 | pllsetreg0_old = memregl[0xf004>>2]; |
2275c676 |
390 | memtimex_old[0] = memregs[0x14802>>1]; |
391 | memtimex_old[1] = memregs[0x14804>>1]; |
ee2a3bdf |
392 | |
393 | gp2x_video_flip = gp2x_video_flip_; |
394 | gp2x_video_flip2 = gp2x_video_flip2_; |
395 | gp2x_video_changemode_ll = gp2x_video_changemode_ll_; |
396 | gp2x_video_setpalette = gp2x_video_setpalette_; |
397 | gp2x_video_RGB_setscaling = gp2x_video_RGB_setscaling_; |
398 | gp2x_video_wait_vsync = gp2x_video_wait_vsync_; |
399 | |
f4750ee0 |
400 | /* some firmwares have sys clk on PLL0, we can't adjust CPU clock |
401 | * by reprogramming the PLL0 then, as it overclocks system bus */ |
402 | if ((memregl[0xf000>>2] & 0x03000030) == 0x01000000) |
403 | gp2x_set_cpuclk = gp2x_set_cpuclk_; |
404 | else { |
405 | fprintf(stderr, "unexpected PLL config (%08x), overclocking disabled\n", |
406 | memregl[0xf000>>2]); |
407 | gp2x_set_cpuclk = NULL; |
408 | } |
ee2a3bdf |
409 | |
410 | set_lcd_custom_rate = set_lcd_custom_rate_; |
411 | unset_lcd_custom_rate = unset_lcd_custom_rate_; |
412 | set_lcd_gamma = set_lcd_gamma_; |
413 | |
414 | set_ram_timings = set_ram_timings_; |
415 | unset_ram_timings = unset_ram_timings_; |
61753a67 |
416 | gp2x_read_battery = gp2x_read_battery_; |
42171343 |
417 | } |
418 | |
419 | void pollux_finish(void) |
420 | { |
ee2a3bdf |
421 | /* switch to default fb mem, turn portrait off */ |
422 | memregl[0x406C>>2] = fb_paddr[0]; |
423 | memregl[0x4058>>2] |= 0x10; |
ee2a3bdf |
424 | close(fbdev); |
425 | |
2275c676 |
426 | gp2x_video_changemode_ll_(16); |
427 | unset_ram_timings_(); |
428 | if (cpuclk_was_changed) { |
9f6a4e90 |
429 | memregl[0xf004>>2] = pllsetreg0_old; |
2275c676 |
430 | memregl[0xf07c>>2] |= 0x8000; |
431 | } |
45285368 |
432 | timer_cleanup(); |
2275c676 |
433 | |
ee2a3bdf |
434 | munmap((void *)memregs, 0x20000); |
435 | close(memdev); |
61753a67 |
436 | if (battdev >= 0) |
437 | close(battdev); |
42171343 |
438 | } |
439 | |