| e14743d1 |
1 | |
| 2 | /* |
| 3 | * MGA Millennium (MGA2064W) functions |
| 4 | * MGA Mystique (MGA1064SG) functions |
| 5 | * |
| 6 | * Copyright 1996 The XFree86 Project, Inc. |
| 7 | * |
| 8 | * Authors |
| 9 | * Dirk Hohndel |
| 10 | * hohndel@XFree86.Org |
| 11 | * David Dawes |
| 12 | * dawes@XFree86.Org |
| 13 | * Contributors: |
| 14 | * Guy DESBIEF, Aix-en-provence, France |
| 15 | * g.desbief@aix.pacwan.net |
| 16 | * MGA1064SG Mystique register file |
| 17 | */ |
| 18 | |
| 19 | |
| 20 | #ifndef _MGA_REG_H_ |
| 21 | #define _MGA_REG_H_ |
| 22 | |
| 23 | #define MGAREG_DWGCTL 0x1c00 |
| 24 | #define MGAREG_MACCESS 0x1c04 |
| 25 | /* the following is a mystique only register */ |
| 26 | #define MGAREG_MCTLWTST 0x1c08 |
| 27 | #define MGAREG_ZORG 0x1c0c |
| 28 | |
| 29 | #define MGAREG_PAT0 0x1c10 |
| 30 | #define MGAREG_PAT1 0x1c14 |
| 31 | #define MGAREG_PLNWT 0x1c1c |
| 32 | |
| 33 | #define MGAREG_BCOL 0x1c20 |
| 34 | #define MGAREG_FCOL 0x1c24 |
| 35 | |
| 36 | #define MGAREG_SRC0 0x1c30 |
| 37 | #define MGAREG_SRC1 0x1c34 |
| 38 | #define MGAREG_SRC2 0x1c38 |
| 39 | #define MGAREG_SRC3 0x1c3c |
| 40 | |
| 41 | #define MGAREG_XYSTRT 0x1c40 |
| 42 | #define MGAREG_XYEND 0x1c44 |
| 43 | |
| 44 | #define MGAREG_SHIFT 0x1c50 |
| 45 | /* the following is a mystique only register */ |
| 46 | #define MGAREG_DMAPAD 0x1c54 |
| 47 | #define MGAREG_SGN 0x1c58 |
| 48 | #define MGAREG_LEN 0x1c5c |
| 49 | |
| 50 | #define MGAREG_AR0 0x1c60 |
| 51 | #define MGAREG_AR1 0x1c64 |
| 52 | #define MGAREG_AR2 0x1c68 |
| 53 | #define MGAREG_AR3 0x1c6c |
| 54 | #define MGAREG_AR4 0x1c70 |
| 55 | #define MGAREG_AR5 0x1c74 |
| 56 | #define MGAREG_AR6 0x1c78 |
| 57 | |
| 58 | #define MGAREG_CXBNDRY 0x1c80 |
| 59 | #define MGAREG_FXBNDRY 0x1c84 |
| 60 | #define MGAREG_YDSTLEN 0x1c88 |
| 61 | #define MGAREG_PITCH 0x1c8c |
| 62 | |
| 63 | #define MGAREG_YDST 0x1c90 |
| 64 | #define MGAREG_YDSTORG 0x1c94 |
| 65 | #define MGAREG_YTOP 0x1c98 |
| 66 | #define MGAREG_YBOT 0x1c9c |
| 67 | |
| 68 | #define MGAREG_CXLEFT 0x1ca0 |
| 69 | #define MGAREG_CXRIGHT 0x1ca4 |
| 70 | #define MGAREG_FXLEFT 0x1ca8 |
| 71 | #define MGAREG_FXRIGHT 0x1cac |
| 72 | |
| 73 | #define MGAREG_XDST 0x1cb0 |
| 74 | |
| 75 | #define MGAREG_DR0 0x1cc0 |
| 76 | #define MGAREG_DR1 0x1cc4 |
| 77 | #define MGAREG_DR2 0x1cc8 |
| 78 | #define MGAREG_DR3 0x1ccc |
| 79 | |
| 80 | #define MGAREG_DR4 0x1cd0 |
| 81 | #define MGAREG_DR5 0x1cd4 |
| 82 | #define MGAREG_DR6 0x1cd8 |
| 83 | #define MGAREG_DR7 0x1cdc |
| 84 | |
| 85 | #define MGAREG_DR8 0x1ce0 |
| 86 | #define MGAREG_DR9 0x1ce4 |
| 87 | #define MGAREG_DR10 0x1ce8 |
| 88 | #define MGAREG_DR11 0x1cec |
| 89 | |
| 90 | #define MGAREG_DR12 0x1cf0 |
| 91 | #define MGAREG_DR13 0x1cf4 |
| 92 | #define MGAREG_DR14 0x1cf8 |
| 93 | #define MGAREG_DR15 0x1cfc |
| 94 | |
| 95 | #define MGAREG_SRCORG 0x2cb4 |
| 96 | #define MGAREG_DSTORG 0x2cb8 |
| 97 | |
| 98 | /* add or or this to one of the previous "power registers" to start |
| 99 | the drawing engine */ |
| 100 | |
| 101 | #define MGAREG_EXEC 0x0100 |
| 102 | |
| 103 | #define MGAREG_FIFOSTATUS 0x1e10 |
| 104 | #define MGAREG_STATUS 0x1e14 |
| 105 | #define MGAREG_ICLEAR 0x1e18 |
| 106 | #define MGAREG_IEN 0x1e1c |
| 107 | |
| 108 | #define MGAREG_VCOUNT 0x1e20 |
| 109 | |
| 110 | #define MGAREG_Reset 0x1e40 |
| 111 | |
| 112 | #define MGAREG_OPMODE 0x1e54 |
| 113 | |
| 114 | /* OPMODE register additives */ |
| 115 | |
| 116 | #define MGAOPM_DMA_GENERAL (0x00 << 2) |
| 117 | #define MGAOPM_DMA_BLIT (0x01 << 2) |
| 118 | #define MGAOPM_DMA_VECTOR (0x10 << 2) |
| 119 | |
| 120 | /* DWGCTL register additives */ |
| 121 | |
| 122 | /* Lines */ |
| 123 | |
| 124 | #define MGADWG_LINE_OPEN 0x00 |
| 125 | #define MGADWG_AUTOLINE_OPEN 0x01 |
| 126 | #define MGADWG_LINE_CLOSE 0x02 |
| 127 | #define MGADWG_AUTOLINE_CLOSE 0x03 |
| 128 | |
| 129 | /* Trapezoids */ |
| 130 | #define MGADWG_TRAP 0x04 |
| 131 | #define MGADWG_TEXTURE_TRAP 0x05 |
| 132 | |
| 133 | /* BitBlts */ |
| 134 | |
| 135 | #define MGADWG_BITBLT 0x08 |
| 136 | #define MGADWG_FBITBLT 0x0c |
| 137 | #define MGADWG_ILOAD 0x09 |
| 138 | #define MGADWG_ILOAD_SCALE 0x0d |
| 139 | #define MGADWG_ILOAD_FILTER 0x0f |
| 140 | #define MGADWG_IDUMP 0x0a |
| 141 | |
| 142 | /* atype access to WRAM */ |
| 143 | |
| 144 | #define MGADWG_RPL ( 0x00 << 4 ) |
| 145 | #define MGADWG_RSTR ( 0x01 << 4 ) |
| 146 | #define MGADWG_ZI ( 0x03 << 4 ) |
| 147 | #define MGADWG_BLK ( 0x04 << 4 ) |
| 148 | #define MGADWG_I ( 0x07 << 4 ) |
| 149 | |
| 150 | /* specifies whether bit blits are linear or xy */ |
| 151 | #define MGADWG_LINEAR ( 0x01 << 7 ) |
| 152 | |
| 153 | /* z drawing mode. use MGADWG_NOZCMP for always */ |
| 154 | |
| 155 | #define MGADWG_NOZCMP ( 0x00 << 8 ) |
| 156 | #define MGADWG_ZE ( 0x02 << 8 ) |
| 157 | #define MGADWG_ZNE ( 0x03 << 8 ) |
| 158 | #define MGADWG_ZLT ( 0x04 << 8 ) |
| 159 | #define MGADWG_ZLTE ( 0x05 << 8 ) |
| 160 | #define MGADWG_GT ( 0x06 << 8 ) |
| 161 | #define MGADWG_GTE ( 0x07 << 8 ) |
| 162 | |
| 163 | /* use this to force colour expansion circuitry to do its stuff */ |
| 164 | |
| 165 | #define MGADWG_SOLID ( 0x01 << 11 ) |
| 166 | |
| 167 | /* ar register at zero */ |
| 168 | |
| 169 | #define MGADWG_ARZERO ( 0x01 << 12 ) |
| 170 | |
| 171 | #define MGADWG_SGNZERO ( 0x01 << 13 ) |
| 172 | |
| 173 | #define MGADWG_SHIFTZERO ( 0x01 << 14 ) |
| 174 | |
| 175 | /* See table on 4-43 for bop ALU operations */ |
| 176 | |
| 177 | /* See table on 4-44 for translucidity masks */ |
| 178 | |
| 179 | #define MGADWG_BMONOLEF ( 0x00 << 25 ) |
| 180 | #define MGADWG_BMONOWF ( 0x04 << 25 ) |
| 181 | #define MGADWG_BPLAN ( 0x01 << 25 ) |
| 182 | |
| 183 | /* note that if bfcol is specified and you're doing a bitblt, it causes |
| 184 | a fbitblt to be performed, so check that you obey the fbitblt rules */ |
| 185 | |
| 186 | #define MGADWG_BFCOL ( 0x02 << 25 ) |
| 187 | #define MGADWG_BUYUV ( 0x0e << 25 ) |
| 188 | #define MGADWG_BU32BGR ( 0x03 << 25 ) |
| 189 | #define MGADWG_BU32RGB ( 0x07 << 25 ) |
| 190 | #define MGADWG_BU24BGR ( 0x0b << 25 ) |
| 191 | #define MGADWG_BU24RGB ( 0x0f << 25 ) |
| 192 | |
| 193 | #define MGADWG_REPLACE 0x000C0000 /* From Linux kernel sources */ |
| 194 | #define MGADWG_PATTERN ( 0x01 << 29 ) |
| 195 | #define MGADWG_TRANSC ( 0x01 << 30 ) |
| 196 | #define MGADWG_NOCLIP ( 0x01 << 31 ) |
| 197 | #define MGAREG_MISC_WRITE 0x3c2 |
| 198 | #define MGAREG_MISC_READ 0x3cc |
| 199 | #define MGAREG_MISC_IOADSEL (0x1 << 0) |
| 200 | #define MGAREG_MISC_RAMMAPEN (0x1 << 1) |
| 201 | #define MGAREG_MISC_CLK_SEL_VGA25 (0x0 << 2) |
| 202 | #define MGAREG_MISC_CLK_SEL_VGA28 (0x1 << 2) |
| 203 | #define MGAREG_MISC_CLK_SEL_MGA_PIX (0x2 << 2) |
| 204 | #define MGAREG_MISC_CLK_SEL_MGA_MSK (0x3 << 2) |
| 205 | #define MGAREG_MISC_VIDEO_DIS (0x1 << 4) |
| 206 | #define MGAREG_MISC_HIGH_PG_SEL (0x1 << 5) |
| 207 | |
| 208 | /* MMIO VGA registers */ |
| 209 | #define MGAREG_CRTC_INDEX 0x1fd4 |
| 210 | #define MGAREG_CRTC_DATA 0x1fd5 |
| 211 | #define MGAREG_CRTCEXT_INDEX 0x1fde |
| 212 | #define MGAREG_CRTCEXT_DATA 0x1fdf |
| 213 | |
| 214 | |
| 215 | /* MGA bits for registers PCI_OPTION_REG */ |
| 216 | #define MGA1064_OPT_SYS_CLK_PCI ( 0x00 << 0 ) |
| 217 | #define MGA1064_OPT_SYS_CLK_PLL ( 0x01 << 0 ) |
| 218 | #define MGA1064_OPT_SYS_CLK_EXT ( 0x02 << 0 ) |
| 219 | #define MGA1064_OPT_SYS_CLK_MSK ( 0x03 << 0 ) |
| 220 | |
| 221 | #define MGA1064_OPT_SYS_CLK_DIS ( 0x01 << 2 ) |
| 222 | #define MGA1064_OPT_G_CLK_DIV_1 ( 0x01 << 3 ) |
| 223 | #define MGA1064_OPT_M_CLK_DIV_1 ( 0x01 << 4 ) |
| 224 | |
| 225 | #define MGA1064_OPT_SYS_PLL_PDN ( 0x01 << 5 ) |
| 226 | #define MGA1064_OPT_VGA_ION ( 0x01 << 8 ) |
| 227 | |
| 228 | /* MGA registers in PCI config space */ |
| 229 | #define PCI_MGA_INDEX 0x44 |
| 230 | #define PCI_MGA_DATA 0x48 |
| 231 | #define PCI_MGA_OPTION2 0x50 |
| 232 | #define PCI_MGA_OPTION3 0x54 |
| 233 | |
| 234 | #define RAMDAC_OFFSET 0x3c00 |
| 235 | |
| 236 | /* TVP3026 direct registers */ |
| 237 | |
| 238 | #define TVP3026_INDEX 0x00 |
| 239 | #define TVP3026_WADR_PAL 0x00 |
| 240 | #define TVP3026_COL_PAL 0x01 |
| 241 | #define TVP3026_PIX_RD_MSK 0x02 |
| 242 | #define TVP3026_RADR_PAL 0x03 |
| 243 | #define TVP3026_CUR_COL_ADDR 0x04 |
| 244 | #define TVP3026_CUR_COL_DATA 0x05 |
| 245 | #define TVP3026_DATA 0x0a |
| 246 | #define TVP3026_CUR_RAM 0x0b |
| 247 | #define TVP3026_CUR_XLOW 0x0c |
| 248 | #define TVP3026_CUR_XHI 0x0d |
| 249 | #define TVP3026_CUR_YLOW 0x0e |
| 250 | #define TVP3026_CUR_YHI 0x0f |
| 251 | |
| 252 | /* TVP3026 indirect registers */ |
| 253 | |
| 254 | #define TVP3026_SILICON_REV 0x01 |
| 255 | #define TVP3026_CURSOR_CTL 0x06 |
| 256 | #define TVP3026_LATCH_CTL 0x0f |
| 257 | #define TVP3026_TRUE_COLOR_CTL 0x18 |
| 258 | #define TVP3026_MUX_CTL 0x19 |
| 259 | #define TVP3026_CLK_SEL 0x1a |
| 260 | #define TVP3026_PAL_PAGE 0x1c |
| 261 | #define TVP3026_GEN_CTL 0x1d |
| 262 | #define TVP3026_MISC_CTL 0x1e |
| 263 | #define TVP3026_GEN_IO_CTL 0x2a |
| 264 | #define TVP3026_GEN_IO_DATA 0x2b |
| 265 | #define TVP3026_PLL_ADDR 0x2c |
| 266 | #define TVP3026_PIX_CLK_DATA 0x2d |
| 267 | #define TVP3026_MEM_CLK_DATA 0x2e |
| 268 | #define TVP3026_LOAD_CLK_DATA 0x2f |
| 269 | #define TVP3026_KEY_RED_LOW 0x32 |
| 270 | #define TVP3026_KEY_RED_HI 0x33 |
| 271 | #define TVP3026_KEY_GREEN_LOW 0x34 |
| 272 | #define TVP3026_KEY_GREEN_HI 0x35 |
| 273 | #define TVP3026_KEY_BLUE_LOW 0x36 |
| 274 | #define TVP3026_KEY_BLUE_HI 0x37 |
| 275 | #define TVP3026_KEY_CTL 0x38 |
| 276 | #define TVP3026_MCLK_CTL 0x39 |
| 277 | #define TVP3026_SENSE_TEST 0x3a |
| 278 | #define TVP3026_TEST_DATA 0x3b |
| 279 | #define TVP3026_CRC_LSB 0x3c |
| 280 | #define TVP3026_CRC_MSB 0x3d |
| 281 | #define TVP3026_CRC_CTL 0x3e |
| 282 | #define TVP3026_ID 0x3f |
| 283 | #define TVP3026_RESET 0xff |
| 284 | |
| 285 | |
| 286 | /* MGA1064 DAC Register file */ |
| 287 | /* MGA1064 direct registers */ |
| 288 | |
| 289 | #define MGA1064_INDEX 0x00 |
| 290 | #define MGA1064_WADR_PAL 0x00 |
| 291 | #define MGA1064_COL_PAL 0x01 |
| 292 | #define MGA1064_PIX_RD_MSK 0x02 |
| 293 | #define MGA1064_RADR_PAL 0x03 |
| 294 | #define MGA1064_DATA 0x0a |
| 295 | |
| 296 | #define MGA1064_CUR_XLOW 0x0c |
| 297 | #define MGA1064_CUR_XHI 0x0d |
| 298 | #define MGA1064_CUR_YLOW 0x0e |
| 299 | #define MGA1064_CUR_YHI 0x0f |
| 300 | |
| 301 | /* MGA1064 indirect registers */ |
| 302 | #define MGA1064_CURSOR_BASE_ADR_LOW 0x04 |
| 303 | #define MGA1064_CURSOR_BASE_ADR_HI 0x05 |
| 304 | #define MGA1064_CURSOR_CTL 0x06 |
| 305 | #define MGA1064_CURSOR_COL0_RED 0x08 |
| 306 | #define MGA1064_CURSOR_COL0_GREEN 0x09 |
| 307 | #define MGA1064_CURSOR_COL0_BLUE 0x0a |
| 308 | |
| 309 | #define MGA1064_CURSOR_COL1_RED 0x0c |
| 310 | #define MGA1064_CURSOR_COL1_GREEN 0x0d |
| 311 | #define MGA1064_CURSOR_COL1_BLUE 0x0e |
| 312 | |
| 313 | #define MGA1064_CURSOR_COL2_RED 0x010 |
| 314 | #define MGA1064_CURSOR_COL2_GREEN 0x011 |
| 315 | #define MGA1064_CURSOR_COL2_BLUE 0x012 |
| 316 | |
| 317 | #define MGA1064_VREF_CTL 0x018 |
| 318 | |
| 319 | #define MGA1064_MUL_CTL 0x19 |
| 320 | #define MGA1064_MUL_CTL_8bits 0x0 |
| 321 | #define MGA1064_MUL_CTL_15bits 0x01 |
| 322 | #define MGA1064_MUL_CTL_16bits 0x02 |
| 323 | #define MGA1064_MUL_CTL_24bits 0x03 |
| 324 | #define MGA1064_MUL_CTL_32bits 0x04 |
| 325 | #define MGA1064_MUL_CTL_2G8V16bits 0x05 |
| 326 | #define MGA1064_MUL_CTL_G16V16bits 0x06 |
| 327 | #define MGA1064_MUL_CTL_32_24bits 0x07 |
| 328 | |
| 329 | #define MGAGDAC_XVREFCTRL 0x18 |
| 330 | #define MGA1064_PIX_CLK_CTL 0x1a |
| 331 | #define MGA1064_PIX_CLK_CTL_CLK_DIS ( 0x01 << 2 ) |
| 332 | #define MGA1064_PIX_CLK_CTL_CLK_POW_DOWN ( 0x01 << 3 ) |
| 333 | #define MGA1064_PIX_CLK_CTL_SEL_PCI ( 0x00 << 0 ) |
| 334 | #define MGA1064_PIX_CLK_CTL_SEL_PLL ( 0x01 << 0 ) |
| 335 | #define MGA1064_PIX_CLK_CTL_SEL_EXT ( 0x02 << 0 ) |
| 336 | #define MGA1064_PIX_CLK_CTL_SEL_MSK ( 0x03 << 0 ) |
| 337 | |
| 338 | #define MGA1064_GEN_CTL 0x1d |
| 339 | #define MGA1064_MISC_CTL 0x1e |
| 340 | #define MGA1064_MISC_CTL_DAC_POW_DN ( 0x01 << 0 ) |
| 341 | #define MGA1064_MISC_CTL_VGA ( 0x01 << 1 ) |
| 342 | #define MGA1064_MISC_CTL_DIS_CON ( 0x03 << 1 ) |
| 343 | #define MGA1064_MISC_CTL_MAFC ( 0x02 << 1 ) |
| 344 | #define MGA1064_MISC_CTL_VGA8 ( 0x01 << 3 ) |
| 345 | #define MGA1064_MISC_CTL_DAC_RAM_CS ( 0x01 << 4 ) |
| 346 | |
| 347 | #define MGA1064_GEN_IO_CTL 0x2a |
| 348 | #define MGA1064_GEN_IO_DATA 0x2b |
| 349 | #define MGA1064_SYS_PLL_M 0x2c |
| 350 | #define MGA1064_SYS_PLL_N 0x2d |
| 351 | #define MGA1064_SYS_PLL_P 0x2e |
| 352 | #define MGA1064_SYS_PLL_STAT 0x2f |
| 353 | #define MGA1064_ZOOM_CTL 0x38 |
| 354 | #define MGA1064_SENSE_TST 0x3a |
| 355 | |
| 356 | #define MGA1064_CRC_LSB 0x3c |
| 357 | #define MGA1064_CRC_MSB 0x3d |
| 358 | #define MGA1064_CRC_CTL 0x3e |
| 359 | #define MGA1064_COL_KEY_MSK_LSB 0x40 |
| 360 | #define MGA1064_COL_KEY_MSK_MSB 0x41 |
| 361 | #define MGA1064_COL_KEY_LSB 0x42 |
| 362 | #define MGA1064_COL_KEY_MSB 0x43 |
| 363 | #define MGA1064_PIX_PLLA_M 0x44 |
| 364 | #define MGA1064_PIX_PLLA_N 0x45 |
| 365 | #define MGA1064_PIX_PLLA_P 0x46 |
| 366 | #define MGA1064_PIX_PLLB_M 0x48 |
| 367 | #define MGA1064_PIX_PLLB_N 0x49 |
| 368 | #define MGA1064_PIX_PLLB_P 0x4a |
| 369 | #define MGA1064_PIX_PLLC_M 0x4c |
| 370 | #define MGA1064_PIX_PLLC_N 0x4d |
| 371 | #define MGA1064_PIX_PLLC_P 0x4e |
| 372 | |
| 373 | #define MGA1064_PIX_PLL_STAT 0x4f |
| 374 | |
| 375 | #endif |
| 376 | |
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