h-int reload test
[megadrive.git] / testpico / sh2_test.sh2
CommitLineData
9d39a80e 1
2 .text
3
4! Master Vector Base Table at 0x06000000
5
6 .long mstart /* Cold Start PC */
7 .long 0x06040000 /* Cold Start SP */
8 .long mstart /* Manual Reset PC */
9 .long 0x06040000 /* Manual Reset SP */
71b41fdd 10 .long master_e4 /* Illegal instruction */
11 .long master_e5 /* reserved */
12 .long master_e6 /* Invalid slot instruction */
13 .long master_e7 /* reserved */
14 .long master_e8 /* reserved */
15 .long master_e9 /* CPU address error */
16 .long master_e10 /* DMA address error */
17 .long master_e11 /* NMI vector */
18 .long master_e12 /* User break vector */
19.rept 19
20 .long main_err /* reserved */
21.endr
22.rept 32
23 .long main_err /* TRAPA #32-63 */
24.endr
9d39a80e 25 .long main_irq /* Level 1 IRQ */
26 .long main_irq /* Level 2 & 3 IRQ's */
27 .long main_irq /* Level 4 & 5 IRQ's */
28 .long main_irq /* PWM interupt */
29 .long main_irq /* Command interupt */
30 .long main_irq /* H Blank interupt */
31 .long main_irq /* V Blank interupt */
32 .long main_irq /* Reset Button */
71b41fdd 33.rept 56
34 .long main_err /* peripherals */
35.endr
9d39a80e 36
71b41fdd 37! Slave Vector Base Table at 0x06000200
9d39a80e 38
39 .long sstart /* Cold Start PC */
40 .long 0x0603f800 /* Cold Start SP */
41 .long sstart /* Manual Reset PC */
42 .long 0x0603f800 /* Manual Reset SP */
71b41fdd 43 .long slave_e4 /* Illegal instruction */
44 .long slave_e5 /* reserved */
45 .long slave_e6 /* Invalid slot instruction */
46 .long slave_e7 /* reserved */
47 .long slave_e8 /* reserved */
48 .long slave_e9 /* CPU address error */
49 .long slave_e10 /* DMA address error */
50 .long slave_e11 /* NMI vector */
51 .long slave_e12 /* User break vector */
52.rept 19
53 .long slave_err /* reserved */
54.endr
55.rept 32
56 .long slave_err /* TRAPA #32-63 */
57.endr
58 .long slave_irq /* Level 1 IRQ */
59 .long slave_irq /* Level 2 & 3 IRQ's */
60 .long slave_irq /* Level 4 & 5 IRQ's */
61 .long slave_irq /* PWM interupt */
62 .long slave_irq /* Command interupt */
63 .long slave_irq /* H Blank interupt */
64 .long slave_irq /* V Blank interupt */
65 .long slave_irq /* Reset Button */
66.rept 56
67 .long slave_err /* peripherals */
68.endr
69
70! trashes r0
71.macro mov_bc const ofs reg
72 mov #\const, r0
73.if \ofs == 0
74 mov.b r0, @\reg
75.else
76 mov.b r0, @(\ofs, \reg)
77.endif
78.endm
9d39a80e 79
80! Stacks set up by BIOS
81
71b41fdd 82! The main SH2 starts here at 0x06000400
9d39a80e 83
84mstart:
71b41fdd 85 bra xstart
9d39a80e 86 mov #0, r4
87
71b41fdd 88! The slave SH2 starts here at 0x06000404
9d39a80e 89
90sstart:
9d39a80e 91 mov #1, r4
92
9d39a80e 93xstart:
71b41fdd 94.if 0
95! cache init - done by BIOS with single 0x11 write
96 mov.l l_cctl, r1 /* cache */
97 mov_bc 0x00, 0, r1 /* disable */
98 mov.b @r1, r0 /* dummy read */
99 mov_bc 0x10, 0, r1 /* purge */
100 mov.b @r1, r0
101 mov_bc 0x01, 0, r1 /* enable */
102.endif
103 mov #0xd0, r0 /* enable irqs */
104 ldc r0, sr
9d39a80e 105 mov.l l_main_c, r0
106 jmp @r0
107 nop
108
71b41fdd 109main_irq:
110 mov.l r0, @-r15
111
112 stc sr, r0 /* SR holds IRQ level in I3-I0 */
113 shlr2 r0
114 and #0x38,r0
115 cmp/eq #0x38,r0
116 bt main_irq_vres
117! todo
1180:
119 bra 0b
120 nop
121
122main_irq_vres:
123 mov.w r0, @(0x14, gbr) /* ack */
124 mov.b @(7, gbr), r0 /* RV */
125 tst #1, r0
126 bt main_irq_ret
127
128! Try to set FTOB pin that's wired to 32X hard reset.
129! Doesn't seem to be working right though, it somehow disturbs
130! 68k reset PC fetch which mysteriously ends up at range
131! 2c8 - 304 in multiples of 4, proportionally to reset delay
132! (0 - ~300 (?) sh2 cycles). Longer delay just hangs, presumably
133! at 880200?
134 mov.l l_frt, r1
135 mov_bc 0xf1, 7, r1 /* TOCR sel OCRB, pin on B match */
136 mov #0, r0
137 mov.b r0, @(4, r1) /* OCRB H - output compare B */
138 mov.b r0, @(5, r1) /* OCRB L */
139 mov.b r0, @(2, r1) /* FRC H */
140 mov.b r0, @(3, r1) /* FRC L */
141 mov.b @(7, r1), r0
142! sleep - docs say not to use
143! sleep
1440:
145 bra 0b
146 nop
147
148main_irq_ret:
149 rte
150 mov.l @r15+, r0
151
152.global _read_frt
153_read_frt:
154 mov.l l_frt, r2
155 mov.b @(2, r2), r0
156 extu.b r0, r1
157 mov.b @(3, r2), r0
158 extu.b r0, r0
159 shll8 r1
160 rts
161 or r1, r0
162
9d39a80e 163.align 2
164l_cctl:
165 .long 0xFFFFFE92
71b41fdd 166l_frt:
167 .long 0xFFFFFE10
9d39a80e 168l_main_c:
169 .long _main_c
170
171! dummy
172.global _start
173_start:
174
71b41fdd 175main_err:
176 bra do_exc_master
177 mov #0xff, r0
178slave_err:
179slave_irq:
180 bra do_exc_slave
181 mov #0xff, r0
182
183.macro exc_master num
184master_e\num:
185 bra do_exc_master
186 mov #\num, r0
187.endm
188
189.macro exc_slave num
190slave_e\num:
191 bra do_exc_slave
192 mov #\num, r0
193.endm
194
195exc_master 4
196exc_master 5
197exc_master 6
198exc_master 7
199exc_master 8
200exc_master 9
201exc_master 10
202exc_master 11
203exc_master 12
204
205exc_slave 4
206exc_slave 5
207exc_slave 6
208exc_slave 7
209exc_slave 8
210exc_slave 9
211exc_slave 10
212exc_slave 11
213exc_slave 12
214
215do_exc_master:
216 mov.w r0, @(0x2c, gbr)
2170:
218 bra 0b
219 nop
220
221do_exc_slave:
222 mov.w r0, @(0x2e, gbr)
2230:
224 bra 0b
225 nop
226
9d39a80e 227.global _spin
228_spin:
229 dt r4
230 bf _spin
231 rts
232 nop
233
9d39a80e 234! vim:ts=8:sw=8:expandtab