[pcsx_rearmed.git] / libpcsxcore / r3000a.c

/***************************************************************************
 *   Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team              *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
 ***************************************************************************/

/*
* R3000A CPU functions.
*/

#include "r3000a.h"
#include "cdrom.h"
#include "mdec.h"
#include "gte.h"
#include "psxinterpreter.h"

R3000Acpu *psxCpu = NULL;
#ifdef DRC_DISABLE
psxRegisters psxRegs;
#endif

int psxInit() {
	SysPrintf(_("Running PCSX Version %s (%s).\n"), PCSX_VERSION, __DATE__);

#ifndef DRC_DISABLE
	if (Config.Cpu == CPU_INTERPRETER) {
		psxCpu = &psxInt;
	} else psxCpu = &psxRec;
#else
	Config.Cpu = CPU_INTERPRETER;
	psxCpu = &psxInt;
#endif

	Log = 0;

	if (psxMemInit() == -1) return -1;

	return psxCpu->Init();
}

void psxReset() {
	psxMemReset();

	memset(&psxRegs, 0, sizeof(psxRegs));

	psxRegs.pc = 0xbfc00000; // Start in bootstrap

	psxRegs.CP0.r[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
	psxRegs.CP0.r[15] = 0x00000002; // PRevID = Revision ID, same as R3000A

	psxCpu->ApplyConfig();
	psxCpu->Reset();

	psxHwReset();
	psxBiosInit();

	if (!Config.HLE)
		psxExecuteBios();

#ifdef EMU_LOG
	EMU_LOG("*BIOS END*\n");
#endif
	Log = 0;
}

void psxShutdown() {
	psxBiosShutdown();

	psxCpu->Shutdown();

	psxMemShutdown();
}

// cp0 is passed separately for lightrec to be less messy
void psxException(u32 code, u32 bd, psxCP0Regs *cp0) {
	psxRegs.code = PSXMu32(psxRegs.pc);
	
	if (!Config.HLE && ((((psxRegs.code) >> 24) & 0xfe) == 0x4a)) {
		// "hokuto no ken" / "Crash Bandicot 2" ...
		// BIOS does not allow to return to GTE instructions
		// (just skips it, supposedly because it's scheduled already)
		// so we execute it here
		psxCP2Regs *cp2 = (void *)(cp0 + 1);
		psxCP2[psxRegs.code & 0x3f](cp2);
	}

	// Set the Cause
	cp0->n.Cause = (cp0->n.Cause & 0x300) | code;

	// Set the EPC & PC
	if (bd) {
#ifdef PSXCPU_LOG
		PSXCPU_LOG("bd set!!!\n");
#endif
		cp0->n.Cause |= 0x80000000;
		cp0->n.EPC = (psxRegs.pc - 4);
	} else
		cp0->n.EPC = (psxRegs.pc);

	if (cp0->n.Status & 0x400000)
		psxRegs.pc = 0xbfc00180;
	else
		psxRegs.pc = 0x80000080;

	// Set the Status
	cp0->n.Status = (cp0->n.Status & ~0x3f) | ((cp0->n.Status & 0x0f) << 2);

	if (Config.HLE) psxBiosException();
}

void psxBranchTest() {
	if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
		psxRcntUpdate();

	if (psxRegs.interrupt) {
		if ((psxRegs.interrupt & (1 << PSXINT_SIO))) { // sio
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_SIO);
				sioInterrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_CDR)) { // cdr
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDR].sCycle) >= psxRegs.intCycle[PSXINT_CDR].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_CDR);
				cdrInterrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_CDREAD)) { // cdr read
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDREAD].sCycle) >= psxRegs.intCycle[PSXINT_CDREAD].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_CDREAD);
				cdrPlayReadInterrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_GPUDMA)) { // gpu dma
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUDMA].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_GPUDMA);
				gpuInterrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_MDECOUTDMA)) { // mdec out dma
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_MDECOUTDMA);
				mdec1Interrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_SPUDMA)) { // spu dma
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_SPUDMA].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_SPUDMA);
				spuInterrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_MDECINDMA)) { // mdec in
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECINDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECINDMA].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_MDECINDMA);
				mdec0Interrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_GPUOTCDMA)) { // gpu otc
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_GPUOTCDMA);
				gpuotcInterrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_CDRDMA)) { // cdrom
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRDMA].sCycle) >= psxRegs.intCycle[PSXINT_CDRDMA].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_CDRDMA);
				cdrDmaInterrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_CDRLID)) { // cdr lid states
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRLID].sCycle) >= psxRegs.intCycle[PSXINT_CDRLID].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_CDRLID);
				cdrLidSeekInterrupt();
			}
		}
		if (psxRegs.interrupt & (1 << PSXINT_SPU_UPDATE)) { // scheduled spu update
			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPU_UPDATE].sCycle) >= psxRegs.intCycle[PSXINT_SPU_UPDATE].cycle) {
				psxRegs.interrupt &= ~(1 << PSXINT_SPU_UPDATE);
				spuUpdate();
			}
		}
	}

	if (psxHu32(0x1070) & psxHu32(0x1074)) {
		if ((psxRegs.CP0.n.Status & 0x401) == 0x401) {
#ifdef PSXCPU_LOG
			PSXCPU_LOG("Interrupt: %x %x\n", psxHu32(0x1070), psxHu32(0x1074));
#endif
//			SysPrintf("Interrupt (%x): %x %x\n", psxRegs.cycle, psxHu32(0x1070), psxHu32(0x1074));
			psxException(0x400, 0, &psxRegs.CP0);
		}
	}
}

void psxJumpTest() {
	if (!Config.HLE && Config.PsxOut) {
		u32 call = psxRegs.GPR.n.t1 & 0xff;
		switch (psxRegs.pc & 0x1fffff) {
			case 0xa0:
#ifdef PSXBIOS_LOG
				if (call != 0x28 && call != 0xe) {
					PSXBIOS_LOG("Bios call a0: %s (%x) %x,%x,%x,%x\n", biosA0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
#endif
				if (biosA0[call])
					biosA0[call]();
				break;
			case 0xb0:
#ifdef PSXBIOS_LOG
				if (call != 0x17 && call != 0xb) {
					PSXBIOS_LOG("Bios call b0: %s (%x) %x,%x,%x,%x\n", biosB0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
#endif
				if (biosB0[call])
					biosB0[call]();
				break;
			case 0xc0:
#ifdef PSXBIOS_LOG
				PSXBIOS_LOG("Bios call c0: %s (%x) %x,%x,%x,%x\n", biosC0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
#endif
				if (biosC0[call])
					biosC0[call]();
				break;
		}
	}
}

void psxExecuteBios() {
	while (psxRegs.pc != 0x80030000)
		psxCpu->ExecuteBlock();
}
Commit	Line	Data
	1	/***************************************************************************
	2	* Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
	3	* *
	4	* This program is free software; you can redistribute it and/or modify *
	5	* it under the terms of the GNU General Public License as published by *
	6	* the Free Software Foundation; either version 2 of the License, or *
	7	* (at your option) any later version. *
	8	* *
	9	* This program is distributed in the hope that it will be useful, *
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	12	* GNU General Public License for more details. *
	13	* *
	14	* You should have received a copy of the GNU General Public License *
	15	* along with this program; if not, write to the *
	16	* Free Software Foundation, Inc., *
	17	* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
	18	***************************************************************************/
	19
	20	/*
	21	* R3000A CPU functions.
	22	*/
	23
	24	#include "r3000a.h"
	25	#include "cdrom.h"
	26	#include "mdec.h"
	27	#include "gte.h"
	28	#include "psxinterpreter.h"
	29
	30	R3000Acpu *psxCpu = NULL;
	31	#ifdef DRC_DISABLE
	32	psxRegisters psxRegs;
	33	#endif
	34
	35	int psxInit() {
	36	SysPrintf(_("Running PCSX Version %s (%s).\n"), PCSX_VERSION, __DATE__);
	37
	38	#ifndef DRC_DISABLE
	39	if (Config.Cpu == CPU_INTERPRETER) {
	40	psxCpu = &psxInt;
	41	} else psxCpu = &psxRec;
	42	#else
	43	Config.Cpu = CPU_INTERPRETER;
	44	psxCpu = &psxInt;
	45	#endif
	46
	47	Log = 0;
	48
	49	if (psxMemInit() == -1) return -1;
	50
	51	return psxCpu->Init();
	52	}
	53
	54	void psxReset() {
	55	psxMemReset();
	56
	57	memset(&psxRegs, 0, sizeof(psxRegs));
	58
	59	psxRegs.pc = 0xbfc00000; // Start in bootstrap
	60
	61	psxRegs.CP0.r[12] = 0x10900000; // COP0 enabled \| BEV = 1 \| TS = 1
	62	psxRegs.CP0.r[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
	63
	64	psxCpu->ApplyConfig();
	65	psxCpu->Reset();
	66
	67	psxHwReset();
	68	psxBiosInit();
	69
	70	if (!Config.HLE)
	71	psxExecuteBios();
	72
	73	#ifdef EMU_LOG
	74	EMU_LOG("BIOS END\n");
	75	#endif
	76	Log = 0;
	77	}
	78
	79	void psxShutdown() {
	80	psxBiosShutdown();
	81
	82	psxCpu->Shutdown();
	83
	84	psxMemShutdown();
	85	}
	86
	87	// cp0 is passed separately for lightrec to be less messy
	88	void psxException(u32 code, u32 bd, psxCP0Regs *cp0) {
	89	psxRegs.code = PSXMu32(psxRegs.pc);
	90
	91	if (!Config.HLE && ((((psxRegs.code) >> 24) & 0xfe) == 0x4a)) {
	92	// "hokuto no ken" / "Crash Bandicot 2" ...
	93	// BIOS does not allow to return to GTE instructions
	94	// (just skips it, supposedly because it's scheduled already)
	95	// so we execute it here
	96	psxCP2Regs cp2 = (void )(cp0 + 1);
	97	psxCP2[psxRegs.code & 0x3f](cp2);
	98	}
	99
	100	// Set the Cause
	101	cp0->n.Cause = (cp0->n.Cause & 0x300) \| code;
	102
	103	// Set the EPC & PC
	104	if (bd) {
	105	#ifdef PSXCPU_LOG
	106	PSXCPU_LOG("bd set!!!\n");
	107	#endif
	108	cp0->n.Cause \|= 0x80000000;
	109	cp0->n.EPC = (psxRegs.pc - 4);
	110	} else
	111	cp0->n.EPC = (psxRegs.pc);
	112
	113	if (cp0->n.Status & 0x400000)
	114	psxRegs.pc = 0xbfc00180;
	115	else
	116	psxRegs.pc = 0x80000080;
	117
	118	// Set the Status
	119	cp0->n.Status = (cp0->n.Status & ~0x3f) \| ((cp0->n.Status & 0x0f) << 2);
	120
	121	if (Config.HLE) psxBiosException();
	122	}
	123
	124	void psxBranchTest() {
	125	if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
	126	psxRcntUpdate();
	127
	128	if (psxRegs.interrupt) {
	129	if ((psxRegs.interrupt & (1 << PSXINT_SIO))) { // sio
	130	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) {
	131	psxRegs.interrupt &= ~(1 << PSXINT_SIO);
	132	sioInterrupt();
	133	}
	134	}
	135	if (psxRegs.interrupt & (1 << PSXINT_CDR)) { // cdr
	136	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDR].sCycle) >= psxRegs.intCycle[PSXINT_CDR].cycle) {
	137	psxRegs.interrupt &= ~(1 << PSXINT_CDR);
	138	cdrInterrupt();
	139	}
	140	}
	141	if (psxRegs.interrupt & (1 << PSXINT_CDREAD)) { // cdr read
	142	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDREAD].sCycle) >= psxRegs.intCycle[PSXINT_CDREAD].cycle) {
	143	psxRegs.interrupt &= ~(1 << PSXINT_CDREAD);
	144	cdrPlayReadInterrupt();
	145	}
	146	}
	147	if (psxRegs.interrupt & (1 << PSXINT_GPUDMA)) { // gpu dma
	148	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUDMA].cycle) {
	149	psxRegs.interrupt &= ~(1 << PSXINT_GPUDMA);
	150	gpuInterrupt();
	151	}
	152	}
	153	if (psxRegs.interrupt & (1 << PSXINT_MDECOUTDMA)) { // mdec out dma
	154	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle) {
	155	psxRegs.interrupt &= ~(1 << PSXINT_MDECOUTDMA);
	156	mdec1Interrupt();
	157	}
	158	}
	159	if (psxRegs.interrupt & (1 << PSXINT_SPUDMA)) { // spu dma
	160	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_SPUDMA].cycle) {
	161	psxRegs.interrupt &= ~(1 << PSXINT_SPUDMA);
	162	spuInterrupt();
	163	}
	164	}
	165	if (psxRegs.interrupt & (1 << PSXINT_MDECINDMA)) { // mdec in
	166	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECINDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECINDMA].cycle) {
	167	psxRegs.interrupt &= ~(1 << PSXINT_MDECINDMA);
	168	mdec0Interrupt();
	169	}
	170	}
	171	if (psxRegs.interrupt & (1 << PSXINT_GPUOTCDMA)) { // gpu otc
	172	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle) {
	173	psxRegs.interrupt &= ~(1 << PSXINT_GPUOTCDMA);
	174	gpuotcInterrupt();
	175	}
	176	}
	177	if (psxRegs.interrupt & (1 << PSXINT_CDRDMA)) { // cdrom
	178	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRDMA].sCycle) >= psxRegs.intCycle[PSXINT_CDRDMA].cycle) {
	179	psxRegs.interrupt &= ~(1 << PSXINT_CDRDMA);
	180	cdrDmaInterrupt();
	181	}
	182	}
	183	if (psxRegs.interrupt & (1 << PSXINT_CDRLID)) { // cdr lid states
	184	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRLID].sCycle) >= psxRegs.intCycle[PSXINT_CDRLID].cycle) {
	185	psxRegs.interrupt &= ~(1 << PSXINT_CDRLID);
	186	cdrLidSeekInterrupt();
	187	}
	188	}
	189	if (psxRegs.interrupt & (1 << PSXINT_SPU_UPDATE)) { // scheduled spu update
	190	if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPU_UPDATE].sCycle) >= psxRegs.intCycle[PSXINT_SPU_UPDATE].cycle) {
	191	psxRegs.interrupt &= ~(1 << PSXINT_SPU_UPDATE);
	192	spuUpdate();
	193	}
	194	}
	195	}
	196
	197	if (psxHu32(0x1070) & psxHu32(0x1074)) {
	198	if ((psxRegs.CP0.n.Status & 0x401) == 0x401) {
	199	#ifdef PSXCPU_LOG
	200	PSXCPU_LOG("Interrupt: %x %x\n", psxHu32(0x1070), psxHu32(0x1074));
	201	#endif
	202	// SysPrintf("Interrupt (%x): %x %x\n", psxRegs.cycle, psxHu32(0x1070), psxHu32(0x1074));
	203	psxException(0x400, 0, &psxRegs.CP0);
	204	}
	205	}
	206	}
	207
	208	void psxJumpTest() {
	209	if (!Config.HLE && Config.PsxOut) {
	210	u32 call = psxRegs.GPR.n.t1 & 0xff;
	211	switch (psxRegs.pc & 0x1fffff) {
	212	case 0xa0:
	213	#ifdef PSXBIOS_LOG
	214	if (call != 0x28 && call != 0xe) {
	215	PSXBIOS_LOG("Bios call a0: %s (%x) %x,%x,%x,%x\n", biosA0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
	216	#endif
	217	if (biosA0[call])
	218	biosA0[call]();
	219	break;
	220	case 0xb0:
	221	#ifdef PSXBIOS_LOG
	222	if (call != 0x17 && call != 0xb) {
	223	PSXBIOS_LOG("Bios call b0: %s (%x) %x,%x,%x,%x\n", biosB0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
	224	#endif
	225	if (biosB0[call])
	226	biosB0[call]();
	227	break;
	228	case 0xc0:
	229	#ifdef PSXBIOS_LOG
	230	PSXBIOS_LOG("Bios call c0: %s (%x) %x,%x,%x,%x\n", biosC0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
	231	#endif
	232	if (biosC0[call])
	233	biosC0[call]();
	234	break;
	235	}
	236	}
	237	}
	238
	239	void psxExecuteBios() {
	240	while (psxRegs.pc != 0x80030000)
	241	psxCpu->ExecuteBlock();
	242	}
	243