3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
9 * - tcache, block descriptor, link buffer overflows result in sh2_translate()
10 * failure, followed by full tcache invalidation for that region
11 * - jumps between blocks are tracked for SMC handling (in block_entry->links),
12 * except jumps between different tcaches
15 * - static register allocation
16 * - remaining register caching and tracking in temporaries
17 * - block-local branch linking
18 * - block linking (except between tcaches)
19 * - some constant propagation
22 * - better constant propagation
31 #include "../../pico/pico_int.h"
34 #include "../drc/cmn.h"
38 #define PROPAGATE_CONSTANTS 1
39 #define LINK_BRANCHES 1
42 #define MAX_BLOCK_SIZE (BLOCK_INSN_LIMIT * 6 * 6)
44 // max literal offset from the block end
45 #define MAX_LITERAL_OFFSET 32*2
46 #define MAX_LITERALS (BLOCK_INSN_LIMIT / 4)
47 #define MAX_LOCAL_BRANCHES 32
50 #define FETCH_OP(pc) \
54 ((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1])
59 // 1 - warnings/errors
62 // 8 - runtime block entry log
69 #define dbg(l,...) { \
70 if ((l) & DRC_DEBUG) \
71 elprintf(EL_STATUS, ##__VA_ARGS__); \
74 #include "mame/sh2dasm.h"
75 #include <platform/libpicofe/linux/host_dasm.h>
76 static int insns_compiled, hash_collisions, host_insn_count;
85 static u8 *tcache_dsm_ptrs[3];
86 static char sh2dasm_buff[64];
87 #define do_host_disasm(tcid) \
88 host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \
89 tcache_dsm_ptrs[tcid] = tcache_ptr
91 #define do_host_disasm(x)
94 #if (DRC_DEBUG & 8) || defined(PDB)
95 static void REGPARM(3) *sh2_drc_log_entry(void *block, SH2 *sh2, u32 sr)
98 dbg(8, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
99 sh2->pc, block, (signed int)sr >> 12);
100 pdb_step(sh2, sh2->pc);
107 #define TCACHE_BUFFERS 3
109 // we have 3 translation cache buffers, split from one drc/cmn buffer.
110 // BIOS shares tcache with data array because it's only used for init
111 // and can be discarded early
112 // XXX: need to tune sizes
113 static const int tcache_sizes[TCACHE_BUFFERS] = {
114 DRC_TCACHE_SIZE * 6 / 8, // ROM (rarely used), DRAM
115 DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
116 DRC_TCACHE_SIZE / 8, // ... slave
119 static u8 *tcache_bases[TCACHE_BUFFERS];
120 static u8 *tcache_ptrs[TCACHE_BUFFERS];
122 // ptr for code emiters
123 static u8 *tcache_ptr;
125 #define MAX_BLOCK_ENTRIES (BLOCK_INSN_LIMIT / 8)
129 void *jump; // insn address
130 struct block_link *next; // either in block_entry->links or
135 void *tcache_ptr; // translated block for above PC
136 struct block_entry *next; // next block in hash_table with same pc hash
137 struct block_link *links; // links to this entry
139 struct block_desc *block;
144 u32 addr; // block start SH2 PC address
145 u32 end_addr; // address after last op or literal
150 struct block_entry entryp[MAX_BLOCK_ENTRIES];
153 static const int block_max_counts[TCACHE_BUFFERS] = {
158 static struct block_desc *block_tables[TCACHE_BUFFERS];
159 static int block_counts[TCACHE_BUFFERS];
161 // we have block_link_pool to avoid using mallocs
162 static const int block_link_pool_max_counts[TCACHE_BUFFERS] = {
167 static struct block_link *block_link_pool[TCACHE_BUFFERS];
168 static int block_link_pool_counts[TCACHE_BUFFERS];
169 static struct block_link *unresolved_links[TCACHE_BUFFERS];
171 // used for invalidation
172 static const int ram_sizes[TCACHE_BUFFERS] = {
177 #define ADDR_TO_BLOCK_PAGE 0x100
180 struct block_desc *block;
181 struct block_list *next;
184 // array of pointers to block_lists for RAM and 2 data arrays
185 // each array has len: sizeof(mem) / ADDR_TO_BLOCK_PAGE
186 static struct block_list **inval_lookup[TCACHE_BUFFERS];
188 static const int hash_table_sizes[TCACHE_BUFFERS] = {
193 static struct block_entry **hash_tables[TCACHE_BUFFERS];
195 #define HASH_FUNC(hash_tab, addr, mask) \
196 (hash_tab)[(((addr) >> 20) ^ ((addr) >> 2)) & (mask)]
198 // host register tracking
201 HR_CACHED, // 'val' has sh2_reg_e
202 // HR_CONST, // 'val' has a constant
203 HR_TEMP, // reg used for temp storage
207 HRF_DIRTY = 1 << 0, // reg has "dirty" value to be written to ctx
208 HRF_LOCKED = 1 << 1, // HR_CACHED can't be evicted
212 u32 hreg:5; // "host" reg
213 u32 greg:5; // "guest" reg
216 u32 stamp:16; // kind of a timestamp
219 // note: reg_temp[] must have at least the amount of
220 // registers used by handlers in worst case (currently 4)
222 #include "../drc/emit_arm.c"
224 static const int reg_map_g2h[] = {
228 -1, -1, -1, 9, // r12 .. sp
229 -1, -1, -1, 10, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
230 -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
233 static temp_reg_t reg_temp[] = {
242 #elif defined(__i386__)
243 #include "../drc/emit_x86.c"
245 static const int reg_map_g2h[] = {
254 // ax, cx, dx are usually temporaries by convention
255 static temp_reg_t reg_temp[] = {
263 #error unsupported arch
271 #define T_save 0x00000800
277 static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2);
278 static void (*sh2_drc_dispatcher)(void);
279 static void (*sh2_drc_exit)(void);
280 static void (*sh2_drc_test_irq)(void);
282 static u32 REGPARM(2) (*sh2_drc_read8)(u32 a, SH2 *sh2);
283 static u32 REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2);
284 static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2);
285 static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
286 static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
287 static int REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
289 // address space stuff
290 static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
294 if ((a & ~0x7ff) == 0) {
296 poffs = offsetof(SH2, p_bios);
299 else if ((a & 0xfffff000) == 0xc0000000) {
301 poffs = offsetof(SH2, p_da);
304 else if ((a & 0xc6000000) == 0x06000000) {
306 poffs = offsetof(SH2, p_sdram);
309 else if ((a & 0xc6000000) == 0x02000000) {
311 poffs = offsetof(SH2, p_rom);
318 static struct block_entry *dr_get_entry(u32 pc, int is_slave, int *tcache_id)
320 struct block_entry *be;
323 // data arrays have their own caches
324 if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0)
329 mask = hash_table_sizes[tcid] - 1;
330 be = HASH_FUNC(hash_tables[tcid], pc, mask);
331 for (; be != NULL; be = be->next)
338 // ---------------------------------------------------------------
341 static void add_to_block_list(struct block_list **blist, struct block_desc *block)
343 struct block_list *added = malloc(sizeof(*added));
345 elprintf(EL_ANOMALY, "drc OOM (1)");
348 added->block = block;
349 added->next = *blist;
353 static void rm_from_block_list(struct block_list **blist, struct block_desc *block)
355 struct block_list *prev = NULL, *current = *blist;
356 for (; current != NULL; prev = current, current = current->next) {
357 if (current->block == block) {
359 *blist = current->next;
361 prev->next = current->next;
366 dbg(1, "can't rm block %p (%08x-%08x)",
367 block, block->addr, block->end_addr);
370 static void rm_block_list(struct block_list **blist)
372 struct block_list *tmp, *current = *blist;
373 while (current != NULL) {
375 current = current->next;
381 static void REGPARM(1) flush_tcache(int tcid)
385 dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid,
386 tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid],
387 block_counts[tcid], block_max_counts[tcid]);
389 block_counts[tcid] = 0;
390 block_link_pool_counts[tcid] = 0;
391 unresolved_links[tcid] = NULL;
392 memset(hash_tables[tcid], 0, sizeof(*hash_tables[0]) * hash_table_sizes[tcid]);
393 tcache_ptrs[tcid] = tcache_bases[tcid];
394 if (Pico32xMem != NULL) {
395 if (tcid == 0) // ROM, RAM
396 memset(Pico32xMem->drcblk_ram, 0,
397 sizeof(Pico32xMem->drcblk_ram));
399 memset(Pico32xMem->drcblk_da[tcid - 1], 0,
400 sizeof(Pico32xMem->drcblk_da[0]));
403 tcache_dsm_ptrs[tcid] = tcache_bases[tcid];
406 for (i = 0; i < ram_sizes[tcid] / ADDR_TO_BLOCK_PAGE; i++)
407 rm_block_list(&inval_lookup[tcid][i]);
410 static void add_to_hashlist(struct block_entry *be, int tcache_id)
412 u32 tcmask = hash_table_sizes[tcache_id] - 1;
414 be->next = HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask);
415 HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask) = be;
418 if (be->next != NULL) {
419 printf(" %08x: hash collision with %08x\n",
420 be->pc, be->next->pc);
426 static void rm_from_hashlist(struct block_entry *be, int tcache_id)
428 u32 tcmask = hash_table_sizes[tcache_id] - 1;
429 struct block_entry *cur, *prev;
431 cur = HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask);
435 if (be == cur) { // first
436 HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask) = be->next;
440 for (prev = cur, cur = cur->next; cur != NULL; cur = cur->next) {
442 prev->next = cur->next;
448 dbg(1, "rm_from_hashlist: be %p %08x missing?", be, be->pc);
451 static struct block_desc *dr_add_block(u32 addr, u32 end_addr, int is_slave, int *blk_id)
453 struct block_entry *be;
454 struct block_desc *bd;
458 // do a lookup to get tcache_id and override check
459 be = dr_get_entry(addr, is_slave, &tcache_id);
461 dbg(1, "block override for %08x", addr);
463 bcount = &block_counts[tcache_id];
464 if (*bcount >= block_max_counts[tcache_id]) {
465 dbg(1, "bd overflow for tcache %d", tcache_id);
469 bd = &block_tables[tcache_id][*bcount];
471 bd->end_addr = end_addr;
474 bd->entryp[0].pc = addr;
475 bd->entryp[0].tcache_ptr = tcache_ptr;
476 bd->entryp[0].links = NULL;
478 bd->entryp[0].block = bd;
481 add_to_hashlist(&bd->entryp[0], tcache_id);
489 static void REGPARM(3) *dr_lookup_block(u32 pc, int is_slave, int *tcache_id)
491 struct block_entry *be = NULL;
494 be = dr_get_entry(pc, is_slave, tcache_id);
496 block = be->tcache_ptr;
500 be->block->refcount++;
505 static void *dr_failure(void)
507 lprintf("recompilation failed\n");
511 static void *dr_prepare_ext_branch(u32 pc, int is_slave, int tcache_id)
514 struct block_link *bl = block_link_pool[tcache_id];
515 int cnt = block_link_pool_counts[tcache_id];
516 struct block_entry *be = NULL;
517 int target_tcache_id;
520 be = dr_get_entry(pc, is_slave, &target_tcache_id);
521 if (target_tcache_id != tcache_id)
522 return sh2_drc_dispatcher;
524 // if pool has been freed, reuse
525 for (i = cnt - 1; i >= 0; i--)
526 if (bl[i].target_pc != 0)
529 if (cnt >= block_link_pool_max_counts[tcache_id]) {
530 dbg(1, "bl overflow for tcache %d\n", tcache_id);
534 block_link_pool_counts[tcache_id]++;
537 bl->jump = tcache_ptr;
540 dbg(2, "- early link from %p to pc %08x", bl->jump, pc);
541 bl->next = be->links;
543 return be->tcache_ptr;
546 bl->next = unresolved_links[tcache_id];
547 unresolved_links[tcache_id] = bl;
548 return sh2_drc_dispatcher;
551 return sh2_drc_dispatcher;
555 static void dr_link_blocks(struct block_entry *be, int tcache_id)
558 struct block_link *first = unresolved_links[tcache_id];
559 struct block_link *bl, *prev, *tmp;
562 for (bl = prev = first; bl != NULL; ) {
563 if (bl->target_pc == pc) {
564 dbg(2, "- link from %p to pc %08x", bl->jump, pc);
565 emith_jump_patch(bl->jump, tcache_ptr);
567 // move bl from unresolved_links to block_entry
569 bl->next = be->links;
573 first = prev = bl = tmp;
575 prev->next = bl = tmp;
581 unresolved_links[tcache_id] = first;
583 // could sync arm caches here, but that's unnecessary
587 #define ADD_TO_ARRAY(array, count, item, failcode) \
588 array[count++] = item; \
589 if (count >= ARRAY_SIZE(array)) { \
590 dbg(1, "warning: " #array " overflow"); \
594 static int find_in_array(u32 *array, size_t size, u32 what)
597 for (i = 0; i < size; i++)
598 if (what == array[i])
604 // ---------------------------------------------------------------
606 // register cache / constant propagation stuff
613 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking);
615 // guest regs with constants
616 static u32 dr_gcregs[24];
617 // a mask of constant/dirty regs
618 static u32 dr_gcregs_mask;
619 static u32 dr_gcregs_dirty;
621 #if PROPAGATE_CONSTANTS
622 static void gconst_new(sh2_reg_e r, u32 val)
626 dr_gcregs_mask |= 1 << r;
627 dr_gcregs_dirty |= 1 << r;
630 // throw away old r that we might have cached
631 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
632 if ((reg_temp[i].type == HR_CACHED) &&
633 reg_temp[i].greg == r) {
634 reg_temp[i].type = HR_FREE;
635 reg_temp[i].flags = 0;
641 static int gconst_get(sh2_reg_e r, u32 *val)
643 if (dr_gcregs_mask & (1 << r)) {
650 static int gconst_check(sh2_reg_e r)
652 if ((dr_gcregs_mask | dr_gcregs_dirty) & (1 << r))
657 // update hr if dirty, else do nothing
658 static int gconst_try_read(int hr, sh2_reg_e r)
660 if (dr_gcregs_dirty & (1 << r)) {
661 emith_move_r_imm(hr, dr_gcregs[r]);
662 dr_gcregs_dirty &= ~(1 << r);
668 static void gconst_check_evict(sh2_reg_e r)
670 if (dr_gcregs_mask & (1 << r))
671 // no longer cached in reg, make dirty again
672 dr_gcregs_dirty |= 1 << r;
675 static void gconst_kill(sh2_reg_e r)
677 dr_gcregs_mask &= ~(1 << r);
678 dr_gcregs_dirty &= ~(1 << r);
681 static void gconst_clean(void)
685 for (i = 0; i < ARRAY_SIZE(dr_gcregs); i++)
686 if (dr_gcregs_dirty & (1 << i)) {
687 // using RC_GR_READ here: it will call gconst_try_read,
688 // cache the reg and mark it dirty.
689 rcache_get_reg_(i, RC_GR_READ, 0);
693 static void gconst_invalidate(void)
695 dr_gcregs_mask = dr_gcregs_dirty = 0;
698 static u16 rcache_counter;
700 static temp_reg_t *rcache_evict(void)
702 // evict reg with oldest stamp
704 u16 min_stamp = (u16)-1;
706 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
707 if (reg_temp[i].type == HR_CACHED && !(reg_temp[i].flags & HRF_LOCKED) &&
708 reg_temp[i].stamp <= min_stamp) {
709 min_stamp = reg_temp[i].stamp;
715 printf("no registers to evict, aborting\n");
720 if (reg_temp[i].type == HR_CACHED) {
721 if (reg_temp[i].flags & HRF_DIRTY)
723 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
724 gconst_check_evict(reg_temp[i].greg);
727 reg_temp[i].type = HR_FREE;
728 reg_temp[i].flags = 0;
732 static int get_reg_static(sh2_reg_e r, rc_gr_mode mode)
734 int i = reg_map_g2h[r];
736 if (mode != RC_GR_WRITE)
737 gconst_try_read(i, r);
742 // note: must not be called when doing conditional code
743 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking)
748 // maybe statically mapped?
749 ret = get_reg_static(r, mode);
755 // maybe already cached?
756 // if so, prefer against gconst (they must be in sync)
757 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
758 if (reg_temp[i].type == HR_CACHED && reg_temp[i].greg == r) {
759 reg_temp[i].stamp = rcache_counter;
760 if (mode != RC_GR_READ)
761 reg_temp[i].flags |= HRF_DIRTY;
762 ret = reg_temp[i].hreg;
768 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
769 if (reg_temp[i].type == HR_FREE) {
778 tr->type = HR_CACHED;
780 tr->flags |= HRF_LOCKED;
781 if (mode != RC_GR_READ)
782 tr->flags |= HRF_DIRTY;
784 tr->stamp = rcache_counter;
787 if (mode != RC_GR_WRITE) {
788 if (gconst_check(r)) {
789 if (gconst_try_read(ret, r))
790 tr->flags |= HRF_DIRTY;
793 emith_ctx_read(tr->hreg, r * 4);
797 if (mode != RC_GR_READ)
803 static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode)
805 return rcache_get_reg_(r, mode, 1);
808 static int rcache_get_tmp(void)
813 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
814 if (reg_temp[i].type == HR_FREE) {
826 static int rcache_get_arg_id(int arg)
829 host_arg2reg(r, arg);
831 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
832 if (reg_temp[i].hreg == r)
835 if (i == ARRAY_SIZE(reg_temp)) // can't happen
838 if (reg_temp[i].type == HR_CACHED) {
840 if (reg_temp[i].flags & HRF_DIRTY)
841 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
842 gconst_check_evict(reg_temp[i].greg);
844 else if (reg_temp[i].type == HR_TEMP) {
845 printf("arg %d reg %d already used, aborting\n", arg, r);
849 reg_temp[i].type = HR_FREE;
850 reg_temp[i].flags = 0;
855 // get a reg to be used as function arg
856 static int rcache_get_tmp_arg(int arg)
858 int id = rcache_get_arg_id(arg);
859 reg_temp[id].type = HR_TEMP;
861 return reg_temp[id].hreg;
864 // same but caches a reg. RC_GR_READ only.
865 static int rcache_get_reg_arg(int arg, sh2_reg_e r)
867 int i, srcr, dstr, dstid;
868 int dirty = 0, src_dirty = 0;
870 dstid = rcache_get_arg_id(arg);
871 dstr = reg_temp[dstid].hreg;
873 // maybe already statically mapped?
874 srcr = get_reg_static(r, RC_GR_READ);
878 // maybe already cached?
879 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
880 if ((reg_temp[i].type == HR_CACHED) &&
881 reg_temp[i].greg == r)
883 srcr = reg_temp[i].hreg;
884 if (reg_temp[i].flags & HRF_DIRTY)
892 if (gconst_check(r)) {
893 if (gconst_try_read(srcr, r))
897 emith_ctx_read(srcr, r * 4);
901 emith_move_r_r(dstr, srcr);
907 // must clean, callers might want to modify the arg before call
908 emith_ctx_write(dstr, r * 4);
911 reg_temp[dstid].flags |= HRF_DIRTY;
914 reg_temp[dstid].stamp = ++rcache_counter;
915 reg_temp[dstid].type = HR_CACHED;
916 reg_temp[dstid].greg = r;
917 reg_temp[dstid].flags |= HRF_LOCKED;
921 static void rcache_free_tmp(int hr)
924 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
925 if (reg_temp[i].hreg == hr)
928 if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) {
929 printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type);
933 reg_temp[i].type = HR_FREE;
934 reg_temp[i].flags = 0;
937 static void rcache_unlock(int hr)
940 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
941 if (reg_temp[i].type == HR_CACHED && reg_temp[i].hreg == hr)
942 reg_temp[i].flags &= ~HRF_LOCKED;
945 static void rcache_unlock_all(void)
948 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
949 reg_temp[i].flags &= ~HRF_LOCKED;
952 static void rcache_clean(void)
957 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
958 if (reg_temp[i].type == HR_CACHED && (reg_temp[i].flags & HRF_DIRTY)) {
960 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
961 reg_temp[i].flags &= ~HRF_DIRTY;
965 static void rcache_invalidate(void)
968 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
969 reg_temp[i].type = HR_FREE;
970 reg_temp[i].flags = 0;
977 static void rcache_flush(void)
983 // ---------------------------------------------------------------
985 static int emit_get_rbase_and_offs(u32 a, u32 *offs)
991 poffs = dr_ctx_get_mem_ptr(a, &mask);
995 // XXX: could use some related reg
996 hr = rcache_get_tmp();
997 emith_ctx_read(hr, poffs);
998 emith_add_r_imm(hr, a & mask & ~0xff);
999 *offs = a & 0xff; // XXX: ARM oriented..
1003 static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
1005 #if PROPAGATE_CONSTANTS
1006 gconst_new(dst, imm);
1008 int hr = rcache_get_reg(dst, RC_GR_WRITE);
1009 emith_move_r_imm(hr, imm);
1013 static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
1015 int hr_d = rcache_get_reg(dst, RC_GR_WRITE);
1016 int hr_s = rcache_get_reg(src, RC_GR_READ);
1018 emith_move_r_r(hr_d, hr_s);
1021 // T must be clear, and comparison done just before this
1022 static void emit_or_t_if_eq(int srr)
1024 EMITH_SJMP_START(DCOND_NE);
1025 emith_or_r_imm_c(DCOND_EQ, srr, T);
1026 EMITH_SJMP_END(DCOND_NE);
1029 // arguments must be ready
1030 // reg cache must be clean before call
1031 static int emit_memhandler_read_(int size, int ram_check)
1034 host_arg2reg(arg0, 0);
1038 // must writeback cycles for poll detection stuff
1040 if (reg_map_g2h[SHR_SR] != -1)
1041 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
1043 arg1 = rcache_get_tmp_arg(1);
1044 emith_move_r_r(arg1, CONTEXT_REG);
1047 if (ram_check && Pico.rom == (void *)0x02000000 && Pico32xMem->sdram == (void *)0x06000000) {
1048 int tmp = rcache_get_tmp();
1049 emith_and_r_r_imm(tmp, arg0, 0xfb000000);
1050 emith_cmp_r_imm(tmp, 0x02000000);
1053 EMITH_SJMP3_START(DCOND_NE);
1054 emith_eor_r_imm_c(DCOND_EQ, arg0, 1);
1055 emith_read8_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1056 EMITH_SJMP3_MID(DCOND_NE);
1057 emith_call_cond(DCOND_NE, sh2_drc_read8);
1061 EMITH_SJMP3_START(DCOND_NE);
1062 emith_read16_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1063 EMITH_SJMP3_MID(DCOND_NE);
1064 emith_call_cond(DCOND_NE, sh2_drc_read16);
1068 EMITH_SJMP3_START(DCOND_NE);
1069 emith_read_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1070 emith_ror_c(DCOND_EQ, arg0, arg0, 16);
1071 EMITH_SJMP3_MID(DCOND_NE);
1072 emith_call_cond(DCOND_NE, sh2_drc_read32);
1082 emith_call(sh2_drc_read8);
1085 emith_call(sh2_drc_read16);
1088 emith_call(sh2_drc_read32);
1092 rcache_invalidate();
1094 if (reg_map_g2h[SHR_SR] != -1)
1095 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
1097 // assuming arg0 and retval reg matches
1098 return rcache_get_tmp_arg(0);
1101 static int emit_memhandler_read(int size)
1103 return emit_memhandler_read_(size, 1);
1106 static int emit_memhandler_read_rr(sh2_reg_e rd, sh2_reg_e rs, u32 offs, int size)
1108 int hr, hr2, ram_check = 1;
1111 if (gconst_get(rs, &val)) {
1112 hr = emit_get_rbase_and_offs(val + offs, &offs2);
1114 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1117 emith_read8_r_r_offs(hr2, hr, offs2 ^ 1);
1118 emith_sext(hr2, hr2, 8);
1121 emith_read16_r_r_offs(hr2, hr, offs2);
1122 emith_sext(hr2, hr2, 16);
1125 emith_read_r_r_offs(hr2, hr, offs2);
1126 emith_ror(hr2, hr2, 16);
1129 rcache_free_tmp(hr);
1136 hr = rcache_get_reg_arg(0, rs);
1138 emith_add_r_imm(hr, offs);
1139 hr = emit_memhandler_read_(size, ram_check);
1140 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1142 emith_sext(hr2, hr, (size == 1) ? 16 : 8);
1144 emith_move_r_r(hr2, hr);
1145 rcache_free_tmp(hr);
1150 static void emit_memhandler_write(int size, u32 pc)
1153 host_arg2reg(ctxr, 2);
1154 if (reg_map_g2h[SHR_SR] != -1)
1155 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
1159 // XXX: consider inlining sh2_drc_write8
1161 emith_call(sh2_drc_write8);
1165 emith_call(sh2_drc_write16);
1168 emith_move_r_r(ctxr, CONTEXT_REG);
1169 emith_call(sh2_drc_write32);
1173 rcache_invalidate();
1174 if (reg_map_g2h[SHR_SR] != -1)
1175 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
1179 static int emit_indirect_indexed_read(int rx, int ry, int size)
1182 a0 = rcache_get_reg_arg(0, rx);
1183 t = rcache_get_reg(ry, RC_GR_READ);
1184 emith_add_r_r(a0, t);
1185 return emit_memhandler_read(size);
1189 static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
1193 rcache_get_reg_arg(0, rn);
1194 tmp = emit_memhandler_read(size);
1195 emith_ctx_write(tmp, offsetof(SH2, drc_tmp));
1196 rcache_free_tmp(tmp);
1197 tmp = rcache_get_reg(rn, RC_GR_RMW);
1198 emith_add_r_imm(tmp, 1 << size);
1201 rcache_get_reg_arg(0, rm);
1202 *rmr = emit_memhandler_read(size);
1203 *rnr = rcache_get_tmp();
1204 emith_ctx_read(*rnr, offsetof(SH2, drc_tmp));
1205 tmp = rcache_get_reg(rm, RC_GR_RMW);
1206 emith_add_r_imm(tmp, 1 << size);
1210 static void emit_do_static_regs(int is_write, int tmpr)
1214 for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) {
1219 for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) {
1220 if (reg_map_g2h[i + 1] != r + 1)
1226 // i, r point to last item
1228 emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1230 emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1233 emith_ctx_write(r, i * 4);
1235 emith_ctx_read(r, i * 4);
1240 static void emit_block_entry(void)
1244 host_arg2reg(arg0, 0);
1246 #if (DRC_DEBUG & 8) || defined(PDB)
1248 host_arg2reg(arg1, 1);
1249 host_arg2reg(arg2, 2);
1251 emit_do_static_regs(1, arg2);
1252 emith_move_r_r(arg1, CONTEXT_REG);
1253 emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ));
1254 emith_call(sh2_drc_log_entry);
1255 rcache_invalidate();
1257 emith_tst_r_r(arg0, arg0);
1258 EMITH_SJMP_START(DCOND_EQ);
1259 emith_jump_reg_c(DCOND_NE, arg0);
1260 EMITH_SJMP_END(DCOND_EQ);
1263 #define DELAYED_OP \
1266 #define DELAY_SAVE_T(sr) { \
1267 emith_bic_r_imm(sr, T_save); \
1268 emith_tst_r_imm(sr, T); \
1269 EMITH_SJMP_START(DCOND_EQ); \
1270 emith_or_r_imm_c(DCOND_NE, sr, T_save); \
1271 EMITH_SJMP_END(DCOND_EQ); \
1272 drcf.use_saved_t = 1; \
1275 #define FLUSH_CYCLES(sr) \
1277 emith_sub_r_imm(sr, cycles << 12); \
1281 #define CHECK_UNHANDLED_BITS(mask) { \
1282 if ((op & (mask)) != 0) \
1289 #define GET_Rm GET_Fx
1294 #define CHECK_FX_LT(n) \
1295 if (GET_Fx() >= n) \
1298 static void *dr_get_pc_base(u32 pc, int is_slave);
1300 static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
1302 // XXX: maybe use structs instead?
1303 u32 branch_target_pc[MAX_LOCAL_BRANCHES];
1304 void *branch_target_ptr[MAX_LOCAL_BRANCHES];
1305 int branch_target_count = 0;
1306 void *branch_patch_ptr[MAX_LOCAL_BRANCHES];
1307 u32 branch_patch_pc[MAX_LOCAL_BRANCHES];
1308 int branch_patch_count = 0;
1309 u32 literal_addr[MAX_LITERALS];
1310 int literal_addr_count = 0;
1311 int pending_branch_cond = -1;
1312 int pending_branch_pc = 0;
1313 u8 op_flags[BLOCK_INSN_LIMIT];
1317 u32 use_saved_t:1; // delayed op modifies T
1320 // PC of current, first, last, last_target_blk SH2 insn
1321 u32 pc, base_pc, end_pc, out_pc;
1322 void *block_entry_ptr;
1323 struct block_desc *block;
1334 // get base/validate PC
1335 dr_pc_base = dr_get_pc_base(base_pc, sh2->is_slave);
1336 if (dr_pc_base == (void *)-1) {
1337 printf("invalid PC, aborting: %08x\n", base_pc);
1338 // FIXME: be less destructive
1342 tcache_ptr = tcache_ptrs[tcache_id];
1344 // predict tcache overflow
1345 tmp = tcache_ptr - tcache_bases[tcache_id];
1346 if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE) {
1347 dbg(1, "tcache %d overflow", tcache_id);
1351 // 1st pass: scan forward for local branches
1352 scan_block(base_pc, sh2->is_slave, op_flags, &end_pc);
1354 block = dr_add_block(base_pc, end_pc + MAX_LITERAL_OFFSET, // XXX
1355 sh2->is_slave, &blkid_main);
1359 block_entry_ptr = tcache_ptr;
1360 dbg(2, "== %csh2 block #%d,%d %08x-%08x -> %p", sh2->is_slave ? 's' : 'm',
1361 tcache_id, blkid_main, base_pc, end_pc, block_entry_ptr);
1363 dr_link_blocks(&block->entryp[0], tcache_id);
1365 // collect branch_targets that don't land on delay slots
1366 for (pc = base_pc; pc < end_pc; pc += 2) {
1367 if (!(OP_FLAGS(pc) & OF_BTARGET))
1369 if (OP_FLAGS(pc) & OF_DELAY_OP) {
1370 OP_FLAGS(pc) &= ~OF_BTARGET;
1373 ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc, break);
1376 if (branch_target_count > 0) {
1377 memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count);
1380 // -------------------------------------------------
1381 // 2nd pass: actual compilation
1384 for (cycles = 0; pc <= end_pc || drcf.delayed_op; )
1388 if (drcf.delayed_op > 0)
1393 if ((OP_FLAGS(pc) & OF_BTARGET) || pc == base_pc)
1395 i = find_in_array(branch_target_pc, branch_target_count, pc);
1400 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1402 // decide if to flush rcache
1403 if ((op & 0xf0ff) == 0x4010 && FETCH_OP(pc + 2) == 0x8bfd) // DT; BF #-2
1407 do_host_disasm(tcache_id);
1409 v = block->entry_count;
1410 if (v < ARRAY_SIZE(block->entryp)) {
1411 block->entryp[v].pc = pc;
1412 block->entryp[v].tcache_ptr = tcache_ptr;
1413 block->entryp[v].links = NULL;
1415 block->entryp[v].block = block;
1417 add_to_hashlist(&block->entryp[v], tcache_id);
1418 block->entry_count++;
1420 dbg(2, "-- %csh2 block #%d,%d entry %08x -> %p", sh2->is_slave ? 's' : 'm',
1421 tcache_id, blkid_main, pc, tcache_ptr);
1423 // since we made a block entry, link any other blocks
1424 // that jump to current pc
1425 dr_link_blocks(&block->entryp[v], tcache_id);
1428 dbg(1, "too many entryp for block #%d,%d pc=%08x",
1429 tcache_id, blkid_main, pc);
1433 branch_target_ptr[i] = tcache_ptr;
1436 emit_move_r_imm32(SHR_PC, pc);
1440 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1441 emith_cmp_r_imm(sr, 0);
1442 emith_jump_cond(DCOND_LE, sh2_drc_exit);
1443 do_host_disasm(tcache_id);
1444 rcache_unlock_all();
1451 DasmSH2(sh2dasm_buff, pc, op);
1452 printf("%c%08x %04x %s\n", (OP_FLAGS(pc) & OF_BTARGET) ? '*' : ' ',
1453 pc, op, sh2dasm_buff);
1456 //if (out_pc != 0 && out_pc != (u32)-1)
1457 // emit_move_r_imm32(SHR_PC, out_pc);
1459 if (!drcf.delayed_op) {
1460 emit_move_r_imm32(SHR_PC, pc);
1461 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1463 // rcache_clean(); // FIXME
1465 emit_do_static_regs(1, 0);
1466 emith_pass_arg_r(0, CONTEXT_REG);
1467 emith_call(do_sh2_cmp);
1479 switch ((op >> 12) & 0x0f)
1481 /////////////////////////////////////////////
1486 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1489 case 0: // STC SR,Rn 0000nnnn00000010
1492 case 1: // STC GBR,Rn 0000nnnn00010010
1495 case 2: // STC VBR,Rn 0000nnnn00100010
1501 tmp3 = rcache_get_reg(tmp2, RC_GR_READ);
1502 emith_move_r_r(tmp, tmp3);
1504 emith_clear_msb(tmp, tmp, 22); // reserved bits defined by ISA as 0
1507 CHECK_UNHANDLED_BITS(0xd0);
1508 // BRAF Rm 0000mmmm00100011
1509 // BSRF Rm 0000mmmm00000011
1511 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1512 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1513 emith_move_r_r(tmp, tmp2);
1515 emith_add_r_imm(tmp, pc + 2);
1517 tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE);
1518 emith_move_r_imm(tmp3, pc + 2);
1519 emith_add_r_r(tmp, tmp3);
1524 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
1525 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
1526 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
1528 tmp = rcache_get_reg_arg(1, GET_Rm());
1529 tmp2 = rcache_get_reg_arg(0, SHR_R0);
1530 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1531 emith_add_r_r(tmp2, tmp3);
1532 emit_memhandler_write(op & 3, pc);
1535 // MUL.L Rm,Rn 0000nnnnmmmm0111
1536 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1537 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1538 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1539 emith_mul(tmp3, tmp2, tmp);
1543 CHECK_UNHANDLED_BITS(0xf00);
1546 case 0: // CLRT 0000000000001000
1547 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1548 if (drcf.delayed_op)
1550 emith_bic_r_imm(sr, T);
1552 case 1: // SETT 0000000000011000
1553 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1554 if (drcf.delayed_op)
1556 emith_or_r_imm(sr, T);
1558 case 2: // CLRMAC 0000000000101000
1559 emit_move_r_imm32(SHR_MACL, 0);
1560 emit_move_r_imm32(SHR_MACH, 0);
1569 case 0: // NOP 0000000000001001
1570 CHECK_UNHANDLED_BITS(0xf00);
1572 case 1: // DIV0U 0000000000011001
1573 CHECK_UNHANDLED_BITS(0xf00);
1574 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1575 if (drcf.delayed_op)
1577 emith_bic_r_imm(sr, M|Q|T);
1579 case 2: // MOVT Rn 0000nnnn00101001
1580 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1581 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1582 emith_clear_msb(tmp2, sr, 31);
1589 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1592 case 0: // STS MACH,Rn 0000nnnn00001010
1595 case 1: // STS MACL,Rn 0000nnnn00011010
1598 case 2: // STS PR,Rn 0000nnnn00101010
1604 tmp2 = rcache_get_reg(tmp2, RC_GR_READ);
1605 emith_move_r_r(tmp, tmp2);
1608 CHECK_UNHANDLED_BITS(0xf00);
1611 case 0: // RTS 0000000000001011
1613 emit_move_r_r(SHR_PC, SHR_PR);
1617 case 1: // SLEEP 0000000000011011
1618 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
1619 emith_clear_msb(tmp, tmp, 20); // clear cycles
1620 out_pc = out_pc - 2;
1623 case 2: // RTE 0000000000101011
1626 emit_memhandler_read_rr(SHR_PC, SHR_SP, 0, 2);
1628 tmp = rcache_get_reg_arg(0, SHR_SP);
1629 emith_add_r_imm(tmp, 4);
1630 tmp = emit_memhandler_read(2);
1631 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1632 emith_write_sr(sr, tmp);
1633 rcache_free_tmp(tmp);
1634 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
1635 emith_add_r_imm(tmp, 4*2);
1644 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
1645 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
1646 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
1647 tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3);
1648 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1649 if ((op & 3) != 2) {
1650 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
1652 emith_move_r_r(tmp2, tmp);
1653 rcache_free_tmp(tmp);
1655 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
1656 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
1657 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
1658 /* MS 16 MAC bits unused if saturated */
1659 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1660 emith_tst_r_imm(sr, S);
1661 EMITH_SJMP_START(DCOND_EQ);
1662 emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
1663 EMITH_SJMP_END(DCOND_EQ);
1665 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
1666 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
1667 rcache_free_tmp(tmp2);
1668 sr = rcache_get_reg(SHR_SR, RC_GR_READ); // reget just in case
1669 emith_tst_r_imm(sr, S);
1671 EMITH_JMP_START(DCOND_EQ);
1672 emith_asr(tmp, tmp4, 15);
1673 emith_cmp_r_imm(tmp, -1); // negative overflow (0x80000000..0xffff7fff)
1674 EMITH_SJMP_START(DCOND_GE);
1675 emith_move_r_imm_c(DCOND_LT, tmp4, 0x8000);
1676 emith_move_r_imm_c(DCOND_LT, tmp3, 0x0000);
1677 EMITH_SJMP_END(DCOND_GE);
1678 emith_cmp_r_imm(tmp, 0); // positive overflow (0x00008000..0x7fffffff)
1679 EMITH_SJMP_START(DCOND_LE);
1680 emith_move_r_imm_c(DCOND_GT, tmp4, 0x00007fff);
1681 emith_move_r_imm_c(DCOND_GT, tmp3, 0xffffffff);
1682 EMITH_SJMP_END(DCOND_LE);
1683 EMITH_JMP_END(DCOND_EQ);
1685 rcache_free_tmp(tmp);
1691 /////////////////////////////////////////////
1693 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
1695 tmp = rcache_get_reg_arg(0, GET_Rn());
1696 tmp2 = rcache_get_reg_arg(1, GET_Rm());
1698 emith_add_r_imm(tmp, (op & 0x0f) * 4);
1699 emit_memhandler_write(2, pc);
1705 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
1706 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
1707 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
1709 rcache_get_reg_arg(0, GET_Rn());
1710 rcache_get_reg_arg(1, GET_Rm());
1711 emit_memhandler_write(op & 3, pc);
1713 case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100
1714 case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101
1715 case 0x06: // MOV.L Rm,@–Rn 0010nnnnmmmm0110
1716 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1717 emith_sub_r_imm(tmp, (1 << (op & 3)));
1719 rcache_get_reg_arg(0, GET_Rn());
1720 rcache_get_reg_arg(1, GET_Rm());
1721 emit_memhandler_write(op & 3, pc);
1723 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
1724 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1725 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1726 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1727 if (drcf.delayed_op)
1729 emith_bic_r_imm(sr, M|Q|T);
1730 emith_tst_r_imm(tmp2, (1<<31));
1731 EMITH_SJMP_START(DCOND_EQ);
1732 emith_or_r_imm_c(DCOND_NE, sr, Q);
1733 EMITH_SJMP_END(DCOND_EQ);
1734 emith_tst_r_imm(tmp3, (1<<31));
1735 EMITH_SJMP_START(DCOND_EQ);
1736 emith_or_r_imm_c(DCOND_NE, sr, M);
1737 EMITH_SJMP_END(DCOND_EQ);
1738 emith_teq_r_r(tmp2, tmp3);
1739 EMITH_SJMP_START(DCOND_PL);
1740 emith_or_r_imm_c(DCOND_MI, sr, T);
1741 EMITH_SJMP_END(DCOND_PL);
1743 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
1744 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1745 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1746 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1747 if (drcf.delayed_op)
1749 emith_bic_r_imm(sr, T);
1750 emith_tst_r_r(tmp2, tmp3);
1751 emit_or_t_if_eq(sr);
1753 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
1754 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1755 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1756 emith_and_r_r(tmp, tmp2);
1758 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
1759 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1760 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1761 emith_eor_r_r(tmp, tmp2);
1763 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
1764 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1765 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1766 emith_or_r_r(tmp, tmp2);
1768 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
1769 tmp = rcache_get_tmp();
1770 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1771 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1772 emith_eor_r_r_r(tmp, tmp2, tmp3);
1773 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1774 if (drcf.delayed_op)
1776 emith_bic_r_imm(sr, T);
1777 emith_tst_r_imm(tmp, 0x000000ff);
1778 emit_or_t_if_eq(tmp);
1779 emith_tst_r_imm(tmp, 0x0000ff00);
1780 emit_or_t_if_eq(tmp);
1781 emith_tst_r_imm(tmp, 0x00ff0000);
1782 emit_or_t_if_eq(tmp);
1783 emith_tst_r_imm(tmp, 0xff000000);
1784 emit_or_t_if_eq(tmp);
1785 rcache_free_tmp(tmp);
1787 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
1788 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1789 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1790 emith_lsr(tmp, tmp, 16);
1791 emith_or_r_r_lsl(tmp, tmp2, 16);
1793 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
1794 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
1795 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1796 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1798 emith_sext(tmp, tmp2, 16);
1800 emith_clear_msb(tmp, tmp2, 16);
1801 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1802 tmp2 = rcache_get_tmp();
1804 emith_sext(tmp2, tmp3, 16);
1806 emith_clear_msb(tmp2, tmp3, 16);
1807 emith_mul(tmp, tmp, tmp2);
1808 rcache_free_tmp(tmp2);
1813 /////////////////////////////////////////////
1817 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
1818 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
1819 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
1820 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
1821 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
1822 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1823 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1824 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1825 if (drcf.delayed_op)
1827 emith_bic_r_imm(sr, T);
1828 emith_cmp_r_r(tmp2, tmp3);
1831 case 0x00: // CMP/EQ
1832 emit_or_t_if_eq(sr);
1834 case 0x02: // CMP/HS
1835 EMITH_SJMP_START(DCOND_LO);
1836 emith_or_r_imm_c(DCOND_HS, sr, T);
1837 EMITH_SJMP_END(DCOND_LO);
1839 case 0x03: // CMP/GE
1840 EMITH_SJMP_START(DCOND_LT);
1841 emith_or_r_imm_c(DCOND_GE, sr, T);
1842 EMITH_SJMP_END(DCOND_LT);
1844 case 0x06: // CMP/HI
1845 EMITH_SJMP_START(DCOND_LS);
1846 emith_or_r_imm_c(DCOND_HI, sr, T);
1847 EMITH_SJMP_END(DCOND_LS);
1849 case 0x07: // CMP/GT
1850 EMITH_SJMP_START(DCOND_LE);
1851 emith_or_r_imm_c(DCOND_GT, sr, T);
1852 EMITH_SJMP_END(DCOND_LE);
1856 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
1857 // Q1 = carry(Rn = (Rn << 1) | T)
1859 // Q2 = carry(Rn += Rm)
1861 // Q2 = carry(Rn -= Rm)
1863 // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2)
1864 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1865 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1866 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1867 if (drcf.delayed_op)
1869 emith_tpop_carry(sr, 0);
1870 emith_adcf_r_r(tmp2, tmp2);
1871 emith_tpush_carry(sr, 0); // keep Q1 in T for now
1872 tmp4 = rcache_get_tmp();
1873 emith_and_r_r_imm(tmp4, sr, M);
1874 emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M
1875 rcache_free_tmp(tmp4);
1876 // add or sub, invert T if carry to get Q1 ^ Q2
1877 // in: (Q ^ M) passed in Q, Q1 in T
1878 emith_sh2_div1_step(tmp2, tmp3, sr);
1879 emith_bic_r_imm(sr, Q);
1880 emith_tst_r_imm(sr, M);
1881 EMITH_SJMP_START(DCOND_EQ);
1882 emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
1883 EMITH_SJMP_END(DCOND_EQ);
1884 emith_tst_r_imm(sr, T);
1885 EMITH_SJMP_START(DCOND_EQ);
1886 emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
1887 EMITH_SJMP_END(DCOND_EQ);
1888 emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
1890 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
1891 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1892 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1893 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1894 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1895 emith_mul_u64(tmp3, tmp4, tmp, tmp2);
1898 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
1899 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
1900 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1901 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1903 emith_add_r_r(tmp, tmp2);
1905 emith_sub_r_r(tmp, tmp2);
1907 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
1908 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
1909 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1910 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1911 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1912 if (drcf.delayed_op)
1914 if (op & 4) { // adc
1915 emith_tpop_carry(sr, 0);
1916 emith_adcf_r_r(tmp, tmp2);
1917 emith_tpush_carry(sr, 0);
1919 emith_tpop_carry(sr, 1);
1920 emith_sbcf_r_r(tmp, tmp2);
1921 emith_tpush_carry(sr, 1);
1924 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
1925 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
1926 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1927 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1928 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1929 if (drcf.delayed_op)
1931 emith_bic_r_imm(sr, T);
1933 emith_addf_r_r(tmp, tmp2);
1935 emith_subf_r_r(tmp, tmp2);
1936 EMITH_SJMP_START(DCOND_VC);
1937 emith_or_r_imm_c(DCOND_VS, sr, T);
1938 EMITH_SJMP_END(DCOND_VC);
1940 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
1941 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1942 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1943 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1944 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1945 emith_mul_s64(tmp3, tmp4, tmp, tmp2);
1951 /////////////////////////////////////////////
1958 case 0: // SHLL Rn 0100nnnn00000000
1959 case 2: // SHAL Rn 0100nnnn00100000
1960 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1961 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1962 if (drcf.delayed_op)
1964 emith_tpop_carry(sr, 0); // dummy
1965 emith_lslf(tmp, tmp, 1);
1966 emith_tpush_carry(sr, 0);
1968 case 1: // DT Rn 0100nnnn00010000
1969 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1970 if (drcf.delayed_op)
1973 if (FETCH_OP(pc) == 0x8bfd) { // BF #-2
1974 if (gconst_get(GET_Rn(), &tmp)) {
1975 // XXX: limit burned cycles
1976 emit_move_r_imm32(GET_Rn(), 0);
1977 emith_or_r_imm(sr, T);
1978 cycles += tmp * 4 + 1; // +1 syncs with noconst version, not sure why
1982 emith_sh2_dtbf_loop();
1986 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1987 emith_bic_r_imm(sr, T);
1988 emith_subf_r_imm(tmp, 1);
1989 emit_or_t_if_eq(sr);
1996 case 0: // SHLR Rn 0100nnnn00000001
1997 case 2: // SHAR Rn 0100nnnn00100001
1998 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1999 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2000 if (drcf.delayed_op)
2002 emith_tpop_carry(sr, 0); // dummy
2004 emith_asrf(tmp, tmp, 1);
2006 emith_lsrf(tmp, tmp, 1);
2007 emith_tpush_carry(sr, 0);
2009 case 1: // CMP/PZ Rn 0100nnnn00010001
2010 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2011 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2012 if (drcf.delayed_op)
2014 emith_bic_r_imm(sr, T);
2015 emith_cmp_r_imm(tmp, 0);
2016 EMITH_SJMP_START(DCOND_LT);
2017 emith_or_r_imm_c(DCOND_GE, sr, T);
2018 EMITH_SJMP_END(DCOND_LT);
2026 case 0x02: // STS.L MACH,@–Rn 0100nnnn00000010
2029 case 0x12: // STS.L MACL,@–Rn 0100nnnn00010010
2032 case 0x22: // STS.L PR,@–Rn 0100nnnn00100010
2035 case 0x03: // STC.L SR,@–Rn 0100nnnn00000011
2039 case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011
2043 case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011
2050 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2051 emith_sub_r_imm(tmp2, 4);
2053 rcache_get_reg_arg(0, GET_Rn());
2054 tmp3 = rcache_get_reg_arg(1, tmp);
2056 emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0
2057 emit_memhandler_write(2, pc);
2063 case 0x04: // ROTL Rn 0100nnnn00000100
2064 case 0x05: // ROTR Rn 0100nnnn00000101
2065 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2066 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2067 if (drcf.delayed_op)
2069 emith_tpop_carry(sr, 0); // dummy
2071 emith_rorf(tmp, tmp, 1);
2073 emith_rolf(tmp, tmp, 1);
2074 emith_tpush_carry(sr, 0);
2076 case 0x24: // ROTCL Rn 0100nnnn00100100
2077 case 0x25: // ROTCR Rn 0100nnnn00100101
2078 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2079 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2080 if (drcf.delayed_op)
2082 emith_tpop_carry(sr, 0);
2087 emith_tpush_carry(sr, 0);
2089 case 0x15: // CMP/PL Rn 0100nnnn00010101
2090 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2091 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2092 if (drcf.delayed_op)
2094 emith_bic_r_imm(sr, T);
2095 emith_cmp_r_imm(tmp, 0);
2096 EMITH_SJMP_START(DCOND_LE);
2097 emith_or_r_imm_c(DCOND_GT, sr, T);
2098 EMITH_SJMP_END(DCOND_LE);
2106 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
2109 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
2112 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
2115 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
2119 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
2123 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
2130 rcache_get_reg_arg(0, GET_Rn());
2131 tmp2 = emit_memhandler_read(2);
2132 if (tmp == SHR_SR) {
2133 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2134 if (drcf.delayed_op)
2136 emith_write_sr(sr, tmp2);
2139 tmp = rcache_get_reg(tmp, RC_GR_WRITE);
2140 emith_move_r_r(tmp, tmp2);
2142 rcache_free_tmp(tmp2);
2143 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2144 emith_add_r_imm(tmp, 4);
2151 // SHLL2 Rn 0100nnnn00001000
2152 // SHLR2 Rn 0100nnnn00001001
2156 // SHLL8 Rn 0100nnnn00011000
2157 // SHLR8 Rn 0100nnnn00011001
2161 // SHLL16 Rn 0100nnnn00101000
2162 // SHLR16 Rn 0100nnnn00101001
2168 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2170 emith_lsr(tmp2, tmp2, tmp);
2172 emith_lsl(tmp2, tmp2, tmp);
2177 case 0: // LDS Rm,MACH 0100mmmm00001010
2180 case 1: // LDS Rm,MACL 0100mmmm00011010
2183 case 2: // LDS Rm,PR 0100mmmm00101010
2189 emit_move_r_r(tmp2, GET_Rn());
2194 case 0: // JSR @Rm 0100mmmm00001011
2195 case 2: // JMP @Rm 0100mmmm00101011
2198 emit_move_r_imm32(SHR_PR, pc + 2);
2199 emit_move_r_r(SHR_PC, (op >> 8) & 0x0f);
2203 case 1: // TAS.B @Rn 0100nnnn00011011
2204 // XXX: is TAS working on 32X?
2205 rcache_get_reg_arg(0, GET_Rn());
2206 tmp = emit_memhandler_read(0);
2207 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2208 if (drcf.delayed_op)
2210 emith_bic_r_imm(sr, T);
2211 emith_cmp_r_imm(tmp, 0);
2212 emit_or_t_if_eq(sr);
2214 emith_or_r_imm(tmp, 0x80);
2215 tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp
2216 emith_move_r_r(tmp2, tmp);
2217 rcache_free_tmp(tmp);
2218 rcache_get_reg_arg(0, GET_Rn());
2219 emit_memhandler_write(0, pc);
2226 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2229 case 0: // LDC Rm,SR 0100mmmm00001110
2232 case 1: // LDC Rm,GBR 0100mmmm00011110
2235 case 2: // LDC Rm,VBR 0100mmmm00101110
2241 if (tmp2 == SHR_SR) {
2242 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2243 if (drcf.delayed_op)
2245 emith_write_sr(sr, tmp);
2248 tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE);
2249 emith_move_r_r(tmp2, tmp);
2253 // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
2254 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1);
2255 emith_sext(tmp, tmp, 16);
2256 emith_sext(tmp2, tmp2, 16);
2257 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
2258 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
2259 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
2260 rcache_free_tmp(tmp2);
2261 // XXX: MACH should be untouched when S is set?
2262 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2263 emith_tst_r_imm(sr, S);
2264 EMITH_JMP_START(DCOND_EQ);
2266 emith_asr(tmp, tmp3, 31);
2267 emith_eorf_r_r(tmp, tmp4); // tmp = ((signed)macl >> 31) ^ mach
2268 EMITH_JMP_START(DCOND_EQ);
2269 emith_move_r_imm(tmp3, 0x80000000);
2270 emith_tst_r_r(tmp4, tmp4);
2271 EMITH_SJMP_START(DCOND_MI);
2272 emith_sub_r_imm_c(DCOND_PL, tmp3, 1); // positive
2273 EMITH_SJMP_END(DCOND_MI);
2274 EMITH_JMP_END(DCOND_EQ);
2276 EMITH_JMP_END(DCOND_EQ);
2277 rcache_free_tmp(tmp);
2283 /////////////////////////////////////////////
2285 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
2286 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), (op & 0x0f) * 4, 2);
2289 /////////////////////////////////////////////
2293 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
2294 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
2295 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
2296 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
2297 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
2298 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
2299 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), 0, op & 3);
2300 if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) {
2301 tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW);
2302 emith_add_r_imm(tmp, (1 << (op & 3)));
2307 tmp = rcache_get_reg(GET_Rm(), RC_GR_READ);
2308 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2311 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
2312 emith_move_r_r(tmp2, tmp);
2314 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
2315 emith_mvn_r_r(tmp2, tmp);
2317 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
2320 tmp3 = rcache_get_tmp();
2321 tmp4 = rcache_get_tmp();
2322 emith_lsr(tmp3, tmp, 16);
2323 emith_or_r_r_lsl(tmp3, tmp, 24);
2324 emith_and_r_r_imm(tmp4, tmp, 0xff00);
2325 emith_or_r_r_lsl(tmp3, tmp4, 8);
2326 emith_rol(tmp2, tmp3, 16);
2327 rcache_free_tmp(tmp4);
2329 rcache_free_tmp(tmp3);
2331 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
2332 emith_rol(tmp2, tmp, 16);
2334 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
2335 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2336 if (drcf.delayed_op)
2338 emith_tpop_carry(sr, 1);
2339 emith_negcf_r_r(tmp2, tmp);
2340 emith_tpush_carry(sr, 1);
2342 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
2343 emith_neg_r_r(tmp2, tmp);
2345 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
2346 emith_clear_msb(tmp2, tmp, 24);
2348 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
2349 emith_clear_msb(tmp2, tmp, 16);
2351 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
2352 emith_sext(tmp2, tmp, 8);
2354 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
2355 emith_sext(tmp2, tmp, 16);
2362 /////////////////////////////////////////////
2364 // ADD #imm,Rn 0111nnnniiiiiiii
2365 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2366 if (op & 0x80) { // adding negative
2367 emith_sub_r_imm(tmp, -op & 0xff);
2369 emith_add_r_imm(tmp, op & 0xff);
2372 /////////////////////////////////////////////
2374 switch (op & 0x0f00)
2376 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
2377 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
2379 tmp = rcache_get_reg_arg(0, GET_Rm());
2380 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2381 tmp3 = (op & 0x100) >> 8;
2383 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
2384 emit_memhandler_write(tmp3, pc);
2386 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
2387 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
2388 tmp = (op & 0x100) >> 8;
2389 emit_memhandler_read_rr(SHR_R0, GET_Rm(), (op & 0x0f) << tmp, tmp);
2391 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
2392 // XXX: could use cmn
2393 tmp = rcache_get_tmp();
2394 tmp2 = rcache_get_reg(0, RC_GR_READ);
2395 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2396 if (drcf.delayed_op)
2398 emith_move_r_imm_s8(tmp, op & 0xff);
2399 emith_bic_r_imm(sr, T);
2400 emith_cmp_r_r(tmp2, tmp);
2401 emit_or_t_if_eq(sr);
2402 rcache_free_tmp(tmp);
2404 case 0x0d00: // BT/S label 10001101dddddddd
2405 case 0x0f00: // BF/S label 10001111dddddddd
2408 case 0x0900: // BT label 10001001dddddddd
2409 case 0x0b00: // BF label 10001011dddddddd
2410 // will handle conditional branches later
2411 pending_branch_cond = (op & 0x0200) ? DCOND_EQ : DCOND_NE;
2412 i = ((signed int)(op << 24) >> 23);
2413 pending_branch_pc = pc + i + 2;
2418 /////////////////////////////////////////////
2420 // MOV.W @(disp,PC),Rn 1001nnnndddddddd
2421 tmp = pc + (op & 0xff) * 2 + 2;
2422 #if PROPAGATE_CONSTANTS
2423 if (tmp < end_pc + MAX_LITERAL_OFFSET && literal_addr_count < MAX_LITERALS) {
2424 ADD_TO_ARRAY(literal_addr, literal_addr_count, tmp,);
2425 gconst_new(GET_Rn(), (u32)(int)(signed short)FETCH_OP(tmp));
2430 tmp2 = rcache_get_tmp_arg(0);
2431 emith_move_r_imm(tmp2, tmp);
2432 tmp2 = emit_memhandler_read(1);
2433 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2434 emith_sext(tmp3, tmp2, 16);
2435 rcache_free_tmp(tmp2);
2439 /////////////////////////////////////////////
2441 // BRA label 1010dddddddddddd
2443 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2444 tmp = ((signed int)(op << 20) >> 19);
2445 out_pc = pc + tmp + 2;
2447 emith_clear_msb(sr, sr, 20); // burn cycles
2451 /////////////////////////////////////////////
2453 // BSR label 1011dddddddddddd
2455 emit_move_r_imm32(SHR_PR, pc + 2);
2456 tmp = ((signed int)(op << 20) >> 19);
2457 out_pc = pc + tmp + 2;
2461 /////////////////////////////////////////////
2463 switch (op & 0x0f00)
2465 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
2466 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
2467 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
2469 tmp = rcache_get_reg_arg(0, SHR_GBR);
2470 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2471 tmp3 = (op & 0x300) >> 8;
2472 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
2473 emit_memhandler_write(tmp3, pc);
2475 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
2476 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
2477 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
2478 tmp = (op & 0x300) >> 8;
2479 emit_memhandler_read_rr(SHR_R0, SHR_GBR, (op & 0xff) << tmp, tmp);
2481 case 0x0300: // TRAPA #imm 11000011iiiiiiii
2482 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2483 emith_sub_r_imm(tmp, 4*2);
2485 tmp = rcache_get_reg_arg(0, SHR_SP);
2486 emith_add_r_imm(tmp, 4);
2487 tmp = rcache_get_reg_arg(1, SHR_SR);
2488 emith_clear_msb(tmp, tmp, 22);
2489 emit_memhandler_write(2, pc);
2491 rcache_get_reg_arg(0, SHR_SP);
2492 tmp = rcache_get_tmp_arg(1);
2493 emith_move_r_imm(tmp, pc);
2494 emit_memhandler_write(2, pc);
2496 emit_memhandler_read_rr(SHR_PC, SHR_VBR, (op & 0xff) * 4, 2);
2500 case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd
2501 emit_move_r_imm32(SHR_R0, (pc + (op & 0xff) * 4 + 2) & ~3);
2503 case 0x0800: // TST #imm,R0 11001000iiiiiiii
2504 tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
2505 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2506 if (drcf.delayed_op)
2508 emith_bic_r_imm(sr, T);
2509 emith_tst_r_imm(tmp, op & 0xff);
2510 emit_or_t_if_eq(sr);
2512 case 0x0900: // AND #imm,R0 11001001iiiiiiii
2513 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2514 emith_and_r_imm(tmp, op & 0xff);
2516 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
2517 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2518 emith_eor_r_imm(tmp, op & 0xff);
2520 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
2521 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2522 emith_or_r_imm(tmp, op & 0xff);
2524 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
2525 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2526 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2527 if (drcf.delayed_op)
2529 emith_bic_r_imm(sr, T);
2530 emith_tst_r_imm(tmp, op & 0xff);
2531 emit_or_t_if_eq(sr);
2532 rcache_free_tmp(tmp);
2535 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
2536 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2537 emith_and_r_imm(tmp, op & 0xff);
2539 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
2540 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2541 emith_eor_r_imm(tmp, op & 0xff);
2543 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
2544 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2545 emith_or_r_imm(tmp, op & 0xff);
2547 tmp2 = rcache_get_tmp_arg(1);
2548 emith_move_r_r(tmp2, tmp);
2549 rcache_free_tmp(tmp);
2550 tmp3 = rcache_get_reg_arg(0, SHR_GBR);
2551 tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ);
2552 emith_add_r_r(tmp3, tmp4);
2553 emit_memhandler_write(0, pc);
2558 /////////////////////////////////////////////
2560 // MOV.L @(disp,PC),Rn 1101nnnndddddddd
2561 tmp = (pc + (op & 0xff) * 4 + 2) & ~3;
2562 #if PROPAGATE_CONSTANTS
2563 if (tmp < end_pc + MAX_LITERAL_OFFSET && literal_addr_count < MAX_LITERALS) {
2564 ADD_TO_ARRAY(literal_addr, literal_addr_count, tmp,);
2565 gconst_new(GET_Rn(), FETCH32(tmp));
2570 tmp2 = rcache_get_tmp_arg(0);
2571 emith_move_r_imm(tmp2, tmp);
2572 tmp2 = emit_memhandler_read(2);
2573 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2574 emith_move_r_r(tmp3, tmp2);
2575 rcache_free_tmp(tmp2);
2579 /////////////////////////////////////////////
2581 // MOV #imm,Rn 1110nnnniiiiiiii
2582 emit_move_r_imm32(GET_Rn(), (u32)(signed int)(signed char)op);
2587 elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
2588 sh2->is_slave ? 's' : 'm', op, pc - 2);
2593 rcache_unlock_all();
2595 // conditional branch handling (with/without delay)
2596 if (pending_branch_cond != -1 && drcf.delayed_op != 2)
2598 u32 target_pc = pending_branch_pc;
2599 int ctaken = drcf.delayed_op ? 1 : 2;
2602 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2604 if (drcf.use_saved_t)
2605 emith_tst_r_imm(sr, T_save);
2607 emith_tst_r_imm(sr, T);
2610 emith_sub_r_imm_c(pending_branch_cond, sr, ctaken<<12);
2614 if (find_in_array(branch_target_pc, branch_target_count, target_pc) >= 0) {
2616 // XXX: jumps back can be linked already
2617 branch_patch_pc[branch_patch_count] = target_pc;
2618 branch_patch_ptr[branch_patch_count] = tcache_ptr;
2619 emith_jump_cond_patchable(pending_branch_cond, tcache_ptr);
2621 branch_patch_count++;
2622 if (branch_patch_count == MAX_LOCAL_BRANCHES) {
2623 dbg(1, "warning: too many local branches");
2630 // can't resolve branch locally, make a block exit
2631 emit_move_r_imm32(SHR_PC, target_pc);
2634 target = dr_prepare_ext_branch(target_pc, sh2->is_slave, tcache_id);
2637 emith_jump_cond_patchable(pending_branch_cond, target);
2640 drcf.use_saved_t = 0;
2641 pending_branch_cond = -1;
2645 // XXX: delay slots..
2646 if (drcf.test_irq && drcf.delayed_op != 2) {
2647 if (!drcf.delayed_op)
2648 emit_move_r_imm32(SHR_PC, pc);
2649 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2652 emith_call(sh2_drc_test_irq);
2656 do_host_disasm(tcache_id);
2658 if (out_pc != 0 && drcf.delayed_op != 2)
2662 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
2666 if (out_pc == (u32)-1) {
2667 // indirect jump -> back to dispatcher
2668 emith_jump(sh2_drc_dispatcher);
2673 emit_move_r_imm32(SHR_PC, out_pc);
2676 target = dr_prepare_ext_branch(out_pc, sh2->is_slave, tcache_id);
2679 emith_jump_patchable(target);
2682 // link local branches
2683 for (i = 0; i < branch_patch_count; i++) {
2686 t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]);
2687 target = branch_target_ptr[t];
2688 if (target == NULL) {
2689 // flush pc and go back to dispatcher (this should no longer happen)
2690 dbg(1, "stray branch to %08x %p", branch_patch_pc[i], tcache_ptr);
2691 target = tcache_ptr;
2692 emit_move_r_imm32(SHR_PC, branch_patch_pc[i]);
2694 emith_jump(sh2_drc_dispatcher);
2696 emith_jump_patch(branch_patch_ptr[i], target);
2701 // mark memory blocks as containing compiled code
2702 // override any overlay blocks as they become unreachable anyway
2703 if (tcache_id != 0 || (block->addr & 0xc7fc0000) == 0x06000000)
2705 u16 *drc_ram_blk = NULL;
2706 u32 addr, mask = 0, shift = 0;
2708 if (tcache_id != 0) {
2710 drc_ram_blk = Pico32xMem->drcblk_da[sh2->is_slave];
2711 shift = SH2_DRCBLK_DA_SHIFT;
2714 else if ((block->addr & 0xc7fc0000) == 0x06000000) {
2716 drc_ram_blk = Pico32xMem->drcblk_ram;
2717 shift = SH2_DRCBLK_RAM_SHIFT;
2721 // mark recompiled insns
2722 drc_ram_blk[(base_pc & mask) >> shift] = 1;
2723 for (pc = base_pc; pc < end_pc; pc += 2)
2724 drc_ram_blk[(pc & mask) >> shift] = 1;
2727 for (i = 0; i < literal_addr_count; i++) {
2728 tmp = literal_addr[i];
2729 drc_ram_blk[(tmp & mask) >> shift] = 1;
2732 // add to invalidation lookup lists
2733 addr = base_pc & ~(ADDR_TO_BLOCK_PAGE - 1);
2734 for (; addr < end_pc + MAX_LITERAL_OFFSET; addr += ADDR_TO_BLOCK_PAGE) {
2735 i = (addr & mask) / ADDR_TO_BLOCK_PAGE;
2736 add_to_block_list(&inval_lookup[tcache_id][i], block);
2740 tcache_ptrs[tcache_id] = tcache_ptr;
2742 host_instructions_updated(block_entry_ptr, tcache_ptr);
2744 do_host_disasm(tcache_id);
2745 dbg(2, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
2746 tcache_id, blkid_main,
2747 tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
2748 insns_compiled, host_insn_count, (float)host_insn_count / insns_compiled);
2749 if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
2750 dbg(2, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
2753 tcache_dsm_ptrs[tcache_id] = block_entry_ptr;
2754 do_host_disasm(tcache_id);
2762 return block_entry_ptr;
2765 static void sh2_generate_utils(void)
2767 int arg0, arg1, arg2, sr, tmp;
2769 sh2_drc_write32 = p32x_sh2_write32;
2770 sh2_drc_read8 = p32x_sh2_read8;
2771 sh2_drc_read16 = p32x_sh2_read16;
2772 sh2_drc_read32 = p32x_sh2_read32;
2774 host_arg2reg(arg0, 0);
2775 host_arg2reg(arg1, 1);
2776 host_arg2reg(arg2, 2);
2777 emith_move_r_r(arg0, arg0); // nop
2779 // sh2_drc_exit(void)
2780 sh2_drc_exit = (void *)tcache_ptr;
2781 emit_do_static_regs(1, arg2);
2782 emith_sh2_drc_exit();
2784 // sh2_drc_dispatcher(void)
2785 sh2_drc_dispatcher = (void *)tcache_ptr;
2786 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2787 emith_cmp_r_imm(sr, 0);
2788 emith_jump_cond(DCOND_LT, sh2_drc_exit);
2789 rcache_invalidate();
2790 emith_ctx_read(arg0, SHR_PC * 4);
2791 emith_ctx_read(arg1, offsetof(SH2, is_slave));
2792 emith_add_r_r_imm(arg2, CONTEXT_REG, offsetof(SH2, drc_tmp));
2793 emith_call(dr_lookup_block);
2795 // lookup failed, call sh2_translate()
2796 emith_move_r_r(arg0, CONTEXT_REG);
2797 emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id
2798 emith_call(sh2_translate);
2800 // sh2_translate() failed, flush cache and retry
2801 emith_ctx_read(arg0, offsetof(SH2, drc_tmp));
2802 emith_call(flush_tcache);
2803 emith_move_r_r(arg0, CONTEXT_REG);
2804 emith_ctx_read(arg1, offsetof(SH2, drc_tmp));
2805 emith_call(sh2_translate);
2807 // XXX: can't translate, fail
2808 emith_call(dr_failure);
2810 // sh2_drc_test_irq(void)
2811 // assumes it's called from main function (may jump to dispatcher)
2812 sh2_drc_test_irq = (void *)tcache_ptr;
2813 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2814 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2815 emith_lsr(arg0, sr, I_SHIFT);
2816 emith_and_r_imm(arg0, 0x0f);
2817 emith_cmp_r_r(arg1, arg0); // pending_level > ((sr >> 4) & 0x0f)?
2818 EMITH_SJMP_START(DCOND_GT);
2819 emith_ret_c(DCOND_LE); // nope, return
2820 EMITH_SJMP_END(DCOND_GT);
2822 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2823 emith_sub_r_imm(tmp, 4*2);
2826 tmp = rcache_get_reg_arg(0, SHR_SP);
2827 emith_add_r_imm(tmp, 4);
2828 tmp = rcache_get_reg_arg(1, SHR_SR);
2829 emith_clear_msb(tmp, tmp, 22);
2830 emith_move_r_r(arg2, CONTEXT_REG);
2831 emith_call(p32x_sh2_write32); // XXX: use sh2_drc_write32?
2832 rcache_invalidate();
2834 rcache_get_reg_arg(0, SHR_SP);
2835 emith_ctx_read(arg1, SHR_PC * 4);
2836 emith_move_r_r(arg2, CONTEXT_REG);
2837 emith_call(p32x_sh2_write32);
2838 rcache_invalidate();
2839 // update I, cycles, do callback
2840 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2841 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2842 emith_bic_r_imm(sr, I);
2843 emith_or_r_r_lsl(sr, arg1, I_SHIFT);
2844 emith_sub_r_imm(sr, 13 << 12); // at least 13 cycles
2846 emith_move_r_r(arg0, CONTEXT_REG);
2847 emith_call_ctx(offsetof(SH2, irq_callback)); // vector = sh2->irq_callback(sh2, level);
2849 emith_lsl(arg0, arg0, 2);
2850 emith_ctx_read(arg1, SHR_VBR * 4);
2851 emith_add_r_r(arg0, arg1);
2852 emit_memhandler_read(2);
2853 emith_ctx_write(arg0, SHR_PC * 4);
2855 emith_add_r_imm(xSP, 4); // fix stack
2857 emith_jump(sh2_drc_dispatcher);
2858 rcache_invalidate();
2860 // sh2_drc_entry(SH2 *sh2)
2861 sh2_drc_entry = (void *)tcache_ptr;
2862 emith_sh2_drc_entry();
2863 emith_move_r_r(CONTEXT_REG, arg0); // move ctx, arg0
2864 emit_do_static_regs(0, arg2);
2865 emith_call(sh2_drc_test_irq);
2866 emith_jump(sh2_drc_dispatcher);
2868 // sh2_drc_write8(u32 a, u32 d)
2869 sh2_drc_write8 = (void *)tcache_ptr;
2870 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2871 emith_sh2_wcall(arg0, arg2);
2873 // sh2_drc_write16(u32 a, u32 d)
2874 sh2_drc_write16 = (void *)tcache_ptr;
2875 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2876 emith_sh2_wcall(arg0, arg2);
2880 #define MAKE_READ_WRAPPER(func) { \
2881 void *tmp = (void *)tcache_ptr; \
2884 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
2885 emith_addf_r_r(arg2, arg0); \
2886 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
2887 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
2888 emith_adc_r_imm(arg2, 0x01000000); \
2889 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
2890 emith_pop_and_ret(); \
2893 #define MAKE_WRITE_WRAPPER(func) { \
2894 void *tmp = (void *)tcache_ptr; \
2895 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
2896 emith_addf_r_r(arg2, arg1); \
2897 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
2898 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
2899 emith_adc_r_imm(arg2, 0x01000000); \
2900 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
2901 emith_move_r_r(arg2, CONTEXT_REG); \
2906 MAKE_READ_WRAPPER(sh2_drc_read8);
2907 MAKE_READ_WRAPPER(sh2_drc_read16);
2908 MAKE_READ_WRAPPER(sh2_drc_read32);
2909 MAKE_WRITE_WRAPPER(sh2_drc_write8);
2910 MAKE_WRITE_WRAPPER(sh2_drc_write16);
2911 MAKE_WRITE_WRAPPER(sh2_drc_write32);
2913 host_dasm_new_symbol(sh2_drc_read8);
2914 host_dasm_new_symbol(sh2_drc_read16);
2915 host_dasm_new_symbol(sh2_drc_read32);
2916 host_dasm_new_symbol(sh2_drc_write32);
2920 rcache_invalidate();
2922 host_dasm_new_symbol(sh2_drc_entry);
2923 host_dasm_new_symbol(sh2_drc_dispatcher);
2924 host_dasm_new_symbol(sh2_drc_exit);
2925 host_dasm_new_symbol(sh2_drc_test_irq);
2926 host_dasm_new_symbol(sh2_drc_write8);
2927 host_dasm_new_symbol(sh2_drc_write16);
2931 static void sh2_smc_rm_block_entry(struct block_desc *bd, int tcache_id, u32 ram_mask)
2933 struct block_link *bl, *bl_next, *bl_unresolved;
2937 dbg(2, " killing entry %08x-%08x, blkid %d,%d",
2938 bd->addr, bd->end_addr, tcache_id, bd - block_tables[tcache_id]);
2939 if (bd->addr == 0 || bd->entry_count == 0) {
2940 dbg(1, " killing dead block!? %08x", bd->addr);
2944 // remove from inval_lookup
2945 addr = bd->addr & ~(ADDR_TO_BLOCK_PAGE - 1);
2946 for (; addr < bd->end_addr; addr += ADDR_TO_BLOCK_PAGE) {
2947 i = (addr & ram_mask) / ADDR_TO_BLOCK_PAGE;
2948 rm_from_block_list(&inval_lookup[tcache_id][i], bd);
2952 bl_unresolved = unresolved_links[tcache_id];
2954 // remove from hash table, make incoming links unresolved
2955 // XXX: maybe patch branches w/flush instead?
2956 for (i = 0; i < bd->entry_count; i++) {
2957 rm_from_hashlist(&bd->entryp[i], tcache_id);
2959 // since we never reuse tcache space of dead blocks,
2960 // insert jump to dispatcher for blocks that are linked to this
2961 tcache_ptr = bd->entryp[i].tcache_ptr;
2962 emit_move_r_imm32(SHR_PC, bd->addr);
2964 emith_jump(sh2_drc_dispatcher);
2966 host_instructions_updated(bd->entryp[i].tcache_ptr, tcache_ptr);
2968 for (bl = bd->entryp[i].links; bl != NULL; ) {
2970 bl->next = bl_unresolved;
2977 unresolved_links[tcache_id] = bl_unresolved;
2979 bd->addr = bd->end_addr = 0;
2980 bd->entry_count = 0;
2983 static void sh2_smc_rm_block(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, u32 mask)
2985 struct block_list **blist = NULL, *entry;
2986 u32 from = ~0, to = 0;
2987 struct block_desc *block;
2989 blist = &inval_lookup[tcache_id][(a & mask) / ADDR_TO_BLOCK_PAGE];
2991 while (entry != NULL) {
2992 block = entry->block;
2993 if (block->addr <= a && a < block->end_addr) {
2994 if (block->addr < from)
2996 if (block->end_addr > to)
2997 to = block->end_addr;
2999 sh2_smc_rm_block_entry(block, tcache_id, mask);
3001 // entry lost, restart search
3005 entry = entry->next;
3008 // clear entry points
3010 u16 *p = drc_ram_blk + ((from & mask) >> shift);
3011 memset(p, 0, (to - from) >> (shift - 1));
3015 void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
3017 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
3018 sh2_smc_rm_block(a, Pico32xMem->drcblk_ram, 0, SH2_DRCBLK_RAM_SHIFT, 0x3ffff);
3021 void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
3023 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
3024 sh2_smc_rm_block(a, Pico32xMem->drcblk_da[cpuid],
3025 1 + cpuid, SH2_DRCBLK_DA_SHIFT, 0xfff);
3028 int sh2_execute(SH2 *sh2c, int cycles)
3032 sh2c->cycles_timeslice = cycles;
3034 // cycles are kept in SHR_SR unused bits (upper 20)
3035 // bit11 contains T saved for delay slot
3036 // others are usual SH2 flags
3038 sh2c->sr |= cycles << 12;
3039 sh2_drc_entry(sh2c);
3042 ret_cycles = (signed int)sh2c->sr >> 12;
3044 dbg(1, "warning: drc returned with cycles: %d", ret_cycles);
3046 return sh2c->cycles_timeslice - ret_cycles;
3050 void block_stats(void)
3052 int c, b, i, total = 0;
3054 printf("block stats:\n");
3055 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
3056 for (i = 0; i < block_counts[b]; i++)
3057 if (block_tables[b][i].addr != 0)
3058 total += block_tables[b][i].refcount;
3060 for (c = 0; c < 10; c++) {
3061 struct block_desc *blk, *maxb = NULL;
3063 for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
3064 for (i = 0; i < block_counts[b]; i++) {
3065 blk = &block_tables[b][i];
3066 if (blk->addr != 0 && blk->refcount > max) {
3067 max = blk->refcount;
3074 printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount,
3075 (double)maxb->refcount / total * 100.0);
3079 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
3080 for (i = 0; i < block_counts[b]; i++)
3081 block_tables[b][i].refcount = 0;
3084 #define block_stats()
3087 void sh2_drc_flush_all(void)
3095 void sh2_drc_mem_setup(SH2 *sh2)
3097 // fill the convenience pointers
3098 sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
3099 sh2->p_da = Pico32xMem->data_array[sh2->is_slave];
3100 sh2->p_sdram = Pico32xMem->sdram;
3101 sh2->p_rom = Pico.rom;
3104 int sh2_drc_init(SH2 *sh2)
3108 if (block_tables[0] == NULL)
3110 for (i = 0; i < TCACHE_BUFFERS; i++) {
3111 block_tables[i] = calloc(block_max_counts[i], sizeof(*block_tables[0]));
3112 if (block_tables[i] == NULL)
3114 // max 2 block links (exits) per block
3115 block_link_pool[i] = calloc(block_link_pool_max_counts[i],
3116 sizeof(*block_link_pool[0]));
3117 if (block_link_pool[i] == NULL)
3120 inval_lookup[i] = calloc(ram_sizes[i] / ADDR_TO_BLOCK_PAGE,
3121 sizeof(inval_lookup[0]));
3122 if (inval_lookup[i] == NULL)
3125 hash_tables[i] = calloc(hash_table_sizes[i], sizeof(*hash_tables[0]));
3126 if (hash_tables[i] == NULL)
3129 memset(block_counts, 0, sizeof(block_counts));
3130 memset(block_link_pool_counts, 0, sizeof(block_link_pool_counts));
3133 tcache_ptr = tcache;
3134 sh2_generate_utils();
3135 host_instructions_updated(tcache, tcache_ptr);
3137 tcache_bases[0] = tcache_ptrs[0] = tcache_ptr;
3138 for (i = 1; i < ARRAY_SIZE(tcache_bases); i++)
3139 tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1];
3142 PicoOpt |= POPT_DIS_VDP_FIFO;
3145 for (i = 0; i < ARRAY_SIZE(block_tables); i++)
3146 tcache_dsm_ptrs[i] = tcache_bases[i];
3148 tcache_dsm_ptrs[0] = tcache;
3152 hash_collisions = 0;
3159 sh2_drc_finish(sh2);
3163 void sh2_drc_finish(SH2 *sh2)
3167 if (block_tables[0] == NULL)
3170 sh2_drc_flush_all();
3172 for (i = 0; i < TCACHE_BUFFERS; i++) {
3174 printf("~~~ tcache %d\n", i);
3175 tcache_dsm_ptrs[i] = tcache_bases[i];
3176 tcache_ptr = tcache_ptrs[i];
3180 if (block_tables[i] != NULL)
3181 free(block_tables[i]);
3182 block_tables[i] = NULL;
3183 if (block_link_pool[i] == NULL)
3184 free(block_link_pool[i]);
3185 block_link_pool[i] = NULL;
3187 if (inval_lookup[i] == NULL)
3188 free(inval_lookup[i]);
3189 inval_lookup[i] = NULL;
3191 if (hash_tables[i] != NULL) {
3192 free(hash_tables[i]);
3193 hash_tables[i] = NULL;
3200 #endif /* DRC_SH2 */
3202 static void *dr_get_pc_base(u32 pc, int is_slave)
3207 if ((pc & ~0x7ff) == 0) {
3209 ret = is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
3212 else if ((pc & 0xfffff000) == 0xc0000000) {
3214 ret = Pico32xMem->data_array[is_slave];
3217 else if ((pc & 0xc6000000) == 0x06000000) {
3219 ret = Pico32xMem->sdram;
3222 else if ((pc & 0xc6000000) == 0x02000000) {
3229 return (void *)-1; // NULL is valid value
3231 return (char *)ret - (pc & ~mask);
3234 void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc)
3240 memset(op_flags, 0, BLOCK_INSN_LIMIT);
3242 dr_pc_base = dr_get_pc_base(base_pc, is_slave);
3244 for (cycles = 0, pc = base_pc; cycles < BLOCK_INSN_LIMIT-1; cycles++, pc += 2) {
3246 if ((op & 0xf000) == 0xa000 || (op & 0xf000) == 0xb000) { // BRA, BSR
3247 signed int offs = ((signed int)(op << 20) >> 19);
3249 OP_FLAGS(pc) |= OF_DELAY_OP;
3250 target = pc + offs + 2;
3251 if (base_pc <= target && target < base_pc + BLOCK_INSN_LIMIT * 2)
3252 OP_FLAGS(target) |= OF_BTARGET;
3255 if ((op & 0xf000) == 0) {
3257 if (op == 0x1b) // SLEEP
3259 // BRAF, BSRF, RTS, RTE
3260 if (op == 0x23 || op == 0x03 || op == 0x0b || op == 0x2b) {
3262 OP_FLAGS(pc) |= OF_DELAY_OP;
3267 if ((op & 0xf0df) == 0x400b) { // JMP, JSR
3269 OP_FLAGS(pc) |= OF_DELAY_OP;
3272 if ((op & 0xf900) == 0x8900) { // BT(S), BF(S)
3273 signed int offs = ((signed int)(op << 24) >> 23);
3275 OP_FLAGS(pc + 2) |= OF_DELAY_OP;
3276 target = pc + offs + 4;
3277 if (base_pc <= target && target < base_pc + BLOCK_INSN_LIMIT * 2)
3278 OP_FLAGS(target) |= OF_BTARGET;
3280 if ((op & 0xff00) == 0xc300) // TRAPA
3286 // vim:shiftwidth=2:ts=2:expandtab