deps/lightrec/disassembler.h

   1 /* SPDX-License-Identifier: LGPL-2.1-or-later */
   2 /*
   3  * Copyright (C) 2014-2021 Paul Cercueil <paul@crapouillou.net>
   4  */
   5
   6 #ifndef __DISASSEMBLER_H__
   7 #define __DISASSEMBLER_H__
   8
   9 #include "debug.h"
  10 #include "lightrec.h"
  11 #include "lightrec-config.h"
  12
  13 #ifndef __packed
  14 #define __packed __attribute__((packed))
  15 #endif
  16
  17 #define BIT(x) (1ULL << (x))
  18
  19 /* Flags for all opcodes */
  20 #define LIGHTREC_NO_DS          BIT(0)
  21 #define LIGHTREC_SYNC           BIT(1)
  22
  23 /* Flags for load/store opcodes */
  24 #define LIGHTREC_SMC            BIT(2)
  25 #define LIGHTREC_NO_INVALIDATE  BIT(3)
  26 #define LIGHTREC_NO_MASK        BIT(4)
  27
  28 /* I/O mode for load/store opcodes */
  29 #define LIGHTREC_IO_MODE_LSB    5
  30 #define LIGHTREC_IO_MODE(x)     ((x) << LIGHTREC_IO_MODE_LSB)
  31 #define LIGHTREC_IO_UNKNOWN     0x0
  32 #define LIGHTREC_IO_DIRECT      0x1
  33 #define LIGHTREC_IO_HW          0x2
  34 #define LIGHTREC_IO_RAM         0x3
  35 #define LIGHTREC_IO_BIOS        0x4
  36 #define LIGHTREC_IO_SCRATCH     0x5
  37 #define LIGHTREC_IO_DIRECT_HW   0x6
  38 #define LIGHTREC_IO_MASK        LIGHTREC_IO_MODE(0x7)
  39 #define LIGHTREC_FLAGS_GET_IO_MODE(x) \
  40         (((x) & LIGHTREC_IO_MASK) >> LIGHTREC_IO_MODE_LSB)
  41
  42 /* Flags for branches */
  43 #define LIGHTREC_EMULATE_BRANCH BIT(2)
  44 #define LIGHTREC_LOCAL_BRANCH   BIT(3)
  45
  46 /* Flags for div/mult opcodes */
  47 #define LIGHTREC_NO_LO          BIT(2)
  48 #define LIGHTREC_NO_HI          BIT(3)
  49 #define LIGHTREC_NO_DIV_CHECK   BIT(4)
  50
  51 #define LIGHTREC_REG_RS_LSB     26
  52 #define LIGHTREC_REG_RS(x)      ((x) << LIGHTREC_REG_RS_LSB)
  53 #define LIGHTREC_REG_RS_MASK    LIGHTREC_REG_RS(0x3)
  54 #define LIGHTREC_FLAGS_GET_RS(x) \
  55         (((x) & LIGHTREC_REG_RS_MASK) >> LIGHTREC_REG_RS_LSB)
  56
  57 #define LIGHTREC_REG_RT_LSB     28
  58 #define LIGHTREC_REG_RT(x)      ((x) << LIGHTREC_REG_RT_LSB)
  59 #define LIGHTREC_REG_RT_MASK    LIGHTREC_REG_RT(0x3)
  60 #define LIGHTREC_FLAGS_GET_RT(x) \
  61         (((x) & LIGHTREC_REG_RT_MASK) >> LIGHTREC_REG_RT_LSB)
  62
  63 #define LIGHTREC_REG_RD_LSB     30
  64 #define LIGHTREC_REG_RD(x)      ((x) << LIGHTREC_REG_RD_LSB)
  65 #define LIGHTREC_REG_RD_MASK    LIGHTREC_REG_RD(0x3)
  66 #define LIGHTREC_FLAGS_GET_RD(x) \
  67         (((x) & LIGHTREC_REG_RD_MASK) >> LIGHTREC_REG_RD_LSB)
  68
  69 #define LIGHTREC_REG_NOOP       0x0
  70 #define LIGHTREC_REG_UNLOAD     0x1
  71 #define LIGHTREC_REG_DISCARD    0x2
  72 #define LIGHTREC_REG_CLEAN      0x3
  73
  74 struct block;
  75
  76 enum standard_opcodes {
  77         OP_SPECIAL              = 0x00,
  78         OP_REGIMM               = 0x01,
  79         OP_J                    = 0x02,
  80         OP_JAL                  = 0x03,
  81         OP_BEQ                  = 0x04,
  82         OP_BNE                  = 0x05,
  83         OP_BLEZ                 = 0x06,
  84         OP_BGTZ                 = 0x07,
  85         OP_ADDI                 = 0x08,
  86         OP_ADDIU                = 0x09,
  87         OP_SLTI                 = 0x0a,
  88         OP_SLTIU                = 0x0b,
  89         OP_ANDI                 = 0x0c,
  90         OP_ORI                  = 0x0d,
  91         OP_XORI                 = 0x0e,
  92         OP_LUI                  = 0x0f,
  93         OP_CP0                  = 0x10,
  94         OP_CP2                  = 0x12,
  95         OP_LB                   = 0x20,
  96         OP_LH                   = 0x21,
  97         OP_LWL                  = 0x22,
  98         OP_LW                   = 0x23,
  99         OP_LBU                  = 0x24,
 100         OP_LHU                  = 0x25,
 101         OP_LWR                  = 0x26,
 102         OP_SB                   = 0x28,
 103         OP_SH                   = 0x29,
 104         OP_SWL                  = 0x2a,
 105         OP_SW                   = 0x2b,
 106         OP_SWR                  = 0x2e,
 107         OP_LWC2                 = 0x32,
 108         OP_SWC2                 = 0x3a,
 109
 110         OP_META_MOV             = 0x16,
 111
 112         OP_META_EXTC            = 0x17,
 113         OP_META_EXTS            = 0x18,
 114
 115         OP_META_MULT2           = 0x19,
 116         OP_META_MULTU2          = 0x1a,
 117 };
 118
 119 enum special_opcodes {
 120         OP_SPECIAL_SLL          = 0x00,
 121         OP_SPECIAL_SRL          = 0x02,
 122         OP_SPECIAL_SRA          = 0x03,
 123         OP_SPECIAL_SLLV         = 0x04,
 124         OP_SPECIAL_SRLV         = 0x06,
 125         OP_SPECIAL_SRAV         = 0x07,
 126         OP_SPECIAL_JR           = 0x08,
 127         OP_SPECIAL_JALR         = 0x09,
 128         OP_SPECIAL_SYSCALL      = 0x0c,
 129         OP_SPECIAL_BREAK        = 0x0d,
 130         OP_SPECIAL_MFHI         = 0x10,
 131         OP_SPECIAL_MTHI         = 0x11,
 132         OP_SPECIAL_MFLO         = 0x12,
 133         OP_SPECIAL_MTLO         = 0x13,
 134         OP_SPECIAL_MULT         = 0x18,
 135         OP_SPECIAL_MULTU        = 0x19,
 136         OP_SPECIAL_DIV          = 0x1a,
 137         OP_SPECIAL_DIVU         = 0x1b,
 138         OP_SPECIAL_ADD          = 0x20,
 139         OP_SPECIAL_ADDU         = 0x21,
 140         OP_SPECIAL_SUB          = 0x22,
 141         OP_SPECIAL_SUBU         = 0x23,
 142         OP_SPECIAL_AND          = 0x24,
 143         OP_SPECIAL_OR           = 0x25,
 144         OP_SPECIAL_XOR          = 0x26,
 145         OP_SPECIAL_NOR          = 0x27,
 146         OP_SPECIAL_SLT          = 0x2a,
 147         OP_SPECIAL_SLTU         = 0x2b,
 148 };
 149
 150 enum regimm_opcodes {
 151         OP_REGIMM_BLTZ          = 0x00,
 152         OP_REGIMM_BGEZ          = 0x01,
 153         OP_REGIMM_BLTZAL        = 0x10,
 154         OP_REGIMM_BGEZAL        = 0x11,
 155 };
 156
 157 enum cp0_opcodes {
 158         OP_CP0_MFC0             = 0x00,
 159         OP_CP0_CFC0             = 0x02,
 160         OP_CP0_MTC0             = 0x04,
 161         OP_CP0_CTC0             = 0x06,
 162         OP_CP0_RFE              = 0x10,
 163 };
 164
 165 enum cp2_opcodes {
 166         OP_CP2_BASIC            = 0x00,
 167         OP_CP2_RTPS             = 0x01,
 168         OP_CP2_NCLIP            = 0x06,
 169         OP_CP2_OP               = 0x0c,
 170         OP_CP2_DPCS             = 0x10,
 171         OP_CP2_INTPL            = 0x11,
 172         OP_CP2_MVMVA            = 0x12,
 173         OP_CP2_NCDS             = 0x13,
 174         OP_CP2_CDP              = 0x14,
 175         OP_CP2_NCDT             = 0x16,
 176         OP_CP2_NCCS             = 0x1b,
 177         OP_CP2_CC               = 0x1c,
 178         OP_CP2_NCS              = 0x1e,
 179         OP_CP2_NCT              = 0x20,
 180         OP_CP2_SQR              = 0x28,
 181         OP_CP2_DCPL             = 0x29,
 182         OP_CP2_DPCT             = 0x2a,
 183         OP_CP2_AVSZ3            = 0x2d,
 184         OP_CP2_AVSZ4            = 0x2e,
 185         OP_CP2_RTPT             = 0x30,
 186         OP_CP2_GPF              = 0x3d,
 187         OP_CP2_GPL              = 0x3e,
 188         OP_CP2_NCCT             = 0x3f,
 189 };
 190
 191 enum cp2_basic_opcodes {
 192         OP_CP2_BASIC_MFC2       = 0x00,
 193         OP_CP2_BASIC_CFC2       = 0x02,
 194         OP_CP2_BASIC_MTC2       = 0x04,
 195         OP_CP2_BASIC_CTC2       = 0x06,
 196 };
 197
 198 struct opcode_r {
 199 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 200         u32 zero :6;
 201         u32 rs   :5;
 202         u32 rt   :5;
 203         u32 rd   :5;
 204         u32 imm  :5;
 205         u32 op   :6;
 206 #else
 207         u32 op   :6;
 208         u32 imm  :5;
 209         u32 rd   :5;
 210         u32 rt   :5;
 211         u32 rs   :5;
 212         u32 zero :6;
 213 #endif
 214 } __packed;
 215
 216 struct opcode_i {
 217 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 218         u32 op  :6;
 219         u32 rs  :5;
 220         u32 rt  :5;
 221         u32 imm :16;
 222 #else
 223         u32 imm :16;
 224         u32 rt  :5;
 225         u32 rs  :5;
 226         u32 op  :6;
 227 #endif
 228 } __packed;
 229
 230 struct opcode_j {
 231 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 232         u32 op  :6;
 233         u32 imm :26;
 234 #else
 235         u32 imm :26;
 236         u32 op  :6;
 237 #endif
 238 } __packed;
 239
 240 union code {
 241         /* Keep in sync with struct opcode */
 242         u32 opcode;
 243         struct opcode_r r;
 244         struct opcode_i i;
 245         struct opcode_j j;
 246 };
 247
 248 struct opcode {
 249         /* Keep this union at the first position */
 250         union {
 251                 union code c;
 252
 253                 /* Keep in sync with union code */
 254                 u32 opcode;
 255                 struct opcode_r r;
 256                 struct opcode_i i;
 257                 struct opcode_j j;
 258         };
 259         u32 flags;
 260 };
 261
 262 struct opcode_list {
 263         u16 nb_ops;
 264         struct opcode ops[];
 265 };
 266
 267 void lightrec_print_disassembly(const struct block *block, const u32 *code);
 268
 269 static inline _Bool op_flag_no_ds(u32 flags)
 270 {
 271         return OPT_SWITCH_DELAY_SLOTS && (flags & LIGHTREC_NO_DS);
 272 }
 273
 274 static inline _Bool op_flag_sync(u32 flags)
 275 {
 276         return OPT_LOCAL_BRANCHES && (flags & LIGHTREC_SYNC);
 277 }
 278
 279 static inline _Bool op_flag_smc(u32 flags)
 280 {
 281         return OPT_FLAG_STORES && (flags & LIGHTREC_SMC);
 282 }
 283
 284 static inline _Bool op_flag_no_invalidate(u32 flags)
 285 {
 286         return (OPT_FLAG_IO || OPT_FLAG_STORES) &&
 287                 (flags & LIGHTREC_NO_INVALIDATE);
 288 }
 289
 290 static inline _Bool op_flag_no_mask(u32 flags)
 291 {
 292         return OPT_FLAG_IO && (flags & LIGHTREC_NO_MASK);
 293 }
 294
 295 static inline _Bool op_flag_emulate_branch(u32 flags)
 296 {
 297         return OPT_DETECT_IMPOSSIBLE_BRANCHES &&
 298                 (flags & LIGHTREC_EMULATE_BRANCH);
 299 }
 300
 301 static inline _Bool op_flag_local_branch(u32 flags)
 302 {
 303         return OPT_LOCAL_BRANCHES && (flags & LIGHTREC_LOCAL_BRANCH);
 304 }
 305
 306 static inline _Bool op_flag_no_lo(u32 flags)
 307 {
 308         return OPT_FLAG_MULT_DIV && (flags & LIGHTREC_NO_LO);
 309 }
 310
 311 static inline _Bool op_flag_no_hi(u32 flags)
 312 {
 313         return OPT_FLAG_MULT_DIV && (flags & LIGHTREC_NO_HI);
 314 }
 315
 316 static inline _Bool op_flag_no_div_check(u32 flags)
 317 {
 318         return OPT_FLAG_MULT_DIV && (flags & LIGHTREC_NO_DIV_CHECK);
 319 }
 320
 321 #endif /* __DISASSEMBLER_H__ */