deps/lightrec/interpreter.c

   1 // SPDX-License-Identifier: LGPL-2.1-or-later
   2 /*
   3  * Copyright (C) 2019-2021 Paul Cercueil <paul@crapouillou.net>
   4  */
   5
   6 #include "disassembler.h"
   7 #include "interpreter.h"
   8 #include "lightrec-private.h"
   9 #include "optimizer.h"
  10 #include "regcache.h"
  11
  12 #include <stdbool.h>
  13
  14 struct interpreter;
  15
  16 static u32 int_CP0(struct interpreter *inter);
  17 static u32 int_CP2(struct interpreter *inter);
  18 static u32 int_SPECIAL(struct interpreter *inter);
  19 static u32 int_REGIMM(struct interpreter *inter);
  20 static u32 int_branch(struct interpreter *inter, u32 pc,
  21                       union code code, bool branch);
  22
  23 typedef u32 (*lightrec_int_func_t)(struct interpreter *inter);
  24
  25 static const lightrec_int_func_t int_standard[64];
  26
  27 struct interpreter {
  28         struct lightrec_state *state;
  29         struct block *block;
  30         struct opcode *op;
  31         u32 cycles;
  32         bool delay_slot;
  33         u16 offset;
  34 };
  35
  36 static u32 int_get_branch_pc(const struct interpreter *inter)
  37 {
  38         return get_branch_pc(inter->block, inter->offset, 0);
  39 }
  40
  41 static inline u32 int_get_ds_pc(const struct interpreter *inter, s16 imm)
  42 {
  43         return get_ds_pc(inter->block, inter->offset, imm);
  44 }
  45
  46 static inline struct opcode *next_op(const struct interpreter *inter)
  47 {
  48         return &inter->block->opcode_list[inter->offset + 1];
  49 }
  50
  51 static inline u32 execute(lightrec_int_func_t func, struct interpreter *inter)
  52 {
  53         return (*func)(inter);
  54 }
  55
  56 static inline u32 lightrec_int_op(struct interpreter *inter)
  57 {
  58         return execute(int_standard[inter->op->i.op], inter);
  59 }
  60
  61 static inline u32 jump_skip(struct interpreter *inter)
  62 {
  63         inter->op = next_op(inter);
  64         inter->offset++;
  65
  66         if (inter->op->flags & LIGHTREC_SYNC) {
  67                 inter->state->current_cycle += inter->cycles;
  68                 inter->cycles = 0;
  69         }
  70
  71         return lightrec_int_op(inter);
  72 }
  73
  74 static inline u32 jump_next(struct interpreter *inter)
  75 {
  76         inter->cycles += lightrec_cycles_of_opcode(inter->op->c);
  77
  78         if (unlikely(inter->delay_slot))
  79                 return 0;
  80
  81         return jump_skip(inter);
  82 }
  83
  84 static inline u32 jump_after_branch(struct interpreter *inter)
  85 {
  86         inter->cycles += lightrec_cycles_of_opcode(inter->op->c);
  87
  88         if (unlikely(inter->delay_slot))
  89                 return 0;
  90
  91         inter->op = next_op(inter);
  92         inter->offset++;
  93
  94         return jump_skip(inter);
  95 }
  96
  97 static void update_cycles_before_branch(struct interpreter *inter)
  98 {
  99         u32 cycles;
 100
 101         if (!inter->delay_slot) {
 102                 cycles = lightrec_cycles_of_opcode(inter->op->c);
 103
 104                 if (has_delay_slot(inter->op->c) &&
 105                     !(inter->op->flags & LIGHTREC_NO_DS))
 106                         cycles += lightrec_cycles_of_opcode(next_op(inter)->c);
 107
 108                 inter->cycles += cycles;
 109                 inter->state->current_cycle += inter->cycles;
 110                 inter->cycles = -cycles;
 111         }
 112 }
 113
 114 static bool is_branch_taken(const u32 *reg_cache, union code op)
 115 {
 116         switch (op.i.op) {
 117         case OP_SPECIAL:
 118                 return op.r.op == OP_SPECIAL_JR || op.r.op == OP_SPECIAL_JALR;
 119         case OP_J:
 120         case OP_JAL:
 121                 return true;
 122         case OP_BEQ:
 123                 return reg_cache[op.r.rs] == reg_cache[op.r.rt];
 124         case OP_BNE:
 125                 return reg_cache[op.r.rs] != reg_cache[op.r.rt];
 126         case OP_REGIMM:
 127                 switch (op.r.rt) {
 128                 case OP_REGIMM_BLTZ:
 129                 case OP_REGIMM_BLTZAL:
 130                         return (s32)reg_cache[op.r.rs] < 0;
 131                 case OP_REGIMM_BGEZ:
 132                 case OP_REGIMM_BGEZAL:
 133                         return (s32)reg_cache[op.r.rs] >= 0;
 134                 }
 135         default:
 136                 break;
 137         }
 138
 139         return false;
 140 }
 141
 142 static u32 int_delay_slot(struct interpreter *inter, u32 pc, bool branch)
 143 {
 144         struct lightrec_state *state = inter->state;
 145         u32 *reg_cache = state->regs.gpr;
 146         struct opcode new_op, *op = next_op(inter);
 147         union code op_next;
 148         struct interpreter inter2 = {
 149                 .state = state,
 150                 .cycles = inter->cycles,
 151                 .delay_slot = true,
 152                 .block = NULL,
 153         };
 154         bool run_first_op = false, dummy_ld = false, save_rs = false,
 155              load_in_ds, branch_in_ds = false, branch_at_addr = false,
 156              branch_taken;
 157         u32 old_rs, new_rs, new_rt;
 158         u32 next_pc, ds_next_pc;
 159         u32 cause, epc;
 160
 161         if (op->i.op == OP_CP0 && op->r.rs == OP_CP0_RFE) {
 162                 /* When an IRQ happens, the PSX exception handlers (when done)
 163                  * will jump back to the instruction that was executed right
 164                  * before the IRQ, unless it was a GTE opcode; in that case, it
 165                  * jumps to the instruction right after.
 166                  * Since we will never handle the IRQ right after a GTE opcode,
 167                  * but on branch boundaries, we need to adjust the return
 168                  * address so that the GTE opcode is effectively executed.
 169                  */
 170                 cause = state->regs.cp0[13];
 171                 epc = state->regs.cp0[14];
 172
 173                 if (!(cause & 0x7c) && epc == pc - 4)
 174                         pc -= 4;
 175         }
 176
 177         if (inter->delay_slot) {
 178                 /* The branch opcode was in a delay slot of another branch
 179                  * opcode. Just return the target address of the second
 180                  * branch. */
 181                 return pc;
 182         }
 183
 184         /* An opcode located in the delay slot performing a delayed read
 185          * requires special handling; we will always resort to using the
 186          * interpreter in that case.
 187          * Same goes for when we have a branch in a delay slot of another
 188          * branch. */
 189         load_in_ds = load_in_delay_slot(op->c);
 190         branch_in_ds = has_delay_slot(op->c);
 191
 192         if (branch) {
 193                 if (load_in_ds || branch_in_ds)
 194                         op_next = lightrec_read_opcode(state, pc);
 195
 196                 if (load_in_ds) {
 197                         /* Verify that the next block actually reads the
 198                          * destination register of the delay slot opcode. */
 199                         run_first_op = opcode_reads_register(op_next, op->r.rt);
 200                 }
 201
 202                 if (branch_in_ds) {
 203                         run_first_op = true;
 204                         next_pc = pc + 4;
 205                 }
 206
 207                 if (load_in_ds && run_first_op) {
 208                         next_pc = pc + 4;
 209
 210                         /* If the first opcode of the next block writes the
 211                          * regiser used as the address for the load, we need to
 212                          * reset to the old value after it has been executed,
 213                          * then restore the new value after the delay slot
 214                          * opcode has been executed. */
 215                         save_rs = opcode_reads_register(op->c, op->r.rs) &&
 216                                 opcode_writes_register(op_next, op->r.rs);
 217                         if (save_rs)
 218                                 old_rs = reg_cache[op->r.rs];
 219
 220                         /* If both the first opcode of the next block and the
 221                          * delay slot opcode write to the same register, the
 222                          * value written by the delay slot opcode is
 223                          * discarded. */
 224                         dummy_ld = opcode_writes_register(op_next, op->r.rt);
 225                 }
 226
 227                 if (!run_first_op) {
 228                         next_pc = pc;
 229                 } else if (has_delay_slot(op_next)) {
 230                         /* The first opcode of the next block is a branch, so we
 231                          * cannot execute it here, because of the load delay.
 232                          * Just check whether or not the branch would be taken,
 233                          * and save that info into the interpreter struct. */
 234                         branch_at_addr = true;
 235                         branch_taken = is_branch_taken(reg_cache, op_next);
 236                         pr_debug("Target of impossible branch is a branch, "
 237                                  "%staken.\n", branch_taken ? "" : "not ");
 238                         inter->cycles += lightrec_cycles_of_opcode(op_next);
 239                         old_rs = reg_cache[op_next.r.rs];
 240                 } else {
 241                         new_op.c = op_next;
 242                         new_op.flags = 0;
 243                         inter2.op = &new_op;
 244
 245                         /* Execute the first opcode of the next block */
 246                         lightrec_int_op(&inter2);
 247
 248                         if (save_rs) {
 249                                 new_rs = reg_cache[op->r.rs];
 250                                 reg_cache[op->r.rs] = old_rs;
 251                         }
 252
 253                         inter->cycles += lightrec_cycles_of_opcode(op_next);
 254                 }
 255         } else {
 256                 next_pc = int_get_ds_pc(inter, 2);
 257         }
 258
 259         inter2.block = inter->block;
 260         inter2.op = op;
 261         inter2.cycles = inter->cycles;
 262
 263         if (dummy_ld)
 264                 new_rt = reg_cache[op->r.rt];
 265
 266         /* Execute delay slot opcode */
 267         ds_next_pc = lightrec_int_op(&inter2);
 268
 269         if (branch_at_addr) {
 270                 if (op_next.i.op == OP_SPECIAL)
 271                         /* TODO: Handle JALR setting $ra */
 272                         ds_next_pc = old_rs;
 273                 else if (op_next.i.op == OP_J || op_next.i.op == OP_JAL)
 274                         /* TODO: Handle JAL setting $ra */
 275                         ds_next_pc = (pc & 0xf0000000) | (op_next.j.imm << 2);
 276                 else
 277                         ds_next_pc = pc + 4 + ((s16)op_next.i.imm << 2);
 278         }
 279
 280         if (branch_at_addr && !branch_taken) {
 281                 /* If the branch at the target of the branch opcode is not
 282                  * taken, we jump to its delay slot */
 283                 next_pc = pc + sizeof(u32);
 284         } else if (branch_at_addr || (!branch && branch_in_ds)) {
 285                 next_pc = ds_next_pc;
 286         }
 287
 288         if (save_rs)
 289                 reg_cache[op->r.rs] = new_rs;
 290         if (dummy_ld)
 291                 reg_cache[op->r.rt] = new_rt;
 292
 293         inter->cycles += lightrec_cycles_of_opcode(op->c);
 294
 295         if (branch_at_addr && branch_taken) {
 296                 /* If the branch at the target of the branch opcode is taken,
 297                  * we execute its delay slot here, and jump to its target
 298                  * address. */
 299                 op_next = lightrec_read_opcode(state, pc + 4);
 300
 301                 new_op.c = op_next;
 302                 new_op.flags = 0;
 303                 inter2.op = &new_op;
 304                 inter2.block = NULL;
 305
 306                 inter->cycles += lightrec_cycles_of_opcode(op_next);
 307
 308                 pr_debug("Running delay slot of branch at target of impossible "
 309                          "branch\n");
 310                 lightrec_int_op(&inter2);
 311         }
 312
 313         return next_pc;
 314 }
 315
 316 static u32 int_unimplemented(struct interpreter *inter)
 317 {
 318         pr_warn("Unimplemented opcode 0x%08x\n", inter->op->opcode);
 319
 320         return jump_next(inter);
 321 }
 322
 323 static u32 int_jump(struct interpreter *inter, bool link)
 324 {
 325         struct lightrec_state *state = inter->state;
 326         u32 old_pc = int_get_branch_pc(inter);
 327         u32 pc = (old_pc & 0xf0000000) | (inter->op->j.imm << 2);
 328
 329         if (link)
 330                 state->regs.gpr[31] = old_pc + 8;
 331
 332         if (inter->op->flags & LIGHTREC_NO_DS)
 333                 return pc;
 334
 335         return int_delay_slot(inter, pc, true);
 336 }
 337
 338 static u32 int_J(struct interpreter *inter)
 339 {
 340         return int_jump(inter, false);
 341 }
 342
 343 static u32 int_JAL(struct interpreter *inter)
 344 {
 345         return int_jump(inter, true);
 346 }
 347
 348 static u32 int_jumpr(struct interpreter *inter, u8 link_reg)
 349 {
 350         struct lightrec_state *state = inter->state;
 351         u32 old_pc, next_pc = state->regs.gpr[inter->op->r.rs];
 352
 353         if (link_reg) {
 354                 old_pc = int_get_branch_pc(inter);
 355                 state->regs.gpr[link_reg] = old_pc + 8;
 356         }
 357
 358         if (inter->op->flags & LIGHTREC_NO_DS)
 359                 return next_pc;
 360
 361         return int_delay_slot(inter, next_pc, true);
 362 }
 363
 364 static u32 int_special_JR(struct interpreter *inter)
 365 {
 366         return int_jumpr(inter, 0);
 367 }
 368
 369 static u32 int_special_JALR(struct interpreter *inter)
 370 {
 371         return int_jumpr(inter, inter->op->r.rd);
 372 }
 373
 374 static u32 int_do_branch(struct interpreter *inter, u32 old_pc, u32 next_pc)
 375 {
 376         if (!inter->delay_slot &&
 377             (inter->op->flags & LIGHTREC_LOCAL_BRANCH) &&
 378             (s16)inter->op->c.i.imm >= 0) {
 379                 next_pc = old_pc + ((1 + (s16)inter->op->c.i.imm) << 2);
 380                 next_pc = lightrec_emulate_block(inter->state, inter->block, next_pc);
 381         }
 382
 383         return next_pc;
 384 }
 385
 386 static u32 int_branch(struct interpreter *inter, u32 pc,
 387                       union code code, bool branch)
 388 {
 389         u32 next_pc = pc + 4 + ((s16)code.i.imm << 2);
 390
 391         update_cycles_before_branch(inter);
 392
 393         if (inter->op->flags & LIGHTREC_NO_DS) {
 394                 if (branch)
 395                         return int_do_branch(inter, pc, next_pc);
 396                 else
 397                         return jump_next(inter);
 398         }
 399
 400         if (!inter->delay_slot)
 401                 next_pc = int_delay_slot(inter, next_pc, branch);
 402
 403         if (branch)
 404                 return int_do_branch(inter, pc, next_pc);
 405
 406         if (inter->op->flags & LIGHTREC_EMULATE_BRANCH)
 407                 return pc + 8;
 408         else
 409                 return jump_after_branch(inter);
 410 }
 411
 412 static u32 int_beq(struct interpreter *inter, bool bne)
 413 {
 414         u32 rs, rt, old_pc = int_get_branch_pc(inter);
 415
 416         rs = inter->state->regs.gpr[inter->op->i.rs];
 417         rt = inter->state->regs.gpr[inter->op->i.rt];
 418
 419         return int_branch(inter, old_pc, inter->op->c, (rs == rt) ^ bne);
 420 }
 421
 422 static u32 int_BEQ(struct interpreter *inter)
 423 {
 424         return int_beq(inter, false);
 425 }
 426
 427 static u32 int_BNE(struct interpreter *inter)
 428 {
 429         return int_beq(inter, true);
 430 }
 431
 432 static u32 int_bgez(struct interpreter *inter, bool link, bool lt, bool regimm)
 433 {
 434         u32 old_pc = int_get_branch_pc(inter);
 435         s32 rs;
 436
 437         if (link)
 438                 inter->state->regs.gpr[31] = old_pc + 8;
 439
 440         rs = (s32)inter->state->regs.gpr[inter->op->i.rs];
 441
 442         return int_branch(inter, old_pc, inter->op->c,
 443                           ((regimm && !rs) || rs > 0) ^ lt);
 444 }
 445
 446 static u32 int_regimm_BLTZ(struct interpreter *inter)
 447 {
 448         return int_bgez(inter, false, true, true);
 449 }
 450
 451 static u32 int_regimm_BGEZ(struct interpreter *inter)
 452 {
 453         return int_bgez(inter, false, false, true);
 454 }
 455
 456 static u32 int_regimm_BLTZAL(struct interpreter *inter)
 457 {
 458         return int_bgez(inter, true, true, true);
 459 }
 460
 461 static u32 int_regimm_BGEZAL(struct interpreter *inter)
 462 {
 463         return int_bgez(inter, true, false, true);
 464 }
 465
 466 static u32 int_BLEZ(struct interpreter *inter)
 467 {
 468         return int_bgez(inter, false, true, false);
 469 }
 470
 471 static u32 int_BGTZ(struct interpreter *inter)
 472 {
 473         return int_bgez(inter, false, false, false);
 474 }
 475
 476 static u32 int_cfc(struct interpreter *inter)
 477 {
 478         struct lightrec_state *state = inter->state;
 479         const struct opcode *op = inter->op;
 480         u32 val;
 481
 482         val = lightrec_mfc(state, op->c);
 483
 484         if (likely(op->r.rt))
 485                 state->regs.gpr[op->r.rt] = val;
 486
 487         return jump_next(inter);
 488 }
 489
 490 static u32 int_ctc(struct interpreter *inter)
 491 {
 492         struct lightrec_state *state = inter->state;
 493         const struct opcode *op = inter->op;
 494
 495         lightrec_mtc(state, op->c, state->regs.gpr[op->r.rt]);
 496
 497         /* If we have a MTC0 or CTC0 to CP0 register 12 (Status) or 13 (Cause),
 498          * return early so that the emulator will be able to check software
 499          * interrupt status. */
 500         if (!(inter->op->flags & LIGHTREC_NO_DS) &&
 501             op->i.op == OP_CP0 && (op->r.rd == 12 || op->r.rd == 13))
 502                 return int_get_ds_pc(inter, 1);
 503         else
 504                 return jump_next(inter);
 505 }
 506
 507 static u32 int_cp0_RFE(struct interpreter *inter)
 508 {
 509         lightrec_rfe(inter->state);
 510
 511         return jump_next(inter);
 512 }
 513
 514 static u32 int_CP(struct interpreter *inter)
 515 {
 516         lightrec_cp(inter->state, inter->op->c);
 517
 518         return jump_next(inter);
 519 }
 520
 521 static u32 int_ADDI(struct interpreter *inter)
 522 {
 523         u32 *reg_cache = inter->state->regs.gpr;
 524         struct opcode_i *op = &inter->op->i;
 525
 526         if (likely(op->rt))
 527                 reg_cache[op->rt] = reg_cache[op->rs] + (s32)(s16)op->imm;
 528
 529         return jump_next(inter);
 530 }
 531
 532 static u32 int_SLTI(struct interpreter *inter)
 533 {
 534         u32 *reg_cache = inter->state->regs.gpr;
 535         struct opcode_i *op = &inter->op->i;
 536
 537         if (likely(op->rt))
 538                 reg_cache[op->rt] = (s32)reg_cache[op->rs] < (s32)(s16)op->imm;
 539
 540         return jump_next(inter);
 541 }
 542
 543 static u32 int_SLTIU(struct interpreter *inter)
 544 {
 545         u32 *reg_cache = inter->state->regs.gpr;
 546         struct opcode_i *op = &inter->op->i;
 547
 548         if (likely(op->rt))
 549                 reg_cache[op->rt] = reg_cache[op->rs] < (u32)(s32)(s16)op->imm;
 550
 551         return jump_next(inter);
 552 }
 553
 554 static u32 int_ANDI(struct interpreter *inter)
 555 {
 556         u32 *reg_cache = inter->state->regs.gpr;
 557         struct opcode_i *op = &inter->op->i;
 558
 559         if (likely(op->rt))
 560                 reg_cache[op->rt] = reg_cache[op->rs] & op->imm;
 561
 562         return jump_next(inter);
 563 }
 564
 565 static u32 int_ORI(struct interpreter *inter)
 566 {
 567         u32 *reg_cache = inter->state->regs.gpr;
 568         struct opcode_i *op = &inter->op->i;
 569
 570         if (likely(op->rt))
 571                 reg_cache[op->rt] = reg_cache[op->rs] | op->imm;
 572
 573         return jump_next(inter);
 574 }
 575
 576 static u32 int_XORI(struct interpreter *inter)
 577 {
 578         u32 *reg_cache = inter->state->regs.gpr;
 579         struct opcode_i *op = &inter->op->i;
 580
 581         if (likely(op->rt))
 582                 reg_cache[op->rt] = reg_cache[op->rs] ^ op->imm;
 583
 584         return jump_next(inter);
 585 }
 586
 587 static u32 int_LUI(struct interpreter *inter)
 588 {
 589         struct opcode_i *op = &inter->op->i;
 590
 591         inter->state->regs.gpr[op->rt] = op->imm << 16;
 592
 593         return jump_next(inter);
 594 }
 595
 596 static u32 int_io(struct interpreter *inter, bool is_load)
 597 {
 598         struct opcode_i *op = &inter->op->i;
 599         u32 *reg_cache = inter->state->regs.gpr;
 600         u32 val;
 601
 602         val = lightrec_rw(inter->state, inter->op->c,
 603                           reg_cache[op->rs], reg_cache[op->rt],
 604                           &inter->op->flags, inter->block);
 605
 606         if (is_load && op->rt)
 607                 reg_cache[op->rt] = val;
 608
 609         return jump_next(inter);
 610 }
 611
 612 static u32 int_load(struct interpreter *inter)
 613 {
 614         return int_io(inter, true);
 615 }
 616
 617 static u32 int_store(struct interpreter *inter)
 618 {
 619         u32 next_pc;
 620
 621         if (likely(!(inter->op->flags & LIGHTREC_SMC)))
 622                 return int_io(inter, false);
 623
 624         lightrec_rw(inter->state, inter->op->c,
 625                     inter->state->regs.gpr[inter->op->i.rs],
 626                     inter->state->regs.gpr[inter->op->i.rt],
 627                     &inter->op->flags, inter->block);
 628
 629         next_pc = int_get_ds_pc(inter, 1);
 630
 631         /* Invalidate next PC, to force the rest of the block to be rebuilt */
 632         lightrec_invalidate(inter->state, next_pc, 4);
 633
 634         return next_pc;
 635 }
 636
 637 static u32 int_LWC2(struct interpreter *inter)
 638 {
 639         return int_io(inter, false);
 640 }
 641
 642 static u32 int_special_SLL(struct interpreter *inter)
 643 {
 644         struct opcode *op = inter->op;
 645         u32 rt;
 646
 647         if (op->opcode) { /* Handle NOPs */
 648                 rt = inter->state->regs.gpr[op->r.rt];
 649                 inter->state->regs.gpr[op->r.rd] = rt << op->r.imm;
 650         }
 651
 652         return jump_next(inter);
 653 }
 654
 655 static u32 int_special_SRL(struct interpreter *inter)
 656 {
 657         struct opcode *op = inter->op;
 658         u32 rt = inter->state->regs.gpr[op->r.rt];
 659
 660         inter->state->regs.gpr[op->r.rd] = rt >> op->r.imm;
 661
 662         return jump_next(inter);
 663 }
 664
 665 static u32 int_special_SRA(struct interpreter *inter)
 666 {
 667         struct opcode *op = inter->op;
 668         s32 rt = inter->state->regs.gpr[op->r.rt];
 669
 670         inter->state->regs.gpr[op->r.rd] = rt >> op->r.imm;
 671
 672         return jump_next(inter);
 673 }
 674
 675 static u32 int_special_SLLV(struct interpreter *inter)
 676 {
 677         struct opcode *op = inter->op;
 678         u32 rs = inter->state->regs.gpr[op->r.rs];
 679         u32 rt = inter->state->regs.gpr[op->r.rt];
 680
 681         inter->state->regs.gpr[op->r.rd] = rt << (rs & 0x1f);
 682
 683         return jump_next(inter);
 684 }
 685
 686 static u32 int_special_SRLV(struct interpreter *inter)
 687 {
 688         struct opcode *op = inter->op;
 689         u32 rs = inter->state->regs.gpr[op->r.rs];
 690         u32 rt = inter->state->regs.gpr[op->r.rt];
 691
 692         inter->state->regs.gpr[op->r.rd] = rt >> (rs & 0x1f);
 693
 694         return jump_next(inter);
 695 }
 696
 697 static u32 int_special_SRAV(struct interpreter *inter)
 698 {
 699         struct opcode *op = inter->op;
 700         u32 rs = inter->state->regs.gpr[op->r.rs];
 701         s32 rt = inter->state->regs.gpr[op->r.rt];
 702
 703         inter->state->regs.gpr[op->r.rd] = rt >> (rs & 0x1f);
 704
 705         return jump_next(inter);
 706 }
 707
 708 static u32 int_syscall_break(struct interpreter *inter)
 709 {
 710
 711         if (inter->op->r.op == OP_SPECIAL_BREAK)
 712                 inter->state->exit_flags |= LIGHTREC_EXIT_BREAK;
 713         else
 714                 inter->state->exit_flags |= LIGHTREC_EXIT_SYSCALL;
 715
 716         return int_get_ds_pc(inter, 0);
 717 }
 718
 719 static u32 int_special_MFHI(struct interpreter *inter)
 720 {
 721         u32 *reg_cache = inter->state->regs.gpr;
 722         struct opcode_r *op = &inter->op->r;
 723
 724         if (likely(op->rd))
 725                 reg_cache[op->rd] = reg_cache[REG_HI];
 726
 727         return jump_next(inter);
 728 }
 729
 730 static u32 int_special_MTHI(struct interpreter *inter)
 731 {
 732         u32 *reg_cache = inter->state->regs.gpr;
 733
 734         reg_cache[REG_HI] = reg_cache[inter->op->r.rs];
 735
 736         return jump_next(inter);
 737 }
 738
 739 static u32 int_special_MFLO(struct interpreter *inter)
 740 {
 741         u32 *reg_cache = inter->state->regs.gpr;
 742         struct opcode_r *op = &inter->op->r;
 743
 744         if (likely(op->rd))
 745                 reg_cache[op->rd] = reg_cache[REG_LO];
 746
 747         return jump_next(inter);
 748 }
 749
 750 static u32 int_special_MTLO(struct interpreter *inter)
 751 {
 752         u32 *reg_cache = inter->state->regs.gpr;
 753
 754         reg_cache[REG_LO] = reg_cache[inter->op->r.rs];
 755
 756         return jump_next(inter);
 757 }
 758
 759 static u32 int_special_MULT(struct interpreter *inter)
 760 {
 761         u32 *reg_cache = inter->state->regs.gpr;
 762         s32 rs = reg_cache[inter->op->r.rs];
 763         s32 rt = reg_cache[inter->op->r.rt];
 764         u8 reg_lo = get_mult_div_lo(inter->op->c);
 765         u8 reg_hi = get_mult_div_hi(inter->op->c);
 766         u64 res = (s64)rs * (s64)rt;
 767
 768         if (!(inter->op->flags & LIGHTREC_NO_HI))
 769                 reg_cache[reg_hi] = res >> 32;
 770         if (!(inter->op->flags & LIGHTREC_NO_LO))
 771                 reg_cache[reg_lo] = res;
 772
 773         return jump_next(inter);
 774 }
 775
 776 static u32 int_special_MULTU(struct interpreter *inter)
 777 {
 778         u32 *reg_cache = inter->state->regs.gpr;
 779         u32 rs = reg_cache[inter->op->r.rs];
 780         u32 rt = reg_cache[inter->op->r.rt];
 781         u8 reg_lo = get_mult_div_lo(inter->op->c);
 782         u8 reg_hi = get_mult_div_hi(inter->op->c);
 783         u64 res = (u64)rs * (u64)rt;
 784
 785         if (!(inter->op->flags & LIGHTREC_NO_HI))
 786                 reg_cache[reg_hi] = res >> 32;
 787         if (!(inter->op->flags & LIGHTREC_NO_LO))
 788                 reg_cache[reg_lo] = res;
 789
 790         return jump_next(inter);
 791 }
 792
 793 static u32 int_special_DIV(struct interpreter *inter)
 794 {
 795         u32 *reg_cache = inter->state->regs.gpr;
 796         s32 rs = reg_cache[inter->op->r.rs];
 797         s32 rt = reg_cache[inter->op->r.rt];
 798         u8 reg_lo = get_mult_div_lo(inter->op->c);
 799         u8 reg_hi = get_mult_div_hi(inter->op->c);
 800         u32 lo, hi;
 801
 802         if (rt == 0) {
 803                 hi = rs;
 804                 lo = (rs < 0) * 2 - 1;
 805         } else {
 806                 lo = rs / rt;
 807                 hi = rs % rt;
 808         }
 809
 810         if (!(inter->op->flags & LIGHTREC_NO_HI))
 811                 reg_cache[reg_hi] = hi;
 812         if (!(inter->op->flags & LIGHTREC_NO_LO))
 813                 reg_cache[reg_lo] = lo;
 814
 815         return jump_next(inter);
 816 }
 817
 818 static u32 int_special_DIVU(struct interpreter *inter)
 819 {
 820         u32 *reg_cache = inter->state->regs.gpr;
 821         u32 rs = reg_cache[inter->op->r.rs];
 822         u32 rt = reg_cache[inter->op->r.rt];
 823         u8 reg_lo = get_mult_div_lo(inter->op->c);
 824         u8 reg_hi = get_mult_div_hi(inter->op->c);
 825         u32 lo, hi;
 826
 827         if (rt == 0) {
 828                 hi = rs;
 829                 lo = (u32)-1;
 830         } else {
 831                 lo = rs / rt;
 832                 hi = rs % rt;
 833         }
 834
 835         if (!(inter->op->flags & LIGHTREC_NO_HI))
 836                 reg_cache[reg_hi] = hi;
 837         if (!(inter->op->flags & LIGHTREC_NO_LO))
 838                 reg_cache[reg_lo] = lo;
 839
 840         return jump_next(inter);
 841 }
 842
 843 static u32 int_special_ADD(struct interpreter *inter)
 844 {
 845         u32 *reg_cache = inter->state->regs.gpr;
 846         struct opcode_r *op = &inter->op->r;
 847         s32 rs = reg_cache[op->rs];
 848         s32 rt = reg_cache[op->rt];
 849
 850         if (likely(op->rd))
 851                 reg_cache[op->rd] = rs + rt;
 852
 853         return jump_next(inter);
 854 }
 855
 856 static u32 int_special_SUB(struct interpreter *inter)
 857 {
 858         u32 *reg_cache = inter->state->regs.gpr;
 859         struct opcode_r *op = &inter->op->r;
 860         u32 rs = reg_cache[op->rs];
 861         u32 rt = reg_cache[op->rt];
 862
 863         if (likely(op->rd))
 864                 reg_cache[op->rd] = rs - rt;
 865
 866         return jump_next(inter);
 867 }
 868
 869 static u32 int_special_AND(struct interpreter *inter)
 870 {
 871         u32 *reg_cache = inter->state->regs.gpr;
 872         struct opcode_r *op = &inter->op->r;
 873         u32 rs = reg_cache[op->rs];
 874         u32 rt = reg_cache[op->rt];
 875
 876         if (likely(op->rd))
 877                 reg_cache[op->rd] = rs & rt;
 878
 879         return jump_next(inter);
 880 }
 881
 882 static u32 int_special_OR(struct interpreter *inter)
 883 {
 884         u32 *reg_cache = inter->state->regs.gpr;
 885         struct opcode_r *op = &inter->op->r;
 886         u32 rs = reg_cache[op->rs];
 887         u32 rt = reg_cache[op->rt];
 888
 889         if (likely(op->rd))
 890                 reg_cache[op->rd] = rs | rt;
 891
 892         return jump_next(inter);
 893 }
 894
 895 static u32 int_special_XOR(struct interpreter *inter)
 896 {
 897         u32 *reg_cache = inter->state->regs.gpr;
 898         struct opcode_r *op = &inter->op->r;
 899         u32 rs = reg_cache[op->rs];
 900         u32 rt = reg_cache[op->rt];
 901
 902         if (likely(op->rd))
 903                 reg_cache[op->rd] = rs ^ rt;
 904
 905         return jump_next(inter);
 906 }
 907
 908 static u32 int_special_NOR(struct interpreter *inter)
 909 {
 910         u32 *reg_cache = inter->state->regs.gpr;
 911         struct opcode_r *op = &inter->op->r;
 912         u32 rs = reg_cache[op->rs];
 913         u32 rt = reg_cache[op->rt];
 914
 915         if (likely(op->rd))
 916                 reg_cache[op->rd] = ~(rs | rt);
 917
 918         return jump_next(inter);
 919 }
 920
 921 static u32 int_special_SLT(struct interpreter *inter)
 922 {
 923         u32 *reg_cache = inter->state->regs.gpr;
 924         struct opcode_r *op = &inter->op->r;
 925         s32 rs = reg_cache[op->rs];
 926         s32 rt = reg_cache[op->rt];
 927
 928         if (likely(op->rd))
 929                 reg_cache[op->rd] = rs < rt;
 930
 931         return jump_next(inter);
 932 }
 933
 934 static u32 int_special_SLTU(struct interpreter *inter)
 935 {
 936         u32 *reg_cache = inter->state->regs.gpr;
 937         struct opcode_r *op = &inter->op->r;
 938         u32 rs = reg_cache[op->rs];
 939         u32 rt = reg_cache[op->rt];
 940
 941         if (likely(op->rd))
 942                 reg_cache[op->rd] = rs < rt;
 943
 944         return jump_next(inter);
 945 }
 946
 947 static u32 int_META_MOV(struct interpreter *inter)
 948 {
 949         u32 *reg_cache = inter->state->regs.gpr;
 950         struct opcode_r *op = &inter->op->r;
 951
 952         if (likely(op->rd))
 953                 reg_cache[op->rd] = reg_cache[op->rs];
 954
 955         return jump_next(inter);
 956 }
 957
 958 static u32 int_META_EXTC(struct interpreter *inter)
 959 {
 960         u32 *reg_cache = inter->state->regs.gpr;
 961         struct opcode_i *op = &inter->op->i;
 962
 963         if (likely(op->rt))
 964                 reg_cache[op->rt] = (u32)(s32)(s8)reg_cache[op->rs];
 965
 966         return jump_next(inter);
 967 }
 968
 969 static u32 int_META_EXTS(struct interpreter *inter)
 970 {
 971         u32 *reg_cache = inter->state->regs.gpr;
 972         struct opcode_i *op = &inter->op->i;
 973
 974         if (likely(op->rt))
 975                 reg_cache[op->rt] = (u32)(s32)(s16)reg_cache[op->rs];
 976
 977         return jump_next(inter);
 978 }
 979
 980 static const lightrec_int_func_t int_standard[64] = {
 981         SET_DEFAULT_ELM(int_standard, int_unimplemented),
 982         [OP_SPECIAL]            = int_SPECIAL,
 983         [OP_REGIMM]             = int_REGIMM,
 984         [OP_J]                  = int_J,
 985         [OP_JAL]                = int_JAL,
 986         [OP_BEQ]                = int_BEQ,
 987         [OP_BNE]                = int_BNE,
 988         [OP_BLEZ]               = int_BLEZ,
 989         [OP_BGTZ]               = int_BGTZ,
 990         [OP_ADDI]               = int_ADDI,
 991         [OP_ADDIU]              = int_ADDI,
 992         [OP_SLTI]               = int_SLTI,
 993         [OP_SLTIU]              = int_SLTIU,
 994         [OP_ANDI]               = int_ANDI,
 995         [OP_ORI]                = int_ORI,
 996         [OP_XORI]               = int_XORI,
 997         [OP_LUI]                = int_LUI,
 998         [OP_CP0]                = int_CP0,
 999         [OP_CP2]                = int_CP2,
1000         [OP_LB]                 = int_load,
1001         [OP_LH]                 = int_load,
1002         [OP_LWL]                = int_load,
1003         [OP_LW]                 = int_load,
1004         [OP_LBU]                = int_load,
1005         [OP_LHU]                = int_load,
1006         [OP_LWR]                = int_load,
1007         [OP_SB]                 = int_store,
1008         [OP_SH]                 = int_store,
1009         [OP_SWL]                = int_store,
1010         [OP_SW]                 = int_store,
1011         [OP_SWR]                = int_store,
1012         [OP_LWC2]               = int_LWC2,
1013         [OP_SWC2]               = int_store,
1014
1015         [OP_META_MOV]           = int_META_MOV,
1016         [OP_META_EXTC]          = int_META_EXTC,
1017         [OP_META_EXTS]          = int_META_EXTS,
1018 };
1019
1020 static const lightrec_int_func_t int_special[64] = {
1021         SET_DEFAULT_ELM(int_special, int_unimplemented),
1022         [OP_SPECIAL_SLL]        = int_special_SLL,
1023         [OP_SPECIAL_SRL]        = int_special_SRL,
1024         [OP_SPECIAL_SRA]        = int_special_SRA,
1025         [OP_SPECIAL_SLLV]       = int_special_SLLV,
1026         [OP_SPECIAL_SRLV]       = int_special_SRLV,
1027         [OP_SPECIAL_SRAV]       = int_special_SRAV,
1028         [OP_SPECIAL_JR]         = int_special_JR,
1029         [OP_SPECIAL_JALR]       = int_special_JALR,
1030         [OP_SPECIAL_SYSCALL]    = int_syscall_break,
1031         [OP_SPECIAL_BREAK]      = int_syscall_break,
1032         [OP_SPECIAL_MFHI]       = int_special_MFHI,
1033         [OP_SPECIAL_MTHI]       = int_special_MTHI,
1034         [OP_SPECIAL_MFLO]       = int_special_MFLO,
1035         [OP_SPECIAL_MTLO]       = int_special_MTLO,
1036         [OP_SPECIAL_MULT]       = int_special_MULT,
1037         [OP_SPECIAL_MULTU]      = int_special_MULTU,
1038         [OP_SPECIAL_DIV]        = int_special_DIV,
1039         [OP_SPECIAL_DIVU]       = int_special_DIVU,
1040         [OP_SPECIAL_ADD]        = int_special_ADD,
1041         [OP_SPECIAL_ADDU]       = int_special_ADD,
1042         [OP_SPECIAL_SUB]        = int_special_SUB,
1043         [OP_SPECIAL_SUBU]       = int_special_SUB,
1044         [OP_SPECIAL_AND]        = int_special_AND,
1045         [OP_SPECIAL_OR]         = int_special_OR,
1046         [OP_SPECIAL_XOR]        = int_special_XOR,
1047         [OP_SPECIAL_NOR]        = int_special_NOR,
1048         [OP_SPECIAL_SLT]        = int_special_SLT,
1049         [OP_SPECIAL_SLTU]       = int_special_SLTU,
1050 };
1051
1052 static const lightrec_int_func_t int_regimm[64] = {
1053         SET_DEFAULT_ELM(int_regimm, int_unimplemented),
1054         [OP_REGIMM_BLTZ]        = int_regimm_BLTZ,
1055         [OP_REGIMM_BGEZ]        = int_regimm_BGEZ,
1056         [OP_REGIMM_BLTZAL]      = int_regimm_BLTZAL,
1057         [OP_REGIMM_BGEZAL]      = int_regimm_BGEZAL,
1058 };
1059
1060 static const lightrec_int_func_t int_cp0[64] = {
1061         SET_DEFAULT_ELM(int_cp0, int_CP),
1062         [OP_CP0_MFC0]           = int_cfc,
1063         [OP_CP0_CFC0]           = int_cfc,
1064         [OP_CP0_MTC0]           = int_ctc,
1065         [OP_CP0_CTC0]           = int_ctc,
1066         [OP_CP0_RFE]            = int_cp0_RFE,
1067 };
1068
1069 static const lightrec_int_func_t int_cp2_basic[64] = {
1070         SET_DEFAULT_ELM(int_cp2_basic, int_CP),
1071         [OP_CP2_BASIC_MFC2]     = int_cfc,
1072         [OP_CP2_BASIC_CFC2]     = int_cfc,
1073         [OP_CP2_BASIC_MTC2]     = int_ctc,
1074         [OP_CP2_BASIC_CTC2]     = int_ctc,
1075 };
1076
1077 static u32 int_SPECIAL(struct interpreter *inter)
1078 {
1079         lightrec_int_func_t f = int_special[inter->op->r.op];
1080
1081         if (!HAS_DEFAULT_ELM && unlikely(!f))
1082                 return int_unimplemented(inter);
1083
1084         return execute(f, inter);
1085 }
1086
1087 static u32 int_REGIMM(struct interpreter *inter)
1088 {
1089         lightrec_int_func_t f = int_regimm[inter->op->r.rt];
1090
1091         if (!HAS_DEFAULT_ELM && unlikely(!f))
1092                 return int_unimplemented(inter);
1093
1094         return execute(f, inter);
1095 }
1096
1097 static u32 int_CP0(struct interpreter *inter)
1098 {
1099         lightrec_int_func_t f = int_cp0[inter->op->r.rs];
1100
1101         if (!HAS_DEFAULT_ELM && unlikely(!f))
1102                 return int_CP(inter);
1103
1104         return execute(f, inter);
1105 }
1106
1107 static u32 int_CP2(struct interpreter *inter)
1108 {
1109         if (inter->op->r.op == OP_CP2_BASIC) {
1110                 lightrec_int_func_t f = int_cp2_basic[inter->op->r.rs];
1111                 if (HAS_DEFAULT_ELM || likely(f))
1112                         return execute(f, inter);
1113         }
1114
1115         return int_CP(inter);
1116 }
1117
1118 static u32 lightrec_emulate_block_list(struct lightrec_state *state,
1119                                        struct block *block, u32 offset)
1120 {
1121         struct interpreter inter;
1122         u32 pc;
1123
1124         inter.block = block;
1125         inter.state = state;
1126         inter.offset = offset;
1127         inter.op = &block->opcode_list[offset];
1128         inter.cycles = 0;
1129         inter.delay_slot = false;
1130
1131         pc = lightrec_int_op(&inter);
1132
1133         /* Add the cycles of the last branch */
1134         inter.cycles += lightrec_cycles_of_opcode(inter.op->c);
1135
1136         state->current_cycle += inter.cycles;
1137
1138         return pc;
1139 }
1140
1141 u32 lightrec_emulate_block(struct lightrec_state *state, struct block *block, u32 pc)
1142 {
1143         u32 offset = (kunseg(pc) - kunseg(block->pc)) >> 2;
1144
1145         if (offset < block->nb_ops)
1146                 return lightrec_emulate_block_list(state, block, offset);
1147
1148         pr_err("PC 0x%x is outside block at PC 0x%x\n", pc, block->pc);
1149
1150         return 0;
1151 }