libpcsxcore/lightrec/plugin.c

   1 #include <lightrec.h>
   2 #include <errno.h>
   3 #include <stdbool.h>
   4 #include <stdio.h>
   5 #include <unistd.h>
   6 #include <signal.h>
   7 #include <assert.h>
   8
   9 #if P_HAVE_MMAP
  10 #include <sys/mman.h>
  11 #endif
  12
  13 #include "../cdrom.h"
  14 #include "../gpu.h"
  15 #include "../gte.h"
  16 #include "../mdec.h"
  17 #include "../psxdma.h"
  18 #include "../psxhw.h"
  19 #include "../psxmem.h"
  20 #include "../r3000a.h"
  21 #include "../psxinterpreter.h"
  22 #include "../psxhle.h"
  23 #include "../psxevents.h"
  24
  25 #include "../frontend/main.h"
  26
  27 #include "mem.h"
  28 #include "plugin.h"
  29
  30 #if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
  31 #error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
  32 #endif
  33
  34 #define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
  35
  36 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
  37 #       define LE32TOH(x)       __builtin_bswap32(x)
  38 #       define HTOLE32(x)       __builtin_bswap32(x)
  39 #       define LE16TOH(x)       __builtin_bswap16(x)
  40 #       define HTOLE16(x)       __builtin_bswap16(x)
  41 #else
  42 #       define LE32TOH(x)       (x)
  43 #       define HTOLE32(x)       (x)
  44 #       define LE16TOH(x)       (x)
  45 #       define HTOLE16(x)       (x)
  46 #endif
  47
  48 #ifdef __GNUC__
  49 #       define likely(x)       __builtin_expect(!!(x),1)
  50 #       define unlikely(x)     __builtin_expect(!!(x),0)
  51 #else
  52 #       define likely(x)       (x)
  53 #       define unlikely(x)     (x)
  54 #endif
  55
  56 psxRegisters psxRegs;
  57 Rcnt rcnts[4];
  58
  59 void* code_buffer;
  60
  61 static struct lightrec_state *lightrec_state;
  62
  63 static char *name = "retroarch.exe";
  64
  65 static bool use_lightrec_interpreter;
  66 static bool use_pcsx_interpreter;
  67 static bool block_stepping;
  68
  69 extern u32 lightrec_hacks;
  70
  71 enum my_cp2_opcodes {
  72         OP_CP2_RTPS             = 0x01,
  73         OP_CP2_NCLIP            = 0x06,
  74         OP_CP2_OP               = 0x0c,
  75         OP_CP2_DPCS             = 0x10,
  76         OP_CP2_INTPL            = 0x11,
  77         OP_CP2_MVMVA            = 0x12,
  78         OP_CP2_NCDS             = 0x13,
  79         OP_CP2_CDP              = 0x14,
  80         OP_CP2_NCDT             = 0x16,
  81         OP_CP2_NCCS             = 0x1b,
  82         OP_CP2_CC               = 0x1c,
  83         OP_CP2_NCS              = 0x1e,
  84         OP_CP2_NCT              = 0x20,
  85         OP_CP2_SQR              = 0x28,
  86         OP_CP2_DCPL             = 0x29,
  87         OP_CP2_DPCT             = 0x2a,
  88         OP_CP2_AVSZ3            = 0x2d,
  89         OP_CP2_AVSZ4            = 0x2e,
  90         OP_CP2_RTPT             = 0x30,
  91         OP_CP2_GPF              = 0x3d,
  92         OP_CP2_GPL              = 0x3e,
  93         OP_CP2_NCCT             = 0x3f,
  94 };
  95
  96 static void (*cp2_ops[])(struct psxCP2Regs *) = {
  97         [OP_CP2_RTPS] = gteRTPS,
  98         [OP_CP2_RTPS] = gteRTPS,
  99         [OP_CP2_NCLIP] = gteNCLIP,
 100         [OP_CP2_OP] = gteOP,
 101         [OP_CP2_DPCS] = gteDPCS,
 102         [OP_CP2_INTPL] = gteINTPL,
 103         [OP_CP2_MVMVA] = gteMVMVA,
 104         [OP_CP2_NCDS] = gteNCDS,
 105         [OP_CP2_CDP] = gteCDP,
 106         [OP_CP2_NCDT] = gteNCDT,
 107         [OP_CP2_NCCS] = gteNCCS,
 108         [OP_CP2_CC] = gteCC,
 109         [OP_CP2_NCS] = gteNCS,
 110         [OP_CP2_NCT] = gteNCT,
 111         [OP_CP2_SQR] = gteSQR,
 112         [OP_CP2_DCPL] = gteDCPL,
 113         [OP_CP2_DPCT] = gteDPCT,
 114         [OP_CP2_AVSZ3] = gteAVSZ3,
 115         [OP_CP2_AVSZ4] = gteAVSZ4,
 116         [OP_CP2_RTPT] = gteRTPT,
 117         [OP_CP2_GPF] = gteGPF,
 118         [OP_CP2_GPL] = gteGPL,
 119         [OP_CP2_NCCT] = gteNCCT,
 120 };
 121
 122 static char cache_buf[64 * 1024];
 123
 124 static void cop2_op(struct lightrec_state *state, u32 func)
 125 {
 126         struct lightrec_registers *regs = lightrec_get_registers(state);
 127
 128         psxRegs.code = func;
 129
 130         if (unlikely(!cp2_ops[func & 0x3f])) {
 131                 fprintf(stderr, "Invalid CP2 function %u\n", func);
 132         } else {
 133                 /* This works because regs->cp2c comes right after regs->cp2d,
 134                  * so it can be cast to a pcsxCP2Regs pointer. */
 135                 cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
 136         }
 137 }
 138
 139 static bool has_interrupt(void)
 140 {
 141         struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
 142
 143         return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
 144                 (regs->cp0[12] & 0x401) == 0x401) ||
 145                 (regs->cp0[12] & regs->cp0[13] & 0x0300);
 146 }
 147
 148 static void lightrec_tansition_to_pcsx(struct lightrec_state *state)
 149 {
 150         psxRegs.cycle += lightrec_current_cycle_count(state) / 1024;
 151         lightrec_reset_cycle_count(state, 0);
 152 }
 153
 154 static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
 155 {
 156         s32 cycles_left = next_interupt - psxRegs.cycle;
 157
 158         if (block_stepping || cycles_left <= 0 || has_interrupt())
 159                 lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
 160         else {
 161                 lightrec_set_target_cycle_count(state, cycles_left * 1024);
 162         }
 163 }
 164
 165 static void hw_write_byte(struct lightrec_state *state,
 166                           u32 op, void *host, u32 mem, u8 val)
 167 {
 168         lightrec_tansition_to_pcsx(state);
 169
 170         psxHwWrite8(mem, val);
 171
 172         lightrec_tansition_from_pcsx(state);
 173 }
 174
 175 static void hw_write_half(struct lightrec_state *state,
 176                           u32 op, void *host, u32 mem, u16 val)
 177 {
 178         lightrec_tansition_to_pcsx(state);
 179
 180         psxHwWrite16(mem, val);
 181
 182         lightrec_tansition_from_pcsx(state);
 183 }
 184
 185 static void hw_write_word(struct lightrec_state *state,
 186                           u32 op, void *host, u32 mem, u32 val)
 187 {
 188         lightrec_tansition_to_pcsx(state);
 189
 190         psxHwWrite32(mem, val);
 191
 192         lightrec_tansition_from_pcsx(state);
 193 }
 194
 195 static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
 196 {
 197         u8 val;
 198
 199         lightrec_tansition_to_pcsx(state);
 200
 201         val = psxHwRead8(mem);
 202
 203         lightrec_tansition_from_pcsx(state);
 204
 205         return val;
 206 }
 207
 208 static u16 hw_read_half(struct lightrec_state *state,
 209                         u32 op, void *host, u32 mem)
 210 {
 211         u16 val;
 212
 213         lightrec_tansition_to_pcsx(state);
 214
 215         val = psxHwRead16(mem);
 216
 217         lightrec_tansition_from_pcsx(state);
 218
 219         return val;
 220 }
 221
 222 static u32 hw_read_word(struct lightrec_state *state,
 223                         u32 op, void *host, u32 mem)
 224 {
 225         u32 val;
 226
 227         lightrec_tansition_to_pcsx(state);
 228
 229         val = psxHwRead32(mem);
 230
 231         lightrec_tansition_from_pcsx(state);
 232
 233         return val;
 234 }
 235
 236 static struct lightrec_mem_map_ops hw_regs_ops = {
 237         .sb = hw_write_byte,
 238         .sh = hw_write_half,
 239         .sw = hw_write_word,
 240         .lb = hw_read_byte,
 241         .lh = hw_read_half,
 242         .lw = hw_read_word,
 243 };
 244
 245 static u32 cache_ctrl;
 246
 247 static void cache_ctrl_write_word(struct lightrec_state *state,
 248                                   u32 op, void *host, u32 mem, u32 val)
 249 {
 250         cache_ctrl = val;
 251 }
 252
 253 static u32 cache_ctrl_read_word(struct lightrec_state *state,
 254                                 u32 op, void *host, u32 mem)
 255 {
 256         return cache_ctrl;
 257 }
 258
 259 static struct lightrec_mem_map_ops cache_ctrl_ops = {
 260         .sw = cache_ctrl_write_word,
 261         .lw = cache_ctrl_read_word,
 262 };
 263
 264 static struct lightrec_mem_map lightrec_map[] = {
 265         [PSX_MAP_KERNEL_USER_RAM] = {
 266                 /* Kernel and user memory */
 267                 .pc = 0x00000000,
 268                 .length = 0x200000,
 269         },
 270         [PSX_MAP_BIOS] = {
 271                 /* BIOS */
 272                 .pc = 0x1fc00000,
 273                 .length = 0x80000,
 274         },
 275         [PSX_MAP_SCRATCH_PAD] = {
 276                 /* Scratch pad */
 277                 .pc = 0x1f800000,
 278                 .length = 0x400,
 279         },
 280         [PSX_MAP_PARALLEL_PORT] = {
 281                 /* Parallel port */
 282                 .pc = 0x1f000000,
 283                 .length = 0x10000,
 284         },
 285         [PSX_MAP_HW_REGISTERS] = {
 286                 /* Hardware registers */
 287                 .pc = 0x1f801000,
 288                 .length = 0x8000,
 289                 .ops = &hw_regs_ops,
 290         },
 291         [PSX_MAP_CACHE_CONTROL] = {
 292                 /* Cache control */
 293                 .pc = 0x5ffe0130,
 294                 .length = 4,
 295                 .ops = &cache_ctrl_ops,
 296         },
 297
 298         /* Mirrors of the kernel/user memory */
 299         [PSX_MAP_MIRROR1] = {
 300                 .pc = 0x00200000,
 301                 .length = 0x200000,
 302                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 303         },
 304         [PSX_MAP_MIRROR2] = {
 305                 .pc = 0x00400000,
 306                 .length = 0x200000,
 307                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 308         },
 309         [PSX_MAP_MIRROR3] = {
 310                 .pc = 0x00600000,
 311                 .length = 0x200000,
 312                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 313         },
 314
 315         /* Mirror of the parallel port. Only used by the PS2/PS3 BIOS */
 316         [PSX_MAP_PPORT_MIRROR] = {
 317                 .pc = 0x1fa00000,
 318                 .length = 0x10000,
 319                 .mirror_of = &lightrec_map[PSX_MAP_PARALLEL_PORT],
 320         },
 321
 322         /* Code buffer */
 323         [PSX_MAP_CODE_BUFFER] = {
 324                 .length = CODE_BUFFER_SIZE,
 325         },
 326 };
 327
 328 static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
 329 {
 330         if (enable)
 331                 memcpy(psxM, cache_buf, sizeof(cache_buf));
 332         else
 333                 memcpy(cache_buf, psxM, sizeof(cache_buf));
 334 }
 335
 336 static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
 337 {
 338         switch (size) {
 339         case 8:
 340                 switch (kaddr) {
 341                 case 0x1f801040:
 342                 case 0x1f801050:
 343                 case 0x1f801800:
 344                 case 0x1f801801:
 345                 case 0x1f801802:
 346                 case 0x1f801803:
 347                         return false;
 348                 default:
 349                         return true;
 350                 }
 351         case 16:
 352                 switch (kaddr) {
 353                 case 0x1f801040:
 354                 case 0x1f801044:
 355                 case 0x1f801048:
 356                 case 0x1f80104a:
 357                 case 0x1f80104e:
 358                 case 0x1f801050:
 359                 case 0x1f801054:
 360                 case 0x1f80105a:
 361                 case 0x1f80105e:
 362                 case 0x1f801100:
 363                 case 0x1f801104:
 364                 case 0x1f801108:
 365                 case 0x1f801110:
 366                 case 0x1f801114:
 367                 case 0x1f801118:
 368                 case 0x1f801120:
 369                 case 0x1f801124:
 370                 case 0x1f801128:
 371                         return false;
 372                 case 0x1f801070:
 373                 case 0x1f801074:
 374                         return !is_write;
 375                 default:
 376                         return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
 377                 }
 378         default:
 379                 switch (kaddr) {
 380                 case 0x1f801040:
 381                 case 0x1f801050:
 382                 case 0x1f801100:
 383                 case 0x1f801104:
 384                 case 0x1f801108:
 385                 case 0x1f801110:
 386                 case 0x1f801114:
 387                 case 0x1f801118:
 388                 case 0x1f801120:
 389                 case 0x1f801124:
 390                 case 0x1f801128:
 391                 case 0x1f801810:
 392                 case 0x1f801814:
 393                 case 0x1f801820:
 394                 case 0x1f801824:
 395                         return false;
 396                 case 0x1f801070:
 397                 case 0x1f801074:
 398                 case 0x1f801088:
 399                 case 0x1f801098:
 400                 case 0x1f8010a8:
 401                 case 0x1f8010b8:
 402                 case 0x1f8010c8:
 403                 case 0x1f8010e8:
 404                 case 0x1f8010f4:
 405                         return !is_write;
 406                 default:
 407                         return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
 408                 }
 409         }
 410 }
 411
 412 #if defined(HW_DOL) || defined(HW_RVL)
 413 static void lightrec_code_inv(void *ptr, uint32_t len)
 414 {
 415         extern void DCFlushRange(void *ptr, u32 len);
 416         extern void ICInvalidateRange(void *ptr, u32 len);
 417
 418         DCFlushRange(ptr, len);
 419         ICInvalidateRange(ptr, len);
 420 }
 421 #elif defined(HW_WUP)
 422 static void lightrec_code_inv(void *ptr, uint32_t len)
 423 {
 424         wiiu_clear_cache(ptr, (void *)((uintptr_t)ptr + len));
 425 }
 426 #endif
 427
 428 static const struct lightrec_ops lightrec_ops = {
 429         .cop2_op = cop2_op,
 430         .enable_ram = lightrec_enable_ram,
 431         .hw_direct = lightrec_can_hw_direct,
 432 #if defined(HW_DOL) || defined(HW_RVL) || defined(HW_WUP)
 433         .code_inv = lightrec_code_inv,
 434 #endif
 435 };
 436
 437 static int lightrec_plugin_init(void)
 438 {
 439         lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
 440         lightrec_map[PSX_MAP_BIOS].address = psxR;
 441         lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
 442         lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
 443         lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
 444
 445         if (!LIGHTREC_CUSTOM_MAP) {
 446 #if P_HAVE_MMAP
 447                 code_buffer = mmap(0, CODE_BUFFER_SIZE,
 448                                    PROT_EXEC | PROT_READ | PROT_WRITE,
 449                                    MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 450                 if (code_buffer == MAP_FAILED)
 451                         return -ENOMEM;
 452 #else
 453                 code_buffer = malloc(CODE_BUFFER_SIZE);
 454                 if (!code_buffer)
 455                         return -ENOMEM;
 456 #endif
 457         }
 458
 459         if (LIGHTREC_CUSTOM_MAP) {
 460                 lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
 461                 lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
 462                 lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
 463         }
 464
 465         lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
 466
 467         use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
 468
 469         lightrec_state = lightrec_init(name,
 470                         lightrec_map, ARRAY_SIZE(lightrec_map),
 471                         &lightrec_ops);
 472
 473         // fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
 474         //              (uintptr_t) psxM,
 475         //              (uintptr_t) psxP,
 476         //              (uintptr_t) psxR,
 477         //              (uintptr_t) psxH);
 478
 479 #ifndef _WIN32
 480         signal(SIGPIPE, exit);
 481 #endif
 482         return 0;
 483 }
 484
 485 static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2);
 486 static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2);
 487
 488 static void lightrec_plugin_execute_internal(bool block_only)
 489 {
 490         struct lightrec_registers *regs;
 491         u32 flags, cycles_pcsx;
 492
 493         regs = lightrec_get_registers(lightrec_state);
 494         gen_interupt((psxCP0Regs *)regs->cp0);
 495         if (!block_only && stop)
 496                 return;
 497
 498         cycles_pcsx = next_interupt - psxRegs.cycle;
 499         assert((s32)cycles_pcsx > 0);
 500
 501         // step during early boot so that 0x80030000 fastboot hack works
 502         block_stepping = block_only;
 503         if (block_only)
 504                 cycles_pcsx = 0;
 505
 506         if (use_pcsx_interpreter) {
 507                 intExecuteBlock(0);
 508         } else {
 509                 u32 cycles_lightrec = cycles_pcsx * 1024;
 510                 if (unlikely(use_lightrec_interpreter)) {
 511                         psxRegs.pc = lightrec_run_interpreter(lightrec_state,
 512                                                               psxRegs.pc,
 513                                                               cycles_lightrec);
 514                 } else {
 515                         psxRegs.pc = lightrec_execute(lightrec_state,
 516                                                       psxRegs.pc, cycles_lightrec);
 517                 }
 518
 519                 lightrec_tansition_to_pcsx(lightrec_state);
 520
 521                 flags = lightrec_exit_flags(lightrec_state);
 522
 523                 if (flags & LIGHTREC_EXIT_SEGFAULT) {
 524                         fprintf(stderr, "Exiting at cycle 0x%08x\n",
 525                                 psxRegs.cycle);
 526                         exit(1);
 527                 }
 528
 529                 if (flags & LIGHTREC_EXIT_SYSCALL)
 530                         psxException(R3000E_Syscall << 2, 0, (psxCP0Regs *)regs->cp0);
 531                 if (flags & LIGHTREC_EXIT_BREAK)
 532                         psxException(R3000E_Bp << 2, 0, (psxCP0Regs *)regs->cp0);
 533                 else if (flags & LIGHTREC_EXIT_UNKNOWN_OP) {
 534                         u32 op = intFakeFetch(psxRegs.pc);
 535                         u32 hlec = op & 0x03ffffff;
 536                         if ((op >> 26) == 0x3b && hlec < ARRAY_SIZE(psxHLEt) && Config.HLE) {
 537                                 lightrec_plugin_sync_regs_to_pcsx(0);
 538                                 psxHLEt[hlec]();
 539                                 lightrec_plugin_sync_regs_from_pcsx(0);
 540                         }
 541                         else
 542                                 psxException(R3000E_RI << 2, 0, (psxCP0Regs *)regs->cp0);
 543                 }
 544         }
 545
 546         if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
 547                 /* Handle software interrupts */
 548                 regs->cp0[13] &= ~0x7c;
 549                 psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
 550         }
 551 }
 552
 553 static void lightrec_plugin_execute(void)
 554 {
 555         while (!stop)
 556                 lightrec_plugin_execute_internal(false);
 557 }
 558
 559 static void lightrec_plugin_execute_block(enum blockExecCaller caller)
 560 {
 561         lightrec_plugin_execute_internal(true);
 562 }
 563
 564 static void lightrec_plugin_clear(u32 addr, u32 size)
 565 {
 566         if (addr == 0 && size == UINT32_MAX)
 567                 lightrec_invalidate_all(lightrec_state);
 568         else
 569                 /* size * 4: PCSX uses DMA units */
 570                 lightrec_invalidate(lightrec_state, addr, size * 4);
 571 }
 572
 573 static void lightrec_plugin_notify(enum R3000Anote note, void *data)
 574 {
 575         switch (note)
 576         {
 577         case R3000ACPU_NOTIFY_CACHE_ISOLATED:
 578         case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
 579                 /* not used, lightrec calls lightrec_enable_ram() instead */
 580                 break;
 581         case R3000ACPU_NOTIFY_BEFORE_SAVE:
 582                 /* non-null 'data' means this is HLE related sync */
 583                 lightrec_plugin_sync_regs_to_pcsx(data == NULL);
 584                 break;
 585         case R3000ACPU_NOTIFY_AFTER_LOAD:
 586                 lightrec_plugin_sync_regs_from_pcsx(data == NULL);
 587                 if (data == NULL)
 588                         lightrec_invalidate_all(lightrec_state);
 589                 break;
 590         }
 591 }
 592
 593 static void lightrec_plugin_apply_config()
 594 {
 595         u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
 596                 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
 597         assert(cycle_mult);
 598
 599         lightrec_set_cycles_per_opcode(lightrec_state, cycle_mult * 1024 / 100);
 600 }
 601
 602 static void lightrec_plugin_shutdown(void)
 603 {
 604         lightrec_destroy(lightrec_state);
 605
 606         if (!LIGHTREC_CUSTOM_MAP) {
 607 #if P_HAVE_MMAP
 608                 munmap(code_buffer, CODE_BUFFER_SIZE);
 609 #else
 610                 free(code_buffer);
 611 #endif
 612         }
 613 }
 614
 615 static void lightrec_plugin_reset(void)
 616 {
 617         struct lightrec_registers *regs;
 618
 619         regs = lightrec_get_registers(lightrec_state);
 620
 621         /* Invalidate all blocks */
 622         lightrec_invalidate_all(lightrec_state);
 623
 624         /* Reset registers */
 625         memset(regs, 0, sizeof(*regs));
 626
 627         regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
 628         regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
 629
 630         lightrec_set_unsafe_opt_flags(lightrec_state, lightrec_hacks);
 631 }
 632
 633 static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2)
 634 {
 635         struct lightrec_registers *regs;
 636
 637         regs = lightrec_get_registers(lightrec_state);
 638         memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
 639         memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
 640         if (need_cp2)
 641                 memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
 642 }
 643
 644 static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2)
 645 {
 646         struct lightrec_registers *regs;
 647
 648         regs = lightrec_get_registers(lightrec_state);
 649         memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
 650         memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
 651         if (need_cp2)
 652                 memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
 653 }
 654
 655 R3000Acpu psxRec =
 656 {
 657         lightrec_plugin_init,
 658         lightrec_plugin_reset,
 659         lightrec_plugin_execute,
 660         lightrec_plugin_execute_block,
 661         lightrec_plugin_clear,
 662         lightrec_plugin_notify,
 663         lightrec_plugin_apply_config,
 664         lightrec_plugin_shutdown,
 665 };