1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus/PCSX - assem_arm.c *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2011 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
26 #include "../gte_arm.h"
27 #include "../gte_neon.h"
29 #include "arm_features.h"
31 #if defined(BASE_ADDR_FIXED)
32 #elif defined(BASE_ADDR_DYNAMIC)
33 char *translation_cache;
35 char translation_cache[1 << TARGET_SIZE_2] __attribute__((aligned(4096)));
39 #define CALLER_SAVE_REGS 0x100f
41 #define CALLER_SAVE_REGS 0x120f
44 #define unused __attribute__((unused))
47 #pragma GCC diagnostic ignored "-Wunused-function"
48 #pragma GCC diagnostic ignored "-Wunused-variable"
49 #pragma GCC diagnostic ignored "-Wunused-but-set-variable"
52 extern int cycle_count;
53 extern int last_count;
55 extern int pending_exception;
56 extern int branch_target;
57 extern uint64_t readmem_dword;
58 extern void *dynarec_local;
59 extern u_int mini_ht[32][2];
61 void indirect_jump_indexed();
74 void jump_vaddr_r10();
75 void jump_vaddr_r12();
77 const u_int jump_vaddr_reg[16] = {
95 void invalidate_addr_r0();
96 void invalidate_addr_r1();
97 void invalidate_addr_r2();
98 void invalidate_addr_r3();
99 void invalidate_addr_r4();
100 void invalidate_addr_r5();
101 void invalidate_addr_r6();
102 void invalidate_addr_r7();
103 void invalidate_addr_r8();
104 void invalidate_addr_r9();
105 void invalidate_addr_r10();
106 void invalidate_addr_r12();
108 const u_int invalidate_addr_reg[16] = {
109 (int)invalidate_addr_r0,
110 (int)invalidate_addr_r1,
111 (int)invalidate_addr_r2,
112 (int)invalidate_addr_r3,
113 (int)invalidate_addr_r4,
114 (int)invalidate_addr_r5,
115 (int)invalidate_addr_r6,
116 (int)invalidate_addr_r7,
117 (int)invalidate_addr_r8,
118 (int)invalidate_addr_r9,
119 (int)invalidate_addr_r10,
121 (int)invalidate_addr_r12,
126 static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
130 static void set_jump_target(int addr,u_int target)
132 u_char *ptr=(u_char *)addr;
133 u_int *ptr2=(u_int *)ptr;
135 assert((target-(u_int)ptr2-8)<1024);
137 assert((target&3)==0);
138 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
139 //printf("target=%x addr=%x insn=%x\n",target,addr,*ptr2);
141 else if(ptr[3]==0x72) {
142 // generated by emit_jno_unlikely
143 if((target-(u_int)ptr2-8)<1024) {
145 assert((target&3)==0);
146 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
148 else if((target-(u_int)ptr2-8)<4096&&!((target-(u_int)ptr2-8)&15)) {
150 assert((target&3)==0);
151 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>4)|0xE00;
153 else *ptr2=(0x7A000000)|(((target-(u_int)ptr2-8)<<6)>>8);
156 assert((ptr[3]&0x0e)==0xa);
157 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
161 // This optionally copies the instruction from the target of the branch into
162 // the space before the branch. Works, but the difference in speed is
163 // usually insignificant.
165 static void set_jump_target_fillslot(int addr,u_int target,int copy)
167 u_char *ptr=(u_char *)addr;
168 u_int *ptr2=(u_int *)ptr;
169 assert(!copy||ptr2[-1]==0xe28dd000);
172 assert((target-(u_int)ptr2-8)<4096);
173 *ptr2=(*ptr2&0xFFFFF000)|(target-(u_int)ptr2-8);
176 assert((ptr[3]&0x0e)==0xa);
177 u_int target_insn=*(u_int *)target;
178 if((target_insn&0x0e100000)==0) { // ALU, no immediate, no flags
181 if((target_insn&0x0c100000)==0x04100000) { // Load
184 if(target_insn&0x08000000) {
188 ptr2[-1]=target_insn;
191 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
197 static void add_literal(int addr,int val)
199 assert(literalcount<sizeof(literals)/sizeof(literals[0]));
200 literals[literalcount][0]=addr;
201 literals[literalcount][1]=val;
205 // from a pointer to external jump stub (which was produced by emit_extjump2)
206 // find where the jumping insn is
207 static void *find_extjump_insn(void *stub)
209 int *ptr=(int *)(stub+4);
210 assert((*ptr&0x0fff0000)==0x059f0000); // ldr rx, [pc, #ofs]
211 u_int offset=*ptr&0xfff;
212 void **l_ptr=(void *)ptr+offset+8;
216 // find where external branch is liked to using addr of it's stub:
217 // get address that insn one after stub loads (dyna_linker arg1),
218 // treat it as a pointer to branch insn,
219 // return addr where that branch jumps to
220 static int get_pointer(void *stub)
222 //printf("get_pointer(%x)\n",(int)stub);
223 int *i_ptr=find_extjump_insn(stub);
224 assert((*i_ptr&0x0f000000)==0x0a000000);
225 return (int)i_ptr+((*i_ptr<<8)>>6)+8;
228 // Find the "clean" entry point from a "dirty" entry point
229 // by skipping past the call to verify_code
230 static u_int get_clean_addr(int addr)
232 int *ptr=(int *)addr;
238 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
239 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
241 if((*ptr&0xFF000000)==0xea000000) {
242 return (int)ptr+((*ptr<<8)>>6)+8; // follow jump
247 static int verify_dirty(u_int *ptr)
251 // get from literal pool
252 assert((*ptr&0xFFFF0000)==0xe59f0000);
254 u_int source=*(u_int*)((void *)ptr+offset+8);
256 assert((*ptr&0xFFFF0000)==0xe59f0000);
258 u_int copy=*(u_int*)((void *)ptr+offset+8);
260 assert((*ptr&0xFFFF0000)==0xe59f0000);
262 u_int len=*(u_int*)((void *)ptr+offset+8);
267 assert((*ptr&0xFFF00000)==0xe3000000);
268 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
269 u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
270 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
273 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
274 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
275 //printf("verify_dirty: %x %x %x\n",source,copy,len);
276 return !memcmp((void *)source,(void *)copy,len);
279 // This doesn't necessarily find all clean entry points, just
280 // guarantees that it's not dirty
281 static int isclean(int addr)
284 u_int *ptr=((u_int *)addr)+4;
286 u_int *ptr=((u_int *)addr)+6;
288 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
289 if((*ptr&0xFF000000)!=0xeb000000) return 1; // bl instruction
290 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code) return 0;
291 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_vm) return 0;
292 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_ds) return 0;
296 // get source that block at addr was compiled from (host pointers)
297 static void get_bounds(int addr,u_int *start,u_int *end)
299 u_int *ptr=(u_int *)addr;
302 // get from literal pool
303 assert((*ptr&0xFFFF0000)==0xe59f0000);
305 u_int source=*(u_int*)((void *)ptr+offset+8);
307 //assert((*ptr&0xFFFF0000)==0xe59f0000);
309 //u_int copy=*(u_int*)((void *)ptr+offset+8);
311 assert((*ptr&0xFFFF0000)==0xe59f0000);
313 u_int len=*(u_int*)((void *)ptr+offset+8);
318 assert((*ptr&0xFFF00000)==0xe3000000);
319 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
320 //u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
321 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
324 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
325 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
330 /* Register allocation */
332 // Note: registers are allocated clean (unmodified state)
333 // if you intend to modify the register, you must call dirty_reg().
334 static void alloc_reg(struct regstat *cur,int i,signed char reg)
337 int preferred_reg = (reg&7);
338 if(reg==CCREG) preferred_reg=HOST_CCREG;
339 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
341 // Don't allocate unused registers
342 if((cur->u>>reg)&1) return;
344 // see if it's already allocated
345 for(hr=0;hr<HOST_REGS;hr++)
347 if(cur->regmap[hr]==reg) return;
350 // Keep the same mapping if the register was already allocated in a loop
351 preferred_reg = loop_reg(i,reg,preferred_reg);
353 // Try to allocate the preferred register
354 if(cur->regmap[preferred_reg]==-1) {
355 cur->regmap[preferred_reg]=reg;
356 cur->dirty&=~(1<<preferred_reg);
357 cur->isconst&=~(1<<preferred_reg);
360 r=cur->regmap[preferred_reg];
361 if(r<64&&((cur->u>>r)&1)) {
362 cur->regmap[preferred_reg]=reg;
363 cur->dirty&=~(1<<preferred_reg);
364 cur->isconst&=~(1<<preferred_reg);
367 if(r>=64&&((cur->uu>>(r&63))&1)) {
368 cur->regmap[preferred_reg]=reg;
369 cur->dirty&=~(1<<preferred_reg);
370 cur->isconst&=~(1<<preferred_reg);
374 // Clear any unneeded registers
375 // We try to keep the mapping consistent, if possible, because it
376 // makes branches easier (especially loops). So we try to allocate
377 // first (see above) before removing old mappings. If this is not
378 // possible then go ahead and clear out the registers that are no
380 for(hr=0;hr<HOST_REGS;hr++)
385 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
389 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
393 // Try to allocate any available register, but prefer
394 // registers that have not been used recently.
396 for(hr=0;hr<HOST_REGS;hr++) {
397 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
398 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
400 cur->dirty&=~(1<<hr);
401 cur->isconst&=~(1<<hr);
407 // Try to allocate any available register
408 for(hr=0;hr<HOST_REGS;hr++) {
409 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
411 cur->dirty&=~(1<<hr);
412 cur->isconst&=~(1<<hr);
417 // Ok, now we have to evict someone
418 // Pick a register we hopefully won't need soon
419 u_char hsn[MAXREG+1];
420 memset(hsn,10,sizeof(hsn));
422 lsn(hsn,i,&preferred_reg);
423 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
424 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
426 // Don't evict the cycle count at entry points, otherwise the entry
427 // stub will have to write it.
428 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
429 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
432 // Alloc preferred register if available
433 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
434 for(hr=0;hr<HOST_REGS;hr++) {
435 // Evict both parts of a 64-bit register
436 if((cur->regmap[hr]&63)==r) {
438 cur->dirty&=~(1<<hr);
439 cur->isconst&=~(1<<hr);
442 cur->regmap[preferred_reg]=reg;
445 for(r=1;r<=MAXREG;r++)
447 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
448 for(hr=0;hr<HOST_REGS;hr++) {
449 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
450 if(cur->regmap[hr]==r+64) {
452 cur->dirty&=~(1<<hr);
453 cur->isconst&=~(1<<hr);
458 for(hr=0;hr<HOST_REGS;hr++) {
459 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
460 if(cur->regmap[hr]==r) {
462 cur->dirty&=~(1<<hr);
463 cur->isconst&=~(1<<hr);
474 for(r=1;r<=MAXREG;r++)
477 for(hr=0;hr<HOST_REGS;hr++) {
478 if(cur->regmap[hr]==r+64) {
480 cur->dirty&=~(1<<hr);
481 cur->isconst&=~(1<<hr);
485 for(hr=0;hr<HOST_REGS;hr++) {
486 if(cur->regmap[hr]==r) {
488 cur->dirty&=~(1<<hr);
489 cur->isconst&=~(1<<hr);
496 SysPrintf("This shouldn't happen (alloc_reg)");exit(1);
499 static void alloc_reg64(struct regstat *cur,int i,signed char reg)
501 int preferred_reg = 8+(reg&1);
504 // allocate the lower 32 bits
505 alloc_reg(cur,i,reg);
507 // Don't allocate unused registers
508 if((cur->uu>>reg)&1) return;
510 // see if the upper half is already allocated
511 for(hr=0;hr<HOST_REGS;hr++)
513 if(cur->regmap[hr]==reg+64) return;
516 // Keep the same mapping if the register was already allocated in a loop
517 preferred_reg = loop_reg(i,reg,preferred_reg);
519 // Try to allocate the preferred register
520 if(cur->regmap[preferred_reg]==-1) {
521 cur->regmap[preferred_reg]=reg|64;
522 cur->dirty&=~(1<<preferred_reg);
523 cur->isconst&=~(1<<preferred_reg);
526 r=cur->regmap[preferred_reg];
527 if(r<64&&((cur->u>>r)&1)) {
528 cur->regmap[preferred_reg]=reg|64;
529 cur->dirty&=~(1<<preferred_reg);
530 cur->isconst&=~(1<<preferred_reg);
533 if(r>=64&&((cur->uu>>(r&63))&1)) {
534 cur->regmap[preferred_reg]=reg|64;
535 cur->dirty&=~(1<<preferred_reg);
536 cur->isconst&=~(1<<preferred_reg);
540 // Clear any unneeded registers
541 // We try to keep the mapping consistent, if possible, because it
542 // makes branches easier (especially loops). So we try to allocate
543 // first (see above) before removing old mappings. If this is not
544 // possible then go ahead and clear out the registers that are no
546 for(hr=HOST_REGS-1;hr>=0;hr--)
551 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
555 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
559 // Try to allocate any available register, but prefer
560 // registers that have not been used recently.
562 for(hr=0;hr<HOST_REGS;hr++) {
563 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
564 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
565 cur->regmap[hr]=reg|64;
566 cur->dirty&=~(1<<hr);
567 cur->isconst&=~(1<<hr);
573 // Try to allocate any available register
574 for(hr=0;hr<HOST_REGS;hr++) {
575 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
576 cur->regmap[hr]=reg|64;
577 cur->dirty&=~(1<<hr);
578 cur->isconst&=~(1<<hr);
583 // Ok, now we have to evict someone
584 // Pick a register we hopefully won't need soon
585 u_char hsn[MAXREG+1];
586 memset(hsn,10,sizeof(hsn));
588 lsn(hsn,i,&preferred_reg);
589 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
590 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
592 // Don't evict the cycle count at entry points, otherwise the entry
593 // stub will have to write it.
594 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
595 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
598 // Alloc preferred register if available
599 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
600 for(hr=0;hr<HOST_REGS;hr++) {
601 // Evict both parts of a 64-bit register
602 if((cur->regmap[hr]&63)==r) {
604 cur->dirty&=~(1<<hr);
605 cur->isconst&=~(1<<hr);
608 cur->regmap[preferred_reg]=reg|64;
611 for(r=1;r<=MAXREG;r++)
613 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
614 for(hr=0;hr<HOST_REGS;hr++) {
615 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
616 if(cur->regmap[hr]==r+64) {
617 cur->regmap[hr]=reg|64;
618 cur->dirty&=~(1<<hr);
619 cur->isconst&=~(1<<hr);
624 for(hr=0;hr<HOST_REGS;hr++) {
625 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
626 if(cur->regmap[hr]==r) {
627 cur->regmap[hr]=reg|64;
628 cur->dirty&=~(1<<hr);
629 cur->isconst&=~(1<<hr);
640 for(r=1;r<=MAXREG;r++)
643 for(hr=0;hr<HOST_REGS;hr++) {
644 if(cur->regmap[hr]==r+64) {
645 cur->regmap[hr]=reg|64;
646 cur->dirty&=~(1<<hr);
647 cur->isconst&=~(1<<hr);
651 for(hr=0;hr<HOST_REGS;hr++) {
652 if(cur->regmap[hr]==r) {
653 cur->regmap[hr]=reg|64;
654 cur->dirty&=~(1<<hr);
655 cur->isconst&=~(1<<hr);
662 SysPrintf("This shouldn't happen");exit(1);
665 // Allocate a temporary register. This is done without regard to
666 // dirty status or whether the register we request is on the unneeded list
667 // Note: This will only allocate one register, even if called multiple times
668 static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
671 int preferred_reg = -1;
673 // see if it's already allocated
674 for(hr=0;hr<HOST_REGS;hr++)
676 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
679 // Try to allocate any available register
680 for(hr=HOST_REGS-1;hr>=0;hr--) {
681 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
683 cur->dirty&=~(1<<hr);
684 cur->isconst&=~(1<<hr);
689 // Find an unneeded register
690 for(hr=HOST_REGS-1;hr>=0;hr--)
696 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
698 cur->dirty&=~(1<<hr);
699 cur->isconst&=~(1<<hr);
706 if((cur->uu>>(r&63))&1) {
707 if(i==0||((unneeded_reg_upper[i-1]>>(r&63))&1)) {
709 cur->dirty&=~(1<<hr);
710 cur->isconst&=~(1<<hr);
718 // Ok, now we have to evict someone
719 // Pick a register we hopefully won't need soon
720 // TODO: we might want to follow unconditional jumps here
721 // TODO: get rid of dupe code and make this into a function
722 u_char hsn[MAXREG+1];
723 memset(hsn,10,sizeof(hsn));
725 lsn(hsn,i,&preferred_reg);
726 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
728 // Don't evict the cycle count at entry points, otherwise the entry
729 // stub will have to write it.
730 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
731 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
734 for(r=1;r<=MAXREG;r++)
736 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
737 for(hr=0;hr<HOST_REGS;hr++) {
738 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
739 if(cur->regmap[hr]==r+64) {
741 cur->dirty&=~(1<<hr);
742 cur->isconst&=~(1<<hr);
747 for(hr=0;hr<HOST_REGS;hr++) {
748 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
749 if(cur->regmap[hr]==r) {
751 cur->dirty&=~(1<<hr);
752 cur->isconst&=~(1<<hr);
763 for(r=1;r<=MAXREG;r++)
766 for(hr=0;hr<HOST_REGS;hr++) {
767 if(cur->regmap[hr]==r+64) {
769 cur->dirty&=~(1<<hr);
770 cur->isconst&=~(1<<hr);
774 for(hr=0;hr<HOST_REGS;hr++) {
775 if(cur->regmap[hr]==r) {
777 cur->dirty&=~(1<<hr);
778 cur->isconst&=~(1<<hr);
785 SysPrintf("This shouldn't happen");exit(1);
788 // Allocate a specific ARM register.
789 static void alloc_arm_reg(struct regstat *cur,int i,signed char reg,int hr)
794 // see if it's already allocated (and dealloc it)
795 for(n=0;n<HOST_REGS;n++)
797 if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {
798 dirty=(cur->dirty>>n)&1;
804 cur->dirty&=~(1<<hr);
805 cur->dirty|=dirty<<hr;
806 cur->isconst&=~(1<<hr);
809 // Alloc cycle count into dedicated register
810 static void alloc_cc(struct regstat *cur,int i)
812 alloc_arm_reg(cur,i,CCREG,HOST_CCREG);
820 static unused char regname[16][4] = {
838 static void output_w32(u_int word)
840 *((u_int *)out)=word;
844 static u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
849 return((rn<<16)|(rd<<12)|rm);
852 static u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
857 assert((shift&1)==0);
858 return((rn<<16)|(rd<<12)|(((32-shift)&30)<<7)|imm);
861 static u_int genimm(u_int imm,u_int *encoded)
869 *encoded=((i&30)<<7)|imm;
872 imm=(imm>>2)|(imm<<30);i-=2;
877 static void genimm_checked(u_int imm,u_int *encoded)
879 u_int ret=genimm(imm,encoded);
884 static u_int genjmp(u_int addr)
886 int offset=addr-(int)out-8;
887 if(offset<-33554432||offset>=33554432) {
889 SysPrintf("genjmp: out of range: %08x\n", offset);
894 return ((u_int)offset>>2)&0xffffff;
897 static void emit_mov(int rs,int rt)
899 assem_debug("mov %s,%s\n",regname[rt],regname[rs]);
900 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs));
903 static void emit_movs(int rs,int rt)
905 assem_debug("movs %s,%s\n",regname[rt],regname[rs]);
906 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs));
909 static void emit_add(int rs1,int rs2,int rt)
911 assem_debug("add %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
912 output_w32(0xe0800000|rd_rn_rm(rt,rs1,rs2));
915 static void emit_adds(int rs1,int rs2,int rt)
917 assem_debug("adds %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
918 output_w32(0xe0900000|rd_rn_rm(rt,rs1,rs2));
921 static void emit_adcs(int rs1,int rs2,int rt)
923 assem_debug("adcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
924 output_w32(0xe0b00000|rd_rn_rm(rt,rs1,rs2));
927 static void emit_sbc(int rs1,int rs2,int rt)
929 assem_debug("sbc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
930 output_w32(0xe0c00000|rd_rn_rm(rt,rs1,rs2));
933 static void emit_sbcs(int rs1,int rs2,int rt)
935 assem_debug("sbcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
936 output_w32(0xe0d00000|rd_rn_rm(rt,rs1,rs2));
939 static void emit_neg(int rs, int rt)
941 assem_debug("rsb %s,%s,#0\n",regname[rt],regname[rs]);
942 output_w32(0xe2600000|rd_rn_rm(rt,rs,0));
945 static void emit_negs(int rs, int rt)
947 assem_debug("rsbs %s,%s,#0\n",regname[rt],regname[rs]);
948 output_w32(0xe2700000|rd_rn_rm(rt,rs,0));
951 static void emit_sub(int rs1,int rs2,int rt)
953 assem_debug("sub %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
954 output_w32(0xe0400000|rd_rn_rm(rt,rs1,rs2));
957 static void emit_subs(int rs1,int rs2,int rt)
959 assem_debug("subs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
960 output_w32(0xe0500000|rd_rn_rm(rt,rs1,rs2));
963 static void emit_zeroreg(int rt)
965 assem_debug("mov %s,#0\n",regname[rt]);
966 output_w32(0xe3a00000|rd_rn_rm(rt,0,0));
969 static void emit_loadlp(u_int imm,u_int rt)
971 add_literal((int)out,imm);
972 assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm);
973 output_w32(0xe5900000|rd_rn_rm(rt,15,0));
976 static void emit_movw(u_int imm,u_int rt)
979 assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm);
980 output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000));
983 static void emit_movt(u_int imm,u_int rt)
985 assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
986 output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
989 static void emit_movimm(u_int imm,u_int rt)
992 if(genimm(imm,&armval)) {
993 assem_debug("mov %s,#%d\n",regname[rt],imm);
994 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
995 }else if(genimm(~imm,&armval)) {
996 assem_debug("mvn %s,#%d\n",regname[rt],imm);
997 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
998 }else if(imm<65536) {
1000 assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00);
1001 output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8));
1002 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1003 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1009 emit_loadlp(imm,rt);
1011 emit_movw(imm&0x0000FFFF,rt);
1012 emit_movt(imm&0xFFFF0000,rt);
1017 static void emit_pcreladdr(u_int rt)
1019 assem_debug("add %s,pc,#?\n",regname[rt]);
1020 output_w32(0xe2800000|rd_rn_rm(rt,15,0));
1023 static void emit_loadreg(int r, int hr)
1026 SysPrintf("64bit load in 32bit mode!\n");
1033 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1034 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1035 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1036 if(r==CCREG) addr=(int)&cycle_count;
1037 if(r==CSREG) addr=(int)&Status;
1038 if(r==FSREG) addr=(int)&FCR31;
1039 if(r==INVCP) addr=(int)&invc_ptr;
1040 u_int offset = addr-(u_int)&dynarec_local;
1041 assert(offset<4096);
1042 assem_debug("ldr %s,fp+%d\n",regname[hr],offset);
1043 output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
1047 static void emit_storereg(int r, int hr)
1050 SysPrintf("64bit store in 32bit mode!\n");
1054 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1055 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1056 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1057 if(r==CCREG) addr=(int)&cycle_count;
1058 if(r==FSREG) addr=(int)&FCR31;
1059 u_int offset = addr-(u_int)&dynarec_local;
1060 assert(offset<4096);
1061 assem_debug("str %s,fp+%d\n",regname[hr],offset);
1062 output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
1065 static void emit_test(int rs, int rt)
1067 assem_debug("tst %s,%s\n",regname[rs],regname[rt]);
1068 output_w32(0xe1100000|rd_rn_rm(0,rs,rt));
1071 static void emit_testimm(int rs,int imm)
1074 assem_debug("tst %s,#%d\n",regname[rs],imm);
1075 genimm_checked(imm,&armval);
1076 output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
1079 static void emit_testeqimm(int rs,int imm)
1082 assem_debug("tsteq %s,$%d\n",regname[rs],imm);
1083 genimm_checked(imm,&armval);
1084 output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
1087 static void emit_not(int rs,int rt)
1089 assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
1090 output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
1093 static void emit_mvnmi(int rs,int rt)
1095 assem_debug("mvnmi %s,%s\n",regname[rt],regname[rs]);
1096 output_w32(0x41e00000|rd_rn_rm(rt,0,rs));
1099 static void emit_and(u_int rs1,u_int rs2,u_int rt)
1101 assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1102 output_w32(0xe0000000|rd_rn_rm(rt,rs1,rs2));
1105 static void emit_or(u_int rs1,u_int rs2,u_int rt)
1107 assem_debug("orr %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1108 output_w32(0xe1800000|rd_rn_rm(rt,rs1,rs2));
1111 static void emit_or_and_set_flags(int rs1,int rs2,int rt)
1113 assem_debug("orrs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1114 output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
1117 static void emit_orrshl_imm(u_int rs,u_int imm,u_int rt)
1122 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs],imm);
1123 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|(imm<<7));
1126 static void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
1131 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs],imm);
1132 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs)|(imm<<7));
1135 static void emit_xor(u_int rs1,u_int rs2,u_int rt)
1137 assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1138 output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2));
1141 static void emit_addimm(u_int rs,int imm,u_int rt)
1147 if(genimm(imm,&armval)) {
1148 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm);
1149 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1150 }else if(genimm(-imm,&armval)) {
1151 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],-imm);
1152 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
1154 }else if(rt!=rs&&(u_int)imm<65536) {
1155 emit_movw(imm&0x0000ffff,rt);
1157 }else if(rt!=rs&&(u_int)-imm<65536) {
1158 emit_movw(-imm&0x0000ffff,rt);
1161 }else if((u_int)-imm<65536) {
1162 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],(-imm)&0xFF00);
1163 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1164 output_w32(0xe2400000|rd_rn_imm_shift(rt,rs,(-imm)>>8,8));
1165 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1168 int shift = (ffs(imm) - 1) & ~1;
1169 int imm8 = imm & (0xff << shift);
1170 genimm_checked(imm8,&armval);
1171 assem_debug("add %s,%s,#0x%x\n",regname[rt],regname[rs],imm8);
1172 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1179 else if(rs!=rt) emit_mov(rs,rt);
1182 static void emit_addimm_and_set_flags(int imm,int rt)
1184 assert(imm>-65536&&imm<65536);
1186 if(genimm(imm,&armval)) {
1187 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm);
1188 output_w32(0xe2900000|rd_rn_rm(rt,rt,0)|armval);
1189 }else if(genimm(-imm,&armval)) {
1190 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],imm);
1191 output_w32(0xe2500000|rd_rn_rm(rt,rt,0)|armval);
1193 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF00);
1194 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1195 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)>>8,8));
1196 output_w32(0xe2500000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1198 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF00);
1199 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1200 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm>>8,8));
1201 output_w32(0xe2900000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1205 static void emit_addimm_no_flags(u_int imm,u_int rt)
1207 emit_addimm(rt,imm,rt);
1210 static void emit_addnop(u_int r)
1213 assem_debug("add %s,%s,#0 (nop)\n",regname[r],regname[r]);
1214 output_w32(0xe2800000|rd_rn_rm(r,r,0));
1217 static void emit_adcimm(u_int rs,int imm,u_int rt)
1220 genimm_checked(imm,&armval);
1221 assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1222 output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
1225 static void emit_rscimm(int rs,int imm,u_int rt)
1229 genimm_checked(imm,&armval);
1230 assem_debug("rsc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1231 output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
1234 static void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
1236 // TODO: if(genimm(imm,&armval)) ...
1238 emit_movimm(imm,HOST_TEMPREG);
1239 emit_adds(HOST_TEMPREG,rsl,rtl);
1240 emit_adcimm(rsh,0,rth);
1243 static void emit_andimm(int rs,int imm,int rt)
1248 }else if(genimm(imm,&armval)) {
1249 assem_debug("and %s,%s,#%d\n",regname[rt],regname[rs],imm);
1250 output_w32(0xe2000000|rd_rn_rm(rt,rs,0)|armval);
1251 }else if(genimm(~imm,&armval)) {
1252 assem_debug("bic %s,%s,#%d\n",regname[rt],regname[rs],imm);
1253 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|armval);
1254 }else if(imm==65535) {
1256 assem_debug("bic %s,%s,#FF000000\n",regname[rt],regname[rs]);
1257 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|0x4FF);
1258 assem_debug("bic %s,%s,#00FF0000\n",regname[rt],regname[rt]);
1259 output_w32(0xe3c00000|rd_rn_rm(rt,rt,0)|0x8FF);
1261 assem_debug("uxth %s,%s\n",regname[rt],regname[rs]);
1262 output_w32(0xe6ff0070|rd_rn_rm(rt,0,rs));
1265 assert(imm>0&&imm<65535);
1267 assem_debug("mov r14,#%d\n",imm&0xFF00);
1268 output_w32(0xe3a00000|rd_rn_imm_shift(HOST_TEMPREG,0,imm>>8,8));
1269 assem_debug("add r14,r14,#%d\n",imm&0xFF);
1270 output_w32(0xe2800000|rd_rn_imm_shift(HOST_TEMPREG,HOST_TEMPREG,imm&0xff,0));
1272 emit_movw(imm,HOST_TEMPREG);
1274 assem_debug("and %s,%s,r14\n",regname[rt],regname[rs]);
1275 output_w32(0xe0000000|rd_rn_rm(rt,rs,HOST_TEMPREG));
1279 static void emit_orimm(int rs,int imm,int rt)
1283 if(rs!=rt) emit_mov(rs,rt);
1284 }else if(genimm(imm,&armval)) {
1285 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1286 output_w32(0xe3800000|rd_rn_rm(rt,rs,0)|armval);
1288 assert(imm>0&&imm<65536);
1289 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1290 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1291 output_w32(0xe3800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1292 output_w32(0xe3800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1296 static void emit_xorimm(int rs,int imm,int rt)
1300 if(rs!=rt) emit_mov(rs,rt);
1301 }else if(genimm(imm,&armval)) {
1302 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm);
1303 output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval);
1305 assert(imm>0&&imm<65536);
1306 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1307 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1308 output_w32(0xe2200000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1309 output_w32(0xe2200000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1313 static void emit_shlimm(int rs,u_int imm,int rt)
1318 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1319 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1322 static void emit_lsls_imm(int rs,int imm,int rt)
1326 assem_debug("lsls %s,%s,#%d\n",regname[rt],regname[rs],imm);
1327 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1330 static unused void emit_lslpls_imm(int rs,int imm,int rt)
1334 assem_debug("lslpls %s,%s,#%d\n",regname[rt],regname[rs],imm);
1335 output_w32(0x51b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1338 static void emit_shrimm(int rs,u_int imm,int rt)
1342 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1343 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
1346 static void emit_sarimm(int rs,u_int imm,int rt)
1350 assem_debug("asr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1351 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x40|(imm<<7));
1354 static void emit_rorimm(int rs,u_int imm,int rt)
1358 assem_debug("ror %s,%s,#%d\n",regname[rt],regname[rs],imm);
1359 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x60|(imm<<7));
1362 static void emit_shldimm(int rs,int rs2,u_int imm,int rt)
1364 assem_debug("shld %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1368 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1369 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1370 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1371 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1374 static void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
1376 assem_debug("shrd %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1380 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1381 output_w32(0xe1a00020|rd_rn_rm(rt,0,rs)|(imm<<7));
1382 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1383 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1386 static void emit_signextend16(int rs,int rt)
1389 emit_shlimm(rs,16,rt);
1390 emit_sarimm(rt,16,rt);
1392 assem_debug("sxth %s,%s\n",regname[rt],regname[rs]);
1393 output_w32(0xe6bf0070|rd_rn_rm(rt,0,rs));
1397 static void emit_signextend8(int rs,int rt)
1400 emit_shlimm(rs,24,rt);
1401 emit_sarimm(rt,24,rt);
1403 assem_debug("sxtb %s,%s\n",regname[rt],regname[rs]);
1404 output_w32(0xe6af0070|rd_rn_rm(rt,0,rs));
1408 static void emit_shl(u_int rs,u_int shift,u_int rt)
1414 assem_debug("lsl %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1415 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x10|(shift<<8));
1418 static void emit_shr(u_int rs,u_int shift,u_int rt)
1423 assem_debug("lsr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1424 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x30|(shift<<8));
1427 static void emit_sar(u_int rs,u_int shift,u_int rt)
1432 assem_debug("asr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1433 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x50|(shift<<8));
1436 static void emit_orrshl(u_int rs,u_int shift,u_int rt)
1441 assem_debug("orr %s,%s,%s,lsl %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1442 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x10|(shift<<8));
1445 static void emit_orrshr(u_int rs,u_int shift,u_int rt)
1450 assem_debug("orr %s,%s,%s,lsr %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1451 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x30|(shift<<8));
1454 static void emit_cmpimm(int rs,int imm)
1457 if(genimm(imm,&armval)) {
1458 assem_debug("cmp %s,#%d\n",regname[rs],imm);
1459 output_w32(0xe3500000|rd_rn_rm(0,rs,0)|armval);
1460 }else if(genimm(-imm,&armval)) {
1461 assem_debug("cmn %s,#%d\n",regname[rs],imm);
1462 output_w32(0xe3700000|rd_rn_rm(0,rs,0)|armval);
1465 emit_movimm(imm,HOST_TEMPREG);
1466 assem_debug("cmp %s,r14\n",regname[rs]);
1467 output_w32(0xe1500000|rd_rn_rm(0,rs,HOST_TEMPREG));
1470 emit_movimm(-imm,HOST_TEMPREG);
1471 assem_debug("cmn %s,r14\n",regname[rs]);
1472 output_w32(0xe1700000|rd_rn_rm(0,rs,HOST_TEMPREG));
1476 static void emit_cmovne_imm(int imm,int rt)
1478 assem_debug("movne %s,#%d\n",regname[rt],imm);
1480 genimm_checked(imm,&armval);
1481 output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
1484 static void emit_cmovl_imm(int imm,int rt)
1486 assem_debug("movlt %s,#%d\n",regname[rt],imm);
1488 genimm_checked(imm,&armval);
1489 output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
1492 static void emit_cmovb_imm(int imm,int rt)
1494 assem_debug("movcc %s,#%d\n",regname[rt],imm);
1496 genimm_checked(imm,&armval);
1497 output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
1500 static void emit_cmovs_imm(int imm,int rt)
1502 assem_debug("movmi %s,#%d\n",regname[rt],imm);
1504 genimm_checked(imm,&armval);
1505 output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
1508 static void emit_cmove_reg(int rs,int rt)
1510 assem_debug("moveq %s,%s\n",regname[rt],regname[rs]);
1511 output_w32(0x01a00000|rd_rn_rm(rt,0,rs));
1514 static void emit_cmovne_reg(int rs,int rt)
1516 assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
1517 output_w32(0x11a00000|rd_rn_rm(rt,0,rs));
1520 static void emit_cmovl_reg(int rs,int rt)
1522 assem_debug("movlt %s,%s\n",regname[rt],regname[rs]);
1523 output_w32(0xb1a00000|rd_rn_rm(rt,0,rs));
1526 static void emit_cmovs_reg(int rs,int rt)
1528 assem_debug("movmi %s,%s\n",regname[rt],regname[rs]);
1529 output_w32(0x41a00000|rd_rn_rm(rt,0,rs));
1532 static void emit_slti32(int rs,int imm,int rt)
1534 if(rs!=rt) emit_zeroreg(rt);
1535 emit_cmpimm(rs,imm);
1536 if(rs==rt) emit_movimm(0,rt);
1537 emit_cmovl_imm(1,rt);
1540 static void emit_sltiu32(int rs,int imm,int rt)
1542 if(rs!=rt) emit_zeroreg(rt);
1543 emit_cmpimm(rs,imm);
1544 if(rs==rt) emit_movimm(0,rt);
1545 emit_cmovb_imm(1,rt);
1548 static void emit_slti64_32(int rsh,int rsl,int imm,int rt)
1551 emit_slti32(rsl,imm,rt);
1555 emit_cmovne_imm(0,rt);
1556 emit_cmovs_imm(1,rt);
1560 emit_cmpimm(rsh,-1);
1561 emit_cmovne_imm(0,rt);
1562 emit_cmovl_imm(1,rt);
1566 static void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
1569 emit_sltiu32(rsl,imm,rt);
1573 emit_cmovne_imm(0,rt);
1577 emit_cmpimm(rsh,-1);
1578 emit_cmovne_imm(1,rt);
1582 static void emit_cmp(int rs,int rt)
1584 assem_debug("cmp %s,%s\n",regname[rs],regname[rt]);
1585 output_w32(0xe1500000|rd_rn_rm(0,rs,rt));
1588 static void emit_set_gz32(int rs, int rt)
1590 //assem_debug("set_gz32\n");
1593 emit_cmovl_imm(0,rt);
1596 static void emit_set_nz32(int rs, int rt)
1598 //assem_debug("set_nz32\n");
1599 if(rs!=rt) emit_movs(rs,rt);
1600 else emit_test(rs,rs);
1601 emit_cmovne_imm(1,rt);
1604 static void emit_set_gz64_32(int rsh, int rsl, int rt)
1606 //assem_debug("set_gz64\n");
1607 emit_set_gz32(rsl,rt);
1609 emit_cmovne_imm(1,rt);
1610 emit_cmovs_imm(0,rt);
1613 static void emit_set_nz64_32(int rsh, int rsl, int rt)
1615 //assem_debug("set_nz64\n");
1616 emit_or_and_set_flags(rsh,rsl,rt);
1617 emit_cmovne_imm(1,rt);
1620 static void emit_set_if_less32(int rs1, int rs2, int rt)
1622 //assem_debug("set if less (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1623 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1625 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1626 emit_cmovl_imm(1,rt);
1629 static void emit_set_if_carry32(int rs1, int rs2, int rt)
1631 //assem_debug("set if carry (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1632 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1634 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1635 emit_cmovb_imm(1,rt);
1638 static void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
1640 //assem_debug("set if less64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1645 emit_sbcs(u1,u2,HOST_TEMPREG);
1646 emit_cmovl_imm(1,rt);
1649 static void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
1651 //assem_debug("set if carry64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1656 emit_sbcs(u1,u2,HOST_TEMPREG);
1657 emit_cmovb_imm(1,rt);
1661 extern void gen_interupt();
1662 extern void do_insn_cmp();
1663 #define FUNCNAME(f) { (intptr_t)f, " " #f }
1664 static const struct {
1667 } function_names[] = {
1668 FUNCNAME(cc_interrupt),
1669 FUNCNAME(gen_interupt),
1670 FUNCNAME(get_addr_ht),
1672 FUNCNAME(jump_handler_read8),
1673 FUNCNAME(jump_handler_read16),
1674 FUNCNAME(jump_handler_read32),
1675 FUNCNAME(jump_handler_write8),
1676 FUNCNAME(jump_handler_write16),
1677 FUNCNAME(jump_handler_write32),
1678 FUNCNAME(invalidate_addr),
1679 FUNCNAME(verify_code_vm),
1680 FUNCNAME(verify_code),
1681 FUNCNAME(jump_hlecall),
1682 FUNCNAME(jump_syscall_hle),
1683 FUNCNAME(new_dyna_leave),
1684 FUNCNAME(pcsx_mtc0),
1685 FUNCNAME(pcsx_mtc0_ds),
1686 FUNCNAME(do_insn_cmp),
1689 static const char *func_name(intptr_t a)
1692 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
1693 if (function_names[i].addr == a)
1694 return function_names[i].name;
1698 #define func_name(x) ""
1701 static void emit_call(int a)
1703 assem_debug("bl %x (%x+%x)%s\n",a,(int)out,a-(int)out-8,func_name(a));
1704 u_int offset=genjmp(a);
1705 output_w32(0xeb000000|offset);
1708 static void emit_jmp(int a)
1710 assem_debug("b %x (%x+%x)%s\n",a,(int)out,a-(int)out-8,func_name(a));
1711 u_int offset=genjmp(a);
1712 output_w32(0xea000000|offset);
1715 static void emit_jne(int a)
1717 assem_debug("bne %x\n",a);
1718 u_int offset=genjmp(a);
1719 output_w32(0x1a000000|offset);
1722 static void emit_jeq(int a)
1724 assem_debug("beq %x\n",a);
1725 u_int offset=genjmp(a);
1726 output_w32(0x0a000000|offset);
1729 static void emit_js(int a)
1731 assem_debug("bmi %x\n",a);
1732 u_int offset=genjmp(a);
1733 output_w32(0x4a000000|offset);
1736 static void emit_jns(int a)
1738 assem_debug("bpl %x\n",a);
1739 u_int offset=genjmp(a);
1740 output_w32(0x5a000000|offset);
1743 static void emit_jl(int a)
1745 assem_debug("blt %x\n",a);
1746 u_int offset=genjmp(a);
1747 output_w32(0xba000000|offset);
1750 static void emit_jge(int a)
1752 assem_debug("bge %x\n",a);
1753 u_int offset=genjmp(a);
1754 output_w32(0xaa000000|offset);
1757 static void emit_jno(int a)
1759 assem_debug("bvc %x\n",a);
1760 u_int offset=genjmp(a);
1761 output_w32(0x7a000000|offset);
1764 static void emit_jc(int a)
1766 assem_debug("bcs %x\n",a);
1767 u_int offset=genjmp(a);
1768 output_w32(0x2a000000|offset);
1771 static void emit_jcc(int a)
1773 assem_debug("bcc %x\n",a);
1774 u_int offset=genjmp(a);
1775 output_w32(0x3a000000|offset);
1778 static void emit_callreg(u_int r)
1781 assem_debug("blx %s\n",regname[r]);
1782 output_w32(0xe12fff30|r);
1785 static void emit_jmpreg(u_int r)
1787 assem_debug("mov pc,%s\n",regname[r]);
1788 output_w32(0xe1a00000|rd_rn_rm(15,0,r));
1791 static void emit_readword_indexed(int offset, int rs, int rt)
1793 assert(offset>-4096&&offset<4096);
1794 assem_debug("ldr %s,%s+%d\n",regname[rt],regname[rs],offset);
1796 output_w32(0xe5900000|rd_rn_rm(rt,rs,0)|offset);
1798 output_w32(0xe5100000|rd_rn_rm(rt,rs,0)|(-offset));
1802 static void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
1804 assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1805 output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
1808 static void emit_ldrcc_dualindexed(int rs1, int rs2, int rt)
1810 assem_debug("ldrcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1811 output_w32(0x37900000|rd_rn_rm(rt,rs1,rs2));
1814 static void emit_ldrccb_dualindexed(int rs1, int rs2, int rt)
1816 assem_debug("ldrccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1817 output_w32(0x37d00000|rd_rn_rm(rt,rs1,rs2));
1820 static void emit_ldrccsb_dualindexed(int rs1, int rs2, int rt)
1822 assem_debug("ldrccsb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1823 output_w32(0x319000d0|rd_rn_rm(rt,rs1,rs2));
1826 static void emit_ldrcch_dualindexed(int rs1, int rs2, int rt)
1828 assem_debug("ldrcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1829 output_w32(0x319000b0|rd_rn_rm(rt,rs1,rs2));
1832 static void emit_ldrccsh_dualindexed(int rs1, int rs2, int rt)
1834 assem_debug("ldrccsh %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1835 output_w32(0x319000f0|rd_rn_rm(rt,rs1,rs2));
1838 static void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
1840 if(map<0) emit_readword_indexed(addr, rs, rt);
1843 emit_readword_dualindexedx4(rs, map, rt);
1847 static void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
1850 if(rh>=0) emit_readword_indexed(addr, rs, rh);
1851 emit_readword_indexed(addr+4, rs, rl);
1854 if(rh>=0) emit_readword_indexed_tlb(addr, rs, map, rh);
1855 emit_addimm(map,1,map);
1856 emit_readword_indexed_tlb(addr, rs, map, rl);
1860 static void emit_movsbl_indexed(int offset, int rs, int rt)
1862 assert(offset>-256&&offset<256);
1863 assem_debug("ldrsb %s,%s+%d\n",regname[rt],regname[rs],offset);
1865 output_w32(0xe1d000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1867 output_w32(0xe15000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1871 static void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
1873 if(map<0) emit_movsbl_indexed(addr, rs, rt);
1876 emit_shlimm(map,2,map);
1877 assem_debug("ldrsb %s,%s+%s\n",regname[rt],regname[rs],regname[map]);
1878 output_w32(0xe19000d0|rd_rn_rm(rt,rs,map));
1880 assert(addr>-256&&addr<256);
1881 assem_debug("add %s,%s,%s,lsl #2\n",regname[rt],regname[rs],regname[map]);
1882 output_w32(0xe0800000|rd_rn_rm(rt,rs,map)|(2<<7));
1883 emit_movsbl_indexed(addr, rt, rt);
1888 static void emit_movswl_indexed(int offset, int rs, int rt)
1890 assert(offset>-256&&offset<256);
1891 assem_debug("ldrsh %s,%s+%d\n",regname[rt],regname[rs],offset);
1893 output_w32(0xe1d000f0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1895 output_w32(0xe15000f0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1899 static void emit_movzbl_indexed(int offset, int rs, int rt)
1901 assert(offset>-4096&&offset<4096);
1902 assem_debug("ldrb %s,%s+%d\n",regname[rt],regname[rs],offset);
1904 output_w32(0xe5d00000|rd_rn_rm(rt,rs,0)|offset);
1906 output_w32(0xe5500000|rd_rn_rm(rt,rs,0)|(-offset));
1910 static void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
1912 assem_debug("ldrb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1913 output_w32(0xe7d00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1916 static void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
1918 if(map<0) emit_movzbl_indexed(addr, rs, rt);
1921 emit_movzbl_dualindexedx4(rs, map, rt);
1923 emit_addimm(rs,addr,rt);
1924 emit_movzbl_dualindexedx4(rt, map, rt);
1929 static void emit_movzwl_indexed(int offset, int rs, int rt)
1931 assert(offset>-256&&offset<256);
1932 assem_debug("ldrh %s,%s+%d\n",regname[rt],regname[rs],offset);
1934 output_w32(0xe1d000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1936 output_w32(0xe15000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1940 static void emit_ldrd(int offset, int rs, int rt)
1942 assert(offset>-256&&offset<256);
1943 assem_debug("ldrd %s,%s+%d\n",regname[rt],regname[rs],offset);
1945 output_w32(0xe1c000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1947 output_w32(0xe14000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1951 static void emit_readword(int addr, int rt)
1953 u_int offset = addr-(u_int)&dynarec_local;
1954 assert(offset<4096);
1955 assem_debug("ldr %s,fp+%d\n",regname[rt],offset);
1956 output_w32(0xe5900000|rd_rn_rm(rt,FP,0)|offset);
1959 static unused void emit_movsbl(int addr, int rt)
1961 u_int offset = addr-(u_int)&dynarec_local;
1963 assem_debug("ldrsb %s,fp+%d\n",regname[rt],offset);
1964 output_w32(0xe1d000d0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1967 static unused void emit_movswl(int addr, int rt)
1969 u_int offset = addr-(u_int)&dynarec_local;
1971 assem_debug("ldrsh %s,fp+%d\n",regname[rt],offset);
1972 output_w32(0xe1d000f0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1975 static unused void emit_movzbl(int addr, int rt)
1977 u_int offset = addr-(u_int)&dynarec_local;
1978 assert(offset<4096);
1979 assem_debug("ldrb %s,fp+%d\n",regname[rt],offset);
1980 output_w32(0xe5d00000|rd_rn_rm(rt,FP,0)|offset);
1983 static unused void emit_movzwl(int addr, int rt)
1985 u_int offset = addr-(u_int)&dynarec_local;
1987 assem_debug("ldrh %s,fp+%d\n",regname[rt],offset);
1988 output_w32(0xe1d000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1991 static void emit_writeword_indexed(int rt, int offset, int rs)
1993 assert(offset>-4096&&offset<4096);
1994 assem_debug("str %s,%s+%d\n",regname[rt],regname[rs],offset);
1996 output_w32(0xe5800000|rd_rn_rm(rt,rs,0)|offset);
1998 output_w32(0xe5000000|rd_rn_rm(rt,rs,0)|(-offset));
2002 static void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
2004 assem_debug("str %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
2005 output_w32(0xe7800000|rd_rn_rm(rt,rs1,rs2)|0x100);
2008 static void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
2010 if(map<0) emit_writeword_indexed(rt, addr, rs);
2013 emit_writeword_dualindexedx4(rt, rs, map);
2017 static void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
2020 if(rh>=0) emit_writeword_indexed(rh, addr, rs);
2021 emit_writeword_indexed(rl, addr+4, rs);
2024 if(temp!=rs) emit_addimm(map,1,temp);
2025 emit_writeword_indexed_tlb(rh, addr, rs, map, temp);
2026 if(temp!=rs) emit_writeword_indexed_tlb(rl, addr, rs, temp, temp);
2028 emit_addimm(rs,4,rs);
2029 emit_writeword_indexed_tlb(rl, addr, rs, map, temp);
2034 static void emit_writehword_indexed(int rt, int offset, int rs)
2036 assert(offset>-256&&offset<256);
2037 assem_debug("strh %s,%s+%d\n",regname[rt],regname[rs],offset);
2039 output_w32(0xe1c000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
2041 output_w32(0xe14000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
2045 static void emit_writebyte_indexed(int rt, int offset, int rs)
2047 assert(offset>-4096&&offset<4096);
2048 assem_debug("strb %s,%s+%d\n",regname[rt],regname[rs],offset);
2050 output_w32(0xe5c00000|rd_rn_rm(rt,rs,0)|offset);
2052 output_w32(0xe5400000|rd_rn_rm(rt,rs,0)|(-offset));
2056 static void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
2058 assem_debug("strb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
2059 output_w32(0xe7c00000|rd_rn_rm(rt,rs1,rs2)|0x100);
2062 static void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
2064 if(map<0) emit_writebyte_indexed(rt, addr, rs);
2067 emit_writebyte_dualindexedx4(rt, rs, map);
2069 emit_addimm(rs,addr,temp);
2070 emit_writebyte_dualindexedx4(rt, temp, map);
2075 static void emit_strcc_dualindexed(int rs1, int rs2, int rt)
2077 assem_debug("strcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2078 output_w32(0x37800000|rd_rn_rm(rt,rs1,rs2));
2081 static void emit_strccb_dualindexed(int rs1, int rs2, int rt)
2083 assem_debug("strccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2084 output_w32(0x37c00000|rd_rn_rm(rt,rs1,rs2));
2087 static void emit_strcch_dualindexed(int rs1, int rs2, int rt)
2089 assem_debug("strcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2090 output_w32(0x318000b0|rd_rn_rm(rt,rs1,rs2));
2093 static void emit_writeword(int rt, int addr)
2095 u_int offset = addr-(u_int)&dynarec_local;
2096 assert(offset<4096);
2097 assem_debug("str %s,fp+%d\n",regname[rt],offset);
2098 output_w32(0xe5800000|rd_rn_rm(rt,FP,0)|offset);
2101 static unused void emit_writehword(int rt, int addr)
2103 u_int offset = addr-(u_int)&dynarec_local;
2105 assem_debug("strh %s,fp+%d\n",regname[rt],offset);
2106 output_w32(0xe1c000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
2109 static unused void emit_writebyte(int rt, int addr)
2111 u_int offset = addr-(u_int)&dynarec_local;
2112 assert(offset<4096);
2113 assem_debug("strb %s,fp+%d\n",regname[rt],offset);
2114 output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
2117 static void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2119 assem_debug("umull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2124 output_w32(0xe0800090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2127 static void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2129 assem_debug("smull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2134 output_w32(0xe0c00090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2137 static void emit_clz(int rs,int rt)
2139 assem_debug("clz %s,%s\n",regname[rt],regname[rs]);
2140 output_w32(0xe16f0f10|rd_rn_rm(rt,0,rs));
2143 static void emit_subcs(int rs1,int rs2,int rt)
2145 assem_debug("subcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2146 output_w32(0x20400000|rd_rn_rm(rt,rs1,rs2));
2149 static void emit_shrcc_imm(int rs,u_int imm,int rt)
2153 assem_debug("lsrcc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2154 output_w32(0x31a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2157 static void emit_shrne_imm(int rs,u_int imm,int rt)
2161 assem_debug("lsrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2162 output_w32(0x11a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2165 static void emit_negmi(int rs, int rt)
2167 assem_debug("rsbmi %s,%s,#0\n",regname[rt],regname[rs]);
2168 output_w32(0x42600000|rd_rn_rm(rt,rs,0));
2171 static void emit_negsmi(int rs, int rt)
2173 assem_debug("rsbsmi %s,%s,#0\n",regname[rt],regname[rs]);
2174 output_w32(0x42700000|rd_rn_rm(rt,rs,0));
2177 static void emit_orreq(u_int rs1,u_int rs2,u_int rt)
2179 assem_debug("orreq %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2180 output_w32(0x01800000|rd_rn_rm(rt,rs1,rs2));
2183 static void emit_orrne(u_int rs1,u_int rs2,u_int rt)
2185 assem_debug("orrne %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2186 output_w32(0x11800000|rd_rn_rm(rt,rs1,rs2));
2189 static void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2191 assem_debug("bic %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2192 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2195 static void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2197 assem_debug("biceq %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2198 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2201 static void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2203 assem_debug("bicne %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2204 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2207 static void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2209 assem_debug("bic %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2210 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2213 static void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2215 assem_debug("biceq %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2216 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2219 static void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2221 assem_debug("bicne %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2222 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2225 static void emit_teq(int rs, int rt)
2227 assem_debug("teq %s,%s\n",regname[rs],regname[rt]);
2228 output_w32(0xe1300000|rd_rn_rm(0,rs,rt));
2231 static void emit_rsbimm(int rs, int imm, int rt)
2234 genimm_checked(imm,&armval);
2235 assem_debug("rsb %s,%s,#%d\n",regname[rt],regname[rs],imm);
2236 output_w32(0xe2600000|rd_rn_rm(rt,rs,0)|armval);
2239 // Load 2 immediates optimizing for small code size
2240 static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
2242 emit_movimm(imm1,rt1);
2244 if(genimm(imm2-imm1,&armval)) {
2245 assem_debug("add %s,%s,#%d\n",regname[rt2],regname[rt1],imm2-imm1);
2246 output_w32(0xe2800000|rd_rn_rm(rt2,rt1,0)|armval);
2247 }else if(genimm(imm1-imm2,&armval)) {
2248 assem_debug("sub %s,%s,#%d\n",regname[rt2],regname[rt1],imm1-imm2);
2249 output_w32(0xe2400000|rd_rn_rm(rt2,rt1,0)|armval);
2251 else emit_movimm(imm2,rt2);
2254 // Conditionally select one of two immediates, optimizing for small code size
2255 // This will only be called if HAVE_CMOV_IMM is defined
2256 static void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
2259 if(genimm(imm2-imm1,&armval)) {
2260 emit_movimm(imm1,rt);
2261 assem_debug("addne %s,%s,#%d\n",regname[rt],regname[rt],imm2-imm1);
2262 output_w32(0x12800000|rd_rn_rm(rt,rt,0)|armval);
2263 }else if(genimm(imm1-imm2,&armval)) {
2264 emit_movimm(imm1,rt);
2265 assem_debug("subne %s,%s,#%d\n",regname[rt],regname[rt],imm1-imm2);
2266 output_w32(0x12400000|rd_rn_rm(rt,rt,0)|armval);
2270 emit_movimm(imm1,rt);
2271 add_literal((int)out,imm2);
2272 assem_debug("ldrne %s,pc+? [=%x]\n",regname[rt],imm2);
2273 output_w32(0x15900000|rd_rn_rm(rt,15,0));
2275 emit_movw(imm1&0x0000FFFF,rt);
2276 if((imm1&0xFFFF)!=(imm2&0xFFFF)) {
2277 assem_debug("movwne %s,#%d (0x%x)\n",regname[rt],imm2&0xFFFF,imm2&0xFFFF);
2278 output_w32(0x13000000|rd_rn_rm(rt,0,0)|(imm2&0xfff)|((imm2<<4)&0xf0000));
2280 emit_movt(imm1&0xFFFF0000,rt);
2281 if((imm1&0xFFFF0000)!=(imm2&0xFFFF0000)) {
2282 assem_debug("movtne %s,#%d (0x%x)\n",regname[rt],imm2&0xffff0000,imm2&0xffff0000);
2283 output_w32(0x13400000|rd_rn_rm(rt,0,0)|((imm2>>16)&0xfff)|((imm2>>12)&0xf0000));
2289 // special case for checking invalid_code
2290 static void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
2292 assert(imm<128&&imm>=0);
2294 assem_debug("ldrb lr,%s,%s lsr #12\n",regname[base],regname[r]);
2295 output_w32(0xe7d00000|rd_rn_rm(HOST_TEMPREG,base,r)|0x620);
2296 emit_cmpimm(HOST_TEMPREG,imm);
2299 static void emit_callne(int a)
2301 assem_debug("blne %x\n",a);
2302 u_int offset=genjmp(a);
2303 output_w32(0x1b000000|offset);
2306 // Used to preload hash table entries
2307 static unused void emit_prefetchreg(int r)
2309 assem_debug("pld %s\n",regname[r]);
2310 output_w32(0xf5d0f000|rd_rn_rm(0,r,0));
2313 // Special case for mini_ht
2314 static void emit_ldreq_indexed(int rs, u_int offset, int rt)
2316 assert(offset<4096);
2317 assem_debug("ldreq %s,[%s, #%d]\n",regname[rt],regname[rs],offset);
2318 output_w32(0x05900000|rd_rn_rm(rt,rs,0)|offset);
2321 static unused void emit_bicne_imm(int rs,int imm,int rt)
2324 genimm_checked(imm,&armval);
2325 assem_debug("bicne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2326 output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
2329 static unused void emit_biccs_imm(int rs,int imm,int rt)
2332 genimm_checked(imm,&armval);
2333 assem_debug("biccs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2334 output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
2337 static unused void emit_bicvc_imm(int rs,int imm,int rt)
2340 genimm_checked(imm,&armval);
2341 assem_debug("bicvc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2342 output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
2345 static unused void emit_bichi_imm(int rs,int imm,int rt)
2348 genimm_checked(imm,&armval);
2349 assem_debug("bichi %s,%s,#%d\n",regname[rt],regname[rs],imm);
2350 output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
2353 static unused void emit_orrvs_imm(int rs,int imm,int rt)
2356 genimm_checked(imm,&armval);
2357 assem_debug("orrvs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2358 output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
2361 static void emit_orrne_imm(int rs,int imm,int rt)
2364 genimm_checked(imm,&armval);
2365 assem_debug("orrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2366 output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
2369 static void emit_andne_imm(int rs,int imm,int rt)
2372 genimm_checked(imm,&armval);
2373 assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2374 output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
2377 static unused void emit_addpl_imm(int rs,int imm,int rt)
2380 genimm_checked(imm,&armval);
2381 assem_debug("addpl %s,%s,#%d\n",regname[rt],regname[rs],imm);
2382 output_w32(0x52800000|rd_rn_rm(rt,rs,0)|armval);
2385 static void emit_jno_unlikely(int a)
2388 assem_debug("addvc pc,pc,#? (%x)\n",/*a-(int)out-8,*/a);
2389 output_w32(0x72800000|rd_rn_rm(15,15,0));
2392 static void save_regs_all(u_int reglist)
2395 if(!reglist) return;
2396 assem_debug("stmia fp,{");
2399 assem_debug("r%d,",i);
2401 output_w32(0xe88b0000|reglist);
2404 static void restore_regs_all(u_int reglist)
2407 if(!reglist) return;
2408 assem_debug("ldmia fp,{");
2411 assem_debug("r%d,",i);
2413 output_w32(0xe89b0000|reglist);
2416 // Save registers before function call
2417 static void save_regs(u_int reglist)
2419 reglist&=CALLER_SAVE_REGS; // only save the caller-save registers, r0-r3, r12
2420 save_regs_all(reglist);
2423 // Restore registers after function call
2424 static void restore_regs(u_int reglist)
2426 reglist&=CALLER_SAVE_REGS;
2427 restore_regs_all(reglist);
2430 /* Stubs/epilogue */
2432 static void literal_pool(int n)
2434 if(!literalcount) return;
2436 if((int)out-literals[0][0]<4096-n) return;
2440 for(i=0;i<literalcount;i++)
2442 u_int l_addr=(u_int)out;
2445 if(literals[j][1]==literals[i][1]) {
2446 //printf("dup %08x\n",literals[i][1]);
2447 l_addr=literals[j][0];
2451 ptr=(u_int *)literals[i][0];
2452 u_int offset=l_addr-(u_int)ptr-8;
2453 assert(offset<4096);
2454 assert(!(offset&3));
2456 if(l_addr==(u_int)out) {
2457 literals[i][0]=l_addr; // remember for dupes
2458 output_w32(literals[i][1]);
2464 static void literal_pool_jumpover(int n)
2466 if(!literalcount) return;
2468 if((int)out-literals[0][0]<4096-n) return;
2473 set_jump_target(jaddr,(int)out);
2476 static void emit_extjump2(u_int addr, int target, int linker)
2478 u_char *ptr=(u_char *)addr;
2479 assert((ptr[3]&0x0e)==0xa);
2482 emit_loadlp(target,0);
2483 emit_loadlp(addr,1);
2484 assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
2485 //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
2487 #ifdef DEBUG_CYCLE_COUNT
2488 emit_readword((int)&last_count,ECX);
2489 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2490 emit_readword((int)&next_interupt,ECX);
2491 emit_writeword(HOST_CCREG,(int)&Count);
2492 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
2493 emit_writeword(ECX,(int)&last_count);
2499 static void emit_extjump(int addr, int target)
2501 emit_extjump2(addr, target, (int)dyna_linker);
2504 static void emit_extjump_ds(int addr, int target)
2506 emit_extjump2(addr, target, (int)dyna_linker_ds);
2509 // put rt_val into rt, potentially making use of rs with value rs_val
2510 static void emit_movimm_from(u_int rs_val,int rs,u_int rt_val,int rt)
2514 if(genimm(rt_val,&armval)) {
2515 assem_debug("mov %s,#%d\n",regname[rt],rt_val);
2516 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
2519 if(genimm(~rt_val,&armval)) {
2520 assem_debug("mvn %s,#%d\n",regname[rt],rt_val);
2521 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
2525 if(genimm(diff,&armval)) {
2526 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],diff);
2527 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
2529 }else if(genimm(-diff,&armval)) {
2530 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],-diff);
2531 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
2534 emit_movimm(rt_val,rt);
2537 // return 1 if above function can do it's job cheaply
2538 static int is_similar_value(u_int v1,u_int v2)
2542 if(v1==v2) return 1;
2544 for(xs=diff;xs!=0&&(xs&3)==0;xs>>=2)
2546 if(xs<0x100) return 1;
2547 for(xs=-diff;xs!=0&&(xs&3)==0;xs>>=2)
2549 if(xs<0x100) return 1;
2554 static void pass_args(int a0, int a1)
2558 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2560 else if(a0!=0&&a1==0) {
2562 if (a0>=0) emit_mov(a0,0);
2565 if(a0>=0&&a0!=0) emit_mov(a0,0);
2566 if(a1>=0&&a1!=1) emit_mov(a1,1);
2570 static void mov_loadtype_adj(int type,int rs,int rt)
2573 case LOADB_STUB: emit_signextend8(rs,rt); break;
2574 case LOADBU_STUB: emit_andimm(rs,0xff,rt); break;
2575 case LOADH_STUB: emit_signextend16(rs,rt); break;
2576 case LOADHU_STUB: emit_andimm(rs,0xffff,rt); break;
2577 case LOADW_STUB: if(rs!=rt) emit_mov(rs,rt); break;
2582 #include "pcsxmem.h"
2583 #include "pcsxmem_inline.c"
2585 static void do_readstub(int n)
2587 assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
2589 set_jump_target(stubs[n][1],(int)out);
2590 int type=stubs[n][0];
2593 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2594 u_int reglist=stubs[n][7];
2595 signed char *i_regmap=i_regs->regmap;
2597 if(itype[i]==C1LS||itype[i]==C2LS||itype[i]==LOADLR) {
2598 rt=get_reg(i_regmap,FTEMP);
2600 rt=get_reg(i_regmap,rt1[i]);
2603 int r,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0;
2605 for(r=0;r<=12;r++) {
2606 if(((1<<r)&0x13ff)&&((1<<r)®list)==0) {
2610 if(rt>=0&&rt1[i]!=0)
2617 if((regs_saved||(reglist&2)==0)&&temp!=1&&rs!=1)
2619 emit_readword((int)&mem_rtab,temp);
2620 emit_shrimm(rs,12,temp2);
2621 emit_readword_dualindexedx4(temp,temp2,temp2);
2622 emit_lsls_imm(temp2,1,temp2);
2623 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2625 case LOADB_STUB: emit_ldrccsb_dualindexed(temp2,rs,rt); break;
2626 case LOADBU_STUB: emit_ldrccb_dualindexed(temp2,rs,rt); break;
2627 case LOADH_STUB: emit_ldrccsh_dualindexed(temp2,rs,rt); break;
2628 case LOADHU_STUB: emit_ldrcch_dualindexed(temp2,rs,rt); break;
2629 case LOADW_STUB: emit_ldrcc_dualindexed(temp2,rs,rt); break;
2633 restore_jump=(int)out;
2634 emit_jcc(0); // jump to reg restore
2637 emit_jcc(stubs[n][2]); // return address
2642 if(type==LOADB_STUB||type==LOADBU_STUB)
2643 handler=(int)jump_handler_read8;
2644 if(type==LOADH_STUB||type==LOADHU_STUB)
2645 handler=(int)jump_handler_read16;
2646 if(type==LOADW_STUB)
2647 handler=(int)jump_handler_read32;
2649 pass_args(rs,temp2);
2650 int cc=get_reg(i_regmap,CCREG);
2652 emit_loadreg(CCREG,2);
2653 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
2655 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2656 mov_loadtype_adj(type,0,rt);
2659 set_jump_target(restore_jump,(int)out);
2660 restore_regs(reglist);
2661 emit_jmp(stubs[n][2]); // return address
2664 // return memhandler, or get directly accessable address and return 0
2665 static u_int get_direct_memhandler(void *table,u_int addr,int type,u_int *addr_host)
2668 l1=((u_int *)table)[addr>>12];
2669 if((l1&(1<<31))==0) {
2676 if(type==LOADB_STUB||type==LOADBU_STUB||type==STOREB_STUB)
2677 l2=((u_int *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2678 else if(type==LOADH_STUB||type==LOADHU_STUB||type==STOREH_STUB)
2679 l2=((u_int *)l1)[0x1000/4 + (addr&0xfff)/2];
2681 l2=((u_int *)l1)[(addr&0xfff)/4];
2682 if((l2&(1<<31))==0) {
2684 *addr_host=v+(addr&0xfff);
2691 static void inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2693 int rs=get_reg(regmap,target);
2694 int rt=get_reg(regmap,target);
2695 if(rs<0) rs=get_reg(regmap,-1);
2697 u_int handler,host_addr=0,is_dynamic,far_call=0;
2698 int cc=get_reg(regmap,CCREG);
2699 if(pcsx_direct_read(type,addr,CLOCK_ADJUST(adj+1),cc,target?rs:-1,rt))
2701 handler=get_direct_memhandler(mem_rtab,addr,type,&host_addr);
2706 emit_movimm_from(addr,rs,host_addr,rs);
2708 case LOADB_STUB: emit_movsbl_indexed(0,rs,rt); break;
2709 case LOADBU_STUB: emit_movzbl_indexed(0,rs,rt); break;
2710 case LOADH_STUB: emit_movswl_indexed(0,rs,rt); break;
2711 case LOADHU_STUB: emit_movzwl_indexed(0,rs,rt); break;
2712 case LOADW_STUB: emit_readword_indexed(0,rs,rt); break;
2717 is_dynamic=pcsxmem_is_handler_dynamic(addr);
2719 if(type==LOADB_STUB||type==LOADBU_STUB)
2720 handler=(int)jump_handler_read8;
2721 if(type==LOADH_STUB||type==LOADHU_STUB)
2722 handler=(int)jump_handler_read16;
2723 if(type==LOADW_STUB)
2724 handler=(int)jump_handler_read32;
2727 // call a memhandler
2728 if(rt>=0&&rt1[i]!=0)
2732 emit_movimm(addr,0);
2735 int offset=(int)handler-(int)out-8;
2736 if(offset<-33554432||offset>=33554432) {
2737 // unreachable memhandler, a plugin func perhaps
2738 emit_movimm(handler,12);
2742 emit_loadreg(CCREG,2);
2744 emit_movimm(((u_int *)mem_rtab)[addr>>12]<<1,1);
2745 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
2748 emit_readword((int)&last_count,3);
2749 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
2751 emit_writeword(2,(int)&Count);
2759 if(rt>=0&&rt1[i]!=0) {
2761 case LOADB_STUB: emit_signextend8(0,rt); break;
2762 case LOADBU_STUB: emit_andimm(0,0xff,rt); break;
2763 case LOADH_STUB: emit_signextend16(0,rt); break;
2764 case LOADHU_STUB: emit_andimm(0,0xffff,rt); break;
2765 case LOADW_STUB: if(rt!=0) emit_mov(0,rt); break;
2769 restore_regs(reglist);
2772 static void do_writestub(int n)
2774 assem_debug("do_writestub %x\n",start+stubs[n][3]*4);
2776 set_jump_target(stubs[n][1],(int)out);
2777 int type=stubs[n][0];
2780 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2781 u_int reglist=stubs[n][7];
2782 signed char *i_regmap=i_regs->regmap;
2784 if(itype[i]==C1LS||itype[i]==C2LS) {
2785 rt=get_reg(i_regmap,r=FTEMP);
2787 rt=get_reg(i_regmap,r=rs2[i]);
2791 int rtmp,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0,ra;
2792 int reglist2=reglist|(1<<rs)|(1<<rt);
2793 for(rtmp=0;rtmp<=12;rtmp++) {
2794 if(((1<<rtmp)&0x13ff)&&((1<<rtmp)®list2)==0) {
2801 for(rtmp=0;rtmp<=3;rtmp++)
2802 if(rtmp!=rs&&rtmp!=rt)
2805 if((regs_saved||(reglist2&8)==0)&&temp!=3&&rs!=3&&rt!=3)
2807 emit_readword((int)&mem_wtab,temp);
2808 emit_shrimm(rs,12,temp2);
2809 emit_readword_dualindexedx4(temp,temp2,temp2);
2810 emit_lsls_imm(temp2,1,temp2);
2812 case STOREB_STUB: emit_strccb_dualindexed(temp2,rs,rt); break;
2813 case STOREH_STUB: emit_strcch_dualindexed(temp2,rs,rt); break;
2814 case STOREW_STUB: emit_strcc_dualindexed(temp2,rs,rt); break;
2818 restore_jump=(int)out;
2819 emit_jcc(0); // jump to reg restore
2822 emit_jcc(stubs[n][2]); // return address (invcode check)
2828 case STOREB_STUB: handler=(int)jump_handler_write8; break;
2829 case STOREH_STUB: handler=(int)jump_handler_write16; break;
2830 case STOREW_STUB: handler=(int)jump_handler_write32; break;
2836 int cc=get_reg(i_regmap,CCREG);
2838 emit_loadreg(CCREG,2);
2839 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
2840 // returns new cycle_count
2842 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n][6]+1),cc<0?2:cc);
2844 emit_storereg(CCREG,2);
2846 set_jump_target(restore_jump,(int)out);
2847 restore_regs(reglist);
2852 static void inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2854 int rs=get_reg(regmap,-1);
2855 int rt=get_reg(regmap,target);
2858 u_int handler,host_addr=0;
2859 handler=get_direct_memhandler(mem_wtab,addr,type,&host_addr);
2862 emit_movimm_from(addr,rs,host_addr,rs);
2864 case STOREB_STUB: emit_writebyte_indexed(rt,0,rs); break;
2865 case STOREH_STUB: emit_writehword_indexed(rt,0,rs); break;
2866 case STOREW_STUB: emit_writeword_indexed(rt,0,rs); break;
2872 // call a memhandler
2875 int cc=get_reg(regmap,CCREG);
2877 emit_loadreg(CCREG,2);
2878 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
2879 emit_movimm(handler,3);
2880 // returns new cycle_count
2881 emit_call((int)jump_handler_write_h);
2882 emit_addimm(0,-CLOCK_ADJUST(adj+1),cc<0?2:cc);
2884 emit_storereg(CCREG,2);
2885 restore_regs(reglist);
2888 static void do_unalignedwritestub(int n)
2890 assem_debug("do_unalignedwritestub %x\n",start+stubs[n][3]*4);
2892 set_jump_target(stubs[n][1],(int)out);
2895 struct regstat *i_regs=(struct regstat *)stubs[n][4];
2896 int addr=stubs[n][5];
2897 u_int reglist=stubs[n][7];
2898 signed char *i_regmap=i_regs->regmap;
2899 int temp2=get_reg(i_regmap,FTEMP);
2901 rt=get_reg(i_regmap,rs2[i]);
2904 assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
2906 reglist&=~(1<<temp2);
2909 // don't bother with it and call write handler
2912 int cc=get_reg(i_regmap,CCREG);
2914 emit_loadreg(CCREG,2);
2915 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
2916 emit_call((int)(opcode[i]==0x2a?jump_handle_swl:jump_handle_swr));
2917 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n][6]+1),cc<0?2:cc);
2919 emit_storereg(CCREG,2);
2920 restore_regs(reglist);
2921 emit_jmp(stubs[n][2]); // return address
2923 emit_andimm(addr,0xfffffffc,temp2);
2924 emit_writeword(temp2,(int)&address);
2927 emit_shrimm(addr,16,1);
2928 int cc=get_reg(i_regmap,CCREG);
2930 emit_loadreg(CCREG,2);
2932 emit_movimm((u_int)readmem,0);
2933 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2934 emit_call((int)&indirect_jump_indexed);
2935 restore_regs(reglist);
2937 emit_readword((int)&readmem_dword,temp2);
2938 int temp=addr; //hmh
2939 emit_shlimm(addr,3,temp);
2940 emit_andimm(temp,24,temp);
2941 #ifdef BIG_ENDIAN_MIPS
2942 if (opcode[i]==0x2e) // SWR
2944 if (opcode[i]==0x2a) // SWL
2946 emit_xorimm(temp,24,temp);
2947 emit_movimm(-1,HOST_TEMPREG);
2948 if (opcode[i]==0x2a) { // SWL
2949 emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
2950 emit_orrshr(rt,temp,temp2);
2952 emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
2953 emit_orrshl(rt,temp,temp2);
2955 emit_readword((int)&address,addr);
2956 emit_writeword(temp2,(int)&word);
2957 //save_regs(reglist); // don't need to, no state changes
2958 emit_shrimm(addr,16,1);
2959 emit_movimm((u_int)writemem,0);
2960 //emit_call((int)&indirect_jump_indexed);
2962 emit_readword_dualindexedx4(0,1,15);
2963 emit_readword((int)&Count,HOST_TEMPREG);
2964 emit_readword((int)&next_interupt,2);
2965 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2966 emit_writeword(2,(int)&last_count);
2967 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2969 emit_storereg(CCREG,HOST_TEMPREG);
2971 restore_regs(reglist);
2972 emit_jmp(stubs[n][2]); // return address
2976 static void do_invstub(int n)
2979 u_int reglist=stubs[n][3];
2980 set_jump_target(stubs[n][1],(int)out);
2982 if(stubs[n][4]!=0) emit_mov(stubs[n][4],0);
2983 emit_call((int)&invalidate_addr);
2984 restore_regs(reglist);
2985 emit_jmp(stubs[n][2]); // return address
2988 int do_dirty_stub(int i)
2990 assem_debug("do_dirty_stub %x\n",start+i*4);
2991 u_int addr=(u_int)source;
2992 // Careful about the code output here, verify_dirty needs to parse it.
2994 emit_loadlp(addr,1);
2995 emit_loadlp((int)copy,2);
2996 emit_loadlp(slen*4,3);
2998 emit_movw(addr&0x0000FFFF,1);
2999 emit_movw(((u_int)copy)&0x0000FFFF,2);
3000 emit_movt(addr&0xFFFF0000,1);
3001 emit_movt(((u_int)copy)&0xFFFF0000,2);
3002 emit_movw(slen*4,3);
3004 emit_movimm(start+i*4,0);
3005 emit_call((int)start<(int)0xC0000000?(int)&verify_code:(int)&verify_code_vm);
3008 if(entry==(int)out) entry=instr_addr[i];
3009 emit_jmp(instr_addr[i]);
3013 static void do_dirty_stub_ds()
3015 // Careful about the code output here, verify_dirty needs to parse it.
3017 emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
3018 emit_loadlp((int)copy,2);
3019 emit_loadlp(slen*4,3);
3021 emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
3022 emit_movw(((u_int)copy)&0x0000FFFF,2);
3023 emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
3024 emit_movt(((u_int)copy)&0xFFFF0000,2);
3025 emit_movw(slen*4,3);
3027 emit_movimm(start+1,0);
3028 emit_call((int)&verify_code_ds);
3031 static void do_cop1stub(int n)
3034 assem_debug("do_cop1stub %x\n",start+stubs[n][3]*4);
3035 set_jump_target(stubs[n][1],(int)out);
3037 // int rs=stubs[n][4];
3038 struct regstat *i_regs=(struct regstat *)stubs[n][5];
3041 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3042 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3044 //else {printf("fp exception in delay slot\n");}
3045 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty);
3046 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3047 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3048 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3049 emit_jmp(ds?(int)fp_exception_ds:(int)fp_exception);
3054 static void shift_assemble_arm(int i,struct regstat *i_regs)
3057 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
3059 signed char s,t,shift;
3060 t=get_reg(i_regs->regmap,rt1[i]);
3061 s=get_reg(i_regs->regmap,rs1[i]);
3062 shift=get_reg(i_regs->regmap,rs2[i]);
3071 if(s!=t) emit_mov(s,t);
3075 emit_andimm(shift,31,HOST_TEMPREG);
3076 if(opcode2[i]==4) // SLLV
3078 emit_shl(s,HOST_TEMPREG,t);
3080 if(opcode2[i]==6) // SRLV
3082 emit_shr(s,HOST_TEMPREG,t);
3084 if(opcode2[i]==7) // SRAV
3086 emit_sar(s,HOST_TEMPREG,t);
3090 } else { // DSLLV/DSRLV/DSRAV
3091 signed char sh,sl,th,tl,shift;
3092 th=get_reg(i_regs->regmap,rt1[i]|64);
3093 tl=get_reg(i_regs->regmap,rt1[i]);
3094 sh=get_reg(i_regs->regmap,rs1[i]|64);
3095 sl=get_reg(i_regs->regmap,rs1[i]);
3096 shift=get_reg(i_regs->regmap,rs2[i]);
3101 if(th>=0) emit_zeroreg(th);
3106 if(sl!=tl) emit_mov(sl,tl);
3107 if(th>=0&&sh!=th) emit_mov(sh,th);
3111 // FIXME: What if shift==tl ?
3113 int temp=get_reg(i_regs->regmap,-1);
3115 if(th<0&&opcode2[i]!=0x14) {th=temp;} // DSLLV doesn't need a temporary register
3118 emit_andimm(shift,31,HOST_TEMPREG);
3119 if(opcode2[i]==0x14) // DSLLV
3121 if(th>=0) emit_shl(sh,HOST_TEMPREG,th);
3122 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3123 emit_orrshr(sl,HOST_TEMPREG,th);
3124 emit_andimm(shift,31,HOST_TEMPREG);
3125 emit_testimm(shift,32);
3126 emit_shl(sl,HOST_TEMPREG,tl);
3127 if(th>=0) emit_cmovne_reg(tl,th);
3128 emit_cmovne_imm(0,tl);
3130 if(opcode2[i]==0x16) // DSRLV
3133 emit_shr(sl,HOST_TEMPREG,tl);
3134 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3135 emit_orrshl(sh,HOST_TEMPREG,tl);
3136 emit_andimm(shift,31,HOST_TEMPREG);
3137 emit_testimm(shift,32);
3138 emit_shr(sh,HOST_TEMPREG,th);
3139 emit_cmovne_reg(th,tl);
3140 if(real_th>=0) emit_cmovne_imm(0,th);
3142 if(opcode2[i]==0x17) // DSRAV
3145 emit_shr(sl,HOST_TEMPREG,tl);
3146 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3149 emit_sarimm(th,31,temp);
3151 emit_orrshl(sh,HOST_TEMPREG,tl);
3152 emit_andimm(shift,31,HOST_TEMPREG);
3153 emit_testimm(shift,32);
3154 emit_sar(sh,HOST_TEMPREG,th);
3155 emit_cmovne_reg(th,tl);
3156 if(real_th>=0) emit_cmovne_reg(temp,th);
3164 static void speculate_mov(int rs,int rt)
3167 smrv_strong_next|=1<<rt;
3172 static void speculate_mov_weak(int rs,int rt)
3175 smrv_weak_next|=1<<rt;
3180 static void speculate_register_values(int i)
3183 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3184 // gp,sp are likely to stay the same throughout the block
3185 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3186 smrv_weak_next=~smrv_strong_next;
3187 //printf(" llr %08x\n", smrv[4]);
3189 smrv_strong=smrv_strong_next;
3190 smrv_weak=smrv_weak_next;
3193 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3194 else if((smrv_strong>>rs2[i])&1) speculate_mov(rs2[i],rt1[i]);
3195 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3196 else if((smrv_weak>>rs2[i])&1) speculate_mov_weak(rs2[i],rt1[i]);
3198 smrv_strong_next&=~(1<<rt1[i]);
3199 smrv_weak_next&=~(1<<rt1[i]);
3203 smrv_strong_next&=~(1<<rt1[i]);
3204 smrv_weak_next&=~(1<<rt1[i]);
3207 if(rt1[i]&&is_const(®s[i],rt1[i])) {
3208 int value,hr=get_reg(regs[i].regmap,rt1[i]);
3210 if(get_final_value(hr,i,&value))
3212 else smrv[rt1[i]]=constmap[i][hr];
3213 smrv_strong_next|=1<<rt1[i];
3217 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3218 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3222 if(start<0x2000&&(rt1[i]==26||(smrv[rt1[i]]>>24)==0xa0)) {
3223 // special case for BIOS
3224 smrv[rt1[i]]=0xa0000000;
3225 smrv_strong_next|=1<<rt1[i];
3232 smrv_strong_next&=~(1<<rt1[i]);
3233 smrv_weak_next&=~(1<<rt1[i]);
3237 if(opcode2[i]==0||opcode2[i]==2) { // MFC/CFC
3238 smrv_strong_next&=~(1<<rt1[i]);
3239 smrv_weak_next&=~(1<<rt1[i]);
3243 if (opcode[i]==0x32) { // LWC2
3244 smrv_strong_next&=~(1<<rt1[i]);
3245 smrv_weak_next&=~(1<<rt1[i]);
3251 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
3252 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
3264 static int get_ptr_mem_type(u_int a)
3266 if(a < 0x00200000) {
3267 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
3268 // return wrong, must use memhandler for BIOS self-test to pass
3269 // 007 does similar stuff from a00 mirror, weird stuff
3273 if(0x1f800000 <= a && a < 0x1f801000)
3275 if(0x80200000 <= a && a < 0x80800000)
3277 if(0xa0000000 <= a && a < 0xa0200000)
3282 static int emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override)
3286 if(((smrv_strong|smrv_weak)>>mr)&1) {
3287 type=get_ptr_mem_type(smrv[mr]);
3288 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
3291 // use the mirror we are running on
3292 type=get_ptr_mem_type(start);
3293 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
3296 if(type==MTYPE_8020) { // RAM 80200000+ mirror
3297 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3298 addr=*addr_reg_override=HOST_TEMPREG;
3301 else if(type==MTYPE_0000) { // RAM 0 mirror
3302 emit_orimm(addr,0x80000000,HOST_TEMPREG);
3303 addr=*addr_reg_override=HOST_TEMPREG;
3306 else if(type==MTYPE_A000) { // RAM A mirror
3307 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
3308 addr=*addr_reg_override=HOST_TEMPREG;
3311 else if(type==MTYPE_1F80) { // scratchpad
3312 if (psxH == (void *)0x1f800000) {
3313 emit_addimm(addr,-0x1f800000,HOST_TEMPREG);
3314 emit_cmpimm(HOST_TEMPREG,0x1000);
3319 // do usual RAM check, jump will go to the right handler
3326 emit_cmpimm(addr,RAM_SIZE);
3328 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3329 // Hint to branch predictor that the branch is unlikely to be taken
3331 emit_jno_unlikely(0);
3336 emit_addimm(addr,ram_offset,HOST_TEMPREG);
3337 addr=*addr_reg_override=HOST_TEMPREG;
3344 #define shift_assemble shift_assemble_arm
3346 static void loadlr_assemble_arm(int i,struct regstat *i_regs)
3348 int s,th,tl,temp,temp2,addr,map=-1;
3351 int memtarget=0,c=0;
3352 int fastload_reg_override=0;
3354 th=get_reg(i_regs->regmap,rt1[i]|64);
3355 tl=get_reg(i_regs->regmap,rt1[i]);
3356 s=get_reg(i_regs->regmap,rs1[i]);
3357 temp=get_reg(i_regs->regmap,-1);
3358 temp2=get_reg(i_regs->regmap,FTEMP);
3359 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
3362 for(hr=0;hr<HOST_REGS;hr++) {
3363 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3366 if(offset||s<0||c) addr=temp2;
3369 c=(i_regs->wasconst>>s)&1;
3371 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3376 map=get_reg(i_regs->regmap,ROREG);
3377 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3379 emit_shlimm(addr,3,temp);
3380 if (opcode[i]==0x22||opcode[i]==0x26) {
3381 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3383 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3385 jaddr=emit_fastpath_cmp_jump(i,temp2,&fastload_reg_override);
3388 if(ram_offset&&memtarget) {
3389 emit_addimm(temp2,ram_offset,HOST_TEMPREG);
3390 fastload_reg_override=HOST_TEMPREG;
3392 if (opcode[i]==0x22||opcode[i]==0x26) {
3393 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3395 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3398 if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
3401 if(fastload_reg_override) a=fastload_reg_override;
3402 //emit_readword_indexed((int)rdram-0x80000000,temp2,temp2);
3403 emit_readword_indexed_tlb(0,a,map,temp2);
3404 if(jaddr) add_stub(LOADW_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3407 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
3410 emit_andimm(temp,24,temp);
3411 #ifdef BIG_ENDIAN_MIPS
3412 if (opcode[i]==0x26) // LWR
3414 if (opcode[i]==0x22) // LWL
3416 emit_xorimm(temp,24,temp);
3417 emit_movimm(-1,HOST_TEMPREG);
3418 if (opcode[i]==0x26) {
3419 emit_shr(temp2,temp,temp2);
3420 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3422 emit_shl(temp2,temp,temp2);
3423 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3425 emit_or(temp2,tl,tl);
3427 //emit_storereg(rt1[i],tl); // DEBUG
3429 if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
3430 // FIXME: little endian, fastload_reg_override
3431 int temp2h=get_reg(i_regs->regmap,FTEMP|64);
3433 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
3434 //emit_readword_indexed((int)rdram-0x7FFFFFFC,temp2,temp2);
3435 emit_readdword_indexed_tlb(0,temp2,map,temp2h,temp2);
3436 if(jaddr) add_stub(LOADD_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3439 inline_readstub(LOADD_STUB,i,(constmap[i][s]+offset)&0xFFFFFFF8,i_regs->regmap,FTEMP,ccadj[i],reglist);
3443 emit_testimm(temp,32);
3444 emit_andimm(temp,24,temp);
3445 if (opcode[i]==0x1A) { // LDL
3446 emit_rsbimm(temp,32,HOST_TEMPREG);
3447 emit_shl(temp2h,temp,temp2h);
3448 emit_orrshr(temp2,HOST_TEMPREG,temp2h);
3449 emit_movimm(-1,HOST_TEMPREG);
3450 emit_shl(temp2,temp,temp2);
3451 emit_cmove_reg(temp2h,th);
3452 emit_biceq_lsl(tl,HOST_TEMPREG,temp,tl);
3453 emit_bicne_lsl(th,HOST_TEMPREG,temp,th);
3454 emit_orreq(temp2,tl,tl);
3455 emit_orrne(temp2,th,th);
3457 if (opcode[i]==0x1B) { // LDR
3458 emit_xorimm(temp,24,temp);
3459 emit_rsbimm(temp,32,HOST_TEMPREG);
3460 emit_shr(temp2,temp,temp2);
3461 emit_orrshl(temp2h,HOST_TEMPREG,temp2);
3462 emit_movimm(-1,HOST_TEMPREG);
3463 emit_shr(temp2h,temp,temp2h);
3464 emit_cmovne_reg(temp2,tl);
3465 emit_bicne_lsr(th,HOST_TEMPREG,temp,th);
3466 emit_biceq_lsr(tl,HOST_TEMPREG,temp,tl);
3467 emit_orrne(temp2h,th,th);
3468 emit_orreq(temp2h,tl,tl);
3473 #define loadlr_assemble loadlr_assemble_arm
3475 static void cop0_assemble(int i,struct regstat *i_regs)
3477 if(opcode2[i]==0) // MFC0
3479 signed char t=get_reg(i_regs->regmap,rt1[i]);
3480 char copr=(source[i]>>11)&0x1f;
3481 //assert(t>=0); // Why does this happen? OOT is weird
3482 if(t>=0&&rt1[i]!=0) {
3483 emit_readword((int)®_cop0+copr*4,t);
3486 else if(opcode2[i]==4) // MTC0
3488 signed char s=get_reg(i_regs->regmap,rs1[i]);
3489 char copr=(source[i]>>11)&0x1f;
3491 wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
3492 if(copr==9||copr==11||copr==12||copr==13) {
3493 emit_readword((int)&last_count,HOST_TEMPREG);
3494 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3495 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3496 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3497 emit_writeword(HOST_CCREG,(int)&Count);
3499 // What a mess. The status register (12) can enable interrupts,
3500 // so needs a special case to handle a pending interrupt.
3501 // The interrupt must be taken immediately, because a subsequent
3502 // instruction might disable interrupts again.
3503 if(copr==12||copr==13) {
3505 // burn cycles to cause cc_interrupt, which will
3506 // reschedule next_interupt. Relies on CCREG from above.
3507 assem_debug("MTC0 DS %d\n", copr);
3508 emit_writeword(HOST_CCREG,(int)&last_count);
3509 emit_movimm(0,HOST_CCREG);
3510 emit_storereg(CCREG,HOST_CCREG);
3511 emit_loadreg(rs1[i],1);
3512 emit_movimm(copr,0);
3513 emit_call((int)pcsx_mtc0_ds);
3514 emit_loadreg(rs1[i],s);
3517 emit_movimm(start+i*4+4,HOST_TEMPREG);
3518 emit_writeword(HOST_TEMPREG,(int)&pcaddr);
3519 emit_movimm(0,HOST_TEMPREG);
3520 emit_writeword(HOST_TEMPREG,(int)&pending_exception);
3522 //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
3525 emit_loadreg(rs1[i],1);
3528 emit_movimm(copr,0);
3529 emit_call((int)pcsx_mtc0);
3530 if(copr==9||copr==11||copr==12||copr==13) {
3531 emit_readword((int)&Count,HOST_CCREG);
3532 emit_readword((int)&next_interupt,HOST_TEMPREG);
3533 emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3534 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3535 emit_writeword(HOST_TEMPREG,(int)&last_count);
3536 emit_storereg(CCREG,HOST_CCREG);
3538 if(copr==12||copr==13) {
3539 assert(!is_delayslot);
3540 emit_readword((int)&pending_exception,14);
3542 emit_jne((int)&do_interrupt);
3544 emit_loadreg(rs1[i],s);
3545 if(get_reg(i_regs->regmap,rs1[i]|64)>=0)
3546 emit_loadreg(rs1[i]|64,get_reg(i_regs->regmap,rs1[i]|64));
3551 assert(opcode2[i]==0x10);
3552 if((source[i]&0x3f)==0x10) // RFE
3554 emit_readword((int)&Status,0);
3555 emit_andimm(0,0x3c,1);
3556 emit_andimm(0,~0xf,0);
3557 emit_orrshr_imm(1,2,0);
3558 emit_writeword(0,(int)&Status);
3563 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3573 emit_readword((int)®_cop2d[copr],tl);
3574 emit_signextend16(tl,tl);
3575 emit_writeword(tl,(int)®_cop2d[copr]); // hmh
3582 emit_readword((int)®_cop2d[copr],tl);
3583 emit_andimm(tl,0xffff,tl);
3584 emit_writeword(tl,(int)®_cop2d[copr]);
3587 emit_readword((int)®_cop2d[14],tl); // SXY2
3588 emit_writeword(tl,(int)®_cop2d[copr]);
3592 emit_readword((int)®_cop2d[9],temp);
3593 emit_testimm(temp,0x8000); // do we need this?
3594 emit_andimm(temp,0xf80,temp);
3595 emit_andne_imm(temp,0,temp);
3596 emit_shrimm(temp,7,tl);
3597 emit_readword((int)®_cop2d[10],temp);
3598 emit_testimm(temp,0x8000);
3599 emit_andimm(temp,0xf80,temp);
3600 emit_andne_imm(temp,0,temp);
3601 emit_orrshr_imm(temp,2,tl);
3602 emit_readword((int)®_cop2d[11],temp);
3603 emit_testimm(temp,0x8000);
3604 emit_andimm(temp,0xf80,temp);
3605 emit_andne_imm(temp,0,temp);
3606 emit_orrshl_imm(temp,3,tl);
3607 emit_writeword(tl,(int)®_cop2d[copr]);
3610 emit_readword((int)®_cop2d[copr],tl);
3615 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3619 emit_readword((int)®_cop2d[13],temp); // SXY1
3620 emit_writeword(sl,(int)®_cop2d[copr]);
3621 emit_writeword(temp,(int)®_cop2d[12]); // SXY0
3622 emit_readword((int)®_cop2d[14],temp); // SXY2
3623 emit_writeword(sl,(int)®_cop2d[14]);
3624 emit_writeword(temp,(int)®_cop2d[13]); // SXY1
3627 emit_andimm(sl,0x001f,temp);
3628 emit_shlimm(temp,7,temp);
3629 emit_writeword(temp,(int)®_cop2d[9]);
3630 emit_andimm(sl,0x03e0,temp);
3631 emit_shlimm(temp,2,temp);
3632 emit_writeword(temp,(int)®_cop2d[10]);
3633 emit_andimm(sl,0x7c00,temp);
3634 emit_shrimm(temp,3,temp);
3635 emit_writeword(temp,(int)®_cop2d[11]);
3636 emit_writeword(sl,(int)®_cop2d[28]);
3640 emit_mvnmi(temp,temp);
3642 emit_clz(temp,temp);
3644 emit_movs(temp,HOST_TEMPREG);
3645 emit_movimm(0,temp);
3646 emit_jeq((int)out+4*4);
3647 emit_addpl_imm(temp,1,temp);
3648 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3649 emit_jns((int)out-2*4);
3651 emit_writeword(sl,(int)®_cop2d[30]);
3652 emit_writeword(temp,(int)®_cop2d[31]);
3657 emit_writeword(sl,(int)®_cop2d[copr]);
3662 static void cop2_assemble(int i,struct regstat *i_regs)
3664 u_int copr=(source[i]>>11)&0x1f;
3665 signed char temp=get_reg(i_regs->regmap,-1);
3666 if (opcode2[i]==0) { // MFC2
3667 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3668 if(tl>=0&&rt1[i]!=0)
3669 cop2_get_dreg(copr,tl,temp);
3671 else if (opcode2[i]==4) { // MTC2
3672 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3673 cop2_put_dreg(copr,sl,temp);
3675 else if (opcode2[i]==2) // CFC2
3677 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3678 if(tl>=0&&rt1[i]!=0)
3679 emit_readword((int)®_cop2c[copr],tl);
3681 else if (opcode2[i]==6) // CTC2
3683 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3692 emit_signextend16(sl,temp);
3695 //value = value & 0x7ffff000;
3696 //if (value & 0x7f87e000) value |= 0x80000000;
3697 emit_shrimm(sl,12,temp);
3698 emit_shlimm(temp,12,temp);
3699 emit_testimm(temp,0x7f000000);
3700 emit_testeqimm(temp,0x00870000);
3701 emit_testeqimm(temp,0x0000e000);
3702 emit_orrne_imm(temp,0x80000000,temp);
3708 emit_writeword(temp,(int)®_cop2c[copr]);
3713 static void c2op_prologue(u_int op,u_int reglist)
3715 save_regs_all(reglist);
3718 emit_call((int)pcnt_gte_start);
3720 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0); // cop2 regs
3723 static void c2op_epilogue(u_int op,u_int reglist)
3727 emit_call((int)pcnt_gte_end);
3729 restore_regs_all(reglist);
3732 static void c2op_call_MACtoIR(int lm,int need_flags)
3735 emit_call((int)(lm?gteMACtoIR_lm1:gteMACtoIR_lm0));
3737 emit_call((int)(lm?gteMACtoIR_lm1_nf:gteMACtoIR_lm0_nf));
3740 static void c2op_call_rgb_func(void *func,int lm,int need_ir,int need_flags)
3742 emit_call((int)func);
3743 // func is C code and trashes r0
3744 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
3745 if(need_flags||need_ir)
3746 c2op_call_MACtoIR(lm,need_flags);
3747 emit_call((int)(need_flags?gteMACtoRGB:gteMACtoRGB_nf));
3750 static void c2op_assemble(int i,struct regstat *i_regs)
3752 u_int c2op=source[i]&0x3f;
3753 u_int hr,reglist_full=0,reglist;
3754 int need_flags,need_ir;
3755 for(hr=0;hr<HOST_REGS;hr++) {
3756 if(i_regs->regmap[hr]>=0) reglist_full|=1<<hr;
3758 reglist=reglist_full&CALLER_SAVE_REGS;
3760 if (gte_handlers[c2op]!=NULL) {
3761 need_flags=!(gte_unneeded[i+1]>>63); // +1 because of how liveness detection works
3762 need_ir=(gte_unneeded[i+1]&0xe00)!=0xe00;
3763 assem_debug("gte op %08x, unneeded %016llx, need_flags %d, need_ir %d\n",
3764 source[i],gte_unneeded[i+1],need_flags,need_ir);
3765 if(new_dynarec_hacks&NDHACK_GTE_NO_FLAGS)
3767 int shift = (source[i] >> 19) & 1;
3768 int lm = (source[i] >> 10) & 1;
3773 int v = (source[i] >> 15) & 3;
3774 int cv = (source[i] >> 13) & 3;
3775 int mx = (source[i] >> 17) & 3;
3776 reglist=reglist_full&(CALLER_SAVE_REGS|0xf0); // +{r4-r7}
3777 c2op_prologue(c2op,reglist);
3778 /* r4,r5 = VXYZ(v) packed; r6 = &MX11(mx); r7 = &CV1(cv) */
3782 emit_movzwl_indexed(9*4,0,4); // gteIR
3783 emit_movzwl_indexed(10*4,0,6);
3784 emit_movzwl_indexed(11*4,0,5);
3785 emit_orrshl_imm(6,16,4);
3788 emit_addimm(0,32*4+mx*8*4,6);
3790 emit_readword((int)&zeromem_ptr,6);
3792 emit_addimm(0,32*4+(cv*8+5)*4,7);
3794 emit_readword((int)&zeromem_ptr,7);
3796 emit_movimm(source[i],1); // opcode
3797 emit_call((int)gteMVMVA_part_neon);
3800 emit_call((int)gteMACtoIR_flags_neon);
3804 emit_call((int)gteMVMVA_part_cv3sh12_arm);
3806 emit_movimm(shift,1);
3807 emit_call((int)(need_flags?gteMVMVA_part_arm:gteMVMVA_part_nf_arm));
3809 if(need_flags||need_ir)
3810 c2op_call_MACtoIR(lm,need_flags);
3812 #else /* if not HAVE_ARMV5 */
3813 c2op_prologue(c2op,reglist);
3814 emit_movimm(source[i],1); // opcode
3815 emit_writeword(1,(int)&psxRegs.code);
3816 emit_call((int)(need_flags?gte_handlers[c2op]:gte_handlers_nf[c2op]));
3821 c2op_prologue(c2op,reglist);
3822 emit_call((int)(shift?gteOP_part_shift:gteOP_part_noshift));
3823 if(need_flags||need_ir) {
3824 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
3825 c2op_call_MACtoIR(lm,need_flags);
3829 c2op_prologue(c2op,reglist);
3830 c2op_call_rgb_func(shift?gteDPCS_part_shift:gteDPCS_part_noshift,lm,need_ir,need_flags);
3833 c2op_prologue(c2op,reglist);
3834 c2op_call_rgb_func(shift?gteINTPL_part_shift:gteINTPL_part_noshift,lm,need_ir,need_flags);
3837 c2op_prologue(c2op,reglist);
3838 emit_call((int)(shift?gteSQR_part_shift:gteSQR_part_noshift));
3839 if(need_flags||need_ir) {
3840 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
3841 c2op_call_MACtoIR(lm,need_flags);
3845 c2op_prologue(c2op,reglist);
3846 c2op_call_rgb_func(gteDCPL_part,lm,need_ir,need_flags);
3849 c2op_prologue(c2op,reglist);
3850 c2op_call_rgb_func(shift?gteGPF_part_shift:gteGPF_part_noshift,lm,need_ir,need_flags);
3853 c2op_prologue(c2op,reglist);
3854 c2op_call_rgb_func(shift?gteGPL_part_shift:gteGPL_part_noshift,lm,need_ir,need_flags);
3858 c2op_prologue(c2op,reglist);
3860 emit_movimm(source[i],1); // opcode
3861 emit_writeword(1,(int)&psxRegs.code);
3863 emit_call((int)(need_flags?gte_handlers[c2op]:gte_handlers_nf[c2op]));
3866 c2op_epilogue(c2op,reglist);
3870 static void cop1_unusable(int i,struct regstat *i_regs)
3872 // XXX: should just just do the exception instead
3876 add_stub(FP_STUB,jaddr,(int)out,i,0,(int)i_regs,is_delayslot,0);
3881 static void cop1_assemble(int i,struct regstat *i_regs)
3883 cop1_unusable(i, i_regs);
3886 static void fconv_assemble_arm(int i,struct regstat *i_regs)
3888 cop1_unusable(i, i_regs);
3890 #define fconv_assemble fconv_assemble_arm
3892 static void fcomp_assemble(int i,struct regstat *i_regs)
3894 cop1_unusable(i, i_regs);
3897 static void float_assemble(int i,struct regstat *i_regs)
3899 cop1_unusable(i, i_regs);
3902 static void multdiv_assemble_arm(int i,struct regstat *i_regs)
3909 // case 0x1D: DMULTU
3914 if((opcode2[i]&4)==0) // 32-bit
3916 if(opcode2[i]==0x18) // MULT
3918 signed char m1=get_reg(i_regs->regmap,rs1[i]);
3919 signed char m2=get_reg(i_regs->regmap,rs2[i]);
3920 signed char hi=get_reg(i_regs->regmap,HIREG);
3921 signed char lo=get_reg(i_regs->regmap,LOREG);
3926 emit_smull(m1,m2,hi,lo);
3928 if(opcode2[i]==0x19) // MULTU
3930 signed char m1=get_reg(i_regs->regmap,rs1[i]);
3931 signed char m2=get_reg(i_regs->regmap,rs2[i]);
3932 signed char hi=get_reg(i_regs->regmap,HIREG);
3933 signed char lo=get_reg(i_regs->regmap,LOREG);
3938 emit_umull(m1,m2,hi,lo);
3940 if(opcode2[i]==0x1A) // DIV
3942 signed char d1=get_reg(i_regs->regmap,rs1[i]);
3943 signed char d2=get_reg(i_regs->regmap,rs2[i]);
3946 signed char quotient=get_reg(i_regs->regmap,LOREG);
3947 signed char remainder=get_reg(i_regs->regmap,HIREG);
3948 assert(quotient>=0);
3949 assert(remainder>=0);
3950 emit_movs(d1,remainder);
3951 emit_movimm(0xffffffff,quotient);
3952 emit_negmi(quotient,quotient); // .. quotient and ..
3953 emit_negmi(remainder,remainder); // .. remainder for div0 case (will be negated back after jump)
3954 emit_movs(d2,HOST_TEMPREG);
3955 emit_jeq((int)out+52); // Division by zero
3956 emit_negsmi(HOST_TEMPREG,HOST_TEMPREG);
3958 emit_clz(HOST_TEMPREG,quotient);
3959 emit_shl(HOST_TEMPREG,quotient,HOST_TEMPREG);
3961 emit_movimm(0,quotient);
3962 emit_addpl_imm(quotient,1,quotient);
3963 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3964 emit_jns((int)out-2*4);
3966 emit_orimm(quotient,1<<31,quotient);
3967 emit_shr(quotient,quotient,quotient);
3968 emit_cmp(remainder,HOST_TEMPREG);
3969 emit_subcs(remainder,HOST_TEMPREG,remainder);
3970 emit_adcs(quotient,quotient,quotient);
3971 emit_shrimm(HOST_TEMPREG,1,HOST_TEMPREG);
3972 emit_jcc((int)out-16); // -4
3974 emit_negmi(quotient,quotient);
3976 emit_negmi(remainder,remainder);
3978 if(opcode2[i]==0x1B) // DIVU
3980 signed char d1=get_reg(i_regs->regmap,rs1[i]); // dividend
3981 signed char d2=get_reg(i_regs->regmap,rs2[i]); // divisor
3984 signed char quotient=get_reg(i_regs->regmap,LOREG);
3985 signed char remainder=get_reg(i_regs->regmap,HIREG);
3986 assert(quotient>=0);
3987 assert(remainder>=0);
3988 emit_mov(d1,remainder);
3989 emit_movimm(0xffffffff,quotient); // div0 case
3991 emit_jeq((int)out+40); // Division by zero
3993 emit_clz(d2,HOST_TEMPREG);
3994 emit_movimm(1<<31,quotient);
3995 emit_shl(d2,HOST_TEMPREG,d2);
3997 emit_movimm(0,HOST_TEMPREG);
3998 emit_addpl_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3999 emit_lslpls_imm(d2,1,d2);
4000 emit_jns((int)out-2*4);
4001 emit_movimm(1<<31,quotient);
4003 emit_shr(quotient,HOST_TEMPREG,quotient);
4004 emit_cmp(remainder,d2);
4005 emit_subcs(remainder,d2,remainder);
4006 emit_adcs(quotient,quotient,quotient);
4007 emit_shrcc_imm(d2,1,d2);
4008 emit_jcc((int)out-16); // -4
4016 // Multiply by zero is zero.
4017 // MIPS does not have a divide by zero exception.
4018 // The result is undefined, we return zero.
4019 signed char hr=get_reg(i_regs->regmap,HIREG);
4020 signed char lr=get_reg(i_regs->regmap,LOREG);
4021 if(hr>=0) emit_zeroreg(hr);
4022 if(lr>=0) emit_zeroreg(lr);
4025 #define multdiv_assemble multdiv_assemble_arm
4027 static void do_preload_rhash(int r) {
4028 // Don't need this for ARM. On x86, this puts the value 0xf8 into the
4029 // register. On ARM the hash can be done with a single instruction (below)
4032 static void do_preload_rhtbl(int ht) {
4033 emit_addimm(FP,(int)&mini_ht-(int)&dynarec_local,ht);
4036 static void do_rhash(int rs,int rh) {
4037 emit_andimm(rs,0xf8,rh);
4040 static void do_miniht_load(int ht,int rh) {
4041 assem_debug("ldr %s,[%s,%s]!\n",regname[rh],regname[ht],regname[rh]);
4042 output_w32(0xe7b00000|rd_rn_rm(rh,ht,rh));
4045 static void do_miniht_jump(int rs,int rh,int ht) {
4047 emit_ldreq_indexed(ht,4,15);
4048 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4050 emit_jmp(jump_vaddr_reg[7]);
4052 emit_jmp(jump_vaddr_reg[rs]);
4056 static void do_miniht_insert(u_int return_address,int rt,int temp) {
4058 emit_movimm(return_address,rt); // PC into link register
4059 add_to_linker((int)out,return_address,1);
4060 emit_pcreladdr(temp);
4061 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4062 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4064 emit_movw(return_address&0x0000FFFF,rt);
4065 add_to_linker((int)out,return_address,1);
4066 emit_pcreladdr(temp);
4067 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4068 emit_movt(return_address&0xFFFF0000,rt);
4069 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4073 static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t is32_pre,uint64_t u,uint64_t uu)
4075 //if(dirty_pre==dirty) return;
4077 for(hr=0;hr<HOST_REGS;hr++) {
4078 if(hr!=EXCLUDE_REG) {
4080 if(((~u)>>(reg&63))&1) {
4082 if(((dirty_pre&~dirty)>>hr)&1) {
4084 emit_storereg(reg,hr);
4085 if( ((is32_pre&~uu)>>reg)&1 ) {
4086 emit_sarimm(hr,31,HOST_TEMPREG);
4087 emit_storereg(reg|64,HOST_TEMPREG);
4091 emit_storereg(reg,hr);
4101 /* using strd could possibly help but you'd have to allocate registers in pairs
4102 static void wb_invalidate_arm(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,uint64_t u,uint64_t uu)
4106 for(hr=HOST_REGS-1;hr>=0;hr--) {
4107 if(hr!=EXCLUDE_REG) {
4108 if(pre[hr]!=entry[hr]) {
4111 if(get_reg(entry,pre[hr])<0) {
4113 if(!((u>>pre[hr])&1)) {
4114 if(hr<10&&(~hr&1)&&(pre[hr+1]<0||wrote==hr+1)) {
4115 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4116 emit_sarimm(hr,31,hr+1);
4117 emit_strdreg(pre[hr],hr);
4120 emit_storereg(pre[hr],hr);
4122 emit_storereg(pre[hr],hr);
4123 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4124 emit_sarimm(hr,31,hr);
4125 emit_storereg(pre[hr]|64,hr);
4130 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4131 emit_storereg(pre[hr],hr);
4141 for(hr=0;hr<HOST_REGS;hr++) {
4142 if(hr!=EXCLUDE_REG) {
4143 if(pre[hr]!=entry[hr]) {
4146 if((nr=get_reg(entry,pre[hr]))>=0) {
4154 #define wb_invalidate wb_invalidate_arm
4157 static void mark_clear_cache(void *target)
4159 u_long offset = (char *)target - (char *)BASE_ADDR;
4160 u_int mask = 1u << ((offset >> 12) & 31);
4161 if (!(needs_clear_cache[offset >> 17] & mask)) {
4162 char *start = (char *)((u_long)target & ~4095ul);
4163 start_tcache_write(start, start + 4096);
4164 needs_clear_cache[offset >> 17] |= mask;
4168 // Clearing the cache is rather slow on ARM Linux, so mark the areas
4169 // that need to be cleared, and then only clear these areas once.
4170 static void do_clear_cache()
4173 for (i=0;i<(1<<(TARGET_SIZE_2-17));i++)
4175 u_int bitmap=needs_clear_cache[i];
4181 start=(u_int)BASE_ADDR+i*131072+j*4096;
4189 end_tcache_write((void *)start,(void *)end);
4195 needs_clear_cache[i]=0;
4200 // CPU-architecture-specific initialization
4201 static void arch_init() {
4204 // vim:shiftwidth=2:expandtab