1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * linkage_arm.s for PCSX *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2013 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include "arm_features.h"
23 #include "new_dynarec_config.h"
24 #include "linkage_offsets.h"
28 #define dynarec_local ESYM(dynarec_local)
29 #define add_link ESYM(add_link)
30 #define new_recompile_block ESYM(new_recompile_block)
31 #define get_addr ESYM(get_addr)
32 #define get_addr_ht ESYM(get_addr_ht)
33 #define clean_blocks ESYM(clean_blocks)
34 #define gen_interupt ESYM(gen_interupt)
35 #define invalidate_addr ESYM(invalidate_addr)
41 .type dynarec_local, %object
42 .size dynarec_local, LO_dynarec_local_size
44 .space LO_dynarec_local_size
46 #define DRC_VAR_(name, vname, size_) \
47 vname = dynarec_local + LO_##name; \
49 .type vname, %object; \
52 #define DRC_VAR(name, size_) \
53 DRC_VAR_(name, ESYM(name), size_)
55 DRC_VAR(next_interupt, 4)
56 DRC_VAR(cycle_count, 4)
57 DRC_VAR(last_count, 4)
58 DRC_VAR(pending_exception, 4)
60 DRC_VAR(branch_target, 4)
62 @DRC_VAR(align0, 4) /* unused/alignment */
63 DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
69 DRC_VAR(reg_cop0, 128)
70 DRC_VAR(reg_cop2d, 128)
71 DRC_VAR(reg_cop2c, 128)
75 @DRC_VAR(interrupt, 4)
76 @DRC_VAR(intCycle, 256)
79 DRC_VAR(inv_code_start, 4)
80 DRC_VAR(inv_code_end, 4)
84 DRC_VAR(zeromem_ptr, 4)
86 DRC_VAR(scratch_buf_ptr, 4)
87 @DRC_VAR(align1, 8) /* unused/alignment */
89 DRC_VAR(restore_candidate, 512)
92 #ifdef TEXRELS_FORBIDDEN
98 .word ESYM(jump_dirty)
100 .word ESYM(hash_table)
115 .macro load_varadr reg var
116 #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
117 movw \reg, #:lower16:(\var-(1678f+8))
118 movt \reg, #:upper16:(\var-(1678f+8))
121 #elif defined(HAVE_ARMV7) && !defined(__PIC__)
122 movw \reg, #:lower16:\var
123 movt \reg, #:upper16:\var
129 .macro load_varadr_ext reg var
130 #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
131 movw \reg, #:lower16:(ptr_\var-(1678f+8))
132 movt \reg, #:upper16:(ptr_\var-(1678f+8))
136 load_varadr \reg \var
140 .macro mov_16 reg imm
144 mov \reg, #(\imm & 0x00ff)
145 orr \reg, #(\imm & 0xff00)
149 .macro mov_24 reg imm
151 movw \reg, #(\imm & 0xffff)
152 movt \reg, #(\imm >> 16)
154 mov \reg, #(\imm & 0x0000ff)
155 orr \reg, #(\imm & 0x00ff00)
156 orr \reg, #(\imm & 0xff0000)
160 /* r0 = virtual target address */
161 /* r1 = instruction to patch */
162 .macro dyna_linker_main
163 #ifndef NO_WRITE_EXEC
164 load_varadr_ext r3, jump_in
177 ldr r5, [r3, r2, lsl #2]
179 add r6, r1, r12, asr #6
185 ldr r3, [r5] /* ll_entry .vaddr */
186 ldrd r4, r5, [r4, #8] /* ll_entry .next, .addr */
190 moveq pc, r4 /* Stale i-cache */
192 b 1b /* jump_in may have dupes, continue search */
195 beq 3f /* r0 not in jump_in */
201 and r1, r7, #0xff000000
204 add r1, r1, r2, lsr #8
208 /* hash_table lookup */
210 load_varadr_ext r3, jump_dirty
211 eor r4, r0, r0, lsl #16
213 load_varadr_ext r6, hash_table
217 ldr r5, [r3, r2, lsl #2]
224 /* jump_dirty lookup */
234 /* hash_table insert */
244 /* XXX: should be able to do better than this... */
251 FUNCTION(dyna_linker):
252 /* r0 = virtual target address */
253 /* r1 = instruction to patch */
258 bl new_recompile_block
266 .size dyna_linker, .-dyna_linker
268 FUNCTION(exec_pagefault):
269 /* r0 = instruction pointer */
270 /* r1 = fault address */
272 ldr r3, [fp, #LO_reg_cop0+48] /* Status */
274 ldr r4, [fp, #LO_reg_cop0+16] /* Context */
275 bic r6, r6, #0x0F800000
276 str r0, [fp, #LO_reg_cop0+56] /* EPC */
278 str r1, [fp, #LO_reg_cop0+32] /* BadVAddr */
280 str r3, [fp, #LO_reg_cop0+48] /* Status */
281 and r5, r6, r1, lsr #9
282 str r2, [fp, #LO_reg_cop0+52] /* Cause */
283 and r1, r1, r6, lsl #9
284 str r1, [fp, #LO_reg_cop0+40] /* EntryHi */
286 str r4, [fp, #LO_reg_cop0+16] /* Context */
290 .size exec_pagefault, .-exec_pagefault
292 /* Special dynamic linker for the case where a page fault
293 may occur in a branch delay slot */
294 FUNCTION(dyna_linker_ds):
295 /* r0 = virtual target address */
296 /* r1 = instruction to patch */
303 bl new_recompile_block
310 mov r2, #0x80000008 /* High bit set indicates pagefault in delay slot */
313 .size dyna_linker_ds, .-dyna_linker_ds
317 FUNCTION(jump_vaddr_r0):
318 eor r2, r0, r0, lsl #16
320 .size jump_vaddr_r0, .-jump_vaddr_r0
321 FUNCTION(jump_vaddr_r1):
322 eor r2, r1, r1, lsl #16
325 .size jump_vaddr_r1, .-jump_vaddr_r1
326 FUNCTION(jump_vaddr_r2):
328 eor r2, r2, r2, lsl #16
330 .size jump_vaddr_r2, .-jump_vaddr_r2
331 FUNCTION(jump_vaddr_r3):
332 eor r2, r3, r3, lsl #16
335 .size jump_vaddr_r3, .-jump_vaddr_r3
336 FUNCTION(jump_vaddr_r4):
337 eor r2, r4, r4, lsl #16
340 .size jump_vaddr_r4, .-jump_vaddr_r4
341 FUNCTION(jump_vaddr_r5):
342 eor r2, r5, r5, lsl #16
345 .size jump_vaddr_r5, .-jump_vaddr_r5
346 FUNCTION(jump_vaddr_r6):
347 eor r2, r6, r6, lsl #16
350 .size jump_vaddr_r6, .-jump_vaddr_r6
351 FUNCTION(jump_vaddr_r8):
352 eor r2, r8, r8, lsl #16
355 .size jump_vaddr_r8, .-jump_vaddr_r8
356 FUNCTION(jump_vaddr_r9):
357 eor r2, r9, r9, lsl #16
360 .size jump_vaddr_r9, .-jump_vaddr_r9
361 FUNCTION(jump_vaddr_r10):
362 eor r2, r10, r10, lsl #16
365 .size jump_vaddr_r10, .-jump_vaddr_r10
366 FUNCTION(jump_vaddr_r12):
367 eor r2, r12, r12, lsl #16
370 .size jump_vaddr_r12, .-jump_vaddr_r12
371 FUNCTION(jump_vaddr_r7):
372 eor r2, r7, r7, lsl #16
374 .size jump_vaddr_r7, .-jump_vaddr_r7
375 FUNCTION(jump_vaddr):
376 load_varadr_ext r1, hash_table
378 and r2, r3, r2, lsr #12
385 str r10, [fp, #LO_cycle_count]
387 ldr r10, [fp, #LO_cycle_count]
389 .size jump_vaddr, .-jump_vaddr
393 FUNCTION(verify_code_ds):
394 str r8, [fp, #LO_branch_target] @ preserve HOST_BTREG?
395 FUNCTION(verify_code):
423 ldr r8, [fp, #LO_branch_target]
428 .size verify_code, .-verify_code
429 .size verify_code_ds, .-verify_code_ds
432 FUNCTION(cc_interrupt):
433 ldr r0, [fp, #LO_last_count]
437 str r1, [fp, #LO_pending_exception]
438 and r2, r2, r10, lsr #17
439 add r3, fp, #LO_restore_candidate
440 str r10, [fp, #LO_cycle] /* PCSX cycles */
441 @@ str r10, [fp, #LO_reg_cop0+36] /* Count */
449 ldr r10, [fp, #LO_cycle]
450 ldr r0, [fp, #LO_next_interupt]
451 ldr r1, [fp, #LO_pending_exception]
452 ldr r2, [fp, #LO_stop]
453 str r0, [fp, #LO_last_count]
456 ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
460 ldr r0, [fp, #LO_pcaddr]
464 /* Move 'dirty' blocks to the 'clean' list */
475 .size cc_interrupt, .-cc_interrupt
478 FUNCTION(fp_exception):
481 ldr r1, [fp, #LO_reg_cop0+48] /* Status */
483 str r0, [fp, #LO_reg_cop0+56] /* EPC */
486 str r1, [fp, #LO_reg_cop0+48] /* Status */
487 str r2, [fp, #LO_reg_cop0+52] /* Cause */
491 .size fp_exception, .-fp_exception
493 FUNCTION(fp_exception_ds):
494 mov r2, #0x90000000 /* Set high bit if delay slot */
496 .size fp_exception_ds, .-fp_exception_ds
499 FUNCTION(jump_syscall):
500 ldr r1, [fp, #LO_reg_cop0+48] /* Status */
502 str r0, [fp, #LO_reg_cop0+56] /* EPC */
505 str r1, [fp, #LO_reg_cop0+48] /* Status */
506 str r2, [fp, #LO_reg_cop0+52] /* Cause */
510 .size jump_syscall, .-jump_syscall
513 /* note: psxException might do recursive recompiler call from it's HLE code,
514 * so be ready for this */
515 FUNCTION(jump_to_new_pc):
516 ldr r1, [fp, #LO_next_interupt]
517 ldr r10, [fp, #LO_cycle]
518 ldr r0, [fp, #LO_pcaddr]
520 str r1, [fp, #LO_last_count]
523 .size jump_to_new_pc, .-jump_to_new_pc
526 FUNCTION(new_dyna_leave):
527 ldr r0, [fp, #LO_last_count]
530 str r10, [fp, #LO_cycle]
531 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
532 .size new_dyna_leave, .-new_dyna_leave
535 FUNCTION(invalidate_addr_r0):
536 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
537 b invalidate_addr_call
538 .size invalidate_addr_r0, .-invalidate_addr_r0
540 FUNCTION(invalidate_addr_r1):
541 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
543 b invalidate_addr_call
544 .size invalidate_addr_r1, .-invalidate_addr_r1
546 FUNCTION(invalidate_addr_r2):
547 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
549 b invalidate_addr_call
550 .size invalidate_addr_r2, .-invalidate_addr_r2
552 FUNCTION(invalidate_addr_r3):
553 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
555 b invalidate_addr_call
556 .size invalidate_addr_r3, .-invalidate_addr_r3
558 FUNCTION(invalidate_addr_r4):
559 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
561 b invalidate_addr_call
562 .size invalidate_addr_r4, .-invalidate_addr_r4
564 FUNCTION(invalidate_addr_r5):
565 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
567 b invalidate_addr_call
568 .size invalidate_addr_r5, .-invalidate_addr_r5
570 FUNCTION(invalidate_addr_r6):
571 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
573 b invalidate_addr_call
574 .size invalidate_addr_r6, .-invalidate_addr_r6
576 FUNCTION(invalidate_addr_r7):
577 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
579 b invalidate_addr_call
580 .size invalidate_addr_r7, .-invalidate_addr_r7
582 FUNCTION(invalidate_addr_r8):
583 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
585 b invalidate_addr_call
586 .size invalidate_addr_r8, .-invalidate_addr_r8
588 FUNCTION(invalidate_addr_r9):
589 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
591 b invalidate_addr_call
592 .size invalidate_addr_r9, .-invalidate_addr_r9
594 FUNCTION(invalidate_addr_r10):
595 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
597 b invalidate_addr_call
598 .size invalidate_addr_r10, .-invalidate_addr_r10
600 FUNCTION(invalidate_addr_r12):
601 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
603 .size invalidate_addr_r12, .-invalidate_addr_r12
605 invalidate_addr_call:
606 ldr r12, [fp, #LO_inv_code_start]
607 ldr lr, [fp, #LO_inv_code_end]
611 ldmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
612 .size invalidate_addr_call, .-invalidate_addr_call
615 FUNCTION(new_dyna_start):
616 /* ip is stored to conform EABI alignment */
617 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
618 mov fp, r0 /* dynarec_local */
619 ldr r0, [fp, #LO_pcaddr]
621 ldr r1, [fp, #LO_next_interupt]
622 ldr r10, [fp, #LO_cycle]
623 str r1, [fp, #LO_last_count]
626 .size new_dyna_start, .-new_dyna_start
628 /* --------------------------------------- */
632 .macro pcsx_read_mem readop tab_shift
633 /* r0 = address, r1 = handler_tab, r2 = cycles */
635 lsr r3, #(20+\tab_shift)
636 ldr r12, [fp, #LO_last_count]
637 ldr r1, [r1, r3, lsl #2]
644 \readop r0, [r1, r3, lsl #\tab_shift]
647 str r2, [fp, #LO_cycle]
651 FUNCTION(jump_handler_read8):
652 add r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
653 pcsx_read_mem ldrbcc, 0
655 FUNCTION(jump_handler_read16):
656 add r1, #0x1000/4*4 @ shift to r16 part
657 pcsx_read_mem ldrhcc, 1
659 FUNCTION(jump_handler_read32):
660 pcsx_read_mem ldrcc, 2
663 .macro pcsx_write_mem wrtop tab_shift
664 /* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
666 lsr r12, #(20+\tab_shift)
667 ldr r3, [r3, r12, lsl #2]
668 str r0, [fp, #LO_address] @ some handlers still need it..
670 mov r0, r2 @ cycle return in case of direct store
675 \wrtop r1, [r3, r12, lsl #\tab_shift]
678 ldr r12, [fp, #LO_last_count]
682 str r2, [fp, #LO_cycle]
685 ldr r0, [fp, #LO_next_interupt]
687 str r0, [fp, #LO_last_count]
692 FUNCTION(jump_handler_write8):
693 add r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
694 pcsx_write_mem strbcc, 0
696 FUNCTION(jump_handler_write16):
697 add r3, #0x1000/4*4 @ shift to r16 part
698 pcsx_write_mem strhcc, 1
700 FUNCTION(jump_handler_write32):
701 pcsx_write_mem strcc, 2
703 FUNCTION(jump_handler_write_h):
704 /* r0 = address, r1 = data, r2 = cycles, r3 = handler */
705 ldr r12, [fp, #LO_last_count]
706 str r0, [fp, #LO_address] @ some handlers still need it..
710 str r2, [fp, #LO_cycle]
713 ldr r0, [fp, #LO_next_interupt]
715 str r0, [fp, #LO_last_count]
719 FUNCTION(jump_handle_swl):
720 /* r0 = address, r1 = data, r2 = cycles */
721 ldr r3, [fp, #LO_mem_wtab]
723 ldr r3, [r3, r12, lsl #2]
744 lsreq r12, r1, #24 @ 0
754 FUNCTION(jump_handle_swr):
755 /* r0 = address, r1 = data, r2 = cycles */
756 ldr r3, [fp, #LO_mem_wtab]
758 ldr r3, [r3, r12, lsl #2]
780 .macro rcntx_read_mode0 num
781 /* r0 = address, r2 = cycles */
782 ldr r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart
784 sub r0, r0, r3, lsl #16
789 FUNCTION(rcnt0_read_count_m0):
792 FUNCTION(rcnt1_read_count_m0):
795 FUNCTION(rcnt2_read_count_m0):
798 FUNCTION(rcnt0_read_count_m1):
799 /* r0 = address, r2 = cycles */
800 ldr r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart
803 mul r0, r1, r2 @ /= 5
807 FUNCTION(rcnt1_read_count_m1):
808 /* r0 = address, r2 = cycles */
809 ldr r3, [fp, #LO_rcnts+6*4+7*4*1]
812 umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd
815 FUNCTION(rcnt2_read_count_m1):
816 /* r0 = address, r2 = cycles */
817 ldr r3, [fp, #LO_rcnts+6*4+7*4*2]
818 mov r0, r2, lsl #16-3
819 sub r0, r0, r3, lsl #16-3
823 @ vim:filetype=armasm