1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
26 #include "emu_if.h" //emulator interface
29 //#define assem_debug printf
30 //#define inv_debug printf
31 #define assem_debug(...)
32 #define inv_debug(...)
35 #include "assem_x86.h"
38 #include "assem_x64.h"
41 #include "assem_arm.h"
45 #define MAX_OUTPUT_BLOCK_SIZE 262144
47 int cycle_multiplier; // 100 for 1.0
48 #define CLOCK_ADJUST(x) (((x) * cycle_multiplier + 50) / 100)
52 signed char regmap_entry[HOST_REGS];
53 signed char regmap[HOST_REGS];
62 uint64_t constmap[HOST_REGS];
70 struct ll_entry *next;
76 char insn[MAXBLOCK][10];
77 u_char itype[MAXBLOCK];
78 u_char opcode[MAXBLOCK];
79 u_char opcode2[MAXBLOCK];
87 u_char dep1[MAXBLOCK];
88 u_char dep2[MAXBLOCK];
90 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
91 static uint64_t gte_rt[MAXBLOCK];
92 static uint64_t gte_unneeded[MAXBLOCK];
93 static int gte_reads_flags; // gte flag read encountered
94 static u_int smrv[32]; // speculated MIPS register values
95 static u_int smrv_strong; // mask or regs that are likely to have correct values
96 static u_int smrv_weak; // same, but somewhat less likely
97 static u_int smrv_strong_next; // same, but after current insn executes
98 static u_int smrv_weak_next;
101 char likely[MAXBLOCK];
102 char is_ds[MAXBLOCK];
104 uint64_t unneeded_reg[MAXBLOCK];
105 uint64_t unneeded_reg_upper[MAXBLOCK];
106 uint64_t branch_unneeded_reg[MAXBLOCK];
107 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
108 uint64_t p32[MAXBLOCK];
109 uint64_t pr32[MAXBLOCK];
110 signed char regmap_pre[MAXBLOCK][HOST_REGS];
111 signed char regmap[MAXBLOCK][HOST_REGS];
112 signed char regmap_entry[MAXBLOCK][HOST_REGS];
113 uint64_t constmap[MAXBLOCK][HOST_REGS];
114 struct regstat regs[MAXBLOCK];
115 struct regstat branch_regs[MAXBLOCK];
116 signed char minimum_free_regs[MAXBLOCK];
117 u_int needed_reg[MAXBLOCK];
118 uint64_t requires_32bit[MAXBLOCK];
119 u_int wont_dirty[MAXBLOCK];
120 u_int will_dirty[MAXBLOCK];
123 u_int instr_addr[MAXBLOCK];
124 u_int link_addr[MAXBLOCK][3];
126 u_int stubs[MAXBLOCK*3][8];
128 u_int literals[1024][2];
133 struct ll_entry *jump_in[4096];
134 struct ll_entry *jump_out[4096];
135 struct ll_entry *jump_dirty[4096];
136 u_int hash_table[65536][4] __attribute__((aligned(16)));
137 char shadow[1048576] __attribute__((aligned(16)));
143 static const u_int using_tlb=0;
145 int new_dynarec_did_compile;
146 u_int stop_after_jal;
147 extern u_char restore_candidate[512];
148 extern int cycle_count;
150 /* registers that may be allocated */
152 #define HIREG 32 // hi
153 #define LOREG 33 // lo
154 #define FSREG 34 // FPU status (FCSR)
155 #define CSREG 35 // Coprocessor status
156 #define CCREG 36 // Cycle count
157 #define INVCP 37 // Pointer to invalid_code
158 #define MMREG 38 // Pointer to memory_map
159 #define ROREG 39 // ram offset (if rdram!=0x80000000)
161 #define FTEMP 40 // FPU temporary register
162 #define PTEMP 41 // Prefetch temporary register
163 #define TLREG 42 // TLB mapping offset
164 #define RHASH 43 // Return address hash
165 #define RHTBL 44 // Return address hash table address
166 #define RTEMP 45 // JR/JALR address register
168 #define AGEN1 46 // Address generation temporary register
169 #define AGEN2 47 // Address generation temporary register
170 #define MGEN1 48 // Maptable address generation temporary register
171 #define MGEN2 49 // Maptable address generation temporary register
172 #define BTREG 50 // Branch target temporary register
174 /* instruction types */
175 #define NOP 0 // No operation
176 #define LOAD 1 // Load
177 #define STORE 2 // Store
178 #define LOADLR 3 // Unaligned load
179 #define STORELR 4 // Unaligned store
180 #define MOV 5 // Move
181 #define ALU 6 // Arithmetic/logic
182 #define MULTDIV 7 // Multiply/divide
183 #define SHIFT 8 // Shift by register
184 #define SHIFTIMM 9// Shift by immediate
185 #define IMM16 10 // 16-bit immediate
186 #define RJUMP 11 // Unconditional jump to register
187 #define UJUMP 12 // Unconditional jump
188 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
189 #define SJUMP 14 // Conditional branch (regimm format)
190 #define COP0 15 // Coprocessor 0
191 #define COP1 16 // Coprocessor 1
192 #define C1LS 17 // Coprocessor 1 load/store
193 #define FJUMP 18 // Conditional branch (floating point)
194 #define FLOAT 19 // Floating point unit
195 #define FCONV 20 // Convert integer to float
196 #define FCOMP 21 // Floating point compare (sets FSREG)
197 #define SYSCALL 22// SYSCALL
198 #define OTHER 23 // Other
199 #define SPAN 24 // Branch/delay slot spans 2 pages
200 #define NI 25 // Not implemented
201 #define HLECALL 26// PCSX fake opcodes for HLE
202 #define COP2 27 // Coprocessor 2 move
203 #define C2LS 28 // Coprocessor 2 load/store
204 #define C2OP 29 // Coprocessor 2 operation
205 #define INTCALL 30// Call interpreter to handle rare corner cases
214 #define LOADBU_STUB 7
215 #define LOADHU_STUB 8
216 #define STOREB_STUB 9
217 #define STOREH_STUB 10
218 #define STOREW_STUB 11
219 #define STORED_STUB 12
220 #define STORELR_STUB 13
221 #define INVCODE_STUB 14
229 int new_recompile_block(int addr);
230 void *get_addr_ht(u_int vaddr);
231 void invalidate_block(u_int block);
232 void invalidate_addr(u_int addr);
233 void remove_hash(int vaddr);
236 void dyna_linker_ds();
238 void verify_code_vm();
239 void verify_code_ds();
242 void fp_exception_ds();
244 void jump_syscall_hle();
248 void new_dyna_leave();
253 void read_nomem_new();
254 void read_nomemb_new();
255 void read_nomemh_new();
256 void read_nomemd_new();
257 void write_nomem_new();
258 void write_nomemb_new();
259 void write_nomemh_new();
260 void write_nomemd_new();
261 void write_rdram_new();
262 void write_rdramb_new();
263 void write_rdramh_new();
264 void write_rdramd_new();
265 extern u_int memory_map[1048576];
267 // Needed by assembler
268 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
269 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
270 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
271 void load_all_regs(signed char i_regmap[]);
272 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
273 void load_regs_entry(int t);
274 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
278 //#define DEBUG_CYCLE_COUNT 1
280 static void tlb_hacks()
284 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
288 switch (ROM_HEADER->Country_code&0xFF)
300 // Unknown country code
304 u_int rom_addr=(u_int)rom;
306 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
307 // in the lower 4G of memory to use this hack. Copy it if necessary.
308 if((void *)rom>(void *)0xffffffff) {
309 munmap(ROM_COPY, 67108864);
310 if(mmap(ROM_COPY, 12582912,
311 PROT_READ | PROT_WRITE,
312 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
313 -1, 0) <= 0) {printf("mmap() failed\n");}
314 memcpy(ROM_COPY,rom,12582912);
315 rom_addr=(u_int)ROM_COPY;
319 for(n=0x7F000;n<0x80000;n++) {
320 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
327 static u_int get_page(u_int vaddr)
330 u_int page=(vaddr^0x80000000)>>12;
332 u_int page=vaddr&~0xe0000000;
333 if (page < 0x1000000)
334 page &= ~0x0e00000; // RAM mirrors
338 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
340 if(page>2048) page=2048+(page&2047);
344 static u_int get_vpage(u_int vaddr)
346 u_int vpage=(vaddr^0x80000000)>>12;
348 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
350 if(vpage>2048) vpage=2048+(vpage&2047);
354 // Get address from virtual address
355 // This is called from the recompiled JR/JALR instructions
356 void *get_addr(u_int vaddr)
358 u_int page=get_page(vaddr);
359 u_int vpage=get_vpage(vaddr);
360 struct ll_entry *head;
361 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
364 if(head->vaddr==vaddr&&head->reg32==0) {
365 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
366 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
369 ht_bin[1]=(int)head->addr;
375 head=jump_dirty[vpage];
377 if(head->vaddr==vaddr&&head->reg32==0) {
378 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
379 // Don't restore blocks which are about to expire from the cache
380 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
381 if(verify_dirty(head->addr)) {
382 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
383 invalid_code[vaddr>>12]=0;
384 inv_code_start=inv_code_end=~0;
386 memory_map[vaddr>>12]|=0x40000000;
390 if(tlb_LUT_r[vaddr>>12]) {
391 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
392 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
395 restore_candidate[vpage>>3]|=1<<(vpage&7);
397 else restore_candidate[page>>3]|=1<<(page&7);
398 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
399 if(ht_bin[0]==vaddr) {
400 ht_bin[1]=(int)head->addr; // Replace existing entry
406 ht_bin[1]=(int)head->addr;
414 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
415 int r=new_recompile_block(vaddr);
416 if(r==0) return get_addr(vaddr);
417 // Execute in unmapped page, generate pagefault execption
419 Cause=(vaddr<<31)|0x8;
420 EPC=(vaddr&1)?vaddr-5:vaddr;
422 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
423 EntryHi=BadVAddr&0xFFFFE000;
424 return get_addr_ht(0x80000000);
426 // Look up address in hash table first
427 void *get_addr_ht(u_int vaddr)
429 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
430 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
431 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
432 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
433 return get_addr(vaddr);
436 void *get_addr_32(u_int vaddr,u_int flags)
439 return get_addr(vaddr);
441 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
442 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
443 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
444 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
445 u_int page=get_page(vaddr);
446 u_int vpage=get_vpage(vaddr);
447 struct ll_entry *head;
450 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
451 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
453 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
455 ht_bin[1]=(int)head->addr;
457 }else if(ht_bin[2]==-1) {
458 ht_bin[3]=(int)head->addr;
461 //ht_bin[3]=ht_bin[1];
462 //ht_bin[2]=ht_bin[0];
463 //ht_bin[1]=(int)head->addr;
470 head=jump_dirty[vpage];
472 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
473 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
474 // Don't restore blocks which are about to expire from the cache
475 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
476 if(verify_dirty(head->addr)) {
477 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
478 invalid_code[vaddr>>12]=0;
479 inv_code_start=inv_code_end=~0;
480 memory_map[vaddr>>12]|=0x40000000;
483 if(tlb_LUT_r[vaddr>>12]) {
484 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
485 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
488 restore_candidate[vpage>>3]|=1<<(vpage&7);
490 else restore_candidate[page>>3]|=1<<(page&7);
492 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
494 ht_bin[1]=(int)head->addr;
496 }else if(ht_bin[2]==-1) {
497 ht_bin[3]=(int)head->addr;
500 //ht_bin[3]=ht_bin[1];
501 //ht_bin[2]=ht_bin[0];
502 //ht_bin[1]=(int)head->addr;
510 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
511 int r=new_recompile_block(vaddr);
512 if(r==0) return get_addr(vaddr);
513 // Execute in unmapped page, generate pagefault execption
515 Cause=(vaddr<<31)|0x8;
516 EPC=(vaddr&1)?vaddr-5:vaddr;
518 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
519 EntryHi=BadVAddr&0xFFFFE000;
520 return get_addr_ht(0x80000000);
524 void clear_all_regs(signed char regmap[])
527 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
530 signed char get_reg(signed char regmap[],int r)
533 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
537 // Find a register that is available for two consecutive cycles
538 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
541 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
545 int count_free_regs(signed char regmap[])
549 for(hr=0;hr<HOST_REGS;hr++)
551 if(hr!=EXCLUDE_REG) {
552 if(regmap[hr]<0) count++;
558 void dirty_reg(struct regstat *cur,signed char reg)
562 for (hr=0;hr<HOST_REGS;hr++) {
563 if((cur->regmap[hr]&63)==reg) {
569 // If we dirty the lower half of a 64 bit register which is now being
570 // sign-extended, we need to dump the upper half.
571 // Note: Do this only after completion of the instruction, because
572 // some instructions may need to read the full 64-bit value even if
573 // overwriting it (eg SLTI, DSRA32).
574 static void flush_dirty_uppers(struct regstat *cur)
577 for (hr=0;hr<HOST_REGS;hr++) {
578 if((cur->dirty>>hr)&1) {
581 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
586 void set_const(struct regstat *cur,signed char reg,uint64_t value)
590 for (hr=0;hr<HOST_REGS;hr++) {
591 if(cur->regmap[hr]==reg) {
593 cur->constmap[hr]=value;
595 else if((cur->regmap[hr]^64)==reg) {
597 cur->constmap[hr]=value>>32;
602 void clear_const(struct regstat *cur,signed char reg)
606 for (hr=0;hr<HOST_REGS;hr++) {
607 if((cur->regmap[hr]&63)==reg) {
608 cur->isconst&=~(1<<hr);
613 int is_const(struct regstat *cur,signed char reg)
618 for (hr=0;hr<HOST_REGS;hr++) {
619 if((cur->regmap[hr]&63)==reg) {
620 return (cur->isconst>>hr)&1;
625 uint64_t get_const(struct regstat *cur,signed char reg)
629 for (hr=0;hr<HOST_REGS;hr++) {
630 if(cur->regmap[hr]==reg) {
631 return cur->constmap[hr];
634 printf("Unknown constant in r%d\n",reg);
638 // Least soon needed registers
639 // Look at the next ten instructions and see which registers
640 // will be used. Try not to reallocate these.
641 void lsn(u_char hsn[], int i, int *preferred_reg)
651 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
653 // Don't go past an unconditonal jump
660 if(rs1[i+j]) hsn[rs1[i+j]]=j;
661 if(rs2[i+j]) hsn[rs2[i+j]]=j;
662 if(rt1[i+j]) hsn[rt1[i+j]]=j;
663 if(rt2[i+j]) hsn[rt2[i+j]]=j;
664 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
665 // Stores can allocate zero
669 // On some architectures stores need invc_ptr
670 #if defined(HOST_IMM8)
671 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
675 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
683 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
685 // Follow first branch
686 int t=(ba[i+b]-start)>>2;
687 j=7-b;if(t+j>=slen) j=slen-t-1;
690 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
691 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
692 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
693 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
696 // TODO: preferred register based on backward branch
698 // Delay slot should preferably not overwrite branch conditions or cycle count
699 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
700 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
701 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
707 // Coprocessor load/store needs FTEMP, even if not declared
708 if(itype[i]==C1LS||itype[i]==C2LS) {
711 // Load L/R also uses FTEMP as a temporary register
712 if(itype[i]==LOADLR) {
715 // Also SWL/SWR/SDL/SDR
716 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
719 // Don't remove the TLB registers either
720 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
723 // Don't remove the miniht registers
724 if(itype[i]==UJUMP||itype[i]==RJUMP)
731 // We only want to allocate registers if we're going to use them again soon
732 int needed_again(int r, int i)
738 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
740 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
741 return 0; // Don't need any registers if exiting the block
749 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
751 // Don't go past an unconditonal jump
755 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
762 if(rs1[i+j]==r) rn=j;
763 if(rs2[i+j]==r) rn=j;
764 if((unneeded_reg[i+j]>>r)&1) rn=10;
765 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
773 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
775 // Follow first branch
777 int t=(ba[i+b]-start)>>2;
778 j=7-b;if(t+j>=slen) j=slen-t-1;
781 if(!((unneeded_reg[t+j]>>r)&1)) {
782 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
783 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
793 // Try to match register allocations at the end of a loop with those
795 int loop_reg(int i, int r, int hr)
804 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
806 // Don't go past an unconditonal jump
813 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
818 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
819 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
820 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
822 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
824 int t=(ba[i+k]-start)>>2;
825 int reg=get_reg(regs[t].regmap_entry,r);
826 if(reg>=0) return reg;
827 //reg=get_reg(regs[t+1].regmap_entry,r);
828 //if(reg>=0) return reg;
836 // Allocate every register, preserving source/target regs
837 void alloc_all(struct regstat *cur,int i)
841 for(hr=0;hr<HOST_REGS;hr++) {
842 if(hr!=EXCLUDE_REG) {
843 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
844 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
847 cur->dirty&=~(1<<hr);
850 if((cur->regmap[hr]&63)==0)
853 cur->dirty&=~(1<<hr);
860 void div64(int64_t dividend,int64_t divisor)
864 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
865 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
867 void divu64(uint64_t dividend,uint64_t divisor)
871 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
872 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
875 void mult64(uint64_t m1,uint64_t m2)
877 unsigned long long int op1, op2, op3, op4;
878 unsigned long long int result1, result2, result3, result4;
879 unsigned long long int temp1, temp2, temp3, temp4;
895 op1 = op2 & 0xFFFFFFFF;
896 op2 = (op2 >> 32) & 0xFFFFFFFF;
897 op3 = op4 & 0xFFFFFFFF;
898 op4 = (op4 >> 32) & 0xFFFFFFFF;
901 temp2 = (temp1 >> 32) + op1 * op4;
903 temp4 = (temp3 >> 32) + op2 * op4;
905 result1 = temp1 & 0xFFFFFFFF;
906 result2 = temp2 + (temp3 & 0xFFFFFFFF);
907 result3 = (result2 >> 32) + temp4;
908 result4 = (result3 >> 32);
910 lo = result1 | (result2 << 32);
911 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
920 void multu64(uint64_t m1,uint64_t m2)
922 unsigned long long int op1, op2, op3, op4;
923 unsigned long long int result1, result2, result3, result4;
924 unsigned long long int temp1, temp2, temp3, temp4;
926 op1 = m1 & 0xFFFFFFFF;
927 op2 = (m1 >> 32) & 0xFFFFFFFF;
928 op3 = m2 & 0xFFFFFFFF;
929 op4 = (m2 >> 32) & 0xFFFFFFFF;
932 temp2 = (temp1 >> 32) + op1 * op4;
934 temp4 = (temp3 >> 32) + op2 * op4;
936 result1 = temp1 & 0xFFFFFFFF;
937 result2 = temp2 + (temp3 & 0xFFFFFFFF);
938 result3 = (result2 >> 32) + temp4;
939 result4 = (result3 >> 32);
941 lo = result1 | (result2 << 32);
942 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
944 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
945 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
948 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
956 else original=loaded;
959 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
962 original>>=64-(bits^56);
963 original<<=64-(bits^56);
967 else original=loaded;
973 #include "assem_x86.c"
976 #include "assem_x64.c"
979 #include "assem_arm.c"
982 // Add virtual address mapping to linked list
983 void ll_add(struct ll_entry **head,int vaddr,void *addr)
985 struct ll_entry *new_entry;
986 new_entry=malloc(sizeof(struct ll_entry));
987 assert(new_entry!=NULL);
988 new_entry->vaddr=vaddr;
990 new_entry->addr=addr;
991 new_entry->next=*head;
995 // Add virtual address mapping for 32-bit compiled block
996 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
998 ll_add(head,vaddr,addr);
1000 (*head)->reg32=reg32;
1004 // Check if an address is already compiled
1005 // but don't return addresses which are about to expire from the cache
1006 void *check_addr(u_int vaddr)
1008 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1009 if(ht_bin[0]==vaddr) {
1010 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1011 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1013 if(ht_bin[2]==vaddr) {
1014 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1015 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1017 u_int page=get_page(vaddr);
1018 struct ll_entry *head;
1021 if(head->vaddr==vaddr&&head->reg32==0) {
1022 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1023 // Update existing entry with current address
1024 if(ht_bin[0]==vaddr) {
1025 ht_bin[1]=(int)head->addr;
1028 if(ht_bin[2]==vaddr) {
1029 ht_bin[3]=(int)head->addr;
1032 // Insert into hash table with low priority.
1033 // Don't evict existing entries, as they are probably
1034 // addresses that are being accessed frequently.
1036 ht_bin[1]=(int)head->addr;
1038 }else if(ht_bin[2]==-1) {
1039 ht_bin[3]=(int)head->addr;
1050 void remove_hash(int vaddr)
1052 //printf("remove hash: %x\n",vaddr);
1053 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1054 if(ht_bin[2]==vaddr) {
1055 ht_bin[2]=ht_bin[3]=-1;
1057 if(ht_bin[0]==vaddr) {
1058 ht_bin[0]=ht_bin[2];
1059 ht_bin[1]=ht_bin[3];
1060 ht_bin[2]=ht_bin[3]=-1;
1064 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1066 struct ll_entry *next;
1068 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1069 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1071 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1072 remove_hash((*head)->vaddr);
1079 head=&((*head)->next);
1084 // Remove all entries from linked list
1085 void ll_clear(struct ll_entry **head)
1087 struct ll_entry *cur;
1088 struct ll_entry *next;
1099 // Dereference the pointers and remove if it matches
1100 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1103 int ptr=get_pointer(head->addr);
1104 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1105 if(((ptr>>shift)==(addr>>shift)) ||
1106 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1108 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1109 u_int host_addr=(u_int)kill_pointer(head->addr);
1111 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1118 // This is called when we write to a compiled block (see do_invstub)
1119 void invalidate_page(u_int page)
1121 struct ll_entry *head;
1122 struct ll_entry *next;
1126 inv_debug("INVALIDATE: %x\n",head->vaddr);
1127 remove_hash(head->vaddr);
1132 head=jump_out[page];
1135 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1136 u_int host_addr=(u_int)kill_pointer(head->addr);
1138 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1146 static void invalidate_block_range(u_int block, u_int first, u_int last)
1148 u_int page=get_page(block<<12);
1149 //printf("first=%d last=%d\n",first,last);
1150 invalidate_page(page);
1151 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1152 assert(last<page+5);
1153 // Invalidate the adjacent pages if a block crosses a 4K boundary
1155 invalidate_page(first);
1158 for(first=page+1;first<last;first++) {
1159 invalidate_page(first);
1165 // Don't trap writes
1166 invalid_code[block]=1;
1168 // If there is a valid TLB entry for this page, remove write protect
1169 if(tlb_LUT_w[block]) {
1170 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1171 // CHECK: Is this right?
1172 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1173 u_int real_block=tlb_LUT_w[block]>>12;
1174 invalid_code[real_block]=1;
1175 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1177 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1181 memset(mini_ht,-1,sizeof(mini_ht));
1185 void invalidate_block(u_int block)
1187 u_int page=get_page(block<<12);
1188 u_int vpage=get_vpage(block<<12);
1189 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1190 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1193 struct ll_entry *head;
1194 head=jump_dirty[vpage];
1195 //printf("page=%d vpage=%d\n",page,vpage);
1198 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1199 get_bounds((int)head->addr,&start,&end);
1200 //printf("start: %x end: %x\n",start,end);
1201 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1202 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1203 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1204 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1208 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1209 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1210 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1211 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1218 invalidate_block_range(block,first,last);
1221 void invalidate_addr(u_int addr)
1225 // this check is done by the caller
1226 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1227 u_int page=get_page(addr);
1228 if(page<2048) { // RAM
1229 struct ll_entry *head;
1230 u_int addr_min=~0, addr_max=0;
1231 int mask=RAM_SIZE-1;
1233 inv_code_start=addr&~0xfff;
1234 inv_code_end=addr|0xfff;
1237 // must check previous page too because of spans..
1239 inv_code_start-=0x1000;
1241 for(;pg1<=page;pg1++) {
1242 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1244 get_bounds((int)head->addr,&start,&end);
1245 if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1246 if(start<addr_min) addr_min=start;
1247 if(end>addr_max) addr_max=end;
1249 else if(addr<start) {
1250 if(start<inv_code_end)
1251 inv_code_end=start-1;
1254 if(end>inv_code_start)
1260 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1261 inv_code_start=inv_code_end=~0;
1262 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1266 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);//rhits);
1269 if(page!=0) // FIXME: don't know what's up with page 0 (Klonoa)
1273 invalidate_block(addr>>12);
1276 // This is called when loading a save state.
1277 // Anything could have changed, so invalidate everything.
1278 void invalidate_all_pages()
1281 for(page=0;page<4096;page++)
1282 invalidate_page(page);
1283 for(page=0;page<1048576;page++)
1284 if(!invalid_code[page]) {
1285 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1286 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1289 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1292 memset(mini_ht,-1,sizeof(mini_ht));
1296 for(page=0;page<0x100000;page++) {
1297 if(tlb_LUT_r[page]) {
1298 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1299 if(!tlb_LUT_w[page]||!invalid_code[page])
1300 memory_map[page]|=0x40000000; // Write protect
1302 else memory_map[page]=-1;
1303 if(page==0x80000) page=0xC0000;
1309 // Add an entry to jump_out after making a link
1310 void add_link(u_int vaddr,void *src)
1312 u_int page=get_page(vaddr);
1313 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1314 int *ptr=(int *)(src+4);
1315 assert((*ptr&0x0fff0000)==0x059f0000);
1316 ll_add(jump_out+page,vaddr,src);
1317 //int ptr=get_pointer(src);
1318 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1321 // If a code block was found to be unmodified (bit was set in
1322 // restore_candidate) and it remains unmodified (bit is clear
1323 // in invalid_code) then move the entries for that 4K page from
1324 // the dirty list to the clean list.
1325 void clean_blocks(u_int page)
1327 struct ll_entry *head;
1328 inv_debug("INV: clean_blocks page=%d\n",page);
1329 head=jump_dirty[page];
1331 if(!invalid_code[head->vaddr>>12]) {
1332 // Don't restore blocks which are about to expire from the cache
1333 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1335 if(verify_dirty((int)head->addr)) {
1336 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1339 get_bounds((int)head->addr,&start,&end);
1340 if(start-(u_int)rdram<RAM_SIZE) {
1341 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1342 inv|=invalid_code[i];
1346 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1347 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1348 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1349 if(addr<start||addr>=end) inv=1;
1352 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1356 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1357 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1360 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1362 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1363 //printf("page=%x, addr=%x\n",page,head->vaddr);
1364 //assert(head->vaddr>>12==(page|0x80000));
1365 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1366 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1368 if(ht_bin[0]==head->vaddr) {
1369 ht_bin[1]=(int)clean_addr; // Replace existing entry
1371 if(ht_bin[2]==head->vaddr) {
1372 ht_bin[3]=(int)clean_addr; // Replace existing entry
1385 void mov_alloc(struct regstat *current,int i)
1387 // Note: Don't need to actually alloc the source registers
1388 if((~current->is32>>rs1[i])&1) {
1389 //alloc_reg64(current,i,rs1[i]);
1390 alloc_reg64(current,i,rt1[i]);
1391 current->is32&=~(1LL<<rt1[i]);
1393 //alloc_reg(current,i,rs1[i]);
1394 alloc_reg(current,i,rt1[i]);
1395 current->is32|=(1LL<<rt1[i]);
1397 clear_const(current,rs1[i]);
1398 clear_const(current,rt1[i]);
1399 dirty_reg(current,rt1[i]);
1402 void shiftimm_alloc(struct regstat *current,int i)
1404 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1407 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1409 alloc_reg(current,i,rt1[i]);
1410 current->is32|=1LL<<rt1[i];
1411 dirty_reg(current,rt1[i]);
1412 if(is_const(current,rs1[i])) {
1413 int v=get_const(current,rs1[i]);
1414 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1415 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1416 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1418 else clear_const(current,rt1[i]);
1423 clear_const(current,rs1[i]);
1424 clear_const(current,rt1[i]);
1427 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1430 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1431 alloc_reg64(current,i,rt1[i]);
1432 current->is32&=~(1LL<<rt1[i]);
1433 dirty_reg(current,rt1[i]);
1436 if(opcode2[i]==0x3c) // DSLL32
1439 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1440 alloc_reg64(current,i,rt1[i]);
1441 current->is32&=~(1LL<<rt1[i]);
1442 dirty_reg(current,rt1[i]);
1445 if(opcode2[i]==0x3e) // DSRL32
1448 alloc_reg64(current,i,rs1[i]);
1450 alloc_reg64(current,i,rt1[i]);
1451 current->is32&=~(1LL<<rt1[i]);
1453 alloc_reg(current,i,rt1[i]);
1454 current->is32|=1LL<<rt1[i];
1456 dirty_reg(current,rt1[i]);
1459 if(opcode2[i]==0x3f) // DSRA32
1462 alloc_reg64(current,i,rs1[i]);
1463 alloc_reg(current,i,rt1[i]);
1464 current->is32|=1LL<<rt1[i];
1465 dirty_reg(current,rt1[i]);
1470 void shift_alloc(struct regstat *current,int i)
1473 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1475 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1476 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1477 alloc_reg(current,i,rt1[i]);
1478 if(rt1[i]==rs2[i]) {
1479 alloc_reg_temp(current,i,-1);
1480 minimum_free_regs[i]=1;
1482 current->is32|=1LL<<rt1[i];
1483 } else { // DSLLV/DSRLV/DSRAV
1484 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1485 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1486 alloc_reg64(current,i,rt1[i]);
1487 current->is32&=~(1LL<<rt1[i]);
1488 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1490 alloc_reg_temp(current,i,-1);
1491 minimum_free_regs[i]=1;
1494 clear_const(current,rs1[i]);
1495 clear_const(current,rs2[i]);
1496 clear_const(current,rt1[i]);
1497 dirty_reg(current,rt1[i]);
1501 void alu_alloc(struct regstat *current,int i)
1503 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1505 if(rs1[i]&&rs2[i]) {
1506 alloc_reg(current,i,rs1[i]);
1507 alloc_reg(current,i,rs2[i]);
1510 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1511 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1513 alloc_reg(current,i,rt1[i]);
1515 current->is32|=1LL<<rt1[i];
1517 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1519 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1521 alloc_reg64(current,i,rs1[i]);
1522 alloc_reg64(current,i,rs2[i]);
1523 alloc_reg(current,i,rt1[i]);
1525 alloc_reg(current,i,rs1[i]);
1526 alloc_reg(current,i,rs2[i]);
1527 alloc_reg(current,i,rt1[i]);
1530 current->is32|=1LL<<rt1[i];
1532 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1534 if(rs1[i]&&rs2[i]) {
1535 alloc_reg(current,i,rs1[i]);
1536 alloc_reg(current,i,rs2[i]);
1540 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1541 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1543 alloc_reg(current,i,rt1[i]);
1544 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1546 if(!((current->uu>>rt1[i])&1)) {
1547 alloc_reg64(current,i,rt1[i]);
1549 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1550 if(rs1[i]&&rs2[i]) {
1551 alloc_reg64(current,i,rs1[i]);
1552 alloc_reg64(current,i,rs2[i]);
1556 // Is is really worth it to keep 64-bit values in registers?
1558 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1559 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1563 current->is32&=~(1LL<<rt1[i]);
1565 current->is32|=1LL<<rt1[i];
1569 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1571 if(rs1[i]&&rs2[i]) {
1572 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1573 alloc_reg64(current,i,rs1[i]);
1574 alloc_reg64(current,i,rs2[i]);
1575 alloc_reg64(current,i,rt1[i]);
1577 alloc_reg(current,i,rs1[i]);
1578 alloc_reg(current,i,rs2[i]);
1579 alloc_reg(current,i,rt1[i]);
1583 alloc_reg(current,i,rt1[i]);
1584 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1585 // DADD used as move, or zeroing
1586 // If we have a 64-bit source, then make the target 64 bits too
1587 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1588 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1589 alloc_reg64(current,i,rt1[i]);
1590 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1591 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1592 alloc_reg64(current,i,rt1[i]);
1594 if(opcode2[i]>=0x2e&&rs2[i]) {
1595 // DSUB used as negation - 64-bit result
1596 // If we have a 32-bit register, extend it to 64 bits
1597 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1598 alloc_reg64(current,i,rt1[i]);
1602 if(rs1[i]&&rs2[i]) {
1603 current->is32&=~(1LL<<rt1[i]);
1605 current->is32&=~(1LL<<rt1[i]);
1606 if((current->is32>>rs1[i])&1)
1607 current->is32|=1LL<<rt1[i];
1609 current->is32&=~(1LL<<rt1[i]);
1610 if((current->is32>>rs2[i])&1)
1611 current->is32|=1LL<<rt1[i];
1613 current->is32|=1LL<<rt1[i];
1617 clear_const(current,rs1[i]);
1618 clear_const(current,rs2[i]);
1619 clear_const(current,rt1[i]);
1620 dirty_reg(current,rt1[i]);
1623 void imm16_alloc(struct regstat *current,int i)
1625 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1627 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1628 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1629 current->is32&=~(1LL<<rt1[i]);
1630 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1631 // TODO: Could preserve the 32-bit flag if the immediate is zero
1632 alloc_reg64(current,i,rt1[i]);
1633 alloc_reg64(current,i,rs1[i]);
1635 clear_const(current,rs1[i]);
1636 clear_const(current,rt1[i]);
1638 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1639 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1640 current->is32|=1LL<<rt1[i];
1641 clear_const(current,rs1[i]);
1642 clear_const(current,rt1[i]);
1644 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1645 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1646 if(rs1[i]!=rt1[i]) {
1647 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1648 alloc_reg64(current,i,rt1[i]);
1649 current->is32&=~(1LL<<rt1[i]);
1652 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1653 if(is_const(current,rs1[i])) {
1654 int v=get_const(current,rs1[i]);
1655 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1656 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1657 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1659 else clear_const(current,rt1[i]);
1661 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1662 if(is_const(current,rs1[i])) {
1663 int v=get_const(current,rs1[i]);
1664 set_const(current,rt1[i],v+imm[i]);
1666 else clear_const(current,rt1[i]);
1667 current->is32|=1LL<<rt1[i];
1670 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1671 current->is32|=1LL<<rt1[i];
1673 dirty_reg(current,rt1[i]);
1676 void load_alloc(struct regstat *current,int i)
1678 clear_const(current,rt1[i]);
1679 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1680 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1681 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1682 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1683 alloc_reg(current,i,rt1[i]);
1684 assert(get_reg(current->regmap,rt1[i])>=0);
1685 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1687 current->is32&=~(1LL<<rt1[i]);
1688 alloc_reg64(current,i,rt1[i]);
1690 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1692 current->is32&=~(1LL<<rt1[i]);
1693 alloc_reg64(current,i,rt1[i]);
1694 alloc_all(current,i);
1695 alloc_reg64(current,i,FTEMP);
1696 minimum_free_regs[i]=HOST_REGS;
1698 else current->is32|=1LL<<rt1[i];
1699 dirty_reg(current,rt1[i]);
1700 // If using TLB, need a register for pointer to the mapping table
1701 if(using_tlb) alloc_reg(current,i,TLREG);
1702 // LWL/LWR need a temporary register for the old value
1703 if(opcode[i]==0x22||opcode[i]==0x26)
1705 alloc_reg(current,i,FTEMP);
1706 alloc_reg_temp(current,i,-1);
1707 minimum_free_regs[i]=1;
1712 // Load to r0 or unneeded register (dummy load)
1713 // but we still need a register to calculate the address
1714 if(opcode[i]==0x22||opcode[i]==0x26)
1716 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1718 // If using TLB, need a register for pointer to the mapping table
1719 if(using_tlb) alloc_reg(current,i,TLREG);
1720 alloc_reg_temp(current,i,-1);
1721 minimum_free_regs[i]=1;
1722 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1724 alloc_all(current,i);
1725 alloc_reg64(current,i,FTEMP);
1726 minimum_free_regs[i]=HOST_REGS;
1731 void store_alloc(struct regstat *current,int i)
1733 clear_const(current,rs2[i]);
1734 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1735 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1736 alloc_reg(current,i,rs2[i]);
1737 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1738 alloc_reg64(current,i,rs2[i]);
1739 if(rs2[i]) alloc_reg(current,i,FTEMP);
1741 // If using TLB, need a register for pointer to the mapping table
1742 if(using_tlb) alloc_reg(current,i,TLREG);
1743 #if defined(HOST_IMM8)
1744 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1745 else alloc_reg(current,i,INVCP);
1747 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1748 alloc_reg(current,i,FTEMP);
1750 // We need a temporary register for address generation
1751 alloc_reg_temp(current,i,-1);
1752 minimum_free_regs[i]=1;
1755 void c1ls_alloc(struct regstat *current,int i)
1757 //clear_const(current,rs1[i]); // FIXME
1758 clear_const(current,rt1[i]);
1759 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1760 alloc_reg(current,i,CSREG); // Status
1761 alloc_reg(current,i,FTEMP);
1762 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1763 alloc_reg64(current,i,FTEMP);
1765 // If using TLB, need a register for pointer to the mapping table
1766 if(using_tlb) alloc_reg(current,i,TLREG);
1767 #if defined(HOST_IMM8)
1768 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1769 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1770 alloc_reg(current,i,INVCP);
1772 // We need a temporary register for address generation
1773 alloc_reg_temp(current,i,-1);
1776 void c2ls_alloc(struct regstat *current,int i)
1778 clear_const(current,rt1[i]);
1779 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1780 alloc_reg(current,i,FTEMP);
1781 // If using TLB, need a register for pointer to the mapping table
1782 if(using_tlb) alloc_reg(current,i,TLREG);
1783 #if defined(HOST_IMM8)
1784 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1785 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1786 alloc_reg(current,i,INVCP);
1788 // We need a temporary register for address generation
1789 alloc_reg_temp(current,i,-1);
1790 minimum_free_regs[i]=1;
1793 #ifndef multdiv_alloc
1794 void multdiv_alloc(struct regstat *current,int i)
1801 // case 0x1D: DMULTU
1804 clear_const(current,rs1[i]);
1805 clear_const(current,rs2[i]);
1808 if((opcode2[i]&4)==0) // 32-bit
1810 current->u&=~(1LL<<HIREG);
1811 current->u&=~(1LL<<LOREG);
1812 alloc_reg(current,i,HIREG);
1813 alloc_reg(current,i,LOREG);
1814 alloc_reg(current,i,rs1[i]);
1815 alloc_reg(current,i,rs2[i]);
1816 current->is32|=1LL<<HIREG;
1817 current->is32|=1LL<<LOREG;
1818 dirty_reg(current,HIREG);
1819 dirty_reg(current,LOREG);
1823 current->u&=~(1LL<<HIREG);
1824 current->u&=~(1LL<<LOREG);
1825 current->uu&=~(1LL<<HIREG);
1826 current->uu&=~(1LL<<LOREG);
1827 alloc_reg64(current,i,HIREG);
1828 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1829 alloc_reg64(current,i,rs1[i]);
1830 alloc_reg64(current,i,rs2[i]);
1831 alloc_all(current,i);
1832 current->is32&=~(1LL<<HIREG);
1833 current->is32&=~(1LL<<LOREG);
1834 dirty_reg(current,HIREG);
1835 dirty_reg(current,LOREG);
1836 minimum_free_regs[i]=HOST_REGS;
1841 // Multiply by zero is zero.
1842 // MIPS does not have a divide by zero exception.
1843 // The result is undefined, we return zero.
1844 alloc_reg(current,i,HIREG);
1845 alloc_reg(current,i,LOREG);
1846 current->is32|=1LL<<HIREG;
1847 current->is32|=1LL<<LOREG;
1848 dirty_reg(current,HIREG);
1849 dirty_reg(current,LOREG);
1854 void cop0_alloc(struct regstat *current,int i)
1856 if(opcode2[i]==0) // MFC0
1859 clear_const(current,rt1[i]);
1860 alloc_all(current,i);
1861 alloc_reg(current,i,rt1[i]);
1862 current->is32|=1LL<<rt1[i];
1863 dirty_reg(current,rt1[i]);
1866 else if(opcode2[i]==4) // MTC0
1869 clear_const(current,rs1[i]);
1870 alloc_reg(current,i,rs1[i]);
1871 alloc_all(current,i);
1874 alloc_all(current,i); // FIXME: Keep r0
1876 alloc_reg(current,i,0);
1881 // TLBR/TLBWI/TLBWR/TLBP/ERET
1882 assert(opcode2[i]==0x10);
1883 alloc_all(current,i);
1885 minimum_free_regs[i]=HOST_REGS;
1888 void cop1_alloc(struct regstat *current,int i)
1890 alloc_reg(current,i,CSREG); // Load status
1891 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1894 clear_const(current,rt1[i]);
1896 alloc_reg64(current,i,rt1[i]); // DMFC1
1897 current->is32&=~(1LL<<rt1[i]);
1899 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1900 current->is32|=1LL<<rt1[i];
1902 dirty_reg(current,rt1[i]);
1904 alloc_reg_temp(current,i,-1);
1906 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1909 clear_const(current,rs1[i]);
1911 alloc_reg64(current,i,rs1[i]); // DMTC1
1913 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1914 alloc_reg_temp(current,i,-1);
1918 alloc_reg(current,i,0);
1919 alloc_reg_temp(current,i,-1);
1922 minimum_free_regs[i]=1;
1924 void fconv_alloc(struct regstat *current,int i)
1926 alloc_reg(current,i,CSREG); // Load status
1927 alloc_reg_temp(current,i,-1);
1928 minimum_free_regs[i]=1;
1930 void float_alloc(struct regstat *current,int i)
1932 alloc_reg(current,i,CSREG); // Load status
1933 alloc_reg_temp(current,i,-1);
1934 minimum_free_regs[i]=1;
1936 void c2op_alloc(struct regstat *current,int i)
1938 alloc_reg_temp(current,i,-1);
1940 void fcomp_alloc(struct regstat *current,int i)
1942 alloc_reg(current,i,CSREG); // Load status
1943 alloc_reg(current,i,FSREG); // Load flags
1944 dirty_reg(current,FSREG); // Flag will be modified
1945 alloc_reg_temp(current,i,-1);
1946 minimum_free_regs[i]=1;
1949 void syscall_alloc(struct regstat *current,int i)
1951 alloc_cc(current,i);
1952 dirty_reg(current,CCREG);
1953 alloc_all(current,i);
1954 minimum_free_regs[i]=HOST_REGS;
1958 void delayslot_alloc(struct regstat *current,int i)
1969 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1970 printf("Disabled speculative precompilation\n");
1974 imm16_alloc(current,i);
1978 load_alloc(current,i);
1982 store_alloc(current,i);
1985 alu_alloc(current,i);
1988 shift_alloc(current,i);
1991 multdiv_alloc(current,i);
1994 shiftimm_alloc(current,i);
1997 mov_alloc(current,i);
2000 cop0_alloc(current,i);
2004 cop1_alloc(current,i);
2007 c1ls_alloc(current,i);
2010 c2ls_alloc(current,i);
2013 fconv_alloc(current,i);
2016 float_alloc(current,i);
2019 fcomp_alloc(current,i);
2022 c2op_alloc(current,i);
2027 // Special case where a branch and delay slot span two pages in virtual memory
2028 static void pagespan_alloc(struct regstat *current,int i)
2031 current->wasconst=0;
2033 minimum_free_regs[i]=HOST_REGS;
2034 alloc_all(current,i);
2035 alloc_cc(current,i);
2036 dirty_reg(current,CCREG);
2037 if(opcode[i]==3) // JAL
2039 alloc_reg(current,i,31);
2040 dirty_reg(current,31);
2042 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2044 alloc_reg(current,i,rs1[i]);
2046 alloc_reg(current,i,rt1[i]);
2047 dirty_reg(current,rt1[i]);
2050 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2052 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2053 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2054 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2056 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2057 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2061 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2063 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2064 if(!((current->is32>>rs1[i])&1))
2066 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2070 if(opcode[i]==0x11) // BC1
2072 alloc_reg(current,i,FSREG);
2073 alloc_reg(current,i,CSREG);
2078 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2080 stubs[stubcount][0]=type;
2081 stubs[stubcount][1]=addr;
2082 stubs[stubcount][2]=retaddr;
2083 stubs[stubcount][3]=a;
2084 stubs[stubcount][4]=b;
2085 stubs[stubcount][5]=c;
2086 stubs[stubcount][6]=d;
2087 stubs[stubcount][7]=e;
2091 // Write out a single register
2092 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2095 for(hr=0;hr<HOST_REGS;hr++) {
2096 if(hr!=EXCLUDE_REG) {
2097 if((regmap[hr]&63)==r) {
2100 emit_storereg(r,hr);
2102 if((is32>>regmap[hr])&1) {
2103 emit_sarimm(hr,31,hr);
2104 emit_storereg(r|64,hr);
2108 emit_storereg(r|64,hr);
2118 //if(!tracedebug) return 0;
2121 for(i=0;i<2097152;i++) {
2122 unsigned int temp=sum;
2125 sum^=((u_int *)rdram)[i];
2134 sum^=((u_int *)reg)[i];
2142 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2144 #ifndef DISABLE_COP1
2147 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2157 void memdebug(int i)
2159 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2160 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2163 //if(Count>=-2084597794) {
2164 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2166 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2167 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2168 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2171 printf("TRACE: %x\n",(&i)[-1]);
2175 printf("TRACE: %x \n",(&j)[10]);
2176 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2180 //printf("TRACE: %x\n",(&i)[-1]);
2183 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2185 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2188 void alu_assemble(int i,struct regstat *i_regs)
2190 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2192 signed char s1,s2,t;
2193 t=get_reg(i_regs->regmap,rt1[i]);
2195 s1=get_reg(i_regs->regmap,rs1[i]);
2196 s2=get_reg(i_regs->regmap,rs2[i]);
2197 if(rs1[i]&&rs2[i]) {
2200 if(opcode2[i]&2) emit_sub(s1,s2,t);
2201 else emit_add(s1,s2,t);
2204 if(s1>=0) emit_mov(s1,t);
2205 else emit_loadreg(rs1[i],t);
2209 if(opcode2[i]&2) emit_neg(s2,t);
2210 else emit_mov(s2,t);
2213 emit_loadreg(rs2[i],t);
2214 if(opcode2[i]&2) emit_neg(t,t);
2217 else emit_zeroreg(t);
2221 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2223 signed char s1l,s2l,s1h,s2h,tl,th;
2224 tl=get_reg(i_regs->regmap,rt1[i]);
2225 th=get_reg(i_regs->regmap,rt1[i]|64);
2227 s1l=get_reg(i_regs->regmap,rs1[i]);
2228 s2l=get_reg(i_regs->regmap,rs2[i]);
2229 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2230 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2231 if(rs1[i]&&rs2[i]) {
2234 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2235 else emit_adds(s1l,s2l,tl);
2237 #ifdef INVERTED_CARRY
2238 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2240 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2242 else emit_add(s1h,s2h,th);
2246 if(s1l>=0) emit_mov(s1l,tl);
2247 else emit_loadreg(rs1[i],tl);
2249 if(s1h>=0) emit_mov(s1h,th);
2250 else emit_loadreg(rs1[i]|64,th);
2255 if(opcode2[i]&2) emit_negs(s2l,tl);
2256 else emit_mov(s2l,tl);
2259 emit_loadreg(rs2[i],tl);
2260 if(opcode2[i]&2) emit_negs(tl,tl);
2263 #ifdef INVERTED_CARRY
2264 if(s2h>=0) emit_mov(s2h,th);
2265 else emit_loadreg(rs2[i]|64,th);
2267 emit_adcimm(-1,th); // x86 has inverted carry flag
2272 if(s2h>=0) emit_rscimm(s2h,0,th);
2274 emit_loadreg(rs2[i]|64,th);
2275 emit_rscimm(th,0,th);
2278 if(s2h>=0) emit_mov(s2h,th);
2279 else emit_loadreg(rs2[i]|64,th);
2286 if(th>=0) emit_zeroreg(th);
2291 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2293 signed char s1l,s1h,s2l,s2h,t;
2294 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2296 t=get_reg(i_regs->regmap,rt1[i]);
2299 s1l=get_reg(i_regs->regmap,rs1[i]);
2300 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2301 s2l=get_reg(i_regs->regmap,rs2[i]);
2302 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2303 if(rs2[i]==0) // rx<r0
2306 if(opcode2[i]==0x2a) // SLT
2307 emit_shrimm(s1h,31,t);
2308 else // SLTU (unsigned can not be less than zero)
2311 else if(rs1[i]==0) // r0<rx
2314 if(opcode2[i]==0x2a) // SLT
2315 emit_set_gz64_32(s2h,s2l,t);
2316 else // SLTU (set if not zero)
2317 emit_set_nz64_32(s2h,s2l,t);
2320 assert(s1l>=0);assert(s1h>=0);
2321 assert(s2l>=0);assert(s2h>=0);
2322 if(opcode2[i]==0x2a) // SLT
2323 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2325 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2329 t=get_reg(i_regs->regmap,rt1[i]);
2332 s1l=get_reg(i_regs->regmap,rs1[i]);
2333 s2l=get_reg(i_regs->regmap,rs2[i]);
2334 if(rs2[i]==0) // rx<r0
2337 if(opcode2[i]==0x2a) // SLT
2338 emit_shrimm(s1l,31,t);
2339 else // SLTU (unsigned can not be less than zero)
2342 else if(rs1[i]==0) // r0<rx
2345 if(opcode2[i]==0x2a) // SLT
2346 emit_set_gz32(s2l,t);
2347 else // SLTU (set if not zero)
2348 emit_set_nz32(s2l,t);
2351 assert(s1l>=0);assert(s2l>=0);
2352 if(opcode2[i]==0x2a) // SLT
2353 emit_set_if_less32(s1l,s2l,t);
2355 emit_set_if_carry32(s1l,s2l,t);
2361 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2363 signed char s1l,s1h,s2l,s2h,th,tl;
2364 tl=get_reg(i_regs->regmap,rt1[i]);
2365 th=get_reg(i_regs->regmap,rt1[i]|64);
2366 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2370 s1l=get_reg(i_regs->regmap,rs1[i]);
2371 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2372 s2l=get_reg(i_regs->regmap,rs2[i]);
2373 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2374 if(rs1[i]&&rs2[i]) {
2375 assert(s1l>=0);assert(s1h>=0);
2376 assert(s2l>=0);assert(s2h>=0);
2377 if(opcode2[i]==0x24) { // AND
2378 emit_and(s1l,s2l,tl);
2379 emit_and(s1h,s2h,th);
2381 if(opcode2[i]==0x25) { // OR
2382 emit_or(s1l,s2l,tl);
2383 emit_or(s1h,s2h,th);
2385 if(opcode2[i]==0x26) { // XOR
2386 emit_xor(s1l,s2l,tl);
2387 emit_xor(s1h,s2h,th);
2389 if(opcode2[i]==0x27) { // NOR
2390 emit_or(s1l,s2l,tl);
2391 emit_or(s1h,s2h,th);
2398 if(opcode2[i]==0x24) { // AND
2402 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2404 if(s1l>=0) emit_mov(s1l,tl);
2405 else emit_loadreg(rs1[i],tl);
2406 if(s1h>=0) emit_mov(s1h,th);
2407 else emit_loadreg(rs1[i]|64,th);
2411 if(s2l>=0) emit_mov(s2l,tl);
2412 else emit_loadreg(rs2[i],tl);
2413 if(s2h>=0) emit_mov(s2h,th);
2414 else emit_loadreg(rs2[i]|64,th);
2421 if(opcode2[i]==0x27) { // NOR
2423 if(s1l>=0) emit_not(s1l,tl);
2425 emit_loadreg(rs1[i],tl);
2428 if(s1h>=0) emit_not(s1h,th);
2430 emit_loadreg(rs1[i]|64,th);
2436 if(s2l>=0) emit_not(s2l,tl);
2438 emit_loadreg(rs2[i],tl);
2441 if(s2h>=0) emit_not(s2h,th);
2443 emit_loadreg(rs2[i]|64,th);
2459 s1l=get_reg(i_regs->regmap,rs1[i]);
2460 s2l=get_reg(i_regs->regmap,rs2[i]);
2461 if(rs1[i]&&rs2[i]) {
2464 if(opcode2[i]==0x24) { // AND
2465 emit_and(s1l,s2l,tl);
2467 if(opcode2[i]==0x25) { // OR
2468 emit_or(s1l,s2l,tl);
2470 if(opcode2[i]==0x26) { // XOR
2471 emit_xor(s1l,s2l,tl);
2473 if(opcode2[i]==0x27) { // NOR
2474 emit_or(s1l,s2l,tl);
2480 if(opcode2[i]==0x24) { // AND
2483 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2485 if(s1l>=0) emit_mov(s1l,tl);
2486 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2490 if(s2l>=0) emit_mov(s2l,tl);
2491 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2493 else emit_zeroreg(tl);
2495 if(opcode2[i]==0x27) { // NOR
2497 if(s1l>=0) emit_not(s1l,tl);
2499 emit_loadreg(rs1[i],tl);
2505 if(s2l>=0) emit_not(s2l,tl);
2507 emit_loadreg(rs2[i],tl);
2511 else emit_movimm(-1,tl);
2520 void imm16_assemble(int i,struct regstat *i_regs)
2522 if (opcode[i]==0x0f) { // LUI
2525 t=get_reg(i_regs->regmap,rt1[i]);
2528 if(!((i_regs->isconst>>t)&1))
2529 emit_movimm(imm[i]<<16,t);
2533 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2536 t=get_reg(i_regs->regmap,rt1[i]);
2537 s=get_reg(i_regs->regmap,rs1[i]);
2542 if(!((i_regs->isconst>>t)&1)) {
2544 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2545 emit_addimm(t,imm[i],t);
2547 if(!((i_regs->wasconst>>s)&1))
2548 emit_addimm(s,imm[i],t);
2550 emit_movimm(constmap[i][s]+imm[i],t);
2556 if(!((i_regs->isconst>>t)&1))
2557 emit_movimm(imm[i],t);
2562 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2564 signed char sh,sl,th,tl;
2565 th=get_reg(i_regs->regmap,rt1[i]|64);
2566 tl=get_reg(i_regs->regmap,rt1[i]);
2567 sh=get_reg(i_regs->regmap,rs1[i]|64);
2568 sl=get_reg(i_regs->regmap,rs1[i]);
2574 emit_addimm64_32(sh,sl,imm[i],th,tl);
2577 emit_addimm(sl,imm[i],tl);
2580 emit_movimm(imm[i],tl);
2581 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2586 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2588 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2589 signed char sh,sl,t;
2590 t=get_reg(i_regs->regmap,rt1[i]);
2591 sh=get_reg(i_regs->regmap,rs1[i]|64);
2592 sl=get_reg(i_regs->regmap,rs1[i]);
2596 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2597 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2598 if(opcode[i]==0x0a) { // SLTI
2600 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2601 emit_slti32(t,imm[i],t);
2603 emit_slti32(sl,imm[i],t);
2608 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2609 emit_sltiu32(t,imm[i],t);
2611 emit_sltiu32(sl,imm[i],t);
2616 if(opcode[i]==0x0a) // SLTI
2617 emit_slti64_32(sh,sl,imm[i],t);
2619 emit_sltiu64_32(sh,sl,imm[i],t);
2622 // SLTI(U) with r0 is just stupid,
2623 // nonetheless examples can be found
2624 if(opcode[i]==0x0a) // SLTI
2625 if(0<imm[i]) emit_movimm(1,t);
2626 else emit_zeroreg(t);
2629 if(imm[i]) emit_movimm(1,t);
2630 else emit_zeroreg(t);
2636 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2638 signed char sh,sl,th,tl;
2639 th=get_reg(i_regs->regmap,rt1[i]|64);
2640 tl=get_reg(i_regs->regmap,rt1[i]);
2641 sh=get_reg(i_regs->regmap,rs1[i]|64);
2642 sl=get_reg(i_regs->regmap,rs1[i]);
2643 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2644 if(opcode[i]==0x0c) //ANDI
2648 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2649 emit_andimm(tl,imm[i],tl);
2651 if(!((i_regs->wasconst>>sl)&1))
2652 emit_andimm(sl,imm[i],tl);
2654 emit_movimm(constmap[i][sl]&imm[i],tl);
2659 if(th>=0) emit_zeroreg(th);
2665 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2669 emit_loadreg(rs1[i]|64,th);
2674 if(opcode[i]==0x0d) //ORI
2676 emit_orimm(tl,imm[i],tl);
2678 if(!((i_regs->wasconst>>sl)&1))
2679 emit_orimm(sl,imm[i],tl);
2681 emit_movimm(constmap[i][sl]|imm[i],tl);
2683 if(opcode[i]==0x0e) //XORI
2685 emit_xorimm(tl,imm[i],tl);
2687 if(!((i_regs->wasconst>>sl)&1))
2688 emit_xorimm(sl,imm[i],tl);
2690 emit_movimm(constmap[i][sl]^imm[i],tl);
2694 emit_movimm(imm[i],tl);
2695 if(th>=0) emit_zeroreg(th);
2703 void shiftimm_assemble(int i,struct regstat *i_regs)
2705 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2709 t=get_reg(i_regs->regmap,rt1[i]);
2710 s=get_reg(i_regs->regmap,rs1[i]);
2712 if(t>=0&&!((i_regs->isconst>>t)&1)){
2719 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2721 if(opcode2[i]==0) // SLL
2723 emit_shlimm(s<0?t:s,imm[i],t);
2725 if(opcode2[i]==2) // SRL
2727 emit_shrimm(s<0?t:s,imm[i],t);
2729 if(opcode2[i]==3) // SRA
2731 emit_sarimm(s<0?t:s,imm[i],t);
2735 if(s>=0 && s!=t) emit_mov(s,t);
2739 //emit_storereg(rt1[i],t); //DEBUG
2742 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2745 signed char sh,sl,th,tl;
2746 th=get_reg(i_regs->regmap,rt1[i]|64);
2747 tl=get_reg(i_regs->regmap,rt1[i]);
2748 sh=get_reg(i_regs->regmap,rs1[i]|64);
2749 sl=get_reg(i_regs->regmap,rs1[i]);
2754 if(th>=0) emit_zeroreg(th);
2761 if(opcode2[i]==0x38) // DSLL
2763 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2764 emit_shlimm(sl,imm[i],tl);
2766 if(opcode2[i]==0x3a) // DSRL
2768 emit_shrdimm(sl,sh,imm[i],tl);
2769 if(th>=0) emit_shrimm(sh,imm[i],th);
2771 if(opcode2[i]==0x3b) // DSRA
2773 emit_shrdimm(sl,sh,imm[i],tl);
2774 if(th>=0) emit_sarimm(sh,imm[i],th);
2778 if(sl!=tl) emit_mov(sl,tl);
2779 if(th>=0&&sh!=th) emit_mov(sh,th);
2785 if(opcode2[i]==0x3c) // DSLL32
2788 signed char sl,tl,th;
2789 tl=get_reg(i_regs->regmap,rt1[i]);
2790 th=get_reg(i_regs->regmap,rt1[i]|64);
2791 sl=get_reg(i_regs->regmap,rs1[i]);
2800 emit_shlimm(th,imm[i]&31,th);
2805 if(opcode2[i]==0x3e) // DSRL32
2808 signed char sh,tl,th;
2809 tl=get_reg(i_regs->regmap,rt1[i]);
2810 th=get_reg(i_regs->regmap,rt1[i]|64);
2811 sh=get_reg(i_regs->regmap,rs1[i]|64);
2815 if(th>=0) emit_zeroreg(th);
2818 emit_shrimm(tl,imm[i]&31,tl);
2823 if(opcode2[i]==0x3f) // DSRA32
2827 tl=get_reg(i_regs->regmap,rt1[i]);
2828 sh=get_reg(i_regs->regmap,rs1[i]|64);
2834 emit_sarimm(tl,imm[i]&31,tl);
2841 #ifndef shift_assemble
2842 void shift_assemble(int i,struct regstat *i_regs)
2844 printf("Need shift_assemble for this architecture.\n");
2849 void load_assemble(int i,struct regstat *i_regs)
2851 int s,th,tl,addr,map=-1;
2854 int memtarget=0,c=0;
2855 int fastload_reg_override=0;
2857 th=get_reg(i_regs->regmap,rt1[i]|64);
2858 tl=get_reg(i_regs->regmap,rt1[i]);
2859 s=get_reg(i_regs->regmap,rs1[i]);
2861 for(hr=0;hr<HOST_REGS;hr++) {
2862 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2864 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2866 c=(i_regs->wasconst>>s)&1;
2868 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2869 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2872 //printf("load_assemble: c=%d\n",c);
2873 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2874 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2876 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2878 // could be FIFO, must perform the read
2880 assem_debug("(forced read)\n");
2881 tl=get_reg(i_regs->regmap,-1);
2885 if(offset||s<0||c) addr=tl;
2887 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2889 //printf("load_assemble: c=%d\n",c);
2890 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2891 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2893 if(th>=0) reglist&=~(1<<th);
2897 map=get_reg(i_regs->regmap,ROREG);
2898 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2900 //#define R29_HACK 1
2902 // Strmnnrmn's speed hack
2903 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2906 jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2911 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2912 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2913 map=get_reg(i_regs->regmap,TLREG);
2916 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2917 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2919 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2920 if (opcode[i]==0x20) { // LB
2923 #ifdef HOST_IMM_ADDR32
2925 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2929 //emit_xorimm(addr,3,tl);
2930 //gen_tlb_addr_r(tl,map);
2931 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2933 #ifdef BIG_ENDIAN_MIPS
2934 if(!c) emit_xorimm(addr,3,tl);
2935 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2939 if(fastload_reg_override) a=fastload_reg_override;
2941 emit_movsbl_indexed_tlb(x,a,map,tl);
2945 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2948 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2950 if (opcode[i]==0x21) { // LH
2953 #ifdef HOST_IMM_ADDR32
2955 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2960 #ifdef BIG_ENDIAN_MIPS
2961 if(!c) emit_xorimm(addr,2,tl);
2962 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2966 if(fastload_reg_override) a=fastload_reg_override;
2968 //emit_movswl_indexed_tlb(x,tl,map,tl);
2971 gen_tlb_addr_r(a,map);
2972 emit_movswl_indexed(x,a,tl);
2975 emit_movswl_indexed(x,a,tl);
2977 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2983 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2986 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2988 if (opcode[i]==0x23) { // LW
2992 if(fastload_reg_override) a=fastload_reg_override;
2993 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2994 #ifdef HOST_IMM_ADDR32
2996 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2999 emit_readword_indexed_tlb(0,a,map,tl);
3002 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3005 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3007 if (opcode[i]==0x24) { // LBU
3010 #ifdef HOST_IMM_ADDR32
3012 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3016 //emit_xorimm(addr,3,tl);
3017 //gen_tlb_addr_r(tl,map);
3018 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3020 #ifdef BIG_ENDIAN_MIPS
3021 if(!c) emit_xorimm(addr,3,tl);
3022 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3026 if(fastload_reg_override) a=fastload_reg_override;
3028 emit_movzbl_indexed_tlb(x,a,map,tl);
3032 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3035 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3037 if (opcode[i]==0x25) { // LHU
3040 #ifdef HOST_IMM_ADDR32
3042 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3047 #ifdef BIG_ENDIAN_MIPS
3048 if(!c) emit_xorimm(addr,2,tl);
3049 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3053 if(fastload_reg_override) a=fastload_reg_override;
3055 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3058 gen_tlb_addr_r(a,map);
3059 emit_movzwl_indexed(x,a,tl);
3062 emit_movzwl_indexed(x,a,tl);
3064 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3070 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3073 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3075 if (opcode[i]==0x27) { // LWU
3080 if(fastload_reg_override) a=fastload_reg_override;
3081 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3082 #ifdef HOST_IMM_ADDR32
3084 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3087 emit_readword_indexed_tlb(0,a,map,tl);
3090 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3093 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3097 if (opcode[i]==0x37) { // LD
3101 if(fastload_reg_override) a=fastload_reg_override;
3102 //gen_tlb_addr_r(tl,map);
3103 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3104 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3105 #ifdef HOST_IMM_ADDR32
3107 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3110 emit_readdword_indexed_tlb(0,a,map,th,tl);
3113 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3116 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3119 //emit_storereg(rt1[i],tl); // DEBUG
3120 //if(opcode[i]==0x23)
3121 //if(opcode[i]==0x24)
3122 //if(opcode[i]==0x23||opcode[i]==0x24)
3123 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3127 emit_readword((int)&last_count,ECX);
3129 if(get_reg(i_regs->regmap,CCREG)<0)
3130 emit_loadreg(CCREG,HOST_CCREG);
3131 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3132 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3133 emit_writeword(HOST_CCREG,(int)&Count);
3136 if(get_reg(i_regs->regmap,CCREG)<0)
3137 emit_loadreg(CCREG,0);
3139 emit_mov(HOST_CCREG,0);
3141 emit_addimm(0,2*ccadj[i],0);
3142 emit_writeword(0,(int)&Count);
3144 emit_call((int)memdebug);
3146 restore_regs(0x100f);
3150 #ifndef loadlr_assemble
3151 void loadlr_assemble(int i,struct regstat *i_regs)
3153 printf("Need loadlr_assemble for this architecture.\n");
3158 void store_assemble(int i,struct regstat *i_regs)
3163 int jaddr=0,jaddr2,type;
3164 int memtarget=0,c=0;
3165 int agr=AGEN1+(i&1);
3166 int faststore_reg_override=0;
3168 th=get_reg(i_regs->regmap,rs2[i]|64);
3169 tl=get_reg(i_regs->regmap,rs2[i]);
3170 s=get_reg(i_regs->regmap,rs1[i]);
3171 temp=get_reg(i_regs->regmap,agr);
3172 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3175 c=(i_regs->wasconst>>s)&1;
3177 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3178 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3183 for(hr=0;hr<HOST_REGS;hr++) {
3184 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3186 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3187 if(offset||s<0||c) addr=temp;
3193 // Strmnnrmn's speed hack
3194 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3196 emit_cmpimm(addr,RAM_SIZE);
3197 #ifdef DESTRUCTIVE_SHIFT
3198 if(s==addr) emit_mov(s,temp);
3202 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3206 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3207 // Hint to branch predictor that the branch is unlikely to be taken
3209 emit_jno_unlikely(0);
3215 jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3220 if (opcode[i]==0x28) x=3; // SB
3221 if (opcode[i]==0x29) x=2; // SH
3222 map=get_reg(i_regs->regmap,TLREG);
3225 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3226 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3229 if (opcode[i]==0x28) { // SB
3232 #ifdef BIG_ENDIAN_MIPS
3233 if(!c) emit_xorimm(addr,3,temp);
3234 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3238 if(faststore_reg_override) a=faststore_reg_override;
3239 //gen_tlb_addr_w(temp,map);
3240 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3241 emit_writebyte_indexed_tlb(tl,x,a,map,a);
3245 if (opcode[i]==0x29) { // SH
3248 #ifdef BIG_ENDIAN_MIPS
3249 if(!c) emit_xorimm(addr,2,temp);
3250 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3254 if(faststore_reg_override) a=faststore_reg_override;
3256 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3259 gen_tlb_addr_w(a,map);
3260 emit_writehword_indexed(tl,x,a);
3262 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3266 if (opcode[i]==0x2B) { // SW
3269 if(faststore_reg_override) a=faststore_reg_override;
3270 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3271 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3275 if (opcode[i]==0x3F) { // SD
3278 if(faststore_reg_override) a=faststore_reg_override;
3281 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3282 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3283 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3286 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3287 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3288 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3295 // PCSX store handlers don't check invcode again
3297 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3303 #ifdef DESTRUCTIVE_SHIFT
3304 // The x86 shift operation is 'destructive'; it overwrites the
3305 // source register, so we need to make a copy first and use that.
3308 #if defined(HOST_IMM8)
3309 int ir=get_reg(i_regs->regmap,INVCP);
3311 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3313 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3315 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3316 emit_callne(invalidate_addr_reg[addr]);
3320 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3325 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3326 } else if(c&&!memtarget) {
3327 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3329 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3330 //if(opcode[i]==0x2B || opcode[i]==0x28)
3331 //if(opcode[i]==0x2B || opcode[i]==0x29)
3332 //if(opcode[i]==0x2B)
3333 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3341 emit_readword((int)&last_count,ECX);
3343 if(get_reg(i_regs->regmap,CCREG)<0)
3344 emit_loadreg(CCREG,HOST_CCREG);
3345 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3346 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3347 emit_writeword(HOST_CCREG,(int)&Count);
3350 if(get_reg(i_regs->regmap,CCREG)<0)
3351 emit_loadreg(CCREG,0);
3353 emit_mov(HOST_CCREG,0);
3355 emit_addimm(0,2*ccadj[i],0);
3356 emit_writeword(0,(int)&Count);
3358 emit_call((int)memdebug);
3363 restore_regs(0x100f);
3368 void storelr_assemble(int i,struct regstat *i_regs)
3375 int case1,case2,case3;
3376 int done0,done1,done2;
3377 int memtarget=0,c=0;
3378 int agr=AGEN1+(i&1);
3380 th=get_reg(i_regs->regmap,rs2[i]|64);
3381 tl=get_reg(i_regs->regmap,rs2[i]);
3382 s=get_reg(i_regs->regmap,rs1[i]);
3383 temp=get_reg(i_regs->regmap,agr);
3384 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3387 c=(i_regs->isconst>>s)&1;
3389 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3390 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3394 for(hr=0;hr<HOST_REGS;hr++) {
3395 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3400 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3401 if(!offset&&s!=temp) emit_mov(s,temp);
3407 if(!memtarget||!rs1[i]) {
3413 int map=get_reg(i_regs->regmap,ROREG);
3414 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3415 gen_tlb_addr_w(temp,map);
3417 if((u_int)rdram!=0x80000000)
3418 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3421 int map=get_reg(i_regs->regmap,TLREG);
3424 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3425 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3426 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3427 if(!jaddr&&!memtarget) {
3431 gen_tlb_addr_w(temp,map);
3434 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3435 temp2=get_reg(i_regs->regmap,FTEMP);
3436 if(!rs2[i]) temp2=th=tl;
3439 #ifndef BIG_ENDIAN_MIPS
3440 emit_xorimm(temp,3,temp);
3442 emit_testimm(temp,2);
3445 emit_testimm(temp,1);
3449 if (opcode[i]==0x2A) { // SWL
3450 emit_writeword_indexed(tl,0,temp);
3452 if (opcode[i]==0x2E) { // SWR
3453 emit_writebyte_indexed(tl,3,temp);
3455 if (opcode[i]==0x2C) { // SDL
3456 emit_writeword_indexed(th,0,temp);
3457 if(rs2[i]) emit_mov(tl,temp2);
3459 if (opcode[i]==0x2D) { // SDR
3460 emit_writebyte_indexed(tl,3,temp);
3461 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3466 set_jump_target(case1,(int)out);
3467 if (opcode[i]==0x2A) { // SWL
3468 // Write 3 msb into three least significant bytes
3469 if(rs2[i]) emit_rorimm(tl,8,tl);
3470 emit_writehword_indexed(tl,-1,temp);
3471 if(rs2[i]) emit_rorimm(tl,16,tl);
3472 emit_writebyte_indexed(tl,1,temp);
3473 if(rs2[i]) emit_rorimm(tl,8,tl);
3475 if (opcode[i]==0x2E) { // SWR
3476 // Write two lsb into two most significant bytes
3477 emit_writehword_indexed(tl,1,temp);
3479 if (opcode[i]==0x2C) { // SDL
3480 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3481 // Write 3 msb into three least significant bytes
3482 if(rs2[i]) emit_rorimm(th,8,th);
3483 emit_writehword_indexed(th,-1,temp);
3484 if(rs2[i]) emit_rorimm(th,16,th);
3485 emit_writebyte_indexed(th,1,temp);
3486 if(rs2[i]) emit_rorimm(th,8,th);
3488 if (opcode[i]==0x2D) { // SDR
3489 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3490 // Write two lsb into two most significant bytes
3491 emit_writehword_indexed(tl,1,temp);
3496 set_jump_target(case2,(int)out);
3497 emit_testimm(temp,1);
3500 if (opcode[i]==0x2A) { // SWL
3501 // Write two msb into two least significant bytes
3502 if(rs2[i]) emit_rorimm(tl,16,tl);
3503 emit_writehword_indexed(tl,-2,temp);
3504 if(rs2[i]) emit_rorimm(tl,16,tl);
3506 if (opcode[i]==0x2E) { // SWR
3507 // Write 3 lsb into three most significant bytes
3508 emit_writebyte_indexed(tl,-1,temp);
3509 if(rs2[i]) emit_rorimm(tl,8,tl);
3510 emit_writehword_indexed(tl,0,temp);
3511 if(rs2[i]) emit_rorimm(tl,24,tl);
3513 if (opcode[i]==0x2C) { // SDL
3514 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3515 // Write two msb into two least significant bytes
3516 if(rs2[i]) emit_rorimm(th,16,th);
3517 emit_writehword_indexed(th,-2,temp);
3518 if(rs2[i]) emit_rorimm(th,16,th);
3520 if (opcode[i]==0x2D) { // SDR
3521 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3522 // Write 3 lsb into three most significant bytes
3523 emit_writebyte_indexed(tl,-1,temp);
3524 if(rs2[i]) emit_rorimm(tl,8,tl);
3525 emit_writehword_indexed(tl,0,temp);
3526 if(rs2[i]) emit_rorimm(tl,24,tl);
3531 set_jump_target(case3,(int)out);
3532 if (opcode[i]==0x2A) { // SWL
3533 // Write msb into least significant byte
3534 if(rs2[i]) emit_rorimm(tl,24,tl);
3535 emit_writebyte_indexed(tl,-3,temp);
3536 if(rs2[i]) emit_rorimm(tl,8,tl);
3538 if (opcode[i]==0x2E) { // SWR
3539 // Write entire word
3540 emit_writeword_indexed(tl,-3,temp);
3542 if (opcode[i]==0x2C) { // SDL
3543 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3544 // Write msb into least significant byte
3545 if(rs2[i]) emit_rorimm(th,24,th);
3546 emit_writebyte_indexed(th,-3,temp);
3547 if(rs2[i]) emit_rorimm(th,8,th);
3549 if (opcode[i]==0x2D) { // SDR
3550 if(rs2[i]) emit_mov(th,temp2);
3551 // Write entire word
3552 emit_writeword_indexed(tl,-3,temp);
3554 set_jump_target(done0,(int)out);
3555 set_jump_target(done1,(int)out);
3556 set_jump_target(done2,(int)out);
3557 if (opcode[i]==0x2C) { // SDL
3558 emit_testimm(temp,4);
3561 emit_andimm(temp,~3,temp);
3562 emit_writeword_indexed(temp2,4,temp);
3563 set_jump_target(done0,(int)out);
3565 if (opcode[i]==0x2D) { // SDR
3566 emit_testimm(temp,4);
3569 emit_andimm(temp,~3,temp);
3570 emit_writeword_indexed(temp2,-4,temp);
3571 set_jump_target(done0,(int)out);
3574 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3577 int map=get_reg(i_regs->regmap,ROREG);
3578 if(map<0) map=HOST_TEMPREG;
3579 gen_orig_addr_w(temp,map);
3581 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3583 #if defined(HOST_IMM8)
3584 int ir=get_reg(i_regs->regmap,INVCP);
3586 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3588 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3590 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3591 emit_callne(invalidate_addr_reg[temp]);
3595 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3600 //save_regs(0x100f);
3601 emit_readword((int)&last_count,ECX);
3602 if(get_reg(i_regs->regmap,CCREG)<0)
3603 emit_loadreg(CCREG,HOST_CCREG);
3604 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3605 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3606 emit_writeword(HOST_CCREG,(int)&Count);
3607 emit_call((int)memdebug);
3609 //restore_regs(0x100f);
3613 void c1ls_assemble(int i,struct regstat *i_regs)
3615 #ifndef DISABLE_COP1
3621 int jaddr,jaddr2=0,jaddr3,type;
3622 int agr=AGEN1+(i&1);
3624 th=get_reg(i_regs->regmap,FTEMP|64);
3625 tl=get_reg(i_regs->regmap,FTEMP);
3626 s=get_reg(i_regs->regmap,rs1[i]);
3627 temp=get_reg(i_regs->regmap,agr);
3628 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3633 for(hr=0;hr<HOST_REGS;hr++) {
3634 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3636 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3637 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3639 // Loads use a temporary register which we need to save
3642 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3646 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3647 //else c=(i_regs->wasconst>>s)&1;
3648 if(s>=0) c=(i_regs->wasconst>>s)&1;
3649 // Check cop1 unusable
3651 signed char rs=get_reg(i_regs->regmap,CSREG);
3653 emit_testimm(rs,0x20000000);
3656 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3659 if (opcode[i]==0x39) { // SWC1 (get float address)
3660 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3662 if (opcode[i]==0x3D) { // SDC1 (get double address)
3663 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3665 // Generate address + offset
3668 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3672 map=get_reg(i_regs->regmap,TLREG);
3675 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3676 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3678 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3679 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3682 if (opcode[i]==0x39) { // SWC1 (read float)
3683 emit_readword_indexed(0,tl,tl);
3685 if (opcode[i]==0x3D) { // SDC1 (read double)
3686 emit_readword_indexed(4,tl,th);
3687 emit_readword_indexed(0,tl,tl);
3689 if (opcode[i]==0x31) { // LWC1 (get target address)
3690 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3692 if (opcode[i]==0x35) { // LDC1 (get target address)
3693 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3700 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3702 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3704 #ifdef DESTRUCTIVE_SHIFT
3705 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3706 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3710 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3711 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3713 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3714 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3717 if (opcode[i]==0x31) { // LWC1
3718 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3719 //gen_tlb_addr_r(ar,map);
3720 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3721 #ifdef HOST_IMM_ADDR32
3722 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3725 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3728 if (opcode[i]==0x35) { // LDC1
3730 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3731 //gen_tlb_addr_r(ar,map);
3732 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3733 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3734 #ifdef HOST_IMM_ADDR32
3735 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3738 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3741 if (opcode[i]==0x39) { // SWC1
3742 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3743 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3746 if (opcode[i]==0x3D) { // SDC1
3748 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3749 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3750 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3754 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3755 #ifndef DESTRUCTIVE_SHIFT
3756 temp=offset||c||s<0?ar:s;
3758 #if defined(HOST_IMM8)
3759 int ir=get_reg(i_regs->regmap,INVCP);
3761 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3763 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3765 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3766 emit_callne(invalidate_addr_reg[temp]);
3770 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3774 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3775 if (opcode[i]==0x31) { // LWC1 (write float)
3776 emit_writeword_indexed(tl,0,temp);
3778 if (opcode[i]==0x35) { // LDC1 (write double)
3779 emit_writeword_indexed(th,4,temp);
3780 emit_writeword_indexed(tl,0,temp);
3782 //if(opcode[i]==0x39)
3783 /*if(opcode[i]==0x39||opcode[i]==0x31)
3786 emit_readword((int)&last_count,ECX);
3787 if(get_reg(i_regs->regmap,CCREG)<0)
3788 emit_loadreg(CCREG,HOST_CCREG);
3789 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3790 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3791 emit_writeword(HOST_CCREG,(int)&Count);
3792 emit_call((int)memdebug);
3796 cop1_unusable(i, i_regs);
3800 void c2ls_assemble(int i,struct regstat *i_regs)
3805 int memtarget=0,c=0;
3806 int jaddr2=0,jaddr3,type;
3807 int agr=AGEN1+(i&1);
3808 int fastio_reg_override=0;
3810 u_int copr=(source[i]>>16)&0x1f;
3811 s=get_reg(i_regs->regmap,rs1[i]);
3812 tl=get_reg(i_regs->regmap,FTEMP);
3818 for(hr=0;hr<HOST_REGS;hr++) {
3819 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3821 if(i_regs->regmap[HOST_CCREG]==CCREG)
3822 reglist&=~(1<<HOST_CCREG);
3825 if (opcode[i]==0x3a) { // SWC2
3826 ar=get_reg(i_regs->regmap,agr);
3827 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3832 if(s>=0) c=(i_regs->wasconst>>s)&1;
3833 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3834 if (!offset&&!c&&s>=0) ar=s;
3837 if (opcode[i]==0x3a) { // SWC2
3838 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3846 emit_jmp(0); // inline_readstub/inline_writestub?
3850 jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3852 if (opcode[i]==0x32) { // LWC2
3853 #ifdef HOST_IMM_ADDR32
3854 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3858 if(fastio_reg_override) a=fastio_reg_override;
3859 emit_readword_indexed(0,a,tl);
3861 if (opcode[i]==0x3a) { // SWC2
3862 #ifdef DESTRUCTIVE_SHIFT
3863 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3866 if(fastio_reg_override) a=fastio_reg_override;
3867 emit_writeword_indexed(tl,0,a);
3871 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3872 if (opcode[i]==0x3a) { // SWC2
3873 #if defined(HOST_IMM8)
3874 int ir=get_reg(i_regs->regmap,INVCP);
3876 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3878 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3880 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3881 emit_callne(invalidate_addr_reg[ar]);
3885 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3888 if (opcode[i]==0x32) { // LWC2
3889 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3893 #ifndef multdiv_assemble
3894 void multdiv_assemble(int i,struct regstat *i_regs)
3896 printf("Need multdiv_assemble for this architecture.\n");
3901 void mov_assemble(int i,struct regstat *i_regs)
3903 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3904 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3906 signed char sh,sl,th,tl;
3907 th=get_reg(i_regs->regmap,rt1[i]|64);
3908 tl=get_reg(i_regs->regmap,rt1[i]);
3911 sh=get_reg(i_regs->regmap,rs1[i]|64);
3912 sl=get_reg(i_regs->regmap,rs1[i]);
3913 if(sl>=0) emit_mov(sl,tl);
3914 else emit_loadreg(rs1[i],tl);
3916 if(sh>=0) emit_mov(sh,th);
3917 else emit_loadreg(rs1[i]|64,th);
3923 #ifndef fconv_assemble
3924 void fconv_assemble(int i,struct regstat *i_regs)
3926 printf("Need fconv_assemble for this architecture.\n");
3932 void float_assemble(int i,struct regstat *i_regs)
3934 printf("Need float_assemble for this architecture.\n");
3939 void syscall_assemble(int i,struct regstat *i_regs)
3941 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3942 assert(ccreg==HOST_CCREG);
3943 assert(!is_delayslot);
3944 emit_movimm(start+i*4,EAX); // Get PC
3945 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3946 emit_jmp((int)jump_syscall_hle); // XXX
3949 void hlecall_assemble(int i,struct regstat *i_regs)
3951 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3952 assert(ccreg==HOST_CCREG);
3953 assert(!is_delayslot);
3954 emit_movimm(start+i*4+4,0); // Get PC
3955 emit_movimm((int)psxHLEt[source[i]&7],1);
3956 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
3957 emit_jmp((int)jump_hlecall);
3960 void intcall_assemble(int i,struct regstat *i_regs)
3962 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3963 assert(ccreg==HOST_CCREG);
3964 assert(!is_delayslot);
3965 emit_movimm(start+i*4,0); // Get PC
3966 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3967 emit_jmp((int)jump_intcall);
3970 void ds_assemble(int i,struct regstat *i_regs)
3972 speculate_register_values(i);
3976 alu_assemble(i,i_regs);break;
3978 imm16_assemble(i,i_regs);break;
3980 shift_assemble(i,i_regs);break;
3982 shiftimm_assemble(i,i_regs);break;
3984 load_assemble(i,i_regs);break;
3986 loadlr_assemble(i,i_regs);break;
3988 store_assemble(i,i_regs);break;
3990 storelr_assemble(i,i_regs);break;
3992 cop0_assemble(i,i_regs);break;
3994 cop1_assemble(i,i_regs);break;
3996 c1ls_assemble(i,i_regs);break;
3998 cop2_assemble(i,i_regs);break;
4000 c2ls_assemble(i,i_regs);break;
4002 c2op_assemble(i,i_regs);break;
4004 fconv_assemble(i,i_regs);break;
4006 float_assemble(i,i_regs);break;
4008 fcomp_assemble(i,i_regs);break;
4010 multdiv_assemble(i,i_regs);break;
4012 mov_assemble(i,i_regs);break;
4022 printf("Jump in the delay slot. This is probably a bug.\n");
4027 // Is the branch target a valid internal jump?
4028 int internal_branch(uint64_t i_is32,int addr)
4030 if(addr&1) return 0; // Indirect (register) jump
4031 if(addr>=start && addr<start+slen*4-4)
4033 int t=(addr-start)>>2;
4034 // Delay slots are not valid branch targets
4035 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4036 // 64 -> 32 bit transition requires a recompile
4037 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4039 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4040 else printf("optimizable: yes\n");
4042 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4044 if(requires_32bit[t]&~i_is32) return 0;
4052 #ifndef wb_invalidate
4053 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4054 uint64_t u,uint64_t uu)
4057 for(hr=0;hr<HOST_REGS;hr++) {
4058 if(hr!=EXCLUDE_REG) {
4059 if(pre[hr]!=entry[hr]) {
4062 if(get_reg(entry,pre[hr])<0) {
4064 if(!((u>>pre[hr])&1)) {
4065 emit_storereg(pre[hr],hr);
4066 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4067 emit_sarimm(hr,31,hr);
4068 emit_storereg(pre[hr]|64,hr);
4072 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4073 emit_storereg(pre[hr],hr);
4082 // Move from one register to another (no writeback)
4083 for(hr=0;hr<HOST_REGS;hr++) {
4084 if(hr!=EXCLUDE_REG) {
4085 if(pre[hr]!=entry[hr]) {
4086 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4088 if((nr=get_reg(entry,pre[hr]))>=0) {
4098 // Load the specified registers
4099 // This only loads the registers given as arguments because
4100 // we don't want to load things that will be overwritten
4101 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4105 for(hr=0;hr<HOST_REGS;hr++) {
4106 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4107 if(entry[hr]!=regmap[hr]) {
4108 if(regmap[hr]==rs1||regmap[hr]==rs2)
4115 emit_loadreg(regmap[hr],hr);
4122 for(hr=0;hr<HOST_REGS;hr++) {
4123 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4124 if(entry[hr]!=regmap[hr]) {
4125 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4127 assert(regmap[hr]!=64);
4128 if((is32>>(regmap[hr]&63))&1) {
4129 int lr=get_reg(regmap,regmap[hr]-64);
4131 emit_sarimm(lr,31,hr);
4133 emit_loadreg(regmap[hr],hr);
4137 emit_loadreg(regmap[hr],hr);
4145 // Load registers prior to the start of a loop
4146 // so that they are not loaded within the loop
4147 static void loop_preload(signed char pre[],signed char entry[])
4150 for(hr=0;hr<HOST_REGS;hr++) {
4151 if(hr!=EXCLUDE_REG) {
4152 if(pre[hr]!=entry[hr]) {
4154 if(get_reg(pre,entry[hr])<0) {
4155 assem_debug("loop preload:\n");
4156 //printf("loop preload: %d\n",hr);
4160 else if(entry[hr]<TEMPREG)
4162 emit_loadreg(entry[hr],hr);
4164 else if(entry[hr]-64<TEMPREG)
4166 emit_loadreg(entry[hr],hr);
4175 // Generate address for load/store instruction
4176 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4177 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4179 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4181 int agr=AGEN1+(i&1);
4182 int mgr=MGEN1+(i&1);
4183 if(itype[i]==LOAD) {
4184 ra=get_reg(i_regs->regmap,rt1[i]);
4185 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4188 if(itype[i]==LOADLR) {
4189 ra=get_reg(i_regs->regmap,FTEMP);
4191 if(itype[i]==STORE||itype[i]==STORELR) {
4192 ra=get_reg(i_regs->regmap,agr);
4193 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4195 if(itype[i]==C1LS||itype[i]==C2LS) {
4196 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4197 ra=get_reg(i_regs->regmap,FTEMP);
4198 else { // SWC1/SDC1/SWC2/SDC2
4199 ra=get_reg(i_regs->regmap,agr);
4200 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4203 int rs=get_reg(i_regs->regmap,rs1[i]);
4204 int rm=get_reg(i_regs->regmap,TLREG);
4207 int c=(i_regs->wasconst>>rs)&1;
4209 // Using r0 as a base address
4211 if(!entry||entry[rm]!=mgr) {
4212 generate_map_const(offset,rm);
4213 } // else did it in the previous cycle
4215 if(!entry||entry[ra]!=agr) {
4216 if (opcode[i]==0x22||opcode[i]==0x26) {
4217 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4218 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4219 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4221 emit_movimm(offset,ra);
4223 } // else did it in the previous cycle
4226 if(!entry||entry[ra]!=rs1[i])
4227 emit_loadreg(rs1[i],ra);
4228 //if(!entry||entry[ra]!=rs1[i])
4229 // printf("poor load scheduling!\n");
4234 if(!entry||entry[rm]!=mgr) {
4235 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4236 // Stores to memory go thru the mapper to detect self-modifying
4237 // code, loads don't.
4238 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4239 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4240 generate_map_const(constmap[i][rs]+offset,rm);
4242 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4243 generate_map_const(constmap[i][rs]+offset,rm);
4248 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4249 if(!entry||entry[ra]!=agr) {
4250 if (opcode[i]==0x22||opcode[i]==0x26) {
4251 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4252 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4253 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4255 #ifdef HOST_IMM_ADDR32
4256 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4257 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4259 emit_movimm(constmap[i][rs]+offset,ra);
4261 } // else did it in the previous cycle
4262 } // else load_consts already did it
4264 if(offset&&!c&&rs1[i]) {
4266 emit_addimm(rs,offset,ra);
4268 emit_addimm(ra,offset,ra);
4273 // Preload constants for next instruction
4274 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4276 #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
4278 agr=MGEN1+((i+1)&1);
4279 ra=get_reg(i_regs->regmap,agr);
4281 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4282 int offset=imm[i+1];
4283 int c=(regs[i+1].wasconst>>rs)&1;
4285 if(itype[i+1]==STORE||itype[i+1]==STORELR
4286 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4287 // Stores to memory go thru the mapper to detect self-modifying
4288 // code, loads don't.
4289 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4290 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4291 generate_map_const(constmap[i+1][rs]+offset,ra);
4293 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4294 generate_map_const(constmap[i+1][rs]+offset,ra);
4297 /*else if(rs1[i]==0) {
4298 generate_map_const(offset,ra);
4303 agr=AGEN1+((i+1)&1);
4304 ra=get_reg(i_regs->regmap,agr);
4306 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4307 int offset=imm[i+1];
4308 int c=(regs[i+1].wasconst>>rs)&1;
4309 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4310 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4311 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4312 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4313 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4315 #ifdef HOST_IMM_ADDR32
4316 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4317 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4319 emit_movimm(constmap[i+1][rs]+offset,ra);
4322 else if(rs1[i+1]==0) {
4323 // Using r0 as a base address
4324 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4325 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4326 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4327 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4329 emit_movimm(offset,ra);
4336 int get_final_value(int hr, int i, int *value)
4338 int reg=regs[i].regmap[hr];
4340 if(regs[i+1].regmap[hr]!=reg) break;
4341 if(!((regs[i+1].isconst>>hr)&1)) break;
4346 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4347 *value=constmap[i][hr];
4351 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4352 // Load in delay slot, out-of-order execution
4353 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4355 #ifdef HOST_IMM_ADDR32
4356 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4358 // Precompute load address
4359 *value=constmap[i][hr]+imm[i+2];
4363 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4365 #ifdef HOST_IMM_ADDR32
4366 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4368 // Precompute load address
4369 *value=constmap[i][hr]+imm[i+1];
4370 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4375 *value=constmap[i][hr];
4376 //printf("c=%x\n",(int)constmap[i][hr]);
4377 if(i==slen-1) return 1;
4379 return !((unneeded_reg[i+1]>>reg)&1);
4381 return !((unneeded_reg_upper[i+1]>>reg)&1);
4385 // Load registers with known constants
4386 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4390 for(hr=0;hr<HOST_REGS;hr++) {
4391 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4392 //if(entry[hr]!=regmap[hr]) {
4393 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4394 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4396 if(get_final_value(hr,i,&value)) {
4401 emit_movimm(value,hr);
4409 for(hr=0;hr<HOST_REGS;hr++) {
4410 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4411 //if(entry[hr]!=regmap[hr]) {
4412 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4413 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4414 if((is32>>(regmap[hr]&63))&1) {
4415 int lr=get_reg(regmap,regmap[hr]-64);
4417 emit_sarimm(lr,31,hr);
4422 if(get_final_value(hr,i,&value)) {
4427 emit_movimm(value,hr);
4436 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4440 for(hr=0;hr<HOST_REGS;hr++) {
4441 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4442 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4443 int value=constmap[i][hr];
4448 emit_movimm(value,hr);
4454 for(hr=0;hr<HOST_REGS;hr++) {
4455 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4456 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4457 if((is32>>(regmap[hr]&63))&1) {
4458 int lr=get_reg(regmap,regmap[hr]-64);
4460 emit_sarimm(lr,31,hr);
4464 int value=constmap[i][hr];
4469 emit_movimm(value,hr);
4477 // Write out all dirty registers (except cycle count)
4478 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4481 for(hr=0;hr<HOST_REGS;hr++) {
4482 if(hr!=EXCLUDE_REG) {
4483 if(i_regmap[hr]>0) {
4484 if(i_regmap[hr]!=CCREG) {
4485 if((i_dirty>>hr)&1) {
4486 if(i_regmap[hr]<64) {
4487 emit_storereg(i_regmap[hr],hr);
4489 if( ((i_is32>>i_regmap[hr])&1) ) {
4490 #ifdef DESTRUCTIVE_WRITEBACK
4491 emit_sarimm(hr,31,hr);
4492 emit_storereg(i_regmap[hr]|64,hr);
4494 emit_sarimm(hr,31,HOST_TEMPREG);
4495 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4500 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4501 emit_storereg(i_regmap[hr],hr);
4510 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4511 // This writes the registers not written by store_regs_bt
4512 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4515 int t=(addr-start)>>2;
4516 for(hr=0;hr<HOST_REGS;hr++) {
4517 if(hr!=EXCLUDE_REG) {
4518 if(i_regmap[hr]>0) {
4519 if(i_regmap[hr]!=CCREG) {
4520 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4521 if((i_dirty>>hr)&1) {
4522 if(i_regmap[hr]<64) {
4523 emit_storereg(i_regmap[hr],hr);
4525 if( ((i_is32>>i_regmap[hr])&1) ) {
4526 #ifdef DESTRUCTIVE_WRITEBACK
4527 emit_sarimm(hr,31,hr);
4528 emit_storereg(i_regmap[hr]|64,hr);
4530 emit_sarimm(hr,31,HOST_TEMPREG);
4531 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4536 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4537 emit_storereg(i_regmap[hr],hr);
4548 // Load all registers (except cycle count)
4549 void load_all_regs(signed char i_regmap[])
4552 for(hr=0;hr<HOST_REGS;hr++) {
4553 if(hr!=EXCLUDE_REG) {
4554 if(i_regmap[hr]==0) {
4558 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4560 emit_loadreg(i_regmap[hr],hr);
4566 // Load all current registers also needed by next instruction
4567 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4570 for(hr=0;hr<HOST_REGS;hr++) {
4571 if(hr!=EXCLUDE_REG) {
4572 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4573 if(i_regmap[hr]==0) {
4577 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4579 emit_loadreg(i_regmap[hr],hr);
4586 // Load all regs, storing cycle count if necessary
4587 void load_regs_entry(int t)
4590 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4591 else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4592 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4593 emit_storereg(CCREG,HOST_CCREG);
4596 for(hr=0;hr<HOST_REGS;hr++) {
4597 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4598 if(regs[t].regmap_entry[hr]==0) {
4601 else if(regs[t].regmap_entry[hr]!=CCREG)
4603 emit_loadreg(regs[t].regmap_entry[hr],hr);
4608 for(hr=0;hr<HOST_REGS;hr++) {
4609 if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4610 assert(regs[t].regmap_entry[hr]!=64);
4611 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4612 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4614 emit_loadreg(regs[t].regmap_entry[hr],hr);
4618 emit_sarimm(lr,31,hr);
4623 emit_loadreg(regs[t].regmap_entry[hr],hr);
4629 // Store dirty registers prior to branch
4630 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4632 if(internal_branch(i_is32,addr))
4634 int t=(addr-start)>>2;
4636 for(hr=0;hr<HOST_REGS;hr++) {
4637 if(hr!=EXCLUDE_REG) {
4638 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4639 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4640 if((i_dirty>>hr)&1) {
4641 if(i_regmap[hr]<64) {
4642 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4643 emit_storereg(i_regmap[hr],hr);
4644 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4645 #ifdef DESTRUCTIVE_WRITEBACK
4646 emit_sarimm(hr,31,hr);
4647 emit_storereg(i_regmap[hr]|64,hr);
4649 emit_sarimm(hr,31,HOST_TEMPREG);
4650 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4655 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4656 emit_storereg(i_regmap[hr],hr);
4667 // Branch out of this block, write out all dirty regs
4668 wb_dirtys(i_regmap,i_is32,i_dirty);
4672 // Load all needed registers for branch target
4673 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4675 //if(addr>=start && addr<(start+slen*4))
4676 if(internal_branch(i_is32,addr))
4678 int t=(addr-start)>>2;
4680 // Store the cycle count before loading something else
4681 if(i_regmap[HOST_CCREG]!=CCREG) {
4682 assert(i_regmap[HOST_CCREG]==-1);
4684 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4685 emit_storereg(CCREG,HOST_CCREG);
4688 for(hr=0;hr<HOST_REGS;hr++) {
4689 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4690 #ifdef DESTRUCTIVE_WRITEBACK
4691 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4693 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4695 if(regs[t].regmap_entry[hr]==0) {
4698 else if(regs[t].regmap_entry[hr]!=CCREG)
4700 emit_loadreg(regs[t].regmap_entry[hr],hr);
4706 for(hr=0;hr<HOST_REGS;hr++) {
4707 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4708 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4709 assert(regs[t].regmap_entry[hr]!=64);
4710 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4711 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4713 emit_loadreg(regs[t].regmap_entry[hr],hr);
4717 emit_sarimm(lr,31,hr);
4722 emit_loadreg(regs[t].regmap_entry[hr],hr);
4725 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4726 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4728 emit_sarimm(lr,31,hr);
4735 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4737 if(addr>=start && addr<start+slen*4-4)
4739 int t=(addr-start)>>2;
4741 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4742 for(hr=0;hr<HOST_REGS;hr++)
4746 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4748 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4755 if(i_regmap[hr]<TEMPREG)
4757 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4760 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4762 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4767 else // Same register but is it 32-bit or dirty?
4770 if(!((regs[t].dirty>>hr)&1))
4774 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4776 //printf("%x: dirty no match\n",addr);
4781 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4783 //printf("%x: is32 no match\n",addr);
4789 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4791 if(requires_32bit[t]&~i_is32) return 0;
4793 // Delay slots are not valid branch targets
4794 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4795 // Delay slots require additional processing, so do not match
4796 if(is_ds[t]) return 0;
4801 for(hr=0;hr<HOST_REGS;hr++)
4807 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4821 // Used when a branch jumps into the delay slot of another branch
4822 void ds_assemble_entry(int i)
4824 int t=(ba[i]-start)>>2;
4825 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4826 assem_debug("Assemble delay slot at %x\n",ba[i]);
4827 assem_debug("<->\n");
4828 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4829 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4830 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4831 address_generation(t,®s[t],regs[t].regmap_entry);
4832 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4833 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4838 alu_assemble(t,®s[t]);break;
4840 imm16_assemble(t,®s[t]);break;
4842 shift_assemble(t,®s[t]);break;
4844 shiftimm_assemble(t,®s[t]);break;
4846 load_assemble(t,®s[t]);break;
4848 loadlr_assemble(t,®s[t]);break;
4850 store_assemble(t,®s[t]);break;
4852 storelr_assemble(t,®s[t]);break;
4854 cop0_assemble(t,®s[t]);break;
4856 cop1_assemble(t,®s[t]);break;
4858 c1ls_assemble(t,®s[t]);break;
4860 cop2_assemble(t,®s[t]);break;
4862 c2ls_assemble(t,®s[t]);break;
4864 c2op_assemble(t,®s[t]);break;
4866 fconv_assemble(t,®s[t]);break;
4868 float_assemble(t,®s[t]);break;
4870 fcomp_assemble(t,®s[t]);break;
4872 multdiv_assemble(t,®s[t]);break;
4874 mov_assemble(t,®s[t]);break;
4884 printf("Jump in the delay slot. This is probably a bug.\n");
4886 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4887 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4888 if(internal_branch(regs[t].is32,ba[i]+4))
4889 assem_debug("branch: internal\n");
4891 assem_debug("branch: external\n");
4892 assert(internal_branch(regs[t].is32,ba[i]+4));
4893 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4897 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4906 //if(ba[i]>=start && ba[i]<(start+slen*4))
4907 if(internal_branch(branch_regs[i].is32,ba[i]))
4909 int t=(ba[i]-start)>>2;
4910 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4918 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4920 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4922 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4923 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4927 else if(*adj==0||invert) {
4928 emit_addimm_and_set_flags(CLOCK_ADJUST(count+2),HOST_CCREG);
4934 emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
4938 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4941 void do_ccstub(int n)
4944 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4945 set_jump_target(stubs[n][1],(int)out);
4947 if(stubs[n][6]==NULLDS) {
4948 // Delay slot instruction is nullified ("likely" branch)
4949 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4951 else if(stubs[n][6]!=TAKEN) {
4952 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4955 if(internal_branch(branch_regs[i].is32,ba[i]))
4956 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4960 // Save PC as return address
4961 emit_movimm(stubs[n][5],EAX);
4962 emit_writeword(EAX,(int)&pcaddr);
4966 // Return address depends on which way the branch goes
4967 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4969 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4970 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4971 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4972 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4982 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4986 #ifdef DESTRUCTIVE_WRITEBACK
4988 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4989 emit_loadreg(rs1[i],s1l);
4992 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4993 emit_loadreg(rs2[i],s1l);
4996 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4997 emit_loadreg(rs2[i],s2l);
5000 int addr=-1,alt=-1,ntaddr=-1;
5003 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5004 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5005 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5013 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5014 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5015 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5021 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5025 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5026 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5027 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5033 assert(hr<HOST_REGS);
5035 if((opcode[i]&0x2f)==4) // BEQ
5037 #ifdef HAVE_CMOV_IMM
5039 if(s2l>=0) emit_cmp(s1l,s2l);
5040 else emit_test(s1l,s1l);
5041 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5046 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5048 if(s2h>=0) emit_cmp(s1h,s2h);
5049 else emit_test(s1h,s1h);
5050 emit_cmovne_reg(alt,addr);
5052 if(s2l>=0) emit_cmp(s1l,s2l);
5053 else emit_test(s1l,s1l);
5054 emit_cmovne_reg(alt,addr);
5057 if((opcode[i]&0x2f)==5) // BNE
5059 #ifdef HAVE_CMOV_IMM
5061 if(s2l>=0) emit_cmp(s1l,s2l);
5062 else emit_test(s1l,s1l);
5063 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5068 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5070 if(s2h>=0) emit_cmp(s1h,s2h);
5071 else emit_test(s1h,s1h);
5072 emit_cmovne_reg(alt,addr);
5074 if(s2l>=0) emit_cmp(s1l,s2l);
5075 else emit_test(s1l,s1l);
5076 emit_cmovne_reg(alt,addr);
5079 if((opcode[i]&0x2f)==6) // BLEZ
5081 //emit_movimm(ba[i],alt);
5082 //emit_movimm(start+i*4+8,addr);
5083 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5085 if(s1h>=0) emit_mov(addr,ntaddr);
5086 emit_cmovl_reg(alt,addr);
5089 emit_cmovne_reg(ntaddr,addr);
5090 emit_cmovs_reg(alt,addr);
5093 if((opcode[i]&0x2f)==7) // BGTZ
5095 //emit_movimm(ba[i],addr);
5096 //emit_movimm(start+i*4+8,ntaddr);
5097 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5099 if(s1h>=0) emit_mov(addr,alt);
5100 emit_cmovl_reg(ntaddr,addr);
5103 emit_cmovne_reg(alt,addr);
5104 emit_cmovs_reg(ntaddr,addr);
5107 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5109 //emit_movimm(ba[i],alt);
5110 //emit_movimm(start+i*4+8,addr);
5111 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5112 if(s1h>=0) emit_test(s1h,s1h);
5113 else emit_test(s1l,s1l);
5114 emit_cmovs_reg(alt,addr);
5116 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5118 //emit_movimm(ba[i],addr);
5119 //emit_movimm(start+i*4+8,alt);
5120 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5121 if(s1h>=0) emit_test(s1h,s1h);
5122 else emit_test(s1l,s1l);
5123 emit_cmovs_reg(alt,addr);
5125 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5126 if(source[i]&0x10000) // BC1T
5128 //emit_movimm(ba[i],alt);
5129 //emit_movimm(start+i*4+8,addr);
5130 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5131 emit_testimm(s1l,0x800000);
5132 emit_cmovne_reg(alt,addr);
5136 //emit_movimm(ba[i],addr);
5137 //emit_movimm(start+i*4+8,alt);
5138 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5139 emit_testimm(s1l,0x800000);
5140 emit_cmovne_reg(alt,addr);
5143 emit_writeword(addr,(int)&pcaddr);
5148 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5149 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5150 r=get_reg(branch_regs[i].regmap,RTEMP);
5152 emit_writeword(r,(int)&pcaddr);
5154 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5156 // Update cycle count
5157 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5158 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5159 emit_call((int)cc_interrupt);
5160 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5161 if(stubs[n][6]==TAKEN) {
5162 if(internal_branch(branch_regs[i].is32,ba[i]))
5163 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5164 else if(itype[i]==RJUMP) {
5165 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5166 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5168 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5170 }else if(stubs[n][6]==NOTTAKEN) {
5171 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5172 else load_all_regs(branch_regs[i].regmap);
5173 }else if(stubs[n][6]==NULLDS) {
5174 // Delay slot instruction is nullified ("likely" branch)
5175 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5176 else load_all_regs(regs[i].regmap);
5178 load_all_regs(branch_regs[i].regmap);
5180 emit_jmp(stubs[n][2]); // return address
5182 /* This works but uses a lot of memory...
5183 emit_readword((int)&last_count,ECX);
5184 emit_add(HOST_CCREG,ECX,EAX);
5185 emit_writeword(EAX,(int)&Count);
5186 emit_call((int)gen_interupt);
5187 emit_readword((int)&Count,HOST_CCREG);
5188 emit_readword((int)&next_interupt,EAX);
5189 emit_readword((int)&pending_exception,EBX);
5190 emit_writeword(EAX,(int)&last_count);
5191 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5193 int jne_instr=(int)out;
5195 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5196 load_all_regs(branch_regs[i].regmap);
5197 emit_jmp(stubs[n][2]); // return address
5198 set_jump_target(jne_instr,(int)out);
5199 emit_readword((int)&pcaddr,EAX);
5200 // Call get_addr_ht instead of doing the hash table here.
5201 // This code is executed infrequently and takes up a lot of space
5202 // so smaller is better.
5203 emit_storereg(CCREG,HOST_CCREG);
5205 emit_call((int)get_addr_ht);
5206 emit_loadreg(CCREG,HOST_CCREG);
5207 emit_addimm(ESP,4,ESP);
5211 add_to_linker(int addr,int target,int ext)
5213 link_addr[linkcount][0]=addr;
5214 link_addr[linkcount][1]=target;
5215 link_addr[linkcount][2]=ext;
5219 static void ujump_assemble_write_ra(int i)
5222 unsigned int return_address;
5223 rt=get_reg(branch_regs[i].regmap,31);
5224 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5226 return_address=start+i*4+8;
5229 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5230 int temp=-1; // note: must be ds-safe
5234 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5235 else emit_movimm(return_address,rt);
5243 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5246 emit_movimm(return_address,rt); // PC into link register
5248 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5254 void ujump_assemble(int i,struct regstat *i_regs)
5256 signed char *i_regmap=i_regs->regmap;
5258 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5259 address_generation(i+1,i_regs,regs[i].regmap_entry);
5261 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5262 if(rt1[i]==31&&temp>=0)
5264 int return_address=start+i*4+8;
5265 if(get_reg(branch_regs[i].regmap,31)>0)
5266 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5269 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5270 ujump_assemble_write_ra(i); // writeback ra for DS
5273 ds_assemble(i+1,i_regs);
5274 uint64_t bc_unneeded=branch_regs[i].u;
5275 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5276 bc_unneeded|=1|(1LL<<rt1[i]);
5277 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5278 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5279 bc_unneeded,bc_unneeded_upper);
5280 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5281 if(!ra_done&&rt1[i]==31)
5282 ujump_assemble_write_ra(i);
5284 cc=get_reg(branch_regs[i].regmap,CCREG);
5285 assert(cc==HOST_CCREG);
5286 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5288 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5290 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5291 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5292 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5293 if(internal_branch(branch_regs[i].is32,ba[i]))
5294 assem_debug("branch: internal\n");
5296 assem_debug("branch: external\n");
5297 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5298 ds_assemble_entry(i);
5301 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5306 static void rjump_assemble_write_ra(int i)
5308 int rt,return_address;
5309 assert(rt1[i+1]!=rt1[i]);
5310 assert(rt2[i+1]!=rt1[i]);
5311 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5312 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5314 return_address=start+i*4+8;
5318 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5321 emit_movimm(return_address,rt); // PC into link register
5323 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5327 void rjump_assemble(int i,struct regstat *i_regs)
5329 signed char *i_regmap=i_regs->regmap;
5333 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5335 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5336 // Delay slot abuse, make a copy of the branch address register
5337 temp=get_reg(branch_regs[i].regmap,RTEMP);
5339 assert(regs[i].regmap[temp]==RTEMP);
5343 address_generation(i+1,i_regs,regs[i].regmap_entry);
5347 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5348 int return_address=start+i*4+8;
5349 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5355 int rh=get_reg(regs[i].regmap,RHASH);
5356 if(rh>=0) do_preload_rhash(rh);
5359 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5360 rjump_assemble_write_ra(i);
5363 ds_assemble(i+1,i_regs);
5364 uint64_t bc_unneeded=branch_regs[i].u;
5365 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5366 bc_unneeded|=1|(1LL<<rt1[i]);
5367 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5368 bc_unneeded&=~(1LL<<rs1[i]);
5369 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5370 bc_unneeded,bc_unneeded_upper);
5371 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5372 if(!ra_done&&rt1[i]!=0)
5373 rjump_assemble_write_ra(i);
5374 cc=get_reg(branch_regs[i].regmap,CCREG);
5375 assert(cc==HOST_CCREG);
5377 int rh=get_reg(branch_regs[i].regmap,RHASH);
5378 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5380 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5381 do_preload_rhtbl(ht);
5385 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5386 #ifdef DESTRUCTIVE_WRITEBACK
5387 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5388 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5389 emit_loadreg(rs1[i],rs);
5394 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5398 do_miniht_load(ht,rh);
5401 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5402 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5404 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5405 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5407 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5410 do_miniht_jump(rs,rh,ht);
5415 //if(rs!=EAX) emit_mov(rs,EAX);
5416 //emit_jmp((int)jump_vaddr_eax);
5417 emit_jmp(jump_vaddr_reg[rs]);
5422 emit_shrimm(rs,16,rs);
5423 emit_xor(temp,rs,rs);
5424 emit_movzwl_reg(rs,rs);
5425 emit_shlimm(rs,4,rs);
5426 emit_cmpmem_indexed((int)hash_table,rs,temp);
5427 emit_jne((int)out+14);
5428 emit_readword_indexed((int)hash_table+4,rs,rs);
5430 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5431 emit_addimm_no_flags(8,rs);
5432 emit_jeq((int)out-17);
5433 // No hit on hash table, call compiler
5436 #ifdef DEBUG_CYCLE_COUNT
5437 emit_readword((int)&last_count,ECX);
5438 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5439 emit_readword((int)&next_interupt,ECX);
5440 emit_writeword(HOST_CCREG,(int)&Count);
5441 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5442 emit_writeword(ECX,(int)&last_count);
5445 emit_storereg(CCREG,HOST_CCREG);
5446 emit_call((int)get_addr);
5447 emit_loadreg(CCREG,HOST_CCREG);
5448 emit_addimm(ESP,4,ESP);
5450 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5451 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5455 void cjump_assemble(int i,struct regstat *i_regs)
5457 signed char *i_regmap=i_regs->regmap;
5460 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5461 assem_debug("match=%d\n",match);
5462 int s1h,s1l,s2h,s2l;
5463 int prev_cop1_usable=cop1_usable;
5464 int unconditional=0,nop=0;
5467 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5468 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5469 if(!match) invert=1;
5470 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5471 if(i>(ba[i]-start)>>2) invert=1;
5475 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5476 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5477 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5478 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5481 s1l=get_reg(i_regmap,rs1[i]);
5482 s1h=get_reg(i_regmap,rs1[i]|64);
5483 s2l=get_reg(i_regmap,rs2[i]);
5484 s2h=get_reg(i_regmap,rs2[i]|64);
5486 if(rs1[i]==0&&rs2[i]==0)
5488 if(opcode[i]&1) nop=1;
5489 else unconditional=1;
5490 //assert(opcode[i]!=5);
5491 //assert(opcode[i]!=7);
5492 //assert(opcode[i]!=0x15);
5493 //assert(opcode[i]!=0x17);
5499 only32=(regs[i].was32>>rs2[i])&1;
5504 only32=(regs[i].was32>>rs1[i])&1;
5507 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5511 // Out of order execution (delay slot first)
5513 address_generation(i+1,i_regs,regs[i].regmap_entry);
5514 ds_assemble(i+1,i_regs);
5516 uint64_t bc_unneeded=branch_regs[i].u;
5517 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5518 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5519 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5521 bc_unneeded_upper|=1;
5522 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5523 bc_unneeded,bc_unneeded_upper);
5524 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5525 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5526 cc=get_reg(branch_regs[i].regmap,CCREG);
5527 assert(cc==HOST_CCREG);
5529 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5530 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5531 //assem_debug("cycle count (adj)\n");
5533 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5534 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5535 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5536 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5538 assem_debug("branch: internal\n");
5540 assem_debug("branch: external\n");
5541 if(internal&&is_ds[(ba[i]-start)>>2]) {
5542 ds_assemble_entry(i);
5545 add_to_linker((int)out,ba[i],internal);
5548 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5549 if(((u_int)out)&7) emit_addnop(0);
5554 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5557 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5560 int taken=0,nottaken=0,nottaken1=0;
5561 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5562 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5566 if(opcode[i]==4) // BEQ
5568 if(s2h>=0) emit_cmp(s1h,s2h);
5569 else emit_test(s1h,s1h);
5573 if(opcode[i]==5) // BNE
5575 if(s2h>=0) emit_cmp(s1h,s2h);
5576 else emit_test(s1h,s1h);
5577 if(invert) taken=(int)out;
5578 else add_to_linker((int)out,ba[i],internal);
5581 if(opcode[i]==6) // BLEZ
5584 if(invert) taken=(int)out;
5585 else add_to_linker((int)out,ba[i],internal);
5590 if(opcode[i]==7) // BGTZ
5595 if(invert) taken=(int)out;
5596 else add_to_linker((int)out,ba[i],internal);
5601 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5603 if(opcode[i]==4) // BEQ
5605 if(s2l>=0) emit_cmp(s1l,s2l);
5606 else emit_test(s1l,s1l);
5611 add_to_linker((int)out,ba[i],internal);
5615 if(opcode[i]==5) // BNE
5617 if(s2l>=0) emit_cmp(s1l,s2l);
5618 else emit_test(s1l,s1l);
5623 add_to_linker((int)out,ba[i],internal);
5627 if(opcode[i]==6) // BLEZ
5634 add_to_linker((int)out,ba[i],internal);
5638 if(opcode[i]==7) // BGTZ
5645 add_to_linker((int)out,ba[i],internal);
5650 if(taken) set_jump_target(taken,(int)out);
5651 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5652 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5654 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5655 add_to_linker((int)out,ba[i],internal);
5658 add_to_linker((int)out,ba[i],internal*2);
5664 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5665 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5666 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5668 assem_debug("branch: internal\n");
5670 assem_debug("branch: external\n");
5671 if(internal&&is_ds[(ba[i]-start)>>2]) {
5672 ds_assemble_entry(i);
5675 add_to_linker((int)out,ba[i],internal);
5679 set_jump_target(nottaken,(int)out);
5682 if(nottaken1) set_jump_target(nottaken1,(int)out);
5684 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5686 } // (!unconditional)
5690 // In-order execution (branch first)
5691 //if(likely[i]) printf("IOL\n");
5694 int taken=0,nottaken=0,nottaken1=0;
5695 if(!unconditional&&!nop) {
5699 if((opcode[i]&0x2f)==4) // BEQ
5701 if(s2h>=0) emit_cmp(s1h,s2h);
5702 else emit_test(s1h,s1h);
5706 if((opcode[i]&0x2f)==5) // BNE
5708 if(s2h>=0) emit_cmp(s1h,s2h);
5709 else emit_test(s1h,s1h);
5713 if((opcode[i]&0x2f)==6) // BLEZ
5721 if((opcode[i]&0x2f)==7) // BGTZ
5731 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5733 if((opcode[i]&0x2f)==4) // BEQ
5735 if(s2l>=0) emit_cmp(s1l,s2l);
5736 else emit_test(s1l,s1l);
5740 if((opcode[i]&0x2f)==5) // BNE
5742 if(s2l>=0) emit_cmp(s1l,s2l);
5743 else emit_test(s1l,s1l);
5747 if((opcode[i]&0x2f)==6) // BLEZ
5753 if((opcode[i]&0x2f)==7) // BGTZ
5759 } // if(!unconditional)
5761 uint64_t ds_unneeded=branch_regs[i].u;
5762 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5763 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5764 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5765 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5767 ds_unneeded_upper|=1;
5770 if(taken) set_jump_target(taken,(int)out);
5771 assem_debug("1:\n");
5772 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5773 ds_unneeded,ds_unneeded_upper);
5775 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5776 address_generation(i+1,&branch_regs[i],0);
5777 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5778 ds_assemble(i+1,&branch_regs[i]);
5779 cc=get_reg(branch_regs[i].regmap,CCREG);
5781 emit_loadreg(CCREG,cc=HOST_CCREG);
5782 // CHECK: Is the following instruction (fall thru) allocated ok?
5784 assert(cc==HOST_CCREG);
5785 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5786 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5787 assem_debug("cycle count (adj)\n");
5788 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5789 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5791 assem_debug("branch: internal\n");
5793 assem_debug("branch: external\n");
5794 if(internal&&is_ds[(ba[i]-start)>>2]) {
5795 ds_assemble_entry(i);
5798 add_to_linker((int)out,ba[i],internal);
5803 cop1_usable=prev_cop1_usable;
5804 if(!unconditional) {
5805 if(nottaken1) set_jump_target(nottaken1,(int)out);
5806 set_jump_target(nottaken,(int)out);
5807 assem_debug("2:\n");
5809 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5810 ds_unneeded,ds_unneeded_upper);
5811 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5812 address_generation(i+1,&branch_regs[i],0);
5813 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5814 ds_assemble(i+1,&branch_regs[i]);
5816 cc=get_reg(branch_regs[i].regmap,CCREG);
5817 if(cc==-1&&!likely[i]) {
5818 // Cycle count isn't in a register, temporarily load it then write it out
5819 emit_loadreg(CCREG,HOST_CCREG);
5820 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5823 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5824 emit_storereg(CCREG,HOST_CCREG);
5827 cc=get_reg(i_regmap,CCREG);
5828 assert(cc==HOST_CCREG);
5829 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5832 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5838 void sjump_assemble(int i,struct regstat *i_regs)
5840 signed char *i_regmap=i_regs->regmap;
5843 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5844 assem_debug("smatch=%d\n",match);
5846 int prev_cop1_usable=cop1_usable;
5847 int unconditional=0,nevertaken=0;
5850 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5851 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5852 if(!match) invert=1;
5853 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5854 if(i>(ba[i]-start)>>2) invert=1;
5857 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5858 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5861 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5862 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5865 s1l=get_reg(i_regmap,rs1[i]);
5866 s1h=get_reg(i_regmap,rs1[i]|64);
5870 if(opcode2[i]&1) unconditional=1;
5872 // These are never taken (r0 is never less than zero)
5873 //assert(opcode2[i]!=0);
5874 //assert(opcode2[i]!=2);
5875 //assert(opcode2[i]!=0x10);
5876 //assert(opcode2[i]!=0x12);
5879 only32=(regs[i].was32>>rs1[i])&1;
5883 // Out of order execution (delay slot first)
5885 address_generation(i+1,i_regs,regs[i].regmap_entry);
5886 ds_assemble(i+1,i_regs);
5888 uint64_t bc_unneeded=branch_regs[i].u;
5889 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5890 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5891 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5893 bc_unneeded_upper|=1;
5894 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5895 bc_unneeded,bc_unneeded_upper);
5896 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5897 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5899 int rt,return_address;
5900 rt=get_reg(branch_regs[i].regmap,31);
5901 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5903 // Save the PC even if the branch is not taken
5904 return_address=start+i*4+8;
5905 emit_movimm(return_address,rt); // PC into link register
5907 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5911 cc=get_reg(branch_regs[i].regmap,CCREG);
5912 assert(cc==HOST_CCREG);
5914 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5915 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5916 assem_debug("cycle count (adj)\n");
5918 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5919 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5920 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5921 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5923 assem_debug("branch: internal\n");
5925 assem_debug("branch: external\n");
5926 if(internal&&is_ds[(ba[i]-start)>>2]) {
5927 ds_assemble_entry(i);
5930 add_to_linker((int)out,ba[i],internal);
5933 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5934 if(((u_int)out)&7) emit_addnop(0);
5938 else if(nevertaken) {
5939 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5942 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5946 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5947 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5951 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5958 add_to_linker((int)out,ba[i],internal);
5962 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5969 add_to_linker((int)out,ba[i],internal);
5977 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5984 add_to_linker((int)out,ba[i],internal);
5988 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5995 add_to_linker((int)out,ba[i],internal);
6002 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6003 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6005 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6006 add_to_linker((int)out,ba[i],internal);
6009 add_to_linker((int)out,ba[i],internal*2);
6015 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6016 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6017 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6019 assem_debug("branch: internal\n");
6021 assem_debug("branch: external\n");
6022 if(internal&&is_ds[(ba[i]-start)>>2]) {
6023 ds_assemble_entry(i);
6026 add_to_linker((int)out,ba[i],internal);
6030 set_jump_target(nottaken,(int)out);
6034 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6036 } // (!unconditional)
6040 // In-order execution (branch first)
6044 int rt,return_address;
6045 rt=get_reg(branch_regs[i].regmap,31);
6047 // Save the PC even if the branch is not taken
6048 return_address=start+i*4+8;
6049 emit_movimm(return_address,rt); // PC into link register
6051 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6055 if(!unconditional) {
6056 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6060 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6066 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6076 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6082 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6089 } // if(!unconditional)
6091 uint64_t ds_unneeded=branch_regs[i].u;
6092 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6093 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6094 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6095 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6097 ds_unneeded_upper|=1;
6100 //assem_debug("1:\n");
6101 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6102 ds_unneeded,ds_unneeded_upper);
6104 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6105 address_generation(i+1,&branch_regs[i],0);
6106 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6107 ds_assemble(i+1,&branch_regs[i]);
6108 cc=get_reg(branch_regs[i].regmap,CCREG);
6110 emit_loadreg(CCREG,cc=HOST_CCREG);
6111 // CHECK: Is the following instruction (fall thru) allocated ok?
6113 assert(cc==HOST_CCREG);
6114 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6115 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6116 assem_debug("cycle count (adj)\n");
6117 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6118 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6120 assem_debug("branch: internal\n");
6122 assem_debug("branch: external\n");
6123 if(internal&&is_ds[(ba[i]-start)>>2]) {
6124 ds_assemble_entry(i);
6127 add_to_linker((int)out,ba[i],internal);
6132 cop1_usable=prev_cop1_usable;
6133 if(!unconditional) {
6134 set_jump_target(nottaken,(int)out);
6135 assem_debug("1:\n");
6137 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6138 ds_unneeded,ds_unneeded_upper);
6139 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6140 address_generation(i+1,&branch_regs[i],0);
6141 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6142 ds_assemble(i+1,&branch_regs[i]);
6144 cc=get_reg(branch_regs[i].regmap,CCREG);
6145 if(cc==-1&&!likely[i]) {
6146 // Cycle count isn't in a register, temporarily load it then write it out
6147 emit_loadreg(CCREG,HOST_CCREG);
6148 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6151 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6152 emit_storereg(CCREG,HOST_CCREG);
6155 cc=get_reg(i_regmap,CCREG);
6156 assert(cc==HOST_CCREG);
6157 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6160 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6166 void fjump_assemble(int i,struct regstat *i_regs)
6168 signed char *i_regmap=i_regs->regmap;
6171 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6172 assem_debug("fmatch=%d\n",match);
6176 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6177 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6178 if(!match) invert=1;
6179 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6180 if(i>(ba[i]-start)>>2) invert=1;
6184 fs=get_reg(branch_regs[i].regmap,FSREG);
6185 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6188 fs=get_reg(i_regmap,FSREG);
6191 // Check cop1 unusable
6193 cs=get_reg(i_regmap,CSREG);
6195 emit_testimm(cs,0x20000000);
6198 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6203 // Out of order execution (delay slot first)
6205 ds_assemble(i+1,i_regs);
6207 uint64_t bc_unneeded=branch_regs[i].u;
6208 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6209 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6210 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6212 bc_unneeded_upper|=1;
6213 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6214 bc_unneeded,bc_unneeded_upper);
6215 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6216 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6217 cc=get_reg(branch_regs[i].regmap,CCREG);
6218 assert(cc==HOST_CCREG);
6219 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6220 assem_debug("cycle count (adj)\n");
6223 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6226 emit_testimm(fs,0x800000);
6227 if(source[i]&0x10000) // BC1T
6233 add_to_linker((int)out,ba[i],internal);
6242 add_to_linker((int)out,ba[i],internal);
6250 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6251 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6252 else if(match) emit_addnop(13);
6254 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6255 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6257 assem_debug("branch: internal\n");
6259 assem_debug("branch: external\n");
6260 if(internal&&is_ds[(ba[i]-start)>>2]) {
6261 ds_assemble_entry(i);
6264 add_to_linker((int)out,ba[i],internal);
6267 set_jump_target(nottaken,(int)out);
6271 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6273 } // (!unconditional)
6277 // In-order execution (branch first)
6281 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6284 emit_testimm(fs,0x800000);
6285 if(source[i]&0x10000) // BC1T
6296 } // if(!unconditional)
6298 uint64_t ds_unneeded=branch_regs[i].u;
6299 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6300 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6301 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6302 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6304 ds_unneeded_upper|=1;
6306 //assem_debug("1:\n");
6307 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6308 ds_unneeded,ds_unneeded_upper);
6310 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6311 address_generation(i+1,&branch_regs[i],0);
6312 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6313 ds_assemble(i+1,&branch_regs[i]);
6314 cc=get_reg(branch_regs[i].regmap,CCREG);
6316 emit_loadreg(CCREG,cc=HOST_CCREG);
6317 // CHECK: Is the following instruction (fall thru) allocated ok?
6319 assert(cc==HOST_CCREG);
6320 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6321 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6322 assem_debug("cycle count (adj)\n");
6323 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6324 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6326 assem_debug("branch: internal\n");
6328 assem_debug("branch: external\n");
6329 if(internal&&is_ds[(ba[i]-start)>>2]) {
6330 ds_assemble_entry(i);
6333 add_to_linker((int)out,ba[i],internal);
6338 if(1) { // <- FIXME (don't need this)
6339 set_jump_target(nottaken,(int)out);
6340 assem_debug("1:\n");
6342 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6343 ds_unneeded,ds_unneeded_upper);
6344 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6345 address_generation(i+1,&branch_regs[i],0);
6346 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6347 ds_assemble(i+1,&branch_regs[i]);
6349 cc=get_reg(branch_regs[i].regmap,CCREG);
6350 if(cc==-1&&!likely[i]) {
6351 // Cycle count isn't in a register, temporarily load it then write it out
6352 emit_loadreg(CCREG,HOST_CCREG);
6353 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6356 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6357 emit_storereg(CCREG,HOST_CCREG);
6360 cc=get_reg(i_regmap,CCREG);
6361 assert(cc==HOST_CCREG);
6362 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6365 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6371 static void pagespan_assemble(int i,struct regstat *i_regs)
6373 int s1l=get_reg(i_regs->regmap,rs1[i]);
6374 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6375 int s2l=get_reg(i_regs->regmap,rs2[i]);
6376 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6377 void *nt_branch=NULL;
6380 int unconditional=0;
6390 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6394 int addr,alt,ntaddr;
6395 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6399 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6400 (i_regs->regmap[hr]&63)!=rs1[i] &&
6401 (i_regs->regmap[hr]&63)!=rs2[i] )
6410 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6411 (i_regs->regmap[hr]&63)!=rs1[i] &&
6412 (i_regs->regmap[hr]&63)!=rs2[i] )
6418 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6422 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6423 (i_regs->regmap[hr]&63)!=rs1[i] &&
6424 (i_regs->regmap[hr]&63)!=rs2[i] )
6431 assert(hr<HOST_REGS);
6432 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6433 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6435 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6436 if(opcode[i]==2) // J
6440 if(opcode[i]==3) // JAL
6443 int rt=get_reg(i_regs->regmap,31);
6444 emit_movimm(start+i*4+8,rt);
6447 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6450 if(opcode2[i]==9) // JALR
6452 int rt=get_reg(i_regs->regmap,rt1[i]);
6453 emit_movimm(start+i*4+8,rt);
6456 if((opcode[i]&0x3f)==4) // BEQ
6463 #ifdef HAVE_CMOV_IMM
6465 if(s2l>=0) emit_cmp(s1l,s2l);
6466 else emit_test(s1l,s1l);
6467 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6473 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6475 if(s2h>=0) emit_cmp(s1h,s2h);
6476 else emit_test(s1h,s1h);
6477 emit_cmovne_reg(alt,addr);
6479 if(s2l>=0) emit_cmp(s1l,s2l);
6480 else emit_test(s1l,s1l);
6481 emit_cmovne_reg(alt,addr);
6484 if((opcode[i]&0x3f)==5) // BNE
6486 #ifdef HAVE_CMOV_IMM
6488 if(s2l>=0) emit_cmp(s1l,s2l);
6489 else emit_test(s1l,s1l);
6490 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6496 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6498 if(s2h>=0) emit_cmp(s1h,s2h);
6499 else emit_test(s1h,s1h);
6500 emit_cmovne_reg(alt,addr);
6502 if(s2l>=0) emit_cmp(s1l,s2l);
6503 else emit_test(s1l,s1l);
6504 emit_cmovne_reg(alt,addr);
6507 if((opcode[i]&0x3f)==0x14) // BEQL
6510 if(s2h>=0) emit_cmp(s1h,s2h);
6511 else emit_test(s1h,s1h);
6515 if(s2l>=0) emit_cmp(s1l,s2l);
6516 else emit_test(s1l,s1l);
6517 if(nottaken) set_jump_target(nottaken,(int)out);
6521 if((opcode[i]&0x3f)==0x15) // BNEL
6524 if(s2h>=0) emit_cmp(s1h,s2h);
6525 else emit_test(s1h,s1h);
6529 if(s2l>=0) emit_cmp(s1l,s2l);
6530 else emit_test(s1l,s1l);
6533 if(taken) set_jump_target(taken,(int)out);
6535 if((opcode[i]&0x3f)==6) // BLEZ
6537 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6539 if(s1h>=0) emit_mov(addr,ntaddr);
6540 emit_cmovl_reg(alt,addr);
6543 emit_cmovne_reg(ntaddr,addr);
6544 emit_cmovs_reg(alt,addr);
6547 if((opcode[i]&0x3f)==7) // BGTZ
6549 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6551 if(s1h>=0) emit_mov(addr,alt);
6552 emit_cmovl_reg(ntaddr,addr);
6555 emit_cmovne_reg(alt,addr);
6556 emit_cmovs_reg(ntaddr,addr);
6559 if((opcode[i]&0x3f)==0x16) // BLEZL
6561 assert((opcode[i]&0x3f)!=0x16);
6563 if((opcode[i]&0x3f)==0x17) // BGTZL
6565 assert((opcode[i]&0x3f)!=0x17);
6567 assert(opcode[i]!=1); // BLTZ/BGEZ
6569 //FIXME: Check CSREG
6570 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6571 if((source[i]&0x30000)==0) // BC1F
6573 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6574 emit_testimm(s1l,0x800000);
6575 emit_cmovne_reg(alt,addr);
6577 if((source[i]&0x30000)==0x10000) // BC1T
6579 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6580 emit_testimm(s1l,0x800000);
6581 emit_cmovne_reg(alt,addr);
6583 if((source[i]&0x30000)==0x20000) // BC1FL
6585 emit_testimm(s1l,0x800000);
6589 if((source[i]&0x30000)==0x30000) // BC1TL
6591 emit_testimm(s1l,0x800000);
6597 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6598 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6599 if(likely[i]||unconditional)
6601 emit_movimm(ba[i],HOST_BTREG);
6603 else if(addr!=HOST_BTREG)
6605 emit_mov(addr,HOST_BTREG);
6607 void *branch_addr=out;
6609 int target_addr=start+i*4+5;
6611 void *compiled_target_addr=check_addr(target_addr);
6612 emit_extjump_ds((int)branch_addr,target_addr);
6613 if(compiled_target_addr) {
6614 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6615 add_link(target_addr,stub);
6617 else set_jump_target((int)branch_addr,(int)stub);
6620 set_jump_target((int)nottaken,(int)out);
6621 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6622 void *branch_addr=out;
6624 int target_addr=start+i*4+8;
6626 void *compiled_target_addr=check_addr(target_addr);
6627 emit_extjump_ds((int)branch_addr,target_addr);
6628 if(compiled_target_addr) {
6629 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6630 add_link(target_addr,stub);
6632 else set_jump_target((int)branch_addr,(int)stub);
6636 // Assemble the delay slot for the above
6637 static void pagespan_ds()
6639 assem_debug("initial delay slot:\n");
6640 u_int vaddr=start+1;
6641 u_int page=get_page(vaddr);
6642 u_int vpage=get_vpage(vaddr);
6643 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6645 ll_add(jump_in+page,vaddr,(void *)out);
6646 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6647 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6648 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6649 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6650 emit_writeword(HOST_BTREG,(int)&branch_target);
6651 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6652 address_generation(0,®s[0],regs[0].regmap_entry);
6653 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6654 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6659 alu_assemble(0,®s[0]);break;
6661 imm16_assemble(0,®s[0]);break;
6663 shift_assemble(0,®s[0]);break;
6665 shiftimm_assemble(0,®s[0]);break;
6667 load_assemble(0,®s[0]);break;
6669 loadlr_assemble(0,®s[0]);break;
6671 store_assemble(0,®s[0]);break;
6673 storelr_assemble(0,®s[0]);break;
6675 cop0_assemble(0,®s[0]);break;
6677 cop1_assemble(0,®s[0]);break;
6679 c1ls_assemble(0,®s[0]);break;
6681 cop2_assemble(0,®s[0]);break;
6683 c2ls_assemble(0,®s[0]);break;
6685 c2op_assemble(0,®s[0]);break;
6687 fconv_assemble(0,®s[0]);break;
6689 float_assemble(0,®s[0]);break;
6691 fcomp_assemble(0,®s[0]);break;
6693 multdiv_assemble(0,®s[0]);break;
6695 mov_assemble(0,®s[0]);break;
6705 printf("Jump in the delay slot. This is probably a bug.\n");
6707 int btaddr=get_reg(regs[0].regmap,BTREG);
6709 btaddr=get_reg(regs[0].regmap,-1);
6710 emit_readword((int)&branch_target,btaddr);
6712 assert(btaddr!=HOST_CCREG);
6713 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6715 emit_movimm(start+4,HOST_TEMPREG);
6716 emit_cmp(btaddr,HOST_TEMPREG);
6718 emit_cmpimm(btaddr,start+4);
6720 int branch=(int)out;
6722 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6723 emit_jmp(jump_vaddr_reg[btaddr]);
6724 set_jump_target(branch,(int)out);
6725 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6726 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6729 // Basic liveness analysis for MIPS registers
6730 void unneeded_registers(int istart,int iend,int r)
6733 uint64_t u,uu,gte_u,b,bu,gte_bu;
6734 uint64_t temp_u,temp_uu,temp_gte_u;
6739 u=unneeded_reg[iend+1];
6740 uu=unneeded_reg_upper[iend+1];
6745 for (i=iend;i>=istart;i--)
6747 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6748 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6750 // If subroutine call, flag return address as a possible branch target
6751 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6753 if(ba[i]<start || ba[i]>=(start+slen*4))
6755 // Branch out of this block, flush all regs
6760 if(itype[i]==UJUMP&&rt1[i]==31)
6762 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6764 if(itype[i]==RJUMP&&rs1[i]==31)
6766 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6768 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6769 if(itype[i]==UJUMP&&rt1[i]==31)
6771 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6772 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6774 if(itype[i]==RJUMP&&rs1[i]==31)
6776 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6777 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6780 branch_unneeded_reg[i]=u;
6781 branch_unneeded_reg_upper[i]=uu;
6782 // Merge in delay slot
6783 tdep=(~uu>>rt1[i+1])&1;
6784 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6785 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6786 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6787 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6788 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6791 gte_u&=~gte_rs[i+1];
6792 // If branch is "likely" (and conditional)
6793 // then we skip the delay slot on the fall-thru path
6796 u&=unneeded_reg[i+2];
6797 uu&=unneeded_reg_upper[i+2];
6798 gte_u&=gte_unneeded[i+2];
6810 // Internal branch, flag target
6811 bt[(ba[i]-start)>>2]=1;
6812 if(ba[i]<=start+i*4) {
6814 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6816 // Unconditional branch
6820 // Conditional branch (not taken case)
6821 temp_u=unneeded_reg[i+2];
6822 temp_uu=unneeded_reg_upper[i+2];
6823 temp_gte_u&=gte_unneeded[i+2];
6825 // Merge in delay slot
6826 tdep=(~temp_uu>>rt1[i+1])&1;
6827 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6828 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6829 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6830 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6831 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6832 temp_u|=1;temp_uu|=1;
6833 temp_gte_u|=gte_rt[i+1];
6834 temp_gte_u&=~gte_rs[i+1];
6835 // If branch is "likely" (and conditional)
6836 // then we skip the delay slot on the fall-thru path
6839 temp_u&=unneeded_reg[i+2];
6840 temp_uu&=unneeded_reg_upper[i+2];
6841 temp_gte_u&=gte_unneeded[i+2];
6850 tdep=(~temp_uu>>rt1[i])&1;
6851 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6852 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6853 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6854 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6855 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6856 temp_u|=1;temp_uu|=1;
6857 temp_gte_u|=gte_rt[i];
6858 temp_gte_u&=~gte_rs[i];
6859 unneeded_reg[i]=temp_u;
6860 unneeded_reg_upper[i]=temp_uu;
6861 gte_unneeded[i]=temp_gte_u;
6862 // Only go three levels deep. This recursion can take an
6863 // excessive amount of time if there are a lot of nested loops.
6865 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6867 unneeded_reg[(ba[i]-start)>>2]=1;
6868 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6869 gte_unneeded[(ba[i]-start)>>2]=0;
6872 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6874 // Unconditional branch
6875 u=unneeded_reg[(ba[i]-start)>>2];
6876 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6877 gte_u=gte_unneeded[(ba[i]-start)>>2];
6878 branch_unneeded_reg[i]=u;
6879 branch_unneeded_reg_upper[i]=uu;
6882 //branch_unneeded_reg[i]=u;
6883 //branch_unneeded_reg_upper[i]=uu;
6884 // Merge in delay slot
6885 tdep=(~uu>>rt1[i+1])&1;
6886 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6887 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6888 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6889 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6890 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6893 gte_u&=~gte_rs[i+1];
6895 // Conditional branch
6896 b=unneeded_reg[(ba[i]-start)>>2];
6897 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6898 gte_bu=gte_unneeded[(ba[i]-start)>>2];
6899 branch_unneeded_reg[i]=b;
6900 branch_unneeded_reg_upper[i]=bu;
6903 //branch_unneeded_reg[i]=b;
6904 //branch_unneeded_reg_upper[i]=bu;
6905 // Branch delay slot
6906 tdep=(~uu>>rt1[i+1])&1;
6907 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6908 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6909 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6910 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6911 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6913 gte_bu|=gte_rt[i+1];
6914 gte_bu&=~gte_rs[i+1];
6915 // If branch is "likely" then we skip the
6916 // delay slot on the fall-thru path
6922 u&=unneeded_reg[i+2];
6923 uu&=unneeded_reg_upper[i+2];
6924 gte_u&=gte_unneeded[i+2];
6936 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6937 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6938 //branch_unneeded_reg[i]=1;
6939 //branch_unneeded_reg_upper[i]=1;
6941 branch_unneeded_reg[i]=1;
6942 branch_unneeded_reg_upper[i]=1;
6948 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6950 // SYSCALL instruction (software interrupt)
6954 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6956 // ERET instruction (return from interrupt)
6961 tdep=(~uu>>rt1[i])&1;
6962 // Written registers are unneeded
6968 // Accessed registers are needed
6974 // Source-target dependencies
6975 uu&=~(tdep<<dep1[i]);
6976 uu&=~(tdep<<dep2[i]);
6977 // R0 is always unneeded
6981 unneeded_reg_upper[i]=uu;
6982 gte_unneeded[i]=gte_u;
6984 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6987 for(r=1;r<=CCREG;r++) {
6988 if((unneeded_reg[i]>>r)&1) {
6989 if(r==HIREG) printf(" HI");
6990 else if(r==LOREG) printf(" LO");
6991 else printf(" r%d",r);
6995 for(r=1;r<=CCREG;r++) {
6996 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6997 if(r==HIREG) printf(" HI");
6998 else if(r==LOREG) printf(" LO");
6999 else printf(" r%d",r);
7005 for (i=iend;i>=istart;i--)
7007 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7012 // Identify registers which are likely to contain 32-bit values
7013 // This is used to predict whether any branches will jump to a
7014 // location with 64-bit values in registers.
7015 static void provisional_32bit()
7019 uint64_t lastbranch=1;
7024 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7025 if(i>1) is32=lastbranch;
7031 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7033 if(i>2) is32=lastbranch;
7037 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7039 if(rs1[i-2]==0||rs2[i-2]==0)
7042 is32|=1LL<<rs1[i-2];
7045 is32|=1LL<<rs2[i-2];
7050 // If something jumps here with 64-bit values
7051 // then promote those registers to 64 bits
7054 uint64_t temp_is32=is32;
7057 if(ba[j]==start+i*4)
7058 //temp_is32&=branch_regs[j].is32;
7063 if(ba[j]==start+i*4)
7074 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7075 // Branches don't write registers, consider the delay slot instead.
7086 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7087 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7096 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7097 if(op==0x22) is32|=1LL<<rt; // LWL
7100 if (op==0x08||op==0x09|| // ADDI/ADDIU
7101 op==0x0a||op==0x0b|| // SLTI/SLTIU
7107 if(op==0x18||op==0x19) { // DADDI/DADDIU
7110 // is32|=((is32>>s1)&1LL)<<rt;
7112 if(op==0x0d||op==0x0e) { // ORI/XORI
7113 uint64_t sr=((is32>>s1)&1LL);
7129 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7132 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7135 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7136 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7140 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7145 uint64_t sr=((is32>>s1)&1LL);
7150 uint64_t sr=((is32>>s2)&1LL);
7158 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7163 uint64_t sr=((is32>>s1)&1LL);
7173 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7174 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7177 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7182 uint64_t sr=((is32>>s1)&1LL);
7188 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7189 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7193 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7194 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7197 if(op2==0) is32|=1LL<<rt; // MFC0
7201 if(op2==0) is32|=1LL<<rt; // MFC1
7202 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7203 if(op2==2) is32|=1LL<<rt; // CFC1
7225 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7227 if(rt1[i-1]==31) // JAL/JALR
7229 // Subroutine call will return here, don't alloc any registers
7234 // Internal branch will jump here, match registers to caller
7242 // Identify registers which may be assumed to contain 32-bit values
7243 // and where optimizations will rely on this.
7244 // This is used to determine whether backward branches can safely
7245 // jump to a location with 64-bit values in registers.
7246 static void provisional_r32()
7251 for (i=slen-1;i>=0;i--)
7254 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7256 if(ba[i]<start || ba[i]>=(start+slen*4))
7258 // Branch out of this block, don't need anything
7264 // Need whatever matches the target
7265 // (and doesn't get overwritten by the delay slot instruction)
7267 int t=(ba[i]-start)>>2;
7268 if(ba[i]>start+i*4) {
7270 //if(!(requires_32bit[t]&~regs[i].was32))
7271 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7272 if(!(pr32[t]&~regs[i].was32))
7273 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7276 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7277 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7280 // Conditional branch may need registers for following instructions
7281 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7284 //r32|=requires_32bit[i+2];
7287 // Mark this address as a branch target since it may be called
7288 // upon return from interrupt
7292 // Merge in delay slot
7294 // These are overwritten unless the branch is "likely"
7295 // and the delay slot is nullified if not taken
7296 r32&=~(1LL<<rt1[i+1]);
7297 r32&=~(1LL<<rt2[i+1]);
7299 // Assume these are needed (delay slot)
7302 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7306 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7308 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7310 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7312 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7314 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7317 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7319 // SYSCALL instruction (software interrupt)
7322 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7324 // ERET instruction (return from interrupt)
7328 r32&=~(1LL<<rt1[i]);
7329 r32&=~(1LL<<rt2[i]);
7332 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7336 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7338 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7340 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7342 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7344 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7346 //requires_32bit[i]=r32;
7349 // Dirty registers which are 32-bit, require 32-bit input
7350 // as they will be written as 32-bit values
7351 for(hr=0;hr<HOST_REGS;hr++)
7353 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7354 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7355 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7356 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7357 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7364 // Write back dirty registers as soon as we will no longer modify them,
7365 // so that we don't end up with lots of writes at the branches.
7366 void clean_registers(int istart,int iend,int wr)
7370 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7371 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7373 will_dirty_i=will_dirty_next=0;
7374 wont_dirty_i=wont_dirty_next=0;
7376 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7377 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7379 for (i=iend;i>=istart;i--)
7381 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7383 if(ba[i]<start || ba[i]>=(start+slen*4))
7385 // Branch out of this block, flush all regs
7386 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7388 // Unconditional branch
7391 // Merge in delay slot (will dirty)
7392 for(r=0;r<HOST_REGS;r++) {
7393 if(r!=EXCLUDE_REG) {
7394 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7395 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7396 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7397 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7398 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7399 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7400 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7401 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7402 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7403 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7404 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7405 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7406 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7407 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7413 // Conditional branch
7415 wont_dirty_i=wont_dirty_next;
7416 // Merge in delay slot (will dirty)
7417 for(r=0;r<HOST_REGS;r++) {
7418 if(r!=EXCLUDE_REG) {
7420 // Might not dirty if likely branch is not taken
7421 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7422 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7423 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7424 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7425 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7426 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7427 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7428 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7429 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7430 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7431 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7432 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7433 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7434 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7439 // Merge in delay slot (wont dirty)
7440 for(r=0;r<HOST_REGS;r++) {
7441 if(r!=EXCLUDE_REG) {
7442 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7443 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7444 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7445 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7446 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7447 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7448 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7449 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7450 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7451 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7455 #ifndef DESTRUCTIVE_WRITEBACK
7456 branch_regs[i].dirty&=wont_dirty_i;
7458 branch_regs[i].dirty|=will_dirty_i;
7464 if(ba[i]<=start+i*4) {
7466 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7468 // Unconditional branch
7471 // Merge in delay slot (will dirty)
7472 for(r=0;r<HOST_REGS;r++) {
7473 if(r!=EXCLUDE_REG) {
7474 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7475 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7476 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7477 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7478 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7479 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7480 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7481 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7482 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7483 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7484 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7485 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7486 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7487 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7491 // Conditional branch (not taken case)
7492 temp_will_dirty=will_dirty_next;
7493 temp_wont_dirty=wont_dirty_next;
7494 // Merge in delay slot (will dirty)
7495 for(r=0;r<HOST_REGS;r++) {
7496 if(r!=EXCLUDE_REG) {
7498 // Will not dirty if likely branch is not taken
7499 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7500 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7501 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7502 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7503 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7504 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7505 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7506 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7507 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7508 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7509 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7510 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7511 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7512 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7517 // Merge in delay slot (wont dirty)
7518 for(r=0;r<HOST_REGS;r++) {
7519 if(r!=EXCLUDE_REG) {
7520 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7521 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7522 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7523 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7524 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7525 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7526 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7527 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7528 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7529 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7532 // Deal with changed mappings
7534 for(r=0;r<HOST_REGS;r++) {
7535 if(r!=EXCLUDE_REG) {
7536 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7537 temp_will_dirty&=~(1<<r);
7538 temp_wont_dirty&=~(1<<r);
7539 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7540 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7541 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7543 temp_will_dirty|=1<<r;
7544 temp_wont_dirty|=1<<r;
7551 will_dirty[i]=temp_will_dirty;
7552 wont_dirty[i]=temp_wont_dirty;
7553 clean_registers((ba[i]-start)>>2,i-1,0);
7555 // Limit recursion. It can take an excessive amount
7556 // of time if there are a lot of nested loops.
7557 will_dirty[(ba[i]-start)>>2]=0;
7558 wont_dirty[(ba[i]-start)>>2]=-1;
7563 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7565 // Unconditional branch
7568 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7569 for(r=0;r<HOST_REGS;r++) {
7570 if(r!=EXCLUDE_REG) {
7571 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7572 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7573 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7575 if(branch_regs[i].regmap[r]>=0) {
7576 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7577 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7582 // Merge in delay slot
7583 for(r=0;r<HOST_REGS;r++) {
7584 if(r!=EXCLUDE_REG) {
7585 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7586 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7587 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7588 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7589 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7590 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7591 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7592 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7593 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7594 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7595 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7596 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7597 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7598 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7602 // Conditional branch
7603 will_dirty_i=will_dirty_next;
7604 wont_dirty_i=wont_dirty_next;
7605 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7606 for(r=0;r<HOST_REGS;r++) {
7607 if(r!=EXCLUDE_REG) {
7608 signed char target_reg=branch_regs[i].regmap[r];
7609 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7610 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7611 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7613 else if(target_reg>=0) {
7614 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7615 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7617 // Treat delay slot as part of branch too
7618 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7619 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7620 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7624 will_dirty[i+1]&=~(1<<r);
7629 // Merge in delay slot
7630 for(r=0;r<HOST_REGS;r++) {
7631 if(r!=EXCLUDE_REG) {
7633 // Might not dirty if likely branch is not taken
7634 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7635 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7636 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7637 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7638 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7639 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7640 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7641 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7642 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7643 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7644 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7645 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7646 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7647 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7652 // Merge in delay slot (won't dirty)
7653 for(r=0;r<HOST_REGS;r++) {
7654 if(r!=EXCLUDE_REG) {
7655 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7656 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7657 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7658 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7659 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7660 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7661 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7662 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7663 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7664 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7668 #ifndef DESTRUCTIVE_WRITEBACK
7669 branch_regs[i].dirty&=wont_dirty_i;
7671 branch_regs[i].dirty|=will_dirty_i;
7676 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7678 // SYSCALL instruction (software interrupt)
7682 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7684 // ERET instruction (return from interrupt)
7688 will_dirty_next=will_dirty_i;
7689 wont_dirty_next=wont_dirty_i;
7690 for(r=0;r<HOST_REGS;r++) {
7691 if(r!=EXCLUDE_REG) {
7692 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7693 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7694 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7695 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7696 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7697 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7698 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7699 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7701 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7703 // Don't store a register immediately after writing it,
7704 // may prevent dual-issue.
7705 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7706 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7712 will_dirty[i]=will_dirty_i;
7713 wont_dirty[i]=wont_dirty_i;
7714 // Mark registers that won't be dirtied as not dirty
7716 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7717 for(r=0;r<HOST_REGS;r++) {
7718 if((will_dirty_i>>r)&1) {
7724 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7725 regs[i].dirty|=will_dirty_i;
7726 #ifndef DESTRUCTIVE_WRITEBACK
7727 regs[i].dirty&=wont_dirty_i;
7728 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7730 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7731 for(r=0;r<HOST_REGS;r++) {
7732 if(r!=EXCLUDE_REG) {
7733 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7734 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7735 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7743 for(r=0;r<HOST_REGS;r++) {
7744 if(r!=EXCLUDE_REG) {
7745 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7746 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7747 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7755 // Deal with changed mappings
7756 temp_will_dirty=will_dirty_i;
7757 temp_wont_dirty=wont_dirty_i;
7758 for(r=0;r<HOST_REGS;r++) {
7759 if(r!=EXCLUDE_REG) {
7761 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7763 #ifndef DESTRUCTIVE_WRITEBACK
7764 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7766 regs[i].wasdirty|=will_dirty_i&(1<<r);
7769 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7770 // Register moved to a different register
7771 will_dirty_i&=~(1<<r);
7772 wont_dirty_i&=~(1<<r);
7773 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7774 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7776 #ifndef DESTRUCTIVE_WRITEBACK
7777 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7779 regs[i].wasdirty|=will_dirty_i&(1<<r);
7783 will_dirty_i&=~(1<<r);
7784 wont_dirty_i&=~(1<<r);
7785 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7786 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7787 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7790 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7800 void disassemble_inst(int i)
7802 if (bt[i]) printf("*"); else printf(" ");
7805 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7807 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7809 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7811 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7813 if (opcode[i]==0x9&&rt1[i]!=31)
7814 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7816 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7819 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7821 if(opcode[i]==0xf) //LUI
7822 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7824 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7828 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7832 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7836 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7839 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7842 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7845 if((opcode2[i]&0x1d)==0x10)
7846 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7847 else if((opcode2[i]&0x1d)==0x11)
7848 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7850 printf (" %x: %s\n",start+i*4,insn[i]);
7854 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7855 else if(opcode2[i]==4)
7856 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7857 else printf (" %x: %s\n",start+i*4,insn[i]);
7861 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7862 else if(opcode2[i]>3)
7863 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7864 else printf (" %x: %s\n",start+i*4,insn[i]);
7868 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7869 else if(opcode2[i]>3)
7870 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7871 else printf (" %x: %s\n",start+i*4,insn[i]);
7874 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7877 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7880 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7883 //printf (" %s %8x\n",insn[i],source[i]);
7884 printf (" %x: %s\n",start+i*4,insn[i]);
7888 static void disassemble_inst(int i) {}
7891 // clear the state completely, instead of just marking
7892 // things invalid like invalidate_all_pages() does
7893 void new_dynarec_clear_full()
7896 out=(u_char *)BASE_ADDR;
7897 memset(invalid_code,1,sizeof(invalid_code));
7898 memset(hash_table,0xff,sizeof(hash_table));
7899 memset(mini_ht,-1,sizeof(mini_ht));
7900 memset(restore_candidate,0,sizeof(restore_candidate));
7901 memset(shadow,0,sizeof(shadow));
7903 expirep=16384; // Expiry pointer, +2 blocks
7904 pending_exception=0;
7907 inv_code_start=inv_code_end=~0;
7912 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7914 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7915 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7916 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7919 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7920 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7921 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7924 void new_dynarec_init()
7926 printf("Init new dynarec\n");
7927 out=(u_char *)BASE_ADDR;
7928 if (mmap (out, 1<<TARGET_SIZE_2,
7929 PROT_READ | PROT_WRITE | PROT_EXEC,
7930 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7931 -1, 0) <= 0) {printf("mmap() failed\n");}
7933 rdword=&readmem_dword;
7934 fake_pc.f.r.rs=&readmem_dword;
7935 fake_pc.f.r.rt=&readmem_dword;
7936 fake_pc.f.r.rd=&readmem_dword;
7939 cycle_multiplier=200;
7940 new_dynarec_clear_full();
7942 // Copy this into local area so we don't have to put it in every literal pool
7943 invc_ptr=invalid_code;
7946 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7947 writemem[n] = write_nomem_new;
7948 writememb[n] = write_nomemb_new;
7949 writememh[n] = write_nomemh_new;
7951 writememd[n] = write_nomemd_new;
7953 readmem[n] = read_nomem_new;
7954 readmemb[n] = read_nomemb_new;
7955 readmemh[n] = read_nomemh_new;
7957 readmemd[n] = read_nomemd_new;
7960 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7961 writemem[n] = write_rdram_new;
7962 writememb[n] = write_rdramb_new;
7963 writememh[n] = write_rdramh_new;
7965 writememd[n] = write_rdramd_new;
7968 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7969 writemem[n] = write_nomem_new;
7970 writememb[n] = write_nomemb_new;
7971 writememh[n] = write_nomemh_new;
7973 writememd[n] = write_nomemd_new;
7975 readmem[n] = read_nomem_new;
7976 readmemb[n] = read_nomemb_new;
7977 readmemh[n] = read_nomemh_new;
7979 readmemd[n] = read_nomemd_new;
7987 void new_dynarec_cleanup()
7990 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7991 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7992 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7993 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7995 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7999 int new_recompile_block(int addr)
8002 if(addr==0x800cd050) {
8004 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
8006 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8009 //if(Count==365117028) tracedebug=1;
8010 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8011 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8012 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8014 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8015 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8016 /*if(Count>=312978186) {
8020 start = (u_int)addr&~3;
8021 //assert(((u_int)addr&1)==0);
8022 new_dynarec_did_compile=1;
8024 if (Config.HLE && start == 0x80001000) // hlecall
8026 // XXX: is this enough? Maybe check hleSoftCall?
8027 u_int beginning=(u_int)out;
8028 u_int page=get_page(start);
8029 invalid_code[start>>12]=0;
8030 emit_movimm(start,0);
8031 emit_writeword(0,(int)&pcaddr);
8032 emit_jmp((int)new_dyna_leave);
8035 __clear_cache((void *)beginning,out);
8037 ll_add(jump_in+page,start,(void *)beginning);
8040 else if ((u_int)addr < 0x00200000 ||
8041 (0xa0000000 <= addr && addr < 0xa0200000)) {
8042 // used for BIOS calls mostly?
8043 source = (u_int *)((u_int)rdram+(start&0x1fffff));
8044 pagelimit = (addr&0xa0000000)|0x00200000;
8046 else if (!Config.HLE && (
8047 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8048 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8050 source = (u_int *)((u_int)psxR+(start&0x7ffff));
8051 pagelimit = (addr&0xfff00000)|0x80000;
8056 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8057 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8058 pagelimit = 0xa4001000;
8062 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8063 source = (u_int *)((u_int)rdram+start-0x80000000);
8064 pagelimit = 0x80000000+RAM_SIZE;
8067 else if ((signed int)addr >= (signed int)0xC0000000) {
8068 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8069 //if(tlb_LUT_r[start>>12])
8070 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8071 if((signed int)memory_map[start>>12]>=0) {
8072 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8073 pagelimit=(start+4096)&0xFFFFF000;
8074 int map=memory_map[start>>12];
8077 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8078 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8080 assem_debug("pagelimit=%x\n",pagelimit);
8081 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8084 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8085 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8086 return -1; // Caller will invoke exception handler
8088 //printf("source= %x\n",(int)source);
8092 printf("Compile at bogus memory address: %x \n", (int)addr);
8096 /* Pass 1: disassemble */
8097 /* Pass 2: register dependencies, branch targets */
8098 /* Pass 3: register allocation */
8099 /* Pass 4: branch dependencies */
8100 /* Pass 5: pre-alloc */
8101 /* Pass 6: optimize clean/dirty state */
8102 /* Pass 7: flag 32-bit registers */
8103 /* Pass 8: assembly */
8104 /* Pass 9: linker */
8105 /* Pass 10: garbage collection / free memory */
8109 unsigned int type,op,op2;
8111 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8113 /* Pass 1 disassembly */
8115 for(i=0;!done;i++) {
8116 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8117 minimum_free_regs[i]=0;
8118 opcode[i]=op=source[i]>>26;
8121 case 0x00: strcpy(insn[i],"special"); type=NI;
8125 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8126 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8127 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8128 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8129 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8130 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8131 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8132 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8133 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8134 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8135 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8136 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8137 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8138 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8139 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8140 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8141 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8142 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8143 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8144 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8145 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8146 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8147 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8148 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8149 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8150 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8151 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8152 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8153 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8154 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8155 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8156 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8157 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8158 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8159 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8161 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8162 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8163 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8164 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8165 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8166 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8167 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8168 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8169 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8170 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8171 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8172 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8173 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8174 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8175 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8176 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8177 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8181 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8182 op2=(source[i]>>16)&0x1f;
8185 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8186 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8187 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8188 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8189 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8190 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8191 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8192 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8193 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8194 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8195 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8196 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8197 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8198 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8201 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8202 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8203 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8204 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8205 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8206 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8207 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8208 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8209 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8210 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8211 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8212 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8213 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8214 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8215 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8216 op2=(source[i]>>21)&0x1f;
8219 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8220 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8221 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8222 switch(source[i]&0x3f)
8224 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8225 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8226 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8227 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8229 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8231 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8236 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8237 op2=(source[i]>>21)&0x1f;
8240 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8241 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8242 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8243 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8244 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8245 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8246 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8247 switch((source[i]>>16)&0x3)
8249 case 0x00: strcpy(insn[i],"BC1F"); break;
8250 case 0x01: strcpy(insn[i],"BC1T"); break;
8251 case 0x02: strcpy(insn[i],"BC1FL"); break;
8252 case 0x03: strcpy(insn[i],"BC1TL"); break;
8255 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8256 switch(source[i]&0x3f)
8258 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8259 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8260 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8261 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8262 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8263 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8264 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8265 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8266 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8267 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8268 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8269 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8270 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8271 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8272 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8273 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8274 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8275 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8276 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8277 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8278 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8279 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8280 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8281 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8282 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8283 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8284 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8285 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8286 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8287 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8288 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8289 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8290 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8291 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8292 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8295 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8296 switch(source[i]&0x3f)
8298 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8299 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8300 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8301 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8302 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8303 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8304 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8305 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8306 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8307 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8308 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8309 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8310 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8311 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8312 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8313 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8314 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8315 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8316 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8317 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8318 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8319 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8320 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8321 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8322 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8323 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8324 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8325 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8326 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8327 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8328 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8329 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8330 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8331 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8332 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8335 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8336 switch(source[i]&0x3f)
8338 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8339 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8342 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8343 switch(source[i]&0x3f)
8345 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8346 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8352 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8353 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8354 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8355 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8356 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8357 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8358 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8359 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8361 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8362 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8363 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8364 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8365 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8366 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8367 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8369 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8371 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8372 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8373 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8374 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8376 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8377 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8379 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8380 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8381 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8382 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8384 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8385 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8386 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8388 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8389 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8391 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8392 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8393 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8396 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8397 op2=(source[i]>>21)&0x1f;
8399 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8400 if (gte_handlers[source[i]&0x3f]!=NULL) {
8401 if (gte_regnames[source[i]&0x3f]!=NULL)
8402 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8404 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8410 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8411 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8412 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8413 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8416 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8417 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8418 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8420 default: strcpy(insn[i],"???"); type=NI;
8421 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8426 /* Get registers/immediates */
8432 gte_rs[i]=gte_rt[i]=0;
8435 rs1[i]=(source[i]>>21)&0x1f;
8437 rt1[i]=(source[i]>>16)&0x1f;
8439 imm[i]=(short)source[i];
8443 rs1[i]=(source[i]>>21)&0x1f;
8444 rs2[i]=(source[i]>>16)&0x1f;
8447 imm[i]=(short)source[i];
8448 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8451 // LWL/LWR only load part of the register,
8452 // therefore the target register must be treated as a source too
8453 rs1[i]=(source[i]>>21)&0x1f;
8454 rs2[i]=(source[i]>>16)&0x1f;
8455 rt1[i]=(source[i]>>16)&0x1f;
8457 imm[i]=(short)source[i];
8458 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8459 if(op==0x26) dep1[i]=rt1[i]; // LWR
8462 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8463 else rs1[i]=(source[i]>>21)&0x1f;
8465 rt1[i]=(source[i]>>16)&0x1f;
8467 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8468 imm[i]=(unsigned short)source[i];
8470 imm[i]=(short)source[i];
8472 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8473 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8474 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8481 // The JAL instruction writes to r31.
8488 rs1[i]=(source[i]>>21)&0x1f;
8492 // The JALR instruction writes to rd.
8494 rt1[i]=(source[i]>>11)&0x1f;
8499 rs1[i]=(source[i]>>21)&0x1f;
8500 rs2[i]=(source[i]>>16)&0x1f;
8503 if(op&2) { // BGTZ/BLEZ
8511 rs1[i]=(source[i]>>21)&0x1f;
8516 if(op2&0x10) { // BxxAL
8518 // NOTE: If the branch is not taken, r31 is still overwritten
8520 likely[i]=(op2&2)>>1;
8527 likely[i]=((source[i])>>17)&1;
8530 rs1[i]=(source[i]>>21)&0x1f; // source
8531 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8532 rt1[i]=(source[i]>>11)&0x1f; // destination
8534 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8535 us1[i]=rs1[i];us2[i]=rs2[i];
8537 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8538 dep1[i]=rs1[i];dep2[i]=rs2[i];
8540 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8541 dep1[i]=rs1[i];dep2[i]=rs2[i];
8545 rs1[i]=(source[i]>>21)&0x1f; // source
8546 rs2[i]=(source[i]>>16)&0x1f; // divisor
8549 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8550 us1[i]=rs1[i];us2[i]=rs2[i];
8558 if(op2==0x10) rs1[i]=HIREG; // MFHI
8559 if(op2==0x11) rt1[i]=HIREG; // MTHI
8560 if(op2==0x12) rs1[i]=LOREG; // MFLO
8561 if(op2==0x13) rt1[i]=LOREG; // MTLO
8562 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8563 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8567 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8568 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8569 rt1[i]=(source[i]>>11)&0x1f; // destination
8571 // DSLLV/DSRLV/DSRAV are 64-bit
8572 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8575 rs1[i]=(source[i]>>16)&0x1f;
8577 rt1[i]=(source[i]>>11)&0x1f;
8579 imm[i]=(source[i]>>6)&0x1f;
8580 // DSxx32 instructions
8581 if(op2>=0x3c) imm[i]|=0x20;
8582 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8583 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8590 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8591 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8592 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8593 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8600 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8601 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8602 if(op2==5) us1[i]=rs1[i]; // DMTC1
8610 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8611 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8613 int gr=(source[i]>>11)&0x1F;
8616 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8617 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8618 case 0x02: gte_rs[i]=1ll<<(gr+32); // CFC2
8619 if(gr==31&&!gte_reads_flags) {
8620 assem_debug("gte flag read encountered @%08x\n",addr + i*4);
8624 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8628 rs1[i]=(source[i]>>21)&0x1F;
8632 imm[i]=(short)source[i];
8635 rs1[i]=(source[i]>>21)&0x1F;
8639 imm[i]=(short)source[i];
8640 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8641 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8648 gte_rt[i]=1ll<<63; // every op changes flags
8649 // TODO: other regs?
8678 /* Calculate branch target addresses */
8680 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8681 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8682 ba[i]=start+i*4+8; // Ignore never taken branch
8683 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8684 ba[i]=start+i*4+8; // Ignore never taken branch
8685 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8686 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8689 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8691 // branch in delay slot?
8692 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8693 // don't handle first branch and call interpreter if it's hit
8694 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8697 // basic load delay detection
8698 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8699 int t=(ba[i-1]-start)/4;
8700 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8701 // jump target wants DS result - potential load delay effect
8702 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8704 bt[t+1]=1; // expected return from interpreter
8706 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8707 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8708 // v0 overwrite like this is a sign of trouble, bail out
8709 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8715 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8719 i--; // don't compile the DS
8723 /* Is this the end of the block? */
8724 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8725 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8729 if(stop_after_jal) done=1;
8731 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8733 // Don't recompile stuff that's already compiled
8734 if(check_addr(start+i*4+4)) done=1;
8735 // Don't get too close to the limit
8736 if(i>MAXBLOCK/2) done=1;
8738 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8739 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8741 // Does the block continue due to a branch?
8744 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8745 if(ba[j]==start+i*4+4) done=j=0;
8746 if(ba[j]==start+i*4+8) done=j=0;
8749 //assert(i<MAXBLOCK-1);
8750 if(start+i*4==pagelimit-4) done=1;
8751 assert(start+i*4<pagelimit);
8752 if (i==MAXBLOCK-1) done=1;
8753 // Stop if we're compiling junk
8754 if(itype[i]==NI&&opcode[i]==0x11) {
8755 done=stop_after_jal=1;
8756 printf("Disabled speculative precompilation\n");
8760 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8761 if(start+i*4==pagelimit) {
8767 /* Pass 2 - Register dependencies and branch targets */
8769 unneeded_registers(0,slen-1,0);
8771 /* Pass 3 - Register allocation */
8773 struct regstat current; // Current register allocations/status
8776 current.u=unneeded_reg[0];
8777 current.uu=unneeded_reg_upper[0];
8778 clear_all_regs(current.regmap);
8779 alloc_reg(¤t,0,CCREG);
8780 dirty_reg(¤t,CCREG);
8788 provisional_32bit();
8791 // First instruction is delay slot
8796 unneeded_reg_upper[0]=1;
8797 current.regmap[HOST_BTREG]=BTREG;
8805 for(hr=0;hr<HOST_REGS;hr++)
8807 // Is this really necessary?
8808 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8814 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8816 if(rs1[i-2]==0||rs2[i-2]==0)
8819 current.is32|=1LL<<rs1[i-2];
8820 int hr=get_reg(current.regmap,rs1[i-2]|64);
8821 if(hr>=0) current.regmap[hr]=-1;
8824 current.is32|=1LL<<rs2[i-2];
8825 int hr=get_reg(current.regmap,rs2[i-2]|64);
8826 if(hr>=0) current.regmap[hr]=-1;
8832 // If something jumps here with 64-bit values
8833 // then promote those registers to 64 bits
8836 uint64_t temp_is32=current.is32;
8839 if(ba[j]==start+i*4)
8840 temp_is32&=branch_regs[j].is32;
8844 if(ba[j]==start+i*4)
8848 if(temp_is32!=current.is32) {
8849 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8850 #ifndef DESTRUCTIVE_WRITEBACK
8853 for(hr=0;hr<HOST_REGS;hr++)
8855 int r=current.regmap[hr];
8858 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8860 //printf("restore %d\n",r);
8864 current.is32=temp_is32;
8871 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8872 regs[i].wasconst=current.isconst;
8873 regs[i].was32=current.is32;
8874 regs[i].wasdirty=current.dirty;
8875 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8876 // To change a dirty register from 32 to 64 bits, we must write
8877 // it out during the previous cycle (for branches, 2 cycles)
8878 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8880 uint64_t temp_is32=current.is32;
8883 if(ba[j]==start+i*4+4)
8884 temp_is32&=branch_regs[j].is32;
8888 if(ba[j]==start+i*4+4)
8892 if(temp_is32!=current.is32) {
8893 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8894 for(hr=0;hr<HOST_REGS;hr++)
8896 int r=current.regmap[hr];
8899 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8900 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8902 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8904 //printf("dump %d/r%d\n",hr,r);
8905 current.regmap[hr]=-1;
8906 if(get_reg(current.regmap,r|64)>=0)
8907 current.regmap[get_reg(current.regmap,r|64)]=-1;
8915 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8917 uint64_t temp_is32=current.is32;
8920 if(ba[j]==start+i*4+8)
8921 temp_is32&=branch_regs[j].is32;
8925 if(ba[j]==start+i*4+8)
8929 if(temp_is32!=current.is32) {
8930 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8931 for(hr=0;hr<HOST_REGS;hr++)
8933 int r=current.regmap[hr];
8936 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8937 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8939 //printf("dump %d/r%d\n",hr,r);
8940 current.regmap[hr]=-1;
8941 if(get_reg(current.regmap,r|64)>=0)
8942 current.regmap[get_reg(current.regmap,r|64)]=-1;
8950 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8952 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8953 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8954 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8963 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8964 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8965 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8966 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8967 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8970 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8974 ds=0; // Skip delay slot, already allocated as part of branch
8975 // ...but we need to alloc it in case something jumps here
8977 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8978 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8980 current.u=branch_unneeded_reg[i-1];
8981 current.uu=branch_unneeded_reg_upper[i-1];
8983 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8984 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8985 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8988 struct regstat temp;
8989 memcpy(&temp,¤t,sizeof(current));
8990 temp.wasdirty=temp.dirty;
8991 temp.was32=temp.is32;
8992 // TODO: Take into account unconditional branches, as below
8993 delayslot_alloc(&temp,i);
8994 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8995 regs[i].wasdirty=temp.wasdirty;
8996 regs[i].was32=temp.was32;
8997 regs[i].dirty=temp.dirty;
8998 regs[i].is32=temp.is32;
9002 // Create entry (branch target) regmap
9003 for(hr=0;hr<HOST_REGS;hr++)
9005 int r=temp.regmap[hr];
9007 if(r!=regmap_pre[i][hr]) {
9008 regs[i].regmap_entry[hr]=-1;
9013 if((current.u>>r)&1) {
9014 regs[i].regmap_entry[hr]=-1;
9015 regs[i].regmap[hr]=-1;
9016 //Don't clear regs in the delay slot as the branch might need them
9017 //current.regmap[hr]=-1;
9019 regs[i].regmap_entry[hr]=r;
9022 if((current.uu>>(r&63))&1) {
9023 regs[i].regmap_entry[hr]=-1;
9024 regs[i].regmap[hr]=-1;
9025 //Don't clear regs in the delay slot as the branch might need them
9026 //current.regmap[hr]=-1;
9028 regs[i].regmap_entry[hr]=r;
9032 // First instruction expects CCREG to be allocated
9033 if(i==0&&hr==HOST_CCREG)
9034 regs[i].regmap_entry[hr]=CCREG;
9036 regs[i].regmap_entry[hr]=-1;
9040 else { // Not delay slot
9043 //current.isconst=0; // DEBUG
9044 //current.wasconst=0; // DEBUG
9045 //regs[i].wasconst=0; // DEBUG
9046 clear_const(¤t,rt1[i]);
9047 alloc_cc(¤t,i);
9048 dirty_reg(¤t,CCREG);
9050 alloc_reg(¤t,i,31);
9051 dirty_reg(¤t,31);
9052 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9053 //assert(rt1[i+1]!=rt1[i]);
9055 alloc_reg(¤t,i,PTEMP);
9057 //current.is32|=1LL<<rt1[i];
9060 delayslot_alloc(¤t,i+1);
9061 //current.isconst=0; // DEBUG
9063 //printf("i=%d, isconst=%x\n",i,current.isconst);
9066 //current.isconst=0;
9067 //current.wasconst=0;
9068 //regs[i].wasconst=0;
9069 clear_const(¤t,rs1[i]);
9070 clear_const(¤t,rt1[i]);
9071 alloc_cc(¤t,i);
9072 dirty_reg(¤t,CCREG);
9073 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9074 alloc_reg(¤t,i,rs1[i]);
9076 alloc_reg(¤t,i,rt1[i]);
9077 dirty_reg(¤t,rt1[i]);
9078 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9079 assert(rt1[i+1]!=rt1[i]);
9081 alloc_reg(¤t,i,PTEMP);
9085 if(rs1[i]==31) { // JALR
9086 alloc_reg(¤t,i,RHASH);
9087 #ifndef HOST_IMM_ADDR32
9088 alloc_reg(¤t,i,RHTBL);
9092 delayslot_alloc(¤t,i+1);
9094 // The delay slot overwrites our source register,
9095 // allocate a temporary register to hold the old value.
9099 delayslot_alloc(¤t,i+1);
9101 alloc_reg(¤t,i,RTEMP);
9103 //current.isconst=0; // DEBUG
9108 //current.isconst=0;
9109 //current.wasconst=0;
9110 //regs[i].wasconst=0;
9111 clear_const(¤t,rs1[i]);
9112 clear_const(¤t,rs2[i]);
9113 if((opcode[i]&0x3E)==4) // BEQ/BNE
9115 alloc_cc(¤t,i);
9116 dirty_reg(¤t,CCREG);
9117 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9118 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9119 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9121 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9122 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9124 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9125 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9126 // The delay slot overwrites one of our conditions.
9127 // Allocate the branch condition registers instead.
9131 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9132 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9133 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9135 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9136 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9142 delayslot_alloc(¤t,i+1);
9146 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9148 alloc_cc(¤t,i);
9149 dirty_reg(¤t,CCREG);
9150 alloc_reg(¤t,i,rs1[i]);
9151 if(!(current.is32>>rs1[i]&1))
9153 alloc_reg64(¤t,i,rs1[i]);
9155 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9156 // The delay slot overwrites one of our conditions.
9157 // Allocate the branch condition registers instead.
9161 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9162 if(!((current.is32>>rs1[i])&1))
9164 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9170 delayslot_alloc(¤t,i+1);
9174 // Don't alloc the delay slot yet because we might not execute it
9175 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9180 alloc_cc(¤t,i);
9181 dirty_reg(¤t,CCREG);
9182 alloc_reg(¤t,i,rs1[i]);
9183 alloc_reg(¤t,i,rs2[i]);
9184 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9186 alloc_reg64(¤t,i,rs1[i]);
9187 alloc_reg64(¤t,i,rs2[i]);
9191 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9196 alloc_cc(¤t,i);
9197 dirty_reg(¤t,CCREG);
9198 alloc_reg(¤t,i,rs1[i]);
9199 if(!(current.is32>>rs1[i]&1))
9201 alloc_reg64(¤t,i,rs1[i]);
9205 //current.isconst=0;
9208 //current.isconst=0;
9209 //current.wasconst=0;
9210 //regs[i].wasconst=0;
9211 clear_const(¤t,rs1[i]);
9212 clear_const(¤t,rt1[i]);
9213 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9214 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9216 alloc_cc(¤t,i);
9217 dirty_reg(¤t,CCREG);
9218 alloc_reg(¤t,i,rs1[i]);
9219 if(!(current.is32>>rs1[i]&1))
9221 alloc_reg64(¤t,i,rs1[i]);
9223 if (rt1[i]==31) { // BLTZAL/BGEZAL
9224 alloc_reg(¤t,i,31);
9225 dirty_reg(¤t,31);
9226 //#ifdef REG_PREFETCH
9227 //alloc_reg(¤t,i,PTEMP);
9229 //current.is32|=1LL<<rt1[i];
9231 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9232 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9233 // Allocate the branch condition registers instead.
9237 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9238 if(!((current.is32>>rs1[i])&1))
9240 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9246 delayslot_alloc(¤t,i+1);
9250 // Don't alloc the delay slot yet because we might not execute it
9251 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9256 alloc_cc(¤t,i);
9257 dirty_reg(¤t,CCREG);
9258 alloc_reg(¤t,i,rs1[i]);
9259 if(!(current.is32>>rs1[i]&1))
9261 alloc_reg64(¤t,i,rs1[i]);
9265 //current.isconst=0;
9271 if(likely[i]==0) // BC1F/BC1T
9273 // TODO: Theoretically we can run out of registers here on x86.
9274 // The delay slot can allocate up to six, and we need to check
9275 // CSREG before executing the delay slot. Possibly we can drop
9276 // the cycle count and then reload it after checking that the
9277 // FPU is in a usable state, or don't do out-of-order execution.
9278 alloc_cc(¤t,i);
9279 dirty_reg(¤t,CCREG);
9280 alloc_reg(¤t,i,FSREG);
9281 alloc_reg(¤t,i,CSREG);
9282 if(itype[i+1]==FCOMP) {
9283 // The delay slot overwrites the branch condition.
9284 // Allocate the branch condition registers instead.
9285 alloc_cc(¤t,i);
9286 dirty_reg(¤t,CCREG);
9287 alloc_reg(¤t,i,CSREG);
9288 alloc_reg(¤t,i,FSREG);
9292 delayslot_alloc(¤t,i+1);
9293 alloc_reg(¤t,i+1,CSREG);
9297 // Don't alloc the delay slot yet because we might not execute it
9298 if(likely[i]) // BC1FL/BC1TL
9300 alloc_cc(¤t,i);
9301 dirty_reg(¤t,CCREG);
9302 alloc_reg(¤t,i,CSREG);
9303 alloc_reg(¤t,i,FSREG);
9309 imm16_alloc(¤t,i);
9313 load_alloc(¤t,i);
9317 store_alloc(¤t,i);
9320 alu_alloc(¤t,i);
9323 shift_alloc(¤t,i);
9326 multdiv_alloc(¤t,i);
9329 shiftimm_alloc(¤t,i);
9332 mov_alloc(¤t,i);
9335 cop0_alloc(¤t,i);
9339 cop1_alloc(¤t,i);
9342 c1ls_alloc(¤t,i);
9345 c2ls_alloc(¤t,i);
9348 c2op_alloc(¤t,i);
9351 fconv_alloc(¤t,i);
9354 float_alloc(¤t,i);
9357 fcomp_alloc(¤t,i);
9362 syscall_alloc(¤t,i);
9365 pagespan_alloc(¤t,i);
9369 // Drop the upper half of registers that have become 32-bit
9370 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9371 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9372 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9373 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9376 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9377 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9378 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9379 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9383 // Create entry (branch target) regmap
9384 for(hr=0;hr<HOST_REGS;hr++)
9387 r=current.regmap[hr];
9389 if(r!=regmap_pre[i][hr]) {
9390 // TODO: delay slot (?)
9391 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9392 if(or<0||(r&63)>=TEMPREG){
9393 regs[i].regmap_entry[hr]=-1;
9397 // Just move it to a different register
9398 regs[i].regmap_entry[hr]=r;
9399 // If it was dirty before, it's still dirty
9400 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9407 regs[i].regmap_entry[hr]=0;
9411 if((current.u>>r)&1) {
9412 regs[i].regmap_entry[hr]=-1;
9413 //regs[i].regmap[hr]=-1;
9414 current.regmap[hr]=-1;
9416 regs[i].regmap_entry[hr]=r;
9419 if((current.uu>>(r&63))&1) {
9420 regs[i].regmap_entry[hr]=-1;
9421 //regs[i].regmap[hr]=-1;
9422 current.regmap[hr]=-1;
9424 regs[i].regmap_entry[hr]=r;
9428 // Branches expect CCREG to be allocated at the target
9429 if(regmap_pre[i][hr]==CCREG)
9430 regs[i].regmap_entry[hr]=CCREG;
9432 regs[i].regmap_entry[hr]=-1;
9435 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9437 /* Branch post-alloc */
9440 current.was32=current.is32;
9441 current.wasdirty=current.dirty;
9442 switch(itype[i-1]) {
9444 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9445 branch_regs[i-1].isconst=0;
9446 branch_regs[i-1].wasconst=0;
9447 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9448 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9449 alloc_cc(&branch_regs[i-1],i-1);
9450 dirty_reg(&branch_regs[i-1],CCREG);
9451 if(rt1[i-1]==31) { // JAL
9452 alloc_reg(&branch_regs[i-1],i-1,31);
9453 dirty_reg(&branch_regs[i-1],31);
9454 branch_regs[i-1].is32|=1LL<<31;
9456 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9457 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9460 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9461 branch_regs[i-1].isconst=0;
9462 branch_regs[i-1].wasconst=0;
9463 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9464 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9465 alloc_cc(&branch_regs[i-1],i-1);
9466 dirty_reg(&branch_regs[i-1],CCREG);
9467 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9468 if(rt1[i-1]!=0) { // JALR
9469 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9470 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9471 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9474 if(rs1[i-1]==31) { // JALR
9475 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9476 #ifndef HOST_IMM_ADDR32
9477 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9481 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9482 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9485 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9487 alloc_cc(¤t,i-1);
9488 dirty_reg(¤t,CCREG);
9489 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9490 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9491 // The delay slot overwrote one of our conditions
9492 // Delay slot goes after the test (in order)
9493 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9494 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9495 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9498 delayslot_alloc(¤t,i);
9503 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9504 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9505 // Alloc the branch condition registers
9506 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9507 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9508 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9510 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9511 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9514 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9515 branch_regs[i-1].isconst=0;
9516 branch_regs[i-1].wasconst=0;
9517 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9518 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9521 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9523 alloc_cc(¤t,i-1);
9524 dirty_reg(¤t,CCREG);
9525 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9526 // The delay slot overwrote the branch condition
9527 // Delay slot goes after the test (in order)
9528 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9529 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9530 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9533 delayslot_alloc(¤t,i);
9538 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9539 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9540 // Alloc the branch condition register
9541 alloc_reg(¤t,i-1,rs1[i-1]);
9542 if(!(current.is32>>rs1[i-1]&1))
9544 alloc_reg64(¤t,i-1,rs1[i-1]);
9547 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9548 branch_regs[i-1].isconst=0;
9549 branch_regs[i-1].wasconst=0;
9550 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9551 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9554 // Alloc the delay slot in case the branch is taken
9555 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9557 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9558 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9559 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9560 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9561 alloc_cc(&branch_regs[i-1],i);
9562 dirty_reg(&branch_regs[i-1],CCREG);
9563 delayslot_alloc(&branch_regs[i-1],i);
9564 branch_regs[i-1].isconst=0;
9565 alloc_reg(¤t,i,CCREG); // Not taken path
9566 dirty_reg(¤t,CCREG);
9567 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9570 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9572 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9573 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9574 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9575 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9576 alloc_cc(&branch_regs[i-1],i);
9577 dirty_reg(&branch_regs[i-1],CCREG);
9578 delayslot_alloc(&branch_regs[i-1],i);
9579 branch_regs[i-1].isconst=0;
9580 alloc_reg(¤t,i,CCREG); // Not taken path
9581 dirty_reg(¤t,CCREG);
9582 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9586 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9587 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9589 alloc_cc(¤t,i-1);
9590 dirty_reg(¤t,CCREG);
9591 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9592 // The delay slot overwrote the branch condition
9593 // Delay slot goes after the test (in order)
9594 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9595 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9596 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9599 delayslot_alloc(¤t,i);
9604 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9605 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9606 // Alloc the branch condition register
9607 alloc_reg(¤t,i-1,rs1[i-1]);
9608 if(!(current.is32>>rs1[i-1]&1))
9610 alloc_reg64(¤t,i-1,rs1[i-1]);
9613 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9614 branch_regs[i-1].isconst=0;
9615 branch_regs[i-1].wasconst=0;
9616 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9617 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9620 // Alloc the delay slot in case the branch is taken
9621 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9623 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9624 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9625 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9626 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9627 alloc_cc(&branch_regs[i-1],i);
9628 dirty_reg(&branch_regs[i-1],CCREG);
9629 delayslot_alloc(&branch_regs[i-1],i);
9630 branch_regs[i-1].isconst=0;
9631 alloc_reg(¤t,i,CCREG); // Not taken path
9632 dirty_reg(¤t,CCREG);
9633 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9635 // FIXME: BLTZAL/BGEZAL
9636 if(opcode2[i-1]&0x10) { // BxxZAL
9637 alloc_reg(&branch_regs[i-1],i-1,31);
9638 dirty_reg(&branch_regs[i-1],31);
9639 branch_regs[i-1].is32|=1LL<<31;
9643 if(likely[i-1]==0) // BC1F/BC1T
9645 alloc_cc(¤t,i-1);
9646 dirty_reg(¤t,CCREG);
9647 if(itype[i]==FCOMP) {
9648 // The delay slot overwrote the branch condition
9649 // Delay slot goes after the test (in order)
9650 delayslot_alloc(¤t,i);
9655 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9656 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9657 // Alloc the branch condition register
9658 alloc_reg(¤t,i-1,FSREG);
9660 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9661 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9665 // Alloc the delay slot in case the branch is taken
9666 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9667 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9668 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9669 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9670 alloc_cc(&branch_regs[i-1],i);
9671 dirty_reg(&branch_regs[i-1],CCREG);
9672 delayslot_alloc(&branch_regs[i-1],i);
9673 branch_regs[i-1].isconst=0;
9674 alloc_reg(¤t,i,CCREG); // Not taken path
9675 dirty_reg(¤t,CCREG);
9676 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9681 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9683 if(rt1[i-1]==31) // JAL/JALR
9685 // Subroutine call will return here, don't alloc any registers
9688 clear_all_regs(current.regmap);
9689 alloc_reg(¤t,i,CCREG);
9690 dirty_reg(¤t,CCREG);
9694 // Internal branch will jump here, match registers to caller
9695 current.is32=0x3FFFFFFFFLL;
9697 clear_all_regs(current.regmap);
9698 alloc_reg(¤t,i,CCREG);
9699 dirty_reg(¤t,CCREG);
9702 if(ba[j]==start+i*4+4) {
9703 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9704 current.is32=branch_regs[j].is32;
9705 current.dirty=branch_regs[j].dirty;
9710 if(ba[j]==start+i*4+4) {
9711 for(hr=0;hr<HOST_REGS;hr++) {
9712 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9713 current.regmap[hr]=-1;
9715 current.is32&=branch_regs[j].is32;
9716 current.dirty&=branch_regs[j].dirty;
9725 // Count cycles in between branches
9727 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9732 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9734 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9736 else if(itype[i]==C2LS)
9746 flush_dirty_uppers(¤t);
9748 regs[i].is32=current.is32;
9749 regs[i].dirty=current.dirty;
9750 regs[i].isconst=current.isconst;
9751 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9753 for(hr=0;hr<HOST_REGS;hr++) {
9754 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9755 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9756 regs[i].wasconst&=~(1<<hr);
9760 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9763 /* Pass 4 - Cull unused host registers */
9767 for (i=slen-1;i>=0;i--)
9770 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9772 if(ba[i]<start || ba[i]>=(start+slen*4))
9774 // Branch out of this block, don't need anything
9780 // Need whatever matches the target
9782 int t=(ba[i]-start)>>2;
9783 for(hr=0;hr<HOST_REGS;hr++)
9785 if(regs[i].regmap_entry[hr]>=0) {
9786 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9790 // Conditional branch may need registers for following instructions
9791 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9794 nr|=needed_reg[i+2];
9795 for(hr=0;hr<HOST_REGS;hr++)
9797 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9798 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9802 // Don't need stuff which is overwritten
9803 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9804 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9805 // Merge in delay slot
9806 for(hr=0;hr<HOST_REGS;hr++)
9809 // These are overwritten unless the branch is "likely"
9810 // and the delay slot is nullified if not taken
9811 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9812 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9814 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9815 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9816 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9817 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9818 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9819 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9820 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9821 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9822 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9823 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9824 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9826 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9827 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9828 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9830 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9831 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9832 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9836 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9838 // SYSCALL instruction (software interrupt)
9841 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9843 // ERET instruction (return from interrupt)
9849 for(hr=0;hr<HOST_REGS;hr++) {
9850 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9851 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9852 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9853 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9857 for(hr=0;hr<HOST_REGS;hr++)
9859 // Overwritten registers are not needed
9860 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9861 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9862 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9863 // Source registers are needed
9864 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9865 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9866 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9867 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9868 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9869 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9870 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9871 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9872 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9873 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9874 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9876 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9877 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9878 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9880 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9881 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9882 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9884 // Don't store a register immediately after writing it,
9885 // may prevent dual-issue.
9886 // But do so if this is a branch target, otherwise we
9887 // might have to load the register before the branch.
9888 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9889 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9890 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9891 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9892 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9894 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9895 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9896 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9897 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9901 // Cycle count is needed at branches. Assume it is needed at the target too.
9902 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9903 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9904 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9909 // Deallocate unneeded registers
9910 for(hr=0;hr<HOST_REGS;hr++)
9913 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9914 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9915 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9916 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9918 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9921 regs[i].regmap[hr]=-1;
9922 regs[i].isconst&=~(1<<hr);
9924 regmap_pre[i+2][hr]=-1;
9925 regs[i+2].wasconst&=~(1<<hr);
9930 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9932 int d1=0,d2=0,map=0,temp=0;
9933 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9939 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9940 itype[i+1]==STORE || itype[i+1]==STORELR ||
9941 itype[i+1]==C1LS || itype[i+1]==C2LS)
9944 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9945 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9948 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9949 itype[i+1]==C1LS || itype[i+1]==C2LS)
9951 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9952 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9953 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9954 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9955 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9956 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9957 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9958 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9959 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9960 regs[i].regmap[hr]!=map )
9962 regs[i].regmap[hr]=-1;
9963 regs[i].isconst&=~(1<<hr);
9964 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9965 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9966 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9967 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9968 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9969 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9970 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9971 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9972 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9973 branch_regs[i].regmap[hr]!=map)
9975 branch_regs[i].regmap[hr]=-1;
9976 branch_regs[i].regmap_entry[hr]=-1;
9977 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9979 if(!likely[i]&&i<slen-2) {
9980 regmap_pre[i+2][hr]=-1;
9981 regs[i+2].wasconst&=~(1<<hr);
9992 int d1=0,d2=0,map=-1,temp=-1;
9993 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9999 if(itype[i]==LOAD || itype[i]==LOADLR ||
10000 itype[i]==STORE || itype[i]==STORELR ||
10001 itype[i]==C1LS || itype[i]==C2LS)
10003 } else if(itype[i]==STORE || itype[i]==STORELR ||
10004 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10007 if(itype[i]==LOADLR || itype[i]==STORELR ||
10008 itype[i]==C1LS || itype[i]==C2LS)
10010 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10011 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10012 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10013 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10014 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10015 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10017 if(i<slen-1&&!is_ds[i]) {
10018 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10019 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10020 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10022 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10023 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10025 regmap_pre[i+1][hr]=-1;
10026 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10027 regs[i+1].wasconst&=~(1<<hr);
10029 regs[i].regmap[hr]=-1;
10030 regs[i].isconst&=~(1<<hr);
10038 /* Pass 5 - Pre-allocate registers */
10040 // If a register is allocated during a loop, try to allocate it for the
10041 // entire loop, if possible. This avoids loading/storing registers
10042 // inside of the loop.
10044 signed char f_regmap[HOST_REGS];
10045 clear_all_regs(f_regmap);
10046 for(i=0;i<slen-1;i++)
10048 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10050 if(ba[i]>=start && ba[i]<(start+i*4))
10051 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10052 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10053 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10054 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10055 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10056 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10058 int t=(ba[i]-start)>>2;
10059 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10060 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10061 for(hr=0;hr<HOST_REGS;hr++)
10063 if(regs[i].regmap[hr]>64) {
10064 if(!((regs[i].dirty>>hr)&1))
10065 f_regmap[hr]=regs[i].regmap[hr];
10066 else f_regmap[hr]=-1;
10068 else if(regs[i].regmap[hr]>=0) {
10069 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10070 // dealloc old register
10072 for(n=0;n<HOST_REGS;n++)
10074 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10076 // and alloc new one
10077 f_regmap[hr]=regs[i].regmap[hr];
10080 if(branch_regs[i].regmap[hr]>64) {
10081 if(!((branch_regs[i].dirty>>hr)&1))
10082 f_regmap[hr]=branch_regs[i].regmap[hr];
10083 else f_regmap[hr]=-1;
10085 else if(branch_regs[i].regmap[hr]>=0) {
10086 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10087 // dealloc old register
10089 for(n=0;n<HOST_REGS;n++)
10091 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10093 // and alloc new one
10094 f_regmap[hr]=branch_regs[i].regmap[hr];
10098 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10099 f_regmap[hr]=branch_regs[i].regmap[hr];
10101 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10102 f_regmap[hr]=branch_regs[i].regmap[hr];
10104 // Avoid dirty->clean transition
10105 #ifdef DESTRUCTIVE_WRITEBACK
10106 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10108 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10109 // case above, however it's always a good idea. We can't hoist the
10110 // load if the register was already allocated, so there's no point
10111 // wasting time analyzing most of these cases. It only "succeeds"
10112 // when the mapping was different and the load can be replaced with
10113 // a mov, which is of negligible benefit. So such cases are
10115 if(f_regmap[hr]>0) {
10116 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10117 int r=f_regmap[hr];
10120 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10121 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10122 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10124 // NB This can exclude the case where the upper-half
10125 // register is lower numbered than the lower-half
10126 // register. Not sure if it's worth fixing...
10127 if(get_reg(regs[j].regmap,r&63)<0) break;
10128 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10129 if(regs[j].is32&(1LL<<(r&63))) break;
10131 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10132 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10134 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10135 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10137 if(get_reg(regs[i].regmap,r&63)<0) break;
10138 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10141 while(k>1&®s[k-1].regmap[hr]==-1) {
10142 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10143 //printf("no free regs for store %x\n",start+(k-1)*4);
10146 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10147 //printf("no-match due to different register\n");
10150 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10151 //printf("no-match due to branch\n");
10154 // call/ret fast path assumes no registers allocated
10155 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10159 // NB This can exclude the case where the upper-half
10160 // register is lower numbered than the lower-half
10161 // register. Not sure if it's worth fixing...
10162 if(get_reg(regs[k-1].regmap,r&63)<0) break;
10163 if(regs[k-1].is32&(1LL<<(r&63))) break;
10168 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10169 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10170 //printf("bad match after branch\n");
10174 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
10175 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10177 regs[k].regmap_entry[hr]=f_regmap[hr];
10178 regs[k].regmap[hr]=f_regmap[hr];
10179 regmap_pre[k+1][hr]=f_regmap[hr];
10180 regs[k].wasdirty&=~(1<<hr);
10181 regs[k].dirty&=~(1<<hr);
10182 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
10183 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
10184 regs[k].wasconst&=~(1<<hr);
10185 regs[k].isconst&=~(1<<hr);
10190 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10193 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10194 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
10195 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10196 regs[i].regmap_entry[hr]=f_regmap[hr];
10197 regs[i].regmap[hr]=f_regmap[hr];
10198 regs[i].wasdirty&=~(1<<hr);
10199 regs[i].dirty&=~(1<<hr);
10200 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
10201 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
10202 regs[i].wasconst&=~(1<<hr);
10203 regs[i].isconst&=~(1<<hr);
10204 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10205 branch_regs[i].wasdirty&=~(1<<hr);
10206 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
10207 branch_regs[i].regmap[hr]=f_regmap[hr];
10208 branch_regs[i].dirty&=~(1<<hr);
10209 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
10210 branch_regs[i].wasconst&=~(1<<hr);
10211 branch_regs[i].isconst&=~(1<<hr);
10212 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10213 regmap_pre[i+2][hr]=f_regmap[hr];
10214 regs[i+2].wasdirty&=~(1<<hr);
10215 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
10216 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10217 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10222 // Alloc register clean at beginning of loop,
10223 // but may dirty it in pass 6
10224 regs[k].regmap_entry[hr]=f_regmap[hr];
10225 regs[k].regmap[hr]=f_regmap[hr];
10226 regs[k].dirty&=~(1<<hr);
10227 regs[k].wasconst&=~(1<<hr);
10228 regs[k].isconst&=~(1<<hr);
10229 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10230 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10231 branch_regs[k].regmap[hr]=f_regmap[hr];
10232 branch_regs[k].dirty&=~(1<<hr);
10233 branch_regs[k].wasconst&=~(1<<hr);
10234 branch_regs[k].isconst&=~(1<<hr);
10235 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10236 regmap_pre[k+2][hr]=f_regmap[hr];
10237 regs[k+2].wasdirty&=~(1<<hr);
10238 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10239 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10244 regmap_pre[k+1][hr]=f_regmap[hr];
10245 regs[k+1].wasdirty&=~(1<<hr);
10248 if(regs[j].regmap[hr]==f_regmap[hr])
10249 regs[j].regmap_entry[hr]=f_regmap[hr];
10253 if(regs[j].regmap[hr]>=0)
10255 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10256 //printf("no-match due to different register\n");
10259 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10260 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10263 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10265 // Stop on unconditional branch
10268 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10271 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10274 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10277 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10278 //printf("no-match due to different register (branch)\n");
10282 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10283 //printf("No free regs for store %x\n",start+j*4);
10286 if(f_regmap[hr]>=64) {
10287 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10292 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10303 // Non branch or undetermined branch target
10304 for(hr=0;hr<HOST_REGS;hr++)
10306 if(hr!=EXCLUDE_REG) {
10307 if(regs[i].regmap[hr]>64) {
10308 if(!((regs[i].dirty>>hr)&1))
10309 f_regmap[hr]=regs[i].regmap[hr];
10311 else if(regs[i].regmap[hr]>=0) {
10312 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10313 // dealloc old register
10315 for(n=0;n<HOST_REGS;n++)
10317 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10319 // and alloc new one
10320 f_regmap[hr]=regs[i].regmap[hr];
10325 // Try to restore cycle count at branch targets
10327 for(j=i;j<slen-1;j++) {
10328 if(regs[j].regmap[HOST_CCREG]!=-1) break;
10329 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10330 //printf("no free regs for store %x\n",start+j*4);
10334 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10336 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10338 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10339 regs[k].regmap[HOST_CCREG]=CCREG;
10340 regmap_pre[k+1][HOST_CCREG]=CCREG;
10341 regs[k+1].wasdirty|=1<<HOST_CCREG;
10342 regs[k].dirty|=1<<HOST_CCREG;
10343 regs[k].wasconst&=~(1<<HOST_CCREG);
10344 regs[k].isconst&=~(1<<HOST_CCREG);
10347 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10349 // Work backwards from the branch target
10350 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10352 //printf("Extend backwards\n");
10355 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10356 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10357 //printf("no free regs for store %x\n",start+(k-1)*4);
10362 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10363 //printf("Extend CC, %x ->\n",start+k*4);
10365 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10366 regs[k].regmap[HOST_CCREG]=CCREG;
10367 regmap_pre[k+1][HOST_CCREG]=CCREG;
10368 regs[k+1].wasdirty|=1<<HOST_CCREG;
10369 regs[k].dirty|=1<<HOST_CCREG;
10370 regs[k].wasconst&=~(1<<HOST_CCREG);
10371 regs[k].isconst&=~(1<<HOST_CCREG);
10376 //printf("Fail Extend CC, %x ->\n",start+k*4);
10380 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10381 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10382 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10383 itype[i]!=FCONV&&itype[i]!=FCOMP)
10385 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10390 // Cache memory offset or tlb map pointer if a register is available
10391 #ifndef HOST_IMM_ADDR32
10396 int earliest_available[HOST_REGS];
10397 int loop_start[HOST_REGS];
10398 int score[HOST_REGS];
10399 int end[HOST_REGS];
10400 int reg=using_tlb?MMREG:ROREG;
10403 for(hr=0;hr<HOST_REGS;hr++) {
10404 score[hr]=0;earliest_available[hr]=0;
10405 loop_start[hr]=MAXBLOCK;
10407 for(i=0;i<slen-1;i++)
10409 // Can't do anything if no registers are available
10410 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10411 for(hr=0;hr<HOST_REGS;hr++) {
10412 score[hr]=0;earliest_available[hr]=i+1;
10413 loop_start[hr]=MAXBLOCK;
10416 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10418 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10419 for(hr=0;hr<HOST_REGS;hr++) {
10420 score[hr]=0;earliest_available[hr]=i+1;
10421 loop_start[hr]=MAXBLOCK;
10425 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10426 for(hr=0;hr<HOST_REGS;hr++) {
10427 score[hr]=0;earliest_available[hr]=i+1;
10428 loop_start[hr]=MAXBLOCK;
10433 // Mark unavailable registers
10434 for(hr=0;hr<HOST_REGS;hr++) {
10435 if(regs[i].regmap[hr]>=0) {
10436 score[hr]=0;earliest_available[hr]=i+1;
10437 loop_start[hr]=MAXBLOCK;
10439 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10440 if(branch_regs[i].regmap[hr]>=0) {
10441 score[hr]=0;earliest_available[hr]=i+2;
10442 loop_start[hr]=MAXBLOCK;
10446 // No register allocations after unconditional jumps
10447 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10449 for(hr=0;hr<HOST_REGS;hr++) {
10450 score[hr]=0;earliest_available[hr]=i+2;
10451 loop_start[hr]=MAXBLOCK;
10453 i++; // Skip delay slot too
10454 //printf("skip delay slot: %x\n",start+i*4);
10458 if(itype[i]==LOAD||itype[i]==LOADLR||
10459 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10460 for(hr=0;hr<HOST_REGS;hr++) {
10461 if(hr!=EXCLUDE_REG) {
10463 for(j=i;j<slen-1;j++) {
10464 if(regs[j].regmap[hr]>=0) break;
10465 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10466 if(branch_regs[j].regmap[hr]>=0) break;
10468 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10470 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10473 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10474 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10475 int t=(ba[j]-start)>>2;
10476 if(t<j&&t>=earliest_available[hr]) {
10477 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10478 // Score a point for hoisting loop invariant
10479 if(t<loop_start[hr]) loop_start[hr]=t;
10480 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10486 if(regs[t].regmap[hr]==reg) {
10487 // Score a point if the branch target matches this register
10492 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10493 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10498 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10500 // Stop on unconditional branch
10504 if(itype[j]==LOAD||itype[j]==LOADLR||
10505 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10512 // Find highest score and allocate that register
10514 for(hr=0;hr<HOST_REGS;hr++) {
10515 if(hr!=EXCLUDE_REG) {
10516 if(score[hr]>score[maxscore]) {
10518 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10522 if(score[maxscore]>1)
10524 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10525 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10526 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10527 assert(regs[j].regmap[maxscore]<0);
10528 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10529 regs[j].regmap[maxscore]=reg;
10530 regs[j].dirty&=~(1<<maxscore);
10531 regs[j].wasconst&=~(1<<maxscore);
10532 regs[j].isconst&=~(1<<maxscore);
10533 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10534 branch_regs[j].regmap[maxscore]=reg;
10535 branch_regs[j].wasdirty&=~(1<<maxscore);
10536 branch_regs[j].dirty&=~(1<<maxscore);
10537 branch_regs[j].wasconst&=~(1<<maxscore);
10538 branch_regs[j].isconst&=~(1<<maxscore);
10539 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10540 regmap_pre[j+2][maxscore]=reg;
10541 regs[j+2].wasdirty&=~(1<<maxscore);
10543 // loop optimization (loop_preload)
10544 int t=(ba[j]-start)>>2;
10545 if(t==loop_start[maxscore]) {
10546 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10547 regs[t].regmap_entry[maxscore]=reg;
10552 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10553 regmap_pre[j+1][maxscore]=reg;
10554 regs[j+1].wasdirty&=~(1<<maxscore);
10559 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10560 for(hr=0;hr<HOST_REGS;hr++) {
10561 score[hr]=0;earliest_available[hr]=i+i;
10562 loop_start[hr]=MAXBLOCK;
10570 // This allocates registers (if possible) one instruction prior
10571 // to use, which can avoid a load-use penalty on certain CPUs.
10572 for(i=0;i<slen-1;i++)
10574 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10578 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10579 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10582 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10584 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10586 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10587 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10588 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10589 regs[i].isconst&=~(1<<hr);
10590 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10591 constmap[i][hr]=constmap[i+1][hr];
10592 regs[i+1].wasdirty&=~(1<<hr);
10593 regs[i].dirty&=~(1<<hr);
10598 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10600 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10602 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10603 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10604 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10605 regs[i].isconst&=~(1<<hr);
10606 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10607 constmap[i][hr]=constmap[i+1][hr];
10608 regs[i+1].wasdirty&=~(1<<hr);
10609 regs[i].dirty&=~(1<<hr);
10613 // Preload target address for load instruction (non-constant)
10614 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10615 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10617 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10619 regs[i].regmap[hr]=rs1[i+1];
10620 regmap_pre[i+1][hr]=rs1[i+1];
10621 regs[i+1].regmap_entry[hr]=rs1[i+1];
10622 regs[i].isconst&=~(1<<hr);
10623 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10624 constmap[i][hr]=constmap[i+1][hr];
10625 regs[i+1].wasdirty&=~(1<<hr);
10626 regs[i].dirty&=~(1<<hr);
10630 // Load source into target register
10631 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10632 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10634 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10636 regs[i].regmap[hr]=rs1[i+1];
10637 regmap_pre[i+1][hr]=rs1[i+1];
10638 regs[i+1].regmap_entry[hr]=rs1[i+1];
10639 regs[i].isconst&=~(1<<hr);
10640 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10641 constmap[i][hr]=constmap[i+1][hr];
10642 regs[i+1].wasdirty&=~(1<<hr);
10643 regs[i].dirty&=~(1<<hr);
10647 // Preload map address
10648 #ifndef HOST_IMM_ADDR32
10649 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10650 hr=get_reg(regs[i+1].regmap,TLREG);
10652 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10653 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10655 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10657 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10658 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10659 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10660 regs[i].isconst&=~(1<<hr);
10661 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10662 constmap[i][hr]=constmap[i+1][hr];
10663 regs[i+1].wasdirty&=~(1<<hr);
10664 regs[i].dirty&=~(1<<hr);
10666 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10668 // move it to another register
10669 regs[i+1].regmap[hr]=-1;
10670 regmap_pre[i+2][hr]=-1;
10671 regs[i+1].regmap[nr]=TLREG;
10672 regmap_pre[i+2][nr]=TLREG;
10673 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10674 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10675 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10676 regs[i].isconst&=~(1<<nr);
10677 regs[i+1].isconst&=~(1<<nr);
10678 regs[i].dirty&=~(1<<nr);
10679 regs[i+1].wasdirty&=~(1<<nr);
10680 regs[i+1].dirty&=~(1<<nr);
10681 regs[i+2].wasdirty&=~(1<<nr);
10687 // Address for store instruction (non-constant)
10688 if(itype[i+1]==STORE||itype[i+1]==STORELR
10689 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10690 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10691 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10692 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10693 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10695 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10697 regs[i].regmap[hr]=rs1[i+1];
10698 regmap_pre[i+1][hr]=rs1[i+1];
10699 regs[i+1].regmap_entry[hr]=rs1[i+1];
10700 regs[i].isconst&=~(1<<hr);
10701 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10702 constmap[i][hr]=constmap[i+1][hr];
10703 regs[i+1].wasdirty&=~(1<<hr);
10704 regs[i].dirty&=~(1<<hr);
10708 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10709 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10711 hr=get_reg(regs[i+1].regmap,FTEMP);
10713 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10715 regs[i].regmap[hr]=rs1[i+1];
10716 regmap_pre[i+1][hr]=rs1[i+1];
10717 regs[i+1].regmap_entry[hr]=rs1[i+1];
10718 regs[i].isconst&=~(1<<hr);
10719 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10720 constmap[i][hr]=constmap[i+1][hr];
10721 regs[i+1].wasdirty&=~(1<<hr);
10722 regs[i].dirty&=~(1<<hr);
10724 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10726 // move it to another register
10727 regs[i+1].regmap[hr]=-1;
10728 regmap_pre[i+2][hr]=-1;
10729 regs[i+1].regmap[nr]=FTEMP;
10730 regmap_pre[i+2][nr]=FTEMP;
10731 regs[i].regmap[nr]=rs1[i+1];
10732 regmap_pre[i+1][nr]=rs1[i+1];
10733 regs[i+1].regmap_entry[nr]=rs1[i+1];
10734 regs[i].isconst&=~(1<<nr);
10735 regs[i+1].isconst&=~(1<<nr);
10736 regs[i].dirty&=~(1<<nr);
10737 regs[i+1].wasdirty&=~(1<<nr);
10738 regs[i+1].dirty&=~(1<<nr);
10739 regs[i+2].wasdirty&=~(1<<nr);
10743 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10744 if(itype[i+1]==LOAD)
10745 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10746 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10747 hr=get_reg(regs[i+1].regmap,FTEMP);
10748 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10749 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10750 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10752 if(hr>=0&®s[i].regmap[hr]<0) {
10753 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10754 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10755 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10756 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10757 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10758 regs[i].isconst&=~(1<<hr);
10759 regs[i+1].wasdirty&=~(1<<hr);
10760 regs[i].dirty&=~(1<<hr);
10769 /* Pass 6 - Optimize clean/dirty state */
10770 clean_registers(0,slen-1,1);
10772 /* Pass 7 - Identify 32-bit registers */
10778 for (i=slen-1;i>=0;i--)
10781 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10783 if(ba[i]<start || ba[i]>=(start+slen*4))
10785 // Branch out of this block, don't need anything
10791 // Need whatever matches the target
10792 // (and doesn't get overwritten by the delay slot instruction)
10794 int t=(ba[i]-start)>>2;
10795 if(ba[i]>start+i*4) {
10797 if(!(requires_32bit[t]&~regs[i].was32))
10798 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10801 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10802 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10803 if(!(pr32[t]&~regs[i].was32))
10804 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10807 // Conditional branch may need registers for following instructions
10808 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10811 r32|=requires_32bit[i+2];
10812 r32&=regs[i].was32;
10813 // Mark this address as a branch target since it may be called
10814 // upon return from interrupt
10818 // Merge in delay slot
10820 // These are overwritten unless the branch is "likely"
10821 // and the delay slot is nullified if not taken
10822 r32&=~(1LL<<rt1[i+1]);
10823 r32&=~(1LL<<rt2[i+1]);
10825 // Assume these are needed (delay slot)
10828 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10832 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10834 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10836 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10838 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10840 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10843 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10845 // SYSCALL instruction (software interrupt)
10848 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10850 // ERET instruction (return from interrupt)
10854 r32&=~(1LL<<rt1[i]);
10855 r32&=~(1LL<<rt2[i]);
10858 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10862 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10864 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10866 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10868 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10870 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10872 requires_32bit[i]=r32;
10874 // Dirty registers which are 32-bit, require 32-bit input
10875 // as they will be written as 32-bit values
10876 for(hr=0;hr<HOST_REGS;hr++)
10878 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
10879 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10880 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10881 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10885 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10888 for (i=slen-1;i>=0;i--)
10890 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10892 // Conditional branch
10893 if((source[i]>>16)!=0x1000&&i<slen-2) {
10894 // Mark this address as a branch target since it may be called
10895 // upon return from interrupt
10902 if(itype[slen-1]==SPAN) {
10903 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10907 /* Debug/disassembly */
10908 for(i=0;i<slen;i++)
10912 for(r=1;r<=CCREG;r++) {
10913 if((unneeded_reg[i]>>r)&1) {
10914 if(r==HIREG) printf(" HI");
10915 else if(r==LOREG) printf(" LO");
10916 else printf(" r%d",r);
10921 for(r=1;r<=CCREG;r++) {
10922 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10923 if(r==HIREG) printf(" HI");
10924 else if(r==LOREG) printf(" LO");
10925 else printf(" r%d",r);
10929 for(r=0;r<=CCREG;r++) {
10930 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10931 if((regs[i].was32>>r)&1) {
10932 if(r==CCREG) printf(" CC");
10933 else if(r==HIREG) printf(" HI");
10934 else if(r==LOREG) printf(" LO");
10935 else printf(" r%d",r);
10940 #if defined(__i386__) || defined(__x86_64__)
10941 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10944 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10947 if(needed_reg[i]&1) printf("eax ");
10948 if((needed_reg[i]>>1)&1) printf("ecx ");
10949 if((needed_reg[i]>>2)&1) printf("edx ");
10950 if((needed_reg[i]>>3)&1) printf("ebx ");
10951 if((needed_reg[i]>>5)&1) printf("ebp ");
10952 if((needed_reg[i]>>6)&1) printf("esi ");
10953 if((needed_reg[i]>>7)&1) printf("edi ");
10955 for(r=0;r<=CCREG;r++) {
10956 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10957 if((requires_32bit[i]>>r)&1) {
10958 if(r==CCREG) printf(" CC");
10959 else if(r==HIREG) printf(" HI");
10960 else if(r==LOREG) printf(" LO");
10961 else printf(" r%d",r);
10966 for(r=0;r<=CCREG;r++) {
10967 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10968 if((pr32[i]>>r)&1) {
10969 if(r==CCREG) printf(" CC");
10970 else if(r==HIREG) printf(" HI");
10971 else if(r==LOREG) printf(" LO");
10972 else printf(" r%d",r);
10975 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10977 #if defined(__i386__) || defined(__x86_64__)
10978 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10980 if(regs[i].wasdirty&1) printf("eax ");
10981 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10982 if((regs[i].wasdirty>>2)&1) printf("edx ");
10983 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10984 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10985 if((regs[i].wasdirty>>6)&1) printf("esi ");
10986 if((regs[i].wasdirty>>7)&1) printf("edi ");
10989 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10991 if(regs[i].wasdirty&1) printf("r0 ");
10992 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10993 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10994 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10995 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10996 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10997 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10998 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10999 if((regs[i].wasdirty>>8)&1) printf("r8 ");
11000 if((regs[i].wasdirty>>9)&1) printf("r9 ");
11001 if((regs[i].wasdirty>>10)&1) printf("r10 ");
11002 if((regs[i].wasdirty>>12)&1) printf("r12 ");
11005 disassemble_inst(i);
11006 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11007 #if defined(__i386__) || defined(__x86_64__)
11008 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11009 if(regs[i].dirty&1) printf("eax ");
11010 if((regs[i].dirty>>1)&1) printf("ecx ");
11011 if((regs[i].dirty>>2)&1) printf("edx ");
11012 if((regs[i].dirty>>3)&1) printf("ebx ");
11013 if((regs[i].dirty>>5)&1) printf("ebp ");
11014 if((regs[i].dirty>>6)&1) printf("esi ");
11015 if((regs[i].dirty>>7)&1) printf("edi ");
11018 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11019 if(regs[i].dirty&1) printf("r0 ");
11020 if((regs[i].dirty>>1)&1) printf("r1 ");
11021 if((regs[i].dirty>>2)&1) printf("r2 ");
11022 if((regs[i].dirty>>3)&1) printf("r3 ");
11023 if((regs[i].dirty>>4)&1) printf("r4 ");
11024 if((regs[i].dirty>>5)&1) printf("r5 ");
11025 if((regs[i].dirty>>6)&1) printf("r6 ");
11026 if((regs[i].dirty>>7)&1) printf("r7 ");
11027 if((regs[i].dirty>>8)&1) printf("r8 ");
11028 if((regs[i].dirty>>9)&1) printf("r9 ");
11029 if((regs[i].dirty>>10)&1) printf("r10 ");
11030 if((regs[i].dirty>>12)&1) printf("r12 ");
11033 if(regs[i].isconst) {
11034 printf("constants: ");
11035 #if defined(__i386__) || defined(__x86_64__)
11036 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11037 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11038 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11039 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11040 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11041 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11042 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11045 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11046 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11047 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11048 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11049 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11050 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11051 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11052 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11053 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11054 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11055 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11056 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11062 for(r=0;r<=CCREG;r++) {
11063 if((regs[i].is32>>r)&1) {
11064 if(r==CCREG) printf(" CC");
11065 else if(r==HIREG) printf(" HI");
11066 else if(r==LOREG) printf(" LO");
11067 else printf(" r%d",r);
11073 for(r=0;r<=CCREG;r++) {
11074 if((p32[i]>>r)&1) {
11075 if(r==CCREG) printf(" CC");
11076 else if(r==HIREG) printf(" HI");
11077 else if(r==LOREG) printf(" LO");
11078 else printf(" r%d",r);
11081 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11082 else printf("\n");*/
11083 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11084 #if defined(__i386__) || defined(__x86_64__)
11085 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11086 if(branch_regs[i].dirty&1) printf("eax ");
11087 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11088 if((branch_regs[i].dirty>>2)&1) printf("edx ");
11089 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11090 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11091 if((branch_regs[i].dirty>>6)&1) printf("esi ");
11092 if((branch_regs[i].dirty>>7)&1) printf("edi ");
11095 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11096 if(branch_regs[i].dirty&1) printf("r0 ");
11097 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11098 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11099 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11100 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11101 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11102 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11103 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11104 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11105 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11106 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11107 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11111 for(r=0;r<=CCREG;r++) {
11112 if((branch_regs[i].is32>>r)&1) {
11113 if(r==CCREG) printf(" CC");
11114 else if(r==HIREG) printf(" HI");
11115 else if(r==LOREG) printf(" LO");
11116 else printf(" r%d",r);
11125 /* Pass 8 - Assembly */
11126 linkcount=0;stubcount=0;
11127 ds=0;is_delayslot=0;
11129 uint64_t is32_pre=0;
11131 u_int beginning=(u_int)out;
11132 if((u_int)addr&1) {
11136 u_int instr_addr0_override=0;
11139 if (start == 0x80030000) {
11140 // nasty hack for fastbios thing
11141 // override block entry to this code
11142 instr_addr0_override=(u_int)out;
11143 emit_movimm(start,0);
11144 // abuse io address var as a flag that we
11145 // have already returned here once
11146 emit_readword((int)&address,1);
11147 emit_writeword(0,(int)&pcaddr);
11148 emit_writeword(0,(int)&address);
11150 emit_jne((int)new_dyna_leave);
11153 for(i=0;i<slen;i++)
11155 //if(ds) printf("ds: ");
11156 disassemble_inst(i);
11158 ds=0; // Skip delay slot
11159 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11162 speculate_register_values(i);
11163 #ifndef DESTRUCTIVE_WRITEBACK
11164 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11166 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11167 unneeded_reg[i],unneeded_reg_upper[i]);
11168 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11169 unneeded_reg[i],unneeded_reg_upper[i]);
11171 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11172 is32_pre=branch_regs[i].is32;
11173 dirty_pre=branch_regs[i].dirty;
11175 is32_pre=regs[i].is32;
11176 dirty_pre=regs[i].dirty;
11180 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11182 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11183 unneeded_reg[i],unneeded_reg_upper[i]);
11184 loop_preload(regmap_pre[i],regs[i].regmap_entry);
11186 // branch target entry point
11187 instr_addr[i]=(u_int)out;
11188 assem_debug("<->\n");
11190 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
11191 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11192 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11193 address_generation(i,®s[i],regs[i].regmap_entry);
11194 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11195 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11197 // Load the delay slot registers if necessary
11198 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11199 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11200 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11201 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11202 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11203 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11207 // Preload registers for following instruction
11208 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11209 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11210 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11211 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11212 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11213 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11215 // TODO: if(is_ooo(i)) address_generation(i+1);
11216 if(itype[i]==CJUMP||itype[i]==FJUMP)
11217 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11218 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11219 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11220 if(bt[i]) cop1_usable=0;
11224 alu_assemble(i,®s[i]);break;
11226 imm16_assemble(i,®s[i]);break;
11228 shift_assemble(i,®s[i]);break;
11230 shiftimm_assemble(i,®s[i]);break;
11232 load_assemble(i,®s[i]);break;
11234 loadlr_assemble(i,®s[i]);break;
11236 store_assemble(i,®s[i]);break;
11238 storelr_assemble(i,®s[i]);break;
11240 cop0_assemble(i,®s[i]);break;
11242 cop1_assemble(i,®s[i]);break;
11244 c1ls_assemble(i,®s[i]);break;
11246 cop2_assemble(i,®s[i]);break;
11248 c2ls_assemble(i,®s[i]);break;
11250 c2op_assemble(i,®s[i]);break;
11252 fconv_assemble(i,®s[i]);break;
11254 float_assemble(i,®s[i]);break;
11256 fcomp_assemble(i,®s[i]);break;
11258 multdiv_assemble(i,®s[i]);break;
11260 mov_assemble(i,®s[i]);break;
11262 syscall_assemble(i,®s[i]);break;
11264 hlecall_assemble(i,®s[i]);break;
11266 intcall_assemble(i,®s[i]);break;
11268 ujump_assemble(i,®s[i]);ds=1;break;
11270 rjump_assemble(i,®s[i]);ds=1;break;
11272 cjump_assemble(i,®s[i]);ds=1;break;
11274 sjump_assemble(i,®s[i]);ds=1;break;
11276 fjump_assemble(i,®s[i]);ds=1;break;
11278 pagespan_assemble(i,®s[i]);break;
11280 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11281 literal_pool(1024);
11283 literal_pool_jumpover(256);
11286 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11287 // If the block did not end with an unconditional branch,
11288 // add a jump to the next instruction.
11290 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11291 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11293 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11294 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11295 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11296 emit_loadreg(CCREG,HOST_CCREG);
11297 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11299 else if(!likely[i-2])
11301 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11302 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11306 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11307 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11309 add_to_linker((int)out,start+i*4,0);
11316 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11317 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11318 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11319 emit_loadreg(CCREG,HOST_CCREG);
11320 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11321 add_to_linker((int)out,start+i*4,0);
11325 // TODO: delay slot stubs?
11327 for(i=0;i<stubcount;i++)
11329 switch(stubs[i][0])
11337 do_readstub(i);break;
11342 do_writestub(i);break;
11344 do_ccstub(i);break;
11346 do_invstub(i);break;
11348 do_cop1stub(i);break;
11350 do_unalignedwritestub(i);break;
11354 if (instr_addr0_override)
11355 instr_addr[0] = instr_addr0_override;
11357 /* Pass 9 - Linker */
11358 for(i=0;i<linkcount;i++)
11360 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11362 if(!link_addr[i][2])
11365 void *addr=check_addr(link_addr[i][1]);
11366 emit_extjump(link_addr[i][0],link_addr[i][1]);
11368 set_jump_target(link_addr[i][0],(int)addr);
11369 add_link(link_addr[i][1],stub);
11371 else set_jump_target(link_addr[i][0],(int)stub);
11376 int target=(link_addr[i][1]-start)>>2;
11377 assert(target>=0&&target<slen);
11378 assert(instr_addr[target]);
11379 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11380 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11382 set_jump_target(link_addr[i][0],instr_addr[target]);
11386 // External Branch Targets (jump_in)
11387 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11388 for(i=0;i<slen;i++)
11392 if(instr_addr[i]) // TODO - delay slots (=null)
11394 u_int vaddr=start+i*4;
11395 u_int page=get_page(vaddr);
11396 u_int vpage=get_vpage(vaddr);
11398 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11400 if(!requires_32bit[i])
11405 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11406 assem_debug("jump_in: %x\n",start+i*4);
11407 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11408 int entry_point=do_dirty_stub(i);
11409 ll_add(jump_in+page,vaddr,(void *)entry_point);
11410 // If there was an existing entry in the hash table,
11411 // replace it with the new address.
11412 // Don't add new entries. We'll insert the
11413 // ones that actually get used in check_addr().
11414 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11415 if(ht_bin[0]==vaddr) {
11416 ht_bin[1]=entry_point;
11418 if(ht_bin[2]==vaddr) {
11419 ht_bin[3]=entry_point;
11424 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11425 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11426 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11427 //int entry_point=(int)out;
11428 ////assem_debug("entry_point: %x\n",entry_point);
11429 //load_regs_entry(i);
11430 //if(entry_point==(int)out)
11431 // entry_point=instr_addr[i];
11433 // emit_jmp(instr_addr[i]);
11434 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11435 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11436 int entry_point=do_dirty_stub(i);
11437 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11442 // Write out the literal pool if necessary
11444 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11446 if(((u_int)out)&7) emit_addnop(13);
11448 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11449 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11450 memcpy(copy,source,slen*4);
11454 __clear_cache((void *)beginning,out);
11457 // If we're within 256K of the end of the buffer,
11458 // start over from the beginning. (Is 256K enough?)
11459 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11461 // Trap writes to any of the pages we compiled
11462 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11464 #ifndef DISABLE_TLB
11465 memory_map[i]|=0x40000000;
11466 if((signed int)start>=(signed int)0xC0000000) {
11468 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11470 memory_map[j]|=0x40000000;
11471 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11475 inv_code_start=inv_code_end=~0;
11477 // for PCSX we need to mark all mirrors too
11478 if(get_page(start)<(RAM_SIZE>>12))
11479 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11480 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11481 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11482 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11485 /* Pass 10 - Free memory by expiring oldest blocks */
11487 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11488 while(expirep!=end)
11490 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11491 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11492 inv_debug("EXP: Phase %d\n",expirep);
11493 switch((expirep>>11)&3)
11496 // Clear jump_in and jump_dirty
11497 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11498 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11499 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11500 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11504 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11505 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11508 // Clear hash table
11509 for(i=0;i<32;i++) {
11510 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11511 if((ht_bin[3]>>shift)==(base>>shift) ||
11512 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11513 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11514 ht_bin[2]=ht_bin[3]=-1;
11516 if((ht_bin[1]>>shift)==(base>>shift) ||
11517 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11518 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11519 ht_bin[0]=ht_bin[2];
11520 ht_bin[1]=ht_bin[3];
11521 ht_bin[2]=ht_bin[3]=-1;
11528 if((expirep&2047)==0)
11531 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11532 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11535 expirep=(expirep+1)&65535;
11540 // vim:shiftwidth=2:expandtab