1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
27 #include <libkern/OSCacheControl.h>
30 #include <3ds_utils.h>
33 #include <psp2/kernel/sysmem.h>
37 #include "new_dynarec_config.h"
38 #include "../psxhle.h"
39 #include "../psxinterpreter.h"
40 #include "emu_if.h" //emulator interface
42 #define noinline __attribute__((noinline,noclone))
44 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
48 //#define assem_debug printf
49 //#define inv_debug printf
50 #define assem_debug(...)
51 #define inv_debug(...)
54 #include "assem_x86.h"
57 #include "assem_x64.h"
60 #include "assem_arm.h"
63 #include "assem_arm64.h"
67 #define MAX_OUTPUT_BLOCK_SIZE 262144
89 signed char regmap_entry[HOST_REGS];
90 signed char regmap[HOST_REGS];
96 u_int loadedconst; // host regs that have constants loaded
97 u_int waswritten; // MIPS regs that were used as store base before
100 // note: asm depends on this layout
106 struct ll_entry *next;
136 struct ht_entry hash_table[65536] __attribute__((aligned(16)));
137 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
138 struct ll_entry *jump_dirty[4096];
140 static struct ll_entry *jump_out[4096];
142 static u_int *source;
143 static char insn[MAXBLOCK][10];
144 static u_char itype[MAXBLOCK];
145 static u_char opcode[MAXBLOCK];
146 static u_char opcode2[MAXBLOCK];
147 static u_char bt[MAXBLOCK];
148 static u_char rs1[MAXBLOCK];
149 static u_char rs2[MAXBLOCK];
150 static u_char rt1[MAXBLOCK];
151 static u_char rt2[MAXBLOCK];
152 static u_char dep1[MAXBLOCK];
153 static u_char dep2[MAXBLOCK];
154 static u_char lt1[MAXBLOCK];
155 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
156 static uint64_t gte_rt[MAXBLOCK];
157 static uint64_t gte_unneeded[MAXBLOCK];
158 static u_int smrv[32]; // speculated MIPS register values
159 static u_int smrv_strong; // mask or regs that are likely to have correct values
160 static u_int smrv_weak; // same, but somewhat less likely
161 static u_int smrv_strong_next; // same, but after current insn executes
162 static u_int smrv_weak_next;
163 static int imm[MAXBLOCK];
164 static u_int ba[MAXBLOCK];
165 static char likely[MAXBLOCK];
166 static char is_ds[MAXBLOCK];
167 static char ooo[MAXBLOCK];
168 static uint64_t unneeded_reg[MAXBLOCK];
169 static uint64_t branch_unneeded_reg[MAXBLOCK];
170 static signed char regmap_pre[MAXBLOCK][HOST_REGS]; // pre-instruction i?
171 static uint64_t current_constmap[HOST_REGS];
172 static uint64_t constmap[MAXBLOCK][HOST_REGS];
173 static struct regstat regs[MAXBLOCK];
174 static struct regstat branch_regs[MAXBLOCK];
175 static signed char minimum_free_regs[MAXBLOCK];
176 static u_int needed_reg[MAXBLOCK];
177 static u_int wont_dirty[MAXBLOCK];
178 static u_int will_dirty[MAXBLOCK];
179 static int ccadj[MAXBLOCK];
181 static void *instr_addr[MAXBLOCK];
182 static struct link_entry link_addr[MAXBLOCK];
183 static int linkcount;
184 static struct code_stub stubs[MAXBLOCK*3];
185 static int stubcount;
186 static u_int literals[1024][2];
187 static int literalcount;
188 static int is_delayslot;
189 static char shadow[1048576] __attribute__((aligned(16)));
192 static u_int stop_after_jal;
194 static uintptr_t ram_offset;
196 static const uintptr_t ram_offset=0;
199 int new_dynarec_hacks;
200 int new_dynarec_did_compile;
202 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
203 extern int last_count; // last absolute target, often = next_interupt
205 extern int pending_exception;
206 extern int branch_target;
207 extern uintptr_t mini_ht[32][2];
208 extern u_char restore_candidate[512];
210 /* registers that may be allocated */
212 #define LOREG 32 // lo
213 #define HIREG 33 // hi
214 //#define FSREG 34 // FPU status (FCSR)
215 #define CSREG 35 // Coprocessor status
216 #define CCREG 36 // Cycle count
217 #define INVCP 37 // Pointer to invalid_code
218 //#define MMREG 38 // Pointer to memory_map
219 //#define ROREG 39 // ram offset (if rdram!=0x80000000)
221 #define FTEMP 40 // FPU temporary register
222 #define PTEMP 41 // Prefetch temporary register
223 //#define TLREG 42 // TLB mapping offset
224 #define RHASH 43 // Return address hash
225 #define RHTBL 44 // Return address hash table address
226 #define RTEMP 45 // JR/JALR address register
228 #define AGEN1 46 // Address generation temporary register
229 //#define AGEN2 47 // Address generation temporary register
230 //#define MGEN1 48 // Maptable address generation temporary register
231 //#define MGEN2 49 // Maptable address generation temporary register
232 #define BTREG 50 // Branch target temporary register
234 /* instruction types */
235 #define NOP 0 // No operation
236 #define LOAD 1 // Load
237 #define STORE 2 // Store
238 #define LOADLR 3 // Unaligned load
239 #define STORELR 4 // Unaligned store
240 #define MOV 5 // Move
241 #define ALU 6 // Arithmetic/logic
242 #define MULTDIV 7 // Multiply/divide
243 #define SHIFT 8 // Shift by register
244 #define SHIFTIMM 9// Shift by immediate
245 #define IMM16 10 // 16-bit immediate
246 #define RJUMP 11 // Unconditional jump to register
247 #define UJUMP 12 // Unconditional jump
248 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
249 #define SJUMP 14 // Conditional branch (regimm format)
250 #define COP0 15 // Coprocessor 0
251 #define COP1 16 // Coprocessor 1
252 #define C1LS 17 // Coprocessor 1 load/store
253 //#define FJUMP 18 // Conditional branch (floating point)
254 //#define FLOAT 19 // Floating point unit
255 //#define FCONV 20 // Convert integer to float
256 //#define FCOMP 21 // Floating point compare (sets FSREG)
257 #define SYSCALL 22// SYSCALL
258 #define OTHER 23 // Other
259 #define SPAN 24 // Branch/delay slot spans 2 pages
260 #define NI 25 // Not implemented
261 #define HLECALL 26// PCSX fake opcodes for HLE
262 #define COP2 27 // Coprocessor 2 move
263 #define C2LS 28 // Coprocessor 2 load/store
264 #define C2OP 29 // Coprocessor 2 operation
265 #define INTCALL 30// Call interpreter to handle rare corner cases
272 #define DJT_1 (void *)1l // no function, just a label in assem_debug log
273 #define DJT_2 (void *)2l
276 int new_recompile_block(u_int addr);
277 void *get_addr_ht(u_int vaddr);
278 void invalidate_block(u_int block);
279 void invalidate_addr(u_int addr);
280 void remove_hash(int vaddr);
282 void dyna_linker_ds();
284 void verify_code_ds();
287 void fp_exception_ds();
288 void jump_to_new_pc();
289 void new_dyna_leave();
291 // Needed by assembler
292 static void wb_register(signed char r,signed char regmap[],uint64_t dirty);
293 static void wb_dirtys(signed char i_regmap[],uint64_t i_dirty);
294 static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_dirty,int addr);
295 static void load_all_regs(signed char i_regmap[]);
296 static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
297 static void load_regs_entry(int t);
298 static void load_all_consts(signed char regmap[],u_int dirty,int i);
300 static int verify_dirty(const u_int *ptr);
301 static int get_final_value(int hr, int i, int *value);
302 static void add_stub(enum stub_type type, void *addr, void *retaddr,
303 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
304 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
305 int i, int addr_reg, struct regstat *i_regs, int ccadj, u_int reglist);
306 static void add_to_linker(void *addr, u_int target, int ext);
307 static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override);
308 static void *get_direct_memhandler(void *table, u_int addr,
309 enum stub_type type, uintptr_t *addr_host);
310 static void pass_args(int a0, int a1);
312 static void mprotect_w_x(void *start, void *end, int is_x)
316 // *Open* enables write on all memory that was
317 // allocated by sceKernelAllocMemBlockForVM()?
319 sceKernelCloseVMDomain();
321 sceKernelOpenVMDomain();
323 u_long mstart = (u_long)start & ~4095ul;
324 u_long mend = (u_long)end;
325 if (mprotect((void *)mstart, mend - mstart,
326 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
327 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
332 static void start_tcache_write(void *start, void *end)
334 mprotect_w_x(start, end, 0);
337 static void end_tcache_write(void *start, void *end)
340 size_t len = (char *)end - (char *)start;
341 #if defined(__BLACKBERRY_QNX__)
342 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
343 #elif defined(__MACH__)
344 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
346 sceKernelSyncVMDomain(sceBlock, start, len);
348 ctr_flush_invalidate_cache();
350 __clear_cache(start, end);
354 __clear_cache(start, end);
357 mprotect_w_x(start, end, 1);
360 static void *start_block(void)
362 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
363 if (end > translation_cache + (1<<TARGET_SIZE_2))
364 end = translation_cache + (1<<TARGET_SIZE_2);
365 start_tcache_write(out, end);
369 static void end_block(void *start)
371 end_tcache_write(start, out);
374 //#define DEBUG_CYCLE_COUNT 1
376 #define NO_CYCLE_PENALTY_THR 12
378 int cycle_multiplier; // 100 for 1.0
380 static int CLOCK_ADJUST(int x)
383 return (x * cycle_multiplier + s * 50) / 100;
386 static u_int get_page(u_int vaddr)
388 u_int page=vaddr&~0xe0000000;
389 if (page < 0x1000000)
390 page &= ~0x0e00000; // RAM mirrors
392 if(page>2048) page=2048+(page&2047);
396 // no virtual mem in PCSX
397 static u_int get_vpage(u_int vaddr)
399 return get_page(vaddr);
402 static struct ht_entry *hash_table_get(u_int vaddr)
404 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
407 static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr)
409 ht_bin->vaddr[1] = ht_bin->vaddr[0];
410 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
411 ht_bin->vaddr[0] = vaddr;
412 ht_bin->tcaddr[0] = tcaddr;
415 // some messy ari64's code, seems to rely on unsigned 32bit overflow
416 static int doesnt_expire_soon(void *tcaddr)
418 u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2);
419 return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2)));
422 // Get address from virtual address
423 // This is called from the recompiled JR/JALR instructions
424 void noinline *get_addr(u_int vaddr)
426 u_int page=get_page(vaddr);
427 u_int vpage=get_vpage(vaddr);
428 struct ll_entry *head;
429 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
432 if(head->vaddr==vaddr) {
433 //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr);
434 hash_table_add(hash_table_get(vaddr), vaddr, head->addr);
439 head=jump_dirty[vpage];
441 if(head->vaddr==vaddr) {
442 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr);
443 // Don't restore blocks which are about to expire from the cache
444 if (doesnt_expire_soon(head->addr))
445 if (verify_dirty(head->addr)) {
446 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
447 invalid_code[vaddr>>12]=0;
448 inv_code_start=inv_code_end=~0;
450 restore_candidate[vpage>>3]|=1<<(vpage&7);
452 else restore_candidate[page>>3]|=1<<(page&7);
453 struct ht_entry *ht_bin = hash_table_get(vaddr);
454 if (ht_bin->vaddr[0] == vaddr)
455 ht_bin->tcaddr[0] = head->addr; // Replace existing entry
457 hash_table_add(ht_bin, vaddr, head->addr);
464 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
465 int r=new_recompile_block(vaddr);
466 if(r==0) return get_addr(vaddr);
467 // Execute in unmapped page, generate pagefault execption
469 Cause=(vaddr<<31)|0x8;
470 EPC=(vaddr&1)?vaddr-5:vaddr;
472 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
473 EntryHi=BadVAddr&0xFFFFE000;
474 return get_addr_ht(0x80000000);
476 // Look up address in hash table first
477 void *get_addr_ht(u_int vaddr)
479 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
480 const struct ht_entry *ht_bin = hash_table_get(vaddr);
481 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
482 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
483 return get_addr(vaddr);
486 void clear_all_regs(signed char regmap[])
489 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
492 static signed char get_reg(const signed char regmap[],int r)
495 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
499 // Find a register that is available for two consecutive cycles
500 static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
503 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
507 int count_free_regs(signed char regmap[])
511 for(hr=0;hr<HOST_REGS;hr++)
513 if(hr!=EXCLUDE_REG) {
514 if(regmap[hr]<0) count++;
520 void dirty_reg(struct regstat *cur,signed char reg)
524 for (hr=0;hr<HOST_REGS;hr++) {
525 if((cur->regmap[hr]&63)==reg) {
531 void set_const(struct regstat *cur,signed char reg,uint64_t value)
535 for (hr=0;hr<HOST_REGS;hr++) {
536 if(cur->regmap[hr]==reg) {
538 current_constmap[hr]=value;
543 void clear_const(struct regstat *cur,signed char reg)
547 for (hr=0;hr<HOST_REGS;hr++) {
548 if((cur->regmap[hr]&63)==reg) {
549 cur->isconst&=~(1<<hr);
554 int is_const(struct regstat *cur,signed char reg)
559 for (hr=0;hr<HOST_REGS;hr++) {
560 if((cur->regmap[hr]&63)==reg) {
561 return (cur->isconst>>hr)&1;
566 uint64_t get_const(struct regstat *cur,signed char reg)
570 for (hr=0;hr<HOST_REGS;hr++) {
571 if(cur->regmap[hr]==reg) {
572 return current_constmap[hr];
575 SysPrintf("Unknown constant in r%d\n",reg);
579 // Least soon needed registers
580 // Look at the next ten instructions and see which registers
581 // will be used. Try not to reallocate these.
582 void lsn(u_char hsn[], int i, int *preferred_reg)
592 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
594 // Don't go past an unconditonal jump
601 if(rs1[i+j]) hsn[rs1[i+j]]=j;
602 if(rs2[i+j]) hsn[rs2[i+j]]=j;
603 if(rt1[i+j]) hsn[rt1[i+j]]=j;
604 if(rt2[i+j]) hsn[rt2[i+j]]=j;
605 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
606 // Stores can allocate zero
610 // On some architectures stores need invc_ptr
611 #if defined(HOST_IMM8)
612 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
616 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP))
624 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
626 // Follow first branch
627 int t=(ba[i+b]-start)>>2;
628 j=7-b;if(t+j>=slen) j=slen-t-1;
631 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
632 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
633 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
634 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
637 // TODO: preferred register based on backward branch
639 // Delay slot should preferably not overwrite branch conditions or cycle count
640 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP)) {
641 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
642 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
648 // Coprocessor load/store needs FTEMP, even if not declared
649 if(itype[i]==C1LS||itype[i]==C2LS) {
652 // Load L/R also uses FTEMP as a temporary register
653 if(itype[i]==LOADLR) {
656 // Also SWL/SWR/SDL/SDR
657 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
660 // Don't remove the miniht registers
661 if(itype[i]==UJUMP||itype[i]==RJUMP)
668 // We only want to allocate registers if we're going to use them again soon
669 int needed_again(int r, int i)
675 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
677 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
678 return 0; // Don't need any registers if exiting the block
686 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
688 // Don't go past an unconditonal jump
692 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
699 if(rs1[i+j]==r) rn=j;
700 if(rs2[i+j]==r) rn=j;
701 if((unneeded_reg[i+j]>>r)&1) rn=10;
702 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP))
710 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
712 // Follow first branch
714 int t=(ba[i+b]-start)>>2;
715 j=7-b;if(t+j>=slen) j=slen-t-1;
718 if(!((unneeded_reg[t+j]>>r)&1)) {
719 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
720 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
731 // Try to match register allocations at the end of a loop with those
733 int loop_reg(int i, int r, int hr)
742 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
744 // Don't go past an unconditonal jump
751 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP)
757 if((unneeded_reg[i+k]>>r)&1) return hr;
758 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP))
760 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
762 int t=(ba[i+k]-start)>>2;
763 int reg=get_reg(regs[t].regmap_entry,r);
764 if(reg>=0) return reg;
765 //reg=get_reg(regs[t+1].regmap_entry,r);
766 //if(reg>=0) return reg;
774 // Allocate every register, preserving source/target regs
775 void alloc_all(struct regstat *cur,int i)
779 for(hr=0;hr<HOST_REGS;hr++) {
780 if(hr!=EXCLUDE_REG) {
781 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
782 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
785 cur->dirty&=~(1<<hr);
788 if((cur->regmap[hr]&63)==0)
791 cur->dirty&=~(1<<hr);
798 static int host_tempreg_in_use;
800 static void host_tempreg_acquire(void)
802 assert(!host_tempreg_in_use);
803 host_tempreg_in_use = 1;
806 static void host_tempreg_release(void)
808 host_tempreg_in_use = 0;
811 static void host_tempreg_acquire(void) {}
812 static void host_tempreg_release(void) {}
816 extern void gen_interupt();
817 extern void do_insn_cmp();
818 #define FUNCNAME(f) { f, " " #f }
819 static const struct {
822 } function_names[] = {
823 FUNCNAME(cc_interrupt),
824 FUNCNAME(gen_interupt),
825 FUNCNAME(get_addr_ht),
827 FUNCNAME(jump_handler_read8),
828 FUNCNAME(jump_handler_read16),
829 FUNCNAME(jump_handler_read32),
830 FUNCNAME(jump_handler_write8),
831 FUNCNAME(jump_handler_write16),
832 FUNCNAME(jump_handler_write32),
833 FUNCNAME(invalidate_addr),
834 FUNCNAME(jump_to_new_pc),
835 FUNCNAME(new_dyna_leave),
837 FUNCNAME(pcsx_mtc0_ds),
838 FUNCNAME(do_insn_cmp),
840 FUNCNAME(verify_code),
844 static const char *func_name(const void *a)
847 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
848 if (function_names[i].addr == a)
849 return function_names[i].name;
853 #define func_name(x) ""
857 #include "assem_x86.c"
860 #include "assem_x64.c"
863 #include "assem_arm.c"
866 #include "assem_arm64.c"
869 // Add virtual address mapping to linked list
870 void ll_add(struct ll_entry **head,int vaddr,void *addr)
872 struct ll_entry *new_entry;
873 new_entry=malloc(sizeof(struct ll_entry));
874 assert(new_entry!=NULL);
875 new_entry->vaddr=vaddr;
876 new_entry->reg_sv_flags=0;
877 new_entry->addr=addr;
878 new_entry->next=*head;
882 void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
884 ll_add(head,vaddr,addr);
885 (*head)->reg_sv_flags=reg_sv_flags;
888 // Check if an address is already compiled
889 // but don't return addresses which are about to expire from the cache
890 void *check_addr(u_int vaddr)
892 struct ht_entry *ht_bin = hash_table_get(vaddr);
894 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
895 if (ht_bin->vaddr[i] == vaddr)
896 if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE))
897 if (isclean(ht_bin->tcaddr[i]))
898 return ht_bin->tcaddr[i];
900 u_int page=get_page(vaddr);
901 struct ll_entry *head;
903 while (head != NULL) {
904 if (head->vaddr == vaddr) {
905 if (doesnt_expire_soon(head->addr)) {
906 // Update existing entry with current address
907 if (ht_bin->vaddr[0] == vaddr) {
908 ht_bin->tcaddr[0] = head->addr;
911 if (ht_bin->vaddr[1] == vaddr) {
912 ht_bin->tcaddr[1] = head->addr;
915 // Insert into hash table with low priority.
916 // Don't evict existing entries, as they are probably
917 // addresses that are being accessed frequently.
918 if (ht_bin->vaddr[0] == -1) {
919 ht_bin->vaddr[0] = vaddr;
920 ht_bin->tcaddr[0] = head->addr;
922 else if (ht_bin->vaddr[1] == -1) {
923 ht_bin->vaddr[1] = vaddr;
924 ht_bin->tcaddr[1] = head->addr;
934 void remove_hash(int vaddr)
936 //printf("remove hash: %x\n",vaddr);
937 struct ht_entry *ht_bin = hash_table_get(vaddr);
938 if (ht_bin->vaddr[1] == vaddr) {
939 ht_bin->vaddr[1] = -1;
940 ht_bin->tcaddr[1] = NULL;
942 if (ht_bin->vaddr[0] == vaddr) {
943 ht_bin->vaddr[0] = ht_bin->vaddr[1];
944 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
945 ht_bin->vaddr[1] = -1;
946 ht_bin->tcaddr[1] = NULL;
950 void ll_remove_matching_addrs(struct ll_entry **head,uintptr_t addr,int shift)
952 struct ll_entry *next;
954 if(((uintptr_t)((*head)->addr)>>shift)==(addr>>shift) ||
955 ((uintptr_t)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
957 inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr);
958 remove_hash((*head)->vaddr);
965 head=&((*head)->next);
970 // Remove all entries from linked list
971 void ll_clear(struct ll_entry **head)
973 struct ll_entry *cur;
974 struct ll_entry *next;
985 // Dereference the pointers and remove if it matches
986 static void ll_kill_pointers(struct ll_entry *head,uintptr_t addr,int shift)
989 uintptr_t ptr = (uintptr_t)get_pointer(head->addr);
990 inv_debug("EXP: Lookup pointer to %lx at %p (%x)\n",(long)ptr,head->addr,head->vaddr);
991 if(((ptr>>shift)==(addr>>shift)) ||
992 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
994 inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
995 void *host_addr=find_extjump_insn(head->addr);
996 #if defined(__arm__) || defined(__aarch64__)
997 mark_clear_cache(host_addr);
999 set_jump_target(host_addr, head->addr);
1005 // This is called when we write to a compiled block (see do_invstub)
1006 static void invalidate_page(u_int page)
1008 struct ll_entry *head;
1009 struct ll_entry *next;
1013 inv_debug("INVALIDATE: %x\n",head->vaddr);
1014 remove_hash(head->vaddr);
1019 head=jump_out[page];
1022 inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr);
1023 void *host_addr=find_extjump_insn(head->addr);
1024 #if defined(__arm__) || defined(__aarch64__)
1025 mark_clear_cache(host_addr);
1027 set_jump_target(host_addr, head->addr);
1034 static void invalidate_block_range(u_int block, u_int first, u_int last)
1036 u_int page=get_page(block<<12);
1037 //printf("first=%d last=%d\n",first,last);
1038 invalidate_page(page);
1039 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1040 assert(last<page+5);
1041 // Invalidate the adjacent pages if a block crosses a 4K boundary
1043 invalidate_page(first);
1046 for(first=page+1;first<last;first++) {
1047 invalidate_page(first);
1049 #if defined(__arm__) || defined(__aarch64__)
1053 // Don't trap writes
1054 invalid_code[block]=1;
1057 memset(mini_ht,-1,sizeof(mini_ht));
1061 void invalidate_block(u_int block)
1063 u_int page=get_page(block<<12);
1064 u_int vpage=get_vpage(block<<12);
1065 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1066 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1069 struct ll_entry *head;
1070 head=jump_dirty[vpage];
1071 //printf("page=%d vpage=%d\n",page,vpage);
1073 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1074 u_char *start, *end;
1075 get_bounds(head->addr, &start, &end);
1076 //printf("start: %p end: %p\n", start, end);
1077 if (page < 2048 && start >= rdram && end < rdram+RAM_SIZE) {
1078 if (((start-rdram)>>12) <= page && ((end-1-rdram)>>12) >= page) {
1079 if ((((start-rdram)>>12)&2047) < first) first = ((start-rdram)>>12)&2047;
1080 if ((((end-1-rdram)>>12)&2047) > last) last = ((end-1-rdram)>>12)&2047;
1086 invalidate_block_range(block,first,last);
1089 void invalidate_addr(u_int addr)
1092 // this check is done by the caller
1093 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1094 u_int page=get_vpage(addr);
1095 if(page<2048) { // RAM
1096 struct ll_entry *head;
1097 u_int addr_min=~0, addr_max=0;
1098 u_int mask=RAM_SIZE-1;
1099 u_int addr_main=0x80000000|(addr&mask);
1101 inv_code_start=addr_main&~0xfff;
1102 inv_code_end=addr_main|0xfff;
1105 // must check previous page too because of spans..
1107 inv_code_start-=0x1000;
1109 for(;pg1<=page;pg1++) {
1110 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1111 u_char *start_h, *end_h;
1113 get_bounds(head->addr, &start_h, &end_h);
1114 start = (uintptr_t)start_h - ram_offset;
1115 end = (uintptr_t)end_h - ram_offset;
1116 if(start<=addr_main&&addr_main<end) {
1117 if(start<addr_min) addr_min=start;
1118 if(end>addr_max) addr_max=end;
1120 else if(addr_main<start) {
1121 if(start<inv_code_end)
1122 inv_code_end=start-1;
1125 if(end>inv_code_start)
1131 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1132 inv_code_start=inv_code_end=~0;
1133 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1137 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1138 inv_code_end=(addr&~mask)|(inv_code_end&mask);
1139 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1143 invalidate_block(addr>>12);
1146 // This is called when loading a save state.
1147 // Anything could have changed, so invalidate everything.
1148 void invalidate_all_pages()
1151 for(page=0;page<4096;page++)
1152 invalidate_page(page);
1153 for(page=0;page<1048576;page++)
1154 if(!invalid_code[page]) {
1155 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1156 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1159 memset(mini_ht,-1,sizeof(mini_ht));
1163 static void do_invstub(int n)
1166 u_int reglist=stubs[n].a;
1167 set_jump_target(stubs[n].addr, out);
1169 if(stubs[n].b!=0) emit_mov(stubs[n].b,0);
1170 emit_call(invalidate_addr);
1171 restore_regs(reglist);
1172 emit_jmp(stubs[n].retaddr); // return address
1175 // Add an entry to jump_out after making a link
1176 // src should point to code by emit_extjump2()
1177 void add_link(u_int vaddr,void *src)
1179 u_int page=get_page(vaddr);
1180 inv_debug("add_link: %p -> %x (%d)\n",src,vaddr,page);
1181 check_extjump2(src);
1182 ll_add(jump_out+page,vaddr,src);
1183 //void *ptr=get_pointer(src);
1184 //inv_debug("add_link: Pointer is to %p\n",ptr);
1187 // If a code block was found to be unmodified (bit was set in
1188 // restore_candidate) and it remains unmodified (bit is clear
1189 // in invalid_code) then move the entries for that 4K page from
1190 // the dirty list to the clean list.
1191 void clean_blocks(u_int page)
1193 struct ll_entry *head;
1194 inv_debug("INV: clean_blocks page=%d\n",page);
1195 head=jump_dirty[page];
1197 if(!invalid_code[head->vaddr>>12]) {
1198 // Don't restore blocks which are about to expire from the cache
1199 if (doesnt_expire_soon(head->addr)) {
1200 if(verify_dirty(head->addr)) {
1201 u_char *start, *end;
1202 //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr);
1205 get_bounds(head->addr, &start, &end);
1206 if (start - rdram < RAM_SIZE) {
1207 for (i = (start-rdram+0x80000000)>>12; i <= (end-1-rdram+0x80000000)>>12; i++) {
1208 inv|=invalid_code[i];
1211 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1215 void *clean_addr = get_clean_addr(head->addr);
1216 if (doesnt_expire_soon(clean_addr)) {
1218 inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr);
1219 //printf("page=%x, addr=%x\n",page,head->vaddr);
1220 //assert(head->vaddr>>12==(page|0x80000));
1221 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
1222 struct ht_entry *ht_bin = hash_table_get(head->vaddr);
1223 if (ht_bin->vaddr[0] == head->vaddr)
1224 ht_bin->tcaddr[0] = clean_addr; // Replace existing entry
1225 if (ht_bin->vaddr[1] == head->vaddr)
1226 ht_bin->tcaddr[1] = clean_addr; // Replace existing entry
1236 /* Register allocation */
1238 // Note: registers are allocated clean (unmodified state)
1239 // if you intend to modify the register, you must call dirty_reg().
1240 static void alloc_reg(struct regstat *cur,int i,signed char reg)
1243 int preferred_reg = (reg&7);
1244 if(reg==CCREG) preferred_reg=HOST_CCREG;
1245 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
1247 // Don't allocate unused registers
1248 if((cur->u>>reg)&1) return;
1250 // see if it's already allocated
1251 for(hr=0;hr<HOST_REGS;hr++)
1253 if(cur->regmap[hr]==reg) return;
1256 // Keep the same mapping if the register was already allocated in a loop
1257 preferred_reg = loop_reg(i,reg,preferred_reg);
1259 // Try to allocate the preferred register
1260 if(cur->regmap[preferred_reg]==-1) {
1261 cur->regmap[preferred_reg]=reg;
1262 cur->dirty&=~(1<<preferred_reg);
1263 cur->isconst&=~(1<<preferred_reg);
1266 r=cur->regmap[preferred_reg];
1269 cur->regmap[preferred_reg]=reg;
1270 cur->dirty&=~(1<<preferred_reg);
1271 cur->isconst&=~(1<<preferred_reg);
1275 // Clear any unneeded registers
1276 // We try to keep the mapping consistent, if possible, because it
1277 // makes branches easier (especially loops). So we try to allocate
1278 // first (see above) before removing old mappings. If this is not
1279 // possible then go ahead and clear out the registers that are no
1281 for(hr=0;hr<HOST_REGS;hr++)
1286 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1289 // Try to allocate any available register, but prefer
1290 // registers that have not been used recently.
1292 for(hr=0;hr<HOST_REGS;hr++) {
1293 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1294 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
1295 cur->regmap[hr]=reg;
1296 cur->dirty&=~(1<<hr);
1297 cur->isconst&=~(1<<hr);
1303 // Try to allocate any available register
1304 for(hr=0;hr<HOST_REGS;hr++) {
1305 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1306 cur->regmap[hr]=reg;
1307 cur->dirty&=~(1<<hr);
1308 cur->isconst&=~(1<<hr);
1313 // Ok, now we have to evict someone
1314 // Pick a register we hopefully won't need soon
1315 u_char hsn[MAXREG+1];
1316 memset(hsn,10,sizeof(hsn));
1318 lsn(hsn,i,&preferred_reg);
1319 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1320 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1322 // Don't evict the cycle count at entry points, otherwise the entry
1323 // stub will have to write it.
1324 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
1325 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP)) hsn[CCREG]=2;
1328 // Alloc preferred register if available
1329 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1330 for(hr=0;hr<HOST_REGS;hr++) {
1331 // Evict both parts of a 64-bit register
1332 if((cur->regmap[hr]&63)==r) {
1334 cur->dirty&=~(1<<hr);
1335 cur->isconst&=~(1<<hr);
1338 cur->regmap[preferred_reg]=reg;
1341 for(r=1;r<=MAXREG;r++)
1343 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
1344 for(hr=0;hr<HOST_REGS;hr++) {
1345 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1346 if(cur->regmap[hr]==r) {
1347 cur->regmap[hr]=reg;
1348 cur->dirty&=~(1<<hr);
1349 cur->isconst&=~(1<<hr);
1360 for(r=1;r<=MAXREG;r++)
1363 for(hr=0;hr<HOST_REGS;hr++) {
1364 if(cur->regmap[hr]==r) {
1365 cur->regmap[hr]=reg;
1366 cur->dirty&=~(1<<hr);
1367 cur->isconst&=~(1<<hr);
1374 SysPrintf("This shouldn't happen (alloc_reg)");abort();
1377 // Allocate a temporary register. This is done without regard to
1378 // dirty status or whether the register we request is on the unneeded list
1379 // Note: This will only allocate one register, even if called multiple times
1380 static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1383 int preferred_reg = -1;
1385 // see if it's already allocated
1386 for(hr=0;hr<HOST_REGS;hr++)
1388 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1391 // Try to allocate any available register
1392 for(hr=HOST_REGS-1;hr>=0;hr--) {
1393 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1394 cur->regmap[hr]=reg;
1395 cur->dirty&=~(1<<hr);
1396 cur->isconst&=~(1<<hr);
1401 // Find an unneeded register
1402 for(hr=HOST_REGS-1;hr>=0;hr--)
1408 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1409 cur->regmap[hr]=reg;
1410 cur->dirty&=~(1<<hr);
1411 cur->isconst&=~(1<<hr);
1418 // Ok, now we have to evict someone
1419 // Pick a register we hopefully won't need soon
1420 // TODO: we might want to follow unconditional jumps here
1421 // TODO: get rid of dupe code and make this into a function
1422 u_char hsn[MAXREG+1];
1423 memset(hsn,10,sizeof(hsn));
1425 lsn(hsn,i,&preferred_reg);
1426 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1428 // Don't evict the cycle count at entry points, otherwise the entry
1429 // stub will have to write it.
1430 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
1431 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP)) hsn[CCREG]=2;
1434 for(r=1;r<=MAXREG;r++)
1436 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
1437 for(hr=0;hr<HOST_REGS;hr++) {
1438 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1439 if(cur->regmap[hr]==r) {
1440 cur->regmap[hr]=reg;
1441 cur->dirty&=~(1<<hr);
1442 cur->isconst&=~(1<<hr);
1453 for(r=1;r<=MAXREG;r++)
1456 for(hr=0;hr<HOST_REGS;hr++) {
1457 if(cur->regmap[hr]==r) {
1458 cur->regmap[hr]=reg;
1459 cur->dirty&=~(1<<hr);
1460 cur->isconst&=~(1<<hr);
1467 SysPrintf("This shouldn't happen");abort();
1470 static void mov_alloc(struct regstat *current,int i)
1472 // Note: Don't need to actually alloc the source registers
1473 //alloc_reg(current,i,rs1[i]);
1474 alloc_reg(current,i,rt1[i]);
1476 clear_const(current,rs1[i]);
1477 clear_const(current,rt1[i]);
1478 dirty_reg(current,rt1[i]);
1481 static void shiftimm_alloc(struct regstat *current,int i)
1483 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1486 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1488 alloc_reg(current,i,rt1[i]);
1489 dirty_reg(current,rt1[i]);
1490 if(is_const(current,rs1[i])) {
1491 int v=get_const(current,rs1[i]);
1492 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1493 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1494 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1496 else clear_const(current,rt1[i]);
1501 clear_const(current,rs1[i]);
1502 clear_const(current,rt1[i]);
1505 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1509 if(opcode2[i]==0x3c) // DSLL32
1513 if(opcode2[i]==0x3e) // DSRL32
1517 if(opcode2[i]==0x3f) // DSRA32
1523 static void shift_alloc(struct regstat *current,int i)
1526 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1528 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1529 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1530 alloc_reg(current,i,rt1[i]);
1531 if(rt1[i]==rs2[i]) {
1532 alloc_reg_temp(current,i,-1);
1533 minimum_free_regs[i]=1;
1535 } else { // DSLLV/DSRLV/DSRAV
1538 clear_const(current,rs1[i]);
1539 clear_const(current,rs2[i]);
1540 clear_const(current,rt1[i]);
1541 dirty_reg(current,rt1[i]);
1545 static void alu_alloc(struct regstat *current,int i)
1547 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1549 if(rs1[i]&&rs2[i]) {
1550 alloc_reg(current,i,rs1[i]);
1551 alloc_reg(current,i,rs2[i]);
1554 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1555 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1557 alloc_reg(current,i,rt1[i]);
1560 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1562 alloc_reg(current,i,rs1[i]);
1563 alloc_reg(current,i,rs2[i]);
1564 alloc_reg(current,i,rt1[i]);
1567 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1569 if(rs1[i]&&rs2[i]) {
1570 alloc_reg(current,i,rs1[i]);
1571 alloc_reg(current,i,rs2[i]);
1575 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1576 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1578 alloc_reg(current,i,rt1[i]);
1581 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1584 clear_const(current,rs1[i]);
1585 clear_const(current,rs2[i]);
1586 clear_const(current,rt1[i]);
1587 dirty_reg(current,rt1[i]);
1590 static void imm16_alloc(struct regstat *current,int i)
1592 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1594 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1595 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1598 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1599 clear_const(current,rs1[i]);
1600 clear_const(current,rt1[i]);
1602 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1603 if(is_const(current,rs1[i])) {
1604 int v=get_const(current,rs1[i]);
1605 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1606 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1607 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1609 else clear_const(current,rt1[i]);
1611 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1612 if(is_const(current,rs1[i])) {
1613 int v=get_const(current,rs1[i]);
1614 set_const(current,rt1[i],v+imm[i]);
1616 else clear_const(current,rt1[i]);
1619 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1621 dirty_reg(current,rt1[i]);
1624 static void load_alloc(struct regstat *current,int i)
1626 clear_const(current,rt1[i]);
1627 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1628 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1629 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1630 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1631 alloc_reg(current,i,rt1[i]);
1632 assert(get_reg(current->regmap,rt1[i])>=0);
1633 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1637 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1641 dirty_reg(current,rt1[i]);
1642 // LWL/LWR need a temporary register for the old value
1643 if(opcode[i]==0x22||opcode[i]==0x26)
1645 alloc_reg(current,i,FTEMP);
1646 alloc_reg_temp(current,i,-1);
1647 minimum_free_regs[i]=1;
1652 // Load to r0 or unneeded register (dummy load)
1653 // but we still need a register to calculate the address
1654 if(opcode[i]==0x22||opcode[i]==0x26)
1656 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1658 alloc_reg_temp(current,i,-1);
1659 minimum_free_regs[i]=1;
1660 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1667 void store_alloc(struct regstat *current,int i)
1669 clear_const(current,rs2[i]);
1670 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1671 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1672 alloc_reg(current,i,rs2[i]);
1673 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1676 #if defined(HOST_IMM8)
1677 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1678 else alloc_reg(current,i,INVCP);
1680 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1681 alloc_reg(current,i,FTEMP);
1683 // We need a temporary register for address generation
1684 alloc_reg_temp(current,i,-1);
1685 minimum_free_regs[i]=1;
1688 void c1ls_alloc(struct regstat *current,int i)
1690 //clear_const(current,rs1[i]); // FIXME
1691 clear_const(current,rt1[i]);
1692 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1693 alloc_reg(current,i,CSREG); // Status
1694 alloc_reg(current,i,FTEMP);
1695 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1698 #if defined(HOST_IMM8)
1699 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1700 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1701 alloc_reg(current,i,INVCP);
1703 // We need a temporary register for address generation
1704 alloc_reg_temp(current,i,-1);
1707 void c2ls_alloc(struct regstat *current,int i)
1709 clear_const(current,rt1[i]);
1710 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1711 alloc_reg(current,i,FTEMP);
1712 #if defined(HOST_IMM8)
1713 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1714 if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1715 alloc_reg(current,i,INVCP);
1717 // We need a temporary register for address generation
1718 alloc_reg_temp(current,i,-1);
1719 minimum_free_regs[i]=1;
1722 #ifndef multdiv_alloc
1723 void multdiv_alloc(struct regstat *current,int i)
1730 // case 0x1D: DMULTU
1733 clear_const(current,rs1[i]);
1734 clear_const(current,rs2[i]);
1737 if((opcode2[i]&4)==0) // 32-bit
1739 current->u&=~(1LL<<HIREG);
1740 current->u&=~(1LL<<LOREG);
1741 alloc_reg(current,i,HIREG);
1742 alloc_reg(current,i,LOREG);
1743 alloc_reg(current,i,rs1[i]);
1744 alloc_reg(current,i,rs2[i]);
1745 dirty_reg(current,HIREG);
1746 dirty_reg(current,LOREG);
1755 // Multiply by zero is zero.
1756 // MIPS does not have a divide by zero exception.
1757 // The result is undefined, we return zero.
1758 alloc_reg(current,i,HIREG);
1759 alloc_reg(current,i,LOREG);
1760 dirty_reg(current,HIREG);
1761 dirty_reg(current,LOREG);
1766 void cop0_alloc(struct regstat *current,int i)
1768 if(opcode2[i]==0) // MFC0
1771 clear_const(current,rt1[i]);
1772 alloc_all(current,i);
1773 alloc_reg(current,i,rt1[i]);
1774 dirty_reg(current,rt1[i]);
1777 else if(opcode2[i]==4) // MTC0
1780 clear_const(current,rs1[i]);
1781 alloc_reg(current,i,rs1[i]);
1782 alloc_all(current,i);
1785 alloc_all(current,i); // FIXME: Keep r0
1787 alloc_reg(current,i,0);
1792 // TLBR/TLBWI/TLBWR/TLBP/ERET
1793 assert(opcode2[i]==0x10);
1794 alloc_all(current,i);
1796 minimum_free_regs[i]=HOST_REGS;
1799 static void cop12_alloc(struct regstat *current,int i)
1801 alloc_reg(current,i,CSREG); // Load status
1802 if(opcode2[i]<3) // MFC1/CFC1
1805 clear_const(current,rt1[i]);
1806 alloc_reg(current,i,rt1[i]);
1807 dirty_reg(current,rt1[i]);
1809 alloc_reg_temp(current,i,-1);
1811 else if(opcode2[i]>3) // MTC1/CTC1
1814 clear_const(current,rs1[i]);
1815 alloc_reg(current,i,rs1[i]);
1819 alloc_reg(current,i,0);
1821 alloc_reg_temp(current,i,-1);
1823 minimum_free_regs[i]=1;
1826 void c2op_alloc(struct regstat *current,int i)
1828 alloc_reg_temp(current,i,-1);
1831 void syscall_alloc(struct regstat *current,int i)
1833 alloc_cc(current,i);
1834 dirty_reg(current,CCREG);
1835 alloc_all(current,i);
1836 minimum_free_regs[i]=HOST_REGS;
1840 void delayslot_alloc(struct regstat *current,int i)
1850 assem_debug("jump in the delay slot. this shouldn't happen.\n");//abort();
1851 SysPrintf("Disabled speculative precompilation\n");
1855 imm16_alloc(current,i);
1859 load_alloc(current,i);
1863 store_alloc(current,i);
1866 alu_alloc(current,i);
1869 shift_alloc(current,i);
1872 multdiv_alloc(current,i);
1875 shiftimm_alloc(current,i);
1878 mov_alloc(current,i);
1881 cop0_alloc(current,i);
1885 cop12_alloc(current,i);
1888 c1ls_alloc(current,i);
1891 c2ls_alloc(current,i);
1894 c2op_alloc(current,i);
1899 // Special case where a branch and delay slot span two pages in virtual memory
1900 static void pagespan_alloc(struct regstat *current,int i)
1903 current->wasconst=0;
1905 minimum_free_regs[i]=HOST_REGS;
1906 alloc_all(current,i);
1907 alloc_cc(current,i);
1908 dirty_reg(current,CCREG);
1909 if(opcode[i]==3) // JAL
1911 alloc_reg(current,i,31);
1912 dirty_reg(current,31);
1914 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1916 alloc_reg(current,i,rs1[i]);
1918 alloc_reg(current,i,rt1[i]);
1919 dirty_reg(current,rt1[i]);
1922 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1924 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1925 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1928 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1930 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1935 static void add_stub(enum stub_type type, void *addr, void *retaddr,
1936 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
1938 assert(stubcount < ARRAY_SIZE(stubs));
1939 stubs[stubcount].type = type;
1940 stubs[stubcount].addr = addr;
1941 stubs[stubcount].retaddr = retaddr;
1942 stubs[stubcount].a = a;
1943 stubs[stubcount].b = b;
1944 stubs[stubcount].c = c;
1945 stubs[stubcount].d = d;
1946 stubs[stubcount].e = e;
1950 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
1951 int i, int addr_reg, struct regstat *i_regs, int ccadj, u_int reglist)
1953 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
1956 // Write out a single register
1957 static void wb_register(signed char r,signed char regmap[],uint64_t dirty)
1960 for(hr=0;hr<HOST_REGS;hr++) {
1961 if(hr!=EXCLUDE_REG) {
1962 if((regmap[hr]&63)==r) {
1964 assert(regmap[hr]<64);
1965 emit_storereg(r,hr);
1972 static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
1974 //if(dirty_pre==dirty) return;
1976 for(hr=0;hr<HOST_REGS;hr++) {
1977 if(hr!=EXCLUDE_REG) {
1979 if(((~u)>>(reg&63))&1) {
1981 if(((dirty_pre&~dirty)>>hr)&1) {
1983 emit_storereg(reg,hr);
1996 static void pass_args(int a0, int a1)
2000 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2002 else if(a0!=0&&a1==0) {
2004 if (a0>=0) emit_mov(a0,0);
2007 if(a0>=0&&a0!=0) emit_mov(a0,0);
2008 if(a1>=0&&a1!=1) emit_mov(a1,1);
2012 static void alu_assemble(int i,struct regstat *i_regs)
2014 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2016 signed char s1,s2,t;
2017 t=get_reg(i_regs->regmap,rt1[i]);
2019 s1=get_reg(i_regs->regmap,rs1[i]);
2020 s2=get_reg(i_regs->regmap,rs2[i]);
2021 if(rs1[i]&&rs2[i]) {
2024 if(opcode2[i]&2) emit_sub(s1,s2,t);
2025 else emit_add(s1,s2,t);
2028 if(s1>=0) emit_mov(s1,t);
2029 else emit_loadreg(rs1[i],t);
2033 if(opcode2[i]&2) emit_neg(s2,t);
2034 else emit_mov(s2,t);
2037 emit_loadreg(rs2[i],t);
2038 if(opcode2[i]&2) emit_neg(t,t);
2041 else emit_zeroreg(t);
2045 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2048 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2050 signed char s1l,s2l,t;
2052 t=get_reg(i_regs->regmap,rt1[i]);
2055 s1l=get_reg(i_regs->regmap,rs1[i]);
2056 s2l=get_reg(i_regs->regmap,rs2[i]);
2057 if(rs2[i]==0) // rx<r0
2060 if(opcode2[i]==0x2a) // SLT
2061 emit_shrimm(s1l,31,t);
2062 else // SLTU (unsigned can not be less than zero)
2065 else if(rs1[i]==0) // r0<rx
2068 if(opcode2[i]==0x2a) // SLT
2069 emit_set_gz32(s2l,t);
2070 else // SLTU (set if not zero)
2071 emit_set_nz32(s2l,t);
2074 assert(s1l>=0);assert(s2l>=0);
2075 if(opcode2[i]==0x2a) // SLT
2076 emit_set_if_less32(s1l,s2l,t);
2078 emit_set_if_carry32(s1l,s2l,t);
2084 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2086 signed char s1l,s2l,tl;
2087 tl=get_reg(i_regs->regmap,rt1[i]);
2090 s1l=get_reg(i_regs->regmap,rs1[i]);
2091 s2l=get_reg(i_regs->regmap,rs2[i]);
2092 if(rs1[i]&&rs2[i]) {
2095 if(opcode2[i]==0x24) { // AND
2096 emit_and(s1l,s2l,tl);
2098 if(opcode2[i]==0x25) { // OR
2099 emit_or(s1l,s2l,tl);
2101 if(opcode2[i]==0x26) { // XOR
2102 emit_xor(s1l,s2l,tl);
2104 if(opcode2[i]==0x27) { // NOR
2105 emit_or(s1l,s2l,tl);
2111 if(opcode2[i]==0x24) { // AND
2114 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2116 if(s1l>=0) emit_mov(s1l,tl);
2117 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2121 if(s2l>=0) emit_mov(s2l,tl);
2122 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2124 else emit_zeroreg(tl);
2126 if(opcode2[i]==0x27) { // NOR
2128 if(s1l>=0) emit_not(s1l,tl);
2130 emit_loadreg(rs1[i],tl);
2136 if(s2l>=0) emit_not(s2l,tl);
2138 emit_loadreg(rs2[i],tl);
2142 else emit_movimm(-1,tl);
2151 void imm16_assemble(int i,struct regstat *i_regs)
2153 if (opcode[i]==0x0f) { // LUI
2156 t=get_reg(i_regs->regmap,rt1[i]);
2159 if(!((i_regs->isconst>>t)&1))
2160 emit_movimm(imm[i]<<16,t);
2164 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2167 t=get_reg(i_regs->regmap,rt1[i]);
2168 s=get_reg(i_regs->regmap,rs1[i]);
2173 if(!((i_regs->isconst>>t)&1)) {
2175 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2176 emit_addimm(t,imm[i],t);
2178 if(!((i_regs->wasconst>>s)&1))
2179 emit_addimm(s,imm[i],t);
2181 emit_movimm(constmap[i][s]+imm[i],t);
2187 if(!((i_regs->isconst>>t)&1))
2188 emit_movimm(imm[i],t);
2193 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2196 tl=get_reg(i_regs->regmap,rt1[i]);
2197 sl=get_reg(i_regs->regmap,rs1[i]);
2201 emit_addimm(sl,imm[i],tl);
2203 emit_movimm(imm[i],tl);
2208 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2210 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2212 t=get_reg(i_regs->regmap,rt1[i]);
2213 sl=get_reg(i_regs->regmap,rs1[i]);
2217 if(opcode[i]==0x0a) { // SLTI
2219 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2220 emit_slti32(t,imm[i],t);
2222 emit_slti32(sl,imm[i],t);
2227 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2228 emit_sltiu32(t,imm[i],t);
2230 emit_sltiu32(sl,imm[i],t);
2234 // SLTI(U) with r0 is just stupid,
2235 // nonetheless examples can be found
2236 if(opcode[i]==0x0a) // SLTI
2237 if(0<imm[i]) emit_movimm(1,t);
2238 else emit_zeroreg(t);
2241 if(imm[i]) emit_movimm(1,t);
2242 else emit_zeroreg(t);
2248 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2251 tl=get_reg(i_regs->regmap,rt1[i]);
2252 sl=get_reg(i_regs->regmap,rs1[i]);
2253 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2254 if(opcode[i]==0x0c) //ANDI
2258 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2259 emit_andimm(tl,imm[i],tl);
2261 if(!((i_regs->wasconst>>sl)&1))
2262 emit_andimm(sl,imm[i],tl);
2264 emit_movimm(constmap[i][sl]&imm[i],tl);
2274 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2276 if(opcode[i]==0x0d) { // ORI
2278 emit_orimm(tl,imm[i],tl);
2280 if(!((i_regs->wasconst>>sl)&1))
2281 emit_orimm(sl,imm[i],tl);
2283 emit_movimm(constmap[i][sl]|imm[i],tl);
2286 if(opcode[i]==0x0e) { // XORI
2288 emit_xorimm(tl,imm[i],tl);
2290 if(!((i_regs->wasconst>>sl)&1))
2291 emit_xorimm(sl,imm[i],tl);
2293 emit_movimm(constmap[i][sl]^imm[i],tl);
2298 emit_movimm(imm[i],tl);
2306 void shiftimm_assemble(int i,struct regstat *i_regs)
2308 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2312 t=get_reg(i_regs->regmap,rt1[i]);
2313 s=get_reg(i_regs->regmap,rs1[i]);
2315 if(t>=0&&!((i_regs->isconst>>t)&1)){
2322 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2324 if(opcode2[i]==0) // SLL
2326 emit_shlimm(s<0?t:s,imm[i],t);
2328 if(opcode2[i]==2) // SRL
2330 emit_shrimm(s<0?t:s,imm[i],t);
2332 if(opcode2[i]==3) // SRA
2334 emit_sarimm(s<0?t:s,imm[i],t);
2338 if(s>=0 && s!=t) emit_mov(s,t);
2342 //emit_storereg(rt1[i],t); //DEBUG
2345 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2349 if(opcode2[i]==0x3c) // DSLL32
2353 if(opcode2[i]==0x3e) // DSRL32
2357 if(opcode2[i]==0x3f) // DSRA32
2363 #ifndef shift_assemble
2364 static void shift_assemble(int i,struct regstat *i_regs)
2366 signed char s,t,shift;
2369 assert(opcode2[i]<=0x07); // SLLV/SRLV/SRAV
2370 t = get_reg(i_regs->regmap, rt1[i]);
2371 s = get_reg(i_regs->regmap, rs1[i]);
2372 shift = get_reg(i_regs->regmap, rs2[i]);
2378 else if(rs2[i]==0) {
2380 if(s!=t) emit_mov(s,t);
2383 host_tempreg_acquire();
2384 emit_andimm(shift,31,HOST_TEMPREG);
2385 switch(opcode2[i]) {
2387 emit_shl(s,HOST_TEMPREG,t);
2390 emit_shr(s,HOST_TEMPREG,t);
2393 emit_sar(s,HOST_TEMPREG,t);
2398 host_tempreg_release();
2412 static int get_ptr_mem_type(u_int a)
2414 if(a < 0x00200000) {
2415 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2416 // return wrong, must use memhandler for BIOS self-test to pass
2417 // 007 does similar stuff from a00 mirror, weird stuff
2421 if(0x1f800000 <= a && a < 0x1f801000)
2423 if(0x80200000 <= a && a < 0x80800000)
2425 if(0xa0000000 <= a && a < 0xa0200000)
2430 static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override)
2435 if(((smrv_strong|smrv_weak)>>mr)&1) {
2436 type=get_ptr_mem_type(smrv[mr]);
2437 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2440 // use the mirror we are running on
2441 type=get_ptr_mem_type(start);
2442 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2445 if(type==MTYPE_8020) { // RAM 80200000+ mirror
2446 host_tempreg_acquire();
2447 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2448 addr=*addr_reg_override=HOST_TEMPREG;
2451 else if(type==MTYPE_0000) { // RAM 0 mirror
2452 host_tempreg_acquire();
2453 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2454 addr=*addr_reg_override=HOST_TEMPREG;
2457 else if(type==MTYPE_A000) { // RAM A mirror
2458 host_tempreg_acquire();
2459 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2460 addr=*addr_reg_override=HOST_TEMPREG;
2463 else if(type==MTYPE_1F80) { // scratchpad
2464 if (psxH == (void *)0x1f800000) {
2465 host_tempreg_acquire();
2466 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
2467 emit_cmpimm(HOST_TEMPREG,0x1000);
2468 host_tempreg_release();
2473 // do the usual RAM check, jump will go to the right handler
2480 emit_cmpimm(addr,RAM_SIZE);
2482 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2483 // Hint to branch predictor that the branch is unlikely to be taken
2485 emit_jno_unlikely(0);
2490 host_tempreg_acquire();
2491 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2492 addr=*addr_reg_override=HOST_TEMPREG;
2499 // return memhandler, or get directly accessable address and return 0
2500 static void *get_direct_memhandler(void *table, u_int addr,
2501 enum stub_type type, uintptr_t *addr_host)
2503 uintptr_t l1, l2 = 0;
2504 l1 = ((uintptr_t *)table)[addr>>12];
2505 if ((l1 & (1ul << (sizeof(l1)*8-1))) == 0) {
2506 uintptr_t v = l1 << 1;
2507 *addr_host = v + addr;
2512 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2513 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2514 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
2515 l2=((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
2517 l2=((uintptr_t *)l1)[(addr&0xfff)/4];
2518 if ((l2 & (1<<31)) == 0) {
2519 uintptr_t v = l2 << 1;
2520 *addr_host = v + (addr&0xfff);
2523 return (void *)(l2 << 1);
2527 static void load_assemble(int i,struct regstat *i_regs)
2532 int memtarget=0,c=0;
2533 int fastio_reg_override=-1;
2535 tl=get_reg(i_regs->regmap,rt1[i]);
2536 s=get_reg(i_regs->regmap,rs1[i]);
2538 for(hr=0;hr<HOST_REGS;hr++) {
2539 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2541 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2543 c=(i_regs->wasconst>>s)&1;
2545 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2548 //printf("load_assemble: c=%d\n",c);
2549 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2550 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2551 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
2553 // could be FIFO, must perform the read
2555 assem_debug("(forced read)\n");
2556 tl=get_reg(i_regs->regmap,-1);
2559 if(offset||s<0||c) addr=tl;
2561 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2563 //printf("load_assemble: c=%d\n",c);
2564 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2565 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2569 // Strmnnrmn's speed hack
2570 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2573 jaddr=emit_fastpath_cmp_jump(i,addr,&fastio_reg_override);
2576 else if(ram_offset&&memtarget) {
2577 host_tempreg_acquire();
2578 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2579 fastio_reg_override=HOST_TEMPREG;
2581 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2582 if (opcode[i]==0x20) { // LB
2588 if(fastio_reg_override>=0) a=fastio_reg_override;
2590 emit_movsbl_indexed(x,a,tl);
2594 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2597 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2599 if (opcode[i]==0x21) { // LH
2604 if(fastio_reg_override>=0) a=fastio_reg_override;
2605 emit_movswl_indexed(x,a,tl);
2608 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2611 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2613 if (opcode[i]==0x23) { // LW
2617 if(fastio_reg_override>=0) a=fastio_reg_override;
2618 emit_readword_indexed(0,a,tl);
2621 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2624 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2626 if (opcode[i]==0x24) { // LBU
2631 if(fastio_reg_override>=0) a=fastio_reg_override;
2633 emit_movzbl_indexed(x,a,tl);
2636 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2639 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2641 if (opcode[i]==0x25) { // LHU
2646 if(fastio_reg_override>=0) a=fastio_reg_override;
2647 emit_movzwl_indexed(x,a,tl);
2650 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2653 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2655 if (opcode[i]==0x27) { // LWU
2658 if (opcode[i]==0x37) { // LD
2662 if (fastio_reg_override == HOST_TEMPREG)
2663 host_tempreg_release();
2666 #ifndef loadlr_assemble
2667 static void loadlr_assemble(int i,struct regstat *i_regs)
2669 int s,tl,temp,temp2,addr;
2672 int memtarget=0,c=0;
2673 int fastio_reg_override=-1;
2675 tl=get_reg(i_regs->regmap,rt1[i]);
2676 s=get_reg(i_regs->regmap,rs1[i]);
2677 temp=get_reg(i_regs->regmap,-1);
2678 temp2=get_reg(i_regs->regmap,FTEMP);
2679 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
2682 for(hr=0;hr<HOST_REGS;hr++) {
2683 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2686 if(offset||s<0||c) addr=temp2;
2689 c=(i_regs->wasconst>>s)&1;
2691 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2695 emit_shlimm(addr,3,temp);
2696 if (opcode[i]==0x22||opcode[i]==0x26) {
2697 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
2699 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
2701 jaddr=emit_fastpath_cmp_jump(i,temp2,&fastio_reg_override);
2704 if(ram_offset&&memtarget) {
2705 host_tempreg_acquire();
2706 emit_addimm(temp2,ram_offset,HOST_TEMPREG);
2707 fastio_reg_override=HOST_TEMPREG;
2709 if (opcode[i]==0x22||opcode[i]==0x26) {
2710 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
2712 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
2715 if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
2718 if(fastio_reg_override>=0) a=fastio_reg_override;
2719 emit_readword_indexed(0,a,temp2);
2720 if(fastio_reg_override==HOST_TEMPREG) host_tempreg_release();
2721 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj[i],reglist);
2724 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
2727 emit_andimm(temp,24,temp);
2728 if (opcode[i]==0x22) // LWL
2729 emit_xorimm(temp,24,temp);
2730 host_tempreg_acquire();
2731 emit_movimm(-1,HOST_TEMPREG);
2732 if (opcode[i]==0x26) {
2733 emit_shr(temp2,temp,temp2);
2734 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
2736 emit_shl(temp2,temp,temp2);
2737 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
2739 host_tempreg_release();
2740 emit_or(temp2,tl,tl);
2742 //emit_storereg(rt1[i],tl); // DEBUG
2744 if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
2750 void store_assemble(int i,struct regstat *i_regs)
2756 enum stub_type type;
2757 int memtarget=0,c=0;
2758 int agr=AGEN1+(i&1);
2759 int fastio_reg_override=-1;
2761 tl=get_reg(i_regs->regmap,rs2[i]);
2762 s=get_reg(i_regs->regmap,rs1[i]);
2763 temp=get_reg(i_regs->regmap,agr);
2764 if(temp<0) temp=get_reg(i_regs->regmap,-1);
2767 c=(i_regs->wasconst>>s)&1;
2769 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2774 for(hr=0;hr<HOST_REGS;hr++) {
2775 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2777 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2778 if(offset||s<0||c) addr=temp;
2781 jaddr=emit_fastpath_cmp_jump(i,addr,&fastio_reg_override);
2783 else if(ram_offset&&memtarget) {
2784 host_tempreg_acquire();
2785 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2786 fastio_reg_override=HOST_TEMPREG;
2789 if (opcode[i]==0x28) { // SB
2793 if(fastio_reg_override>=0) a=fastio_reg_override;
2794 emit_writebyte_indexed(tl,x,a);
2798 if (opcode[i]==0x29) { // SH
2802 if(fastio_reg_override>=0) a=fastio_reg_override;
2803 emit_writehword_indexed(tl,x,a);
2807 if (opcode[i]==0x2B) { // SW
2810 if(fastio_reg_override>=0) a=fastio_reg_override;
2811 emit_writeword_indexed(tl,0,a);
2815 if (opcode[i]==0x3F) { // SD
2819 if(fastio_reg_override==HOST_TEMPREG)
2820 host_tempreg_release();
2822 // PCSX store handlers don't check invcode again
2824 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2827 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
2829 #ifdef DESTRUCTIVE_SHIFT
2830 // The x86 shift operation is 'destructive'; it overwrites the
2831 // source register, so we need to make a copy first and use that.
2834 #if defined(HOST_IMM8)
2835 int ir=get_reg(i_regs->regmap,INVCP);
2837 emit_cmpmem_indexedsr12_reg(ir,addr,1);
2839 emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
2841 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
2842 emit_callne(invalidate_addr_reg[addr]);
2846 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
2850 u_int addr_val=constmap[i][s]+offset;
2852 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2853 } else if(c&&!memtarget) {
2854 inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
2856 // basic current block modification detection..
2857 // not looking back as that should be in mips cache already
2858 // (see Spyro2 title->attract mode)
2859 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
2860 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
2861 assert(i_regs->regmap==regs[i].regmap); // not delay slot
2862 if(i_regs->regmap==regs[i].regmap) {
2863 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
2864 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
2865 emit_movimm(start+i*4+4,0);
2866 emit_writeword(0,&pcaddr);
2867 emit_addimm(HOST_CCREG,2,HOST_CCREG);
2868 emit_call(get_addr_ht);
2874 static void storelr_assemble(int i,struct regstat *i_regs)
2880 void *case1, *case2, *case3;
2881 void *done0, *done1, *done2;
2882 int memtarget=0,c=0;
2883 int agr=AGEN1+(i&1);
2885 tl=get_reg(i_regs->regmap,rs2[i]);
2886 s=get_reg(i_regs->regmap,rs1[i]);
2887 temp=get_reg(i_regs->regmap,agr);
2888 if(temp<0) temp=get_reg(i_regs->regmap,-1);
2891 c=(i_regs->isconst>>s)&1;
2893 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2897 for(hr=0;hr<HOST_REGS;hr++) {
2898 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2902 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
2903 if(!offset&&s!=temp) emit_mov(s,temp);
2909 if(!memtarget||!rs1[i]) {
2915 emit_addimm_no_flags(ram_offset,temp);
2917 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
2921 emit_xorimm(temp,3,temp);
2922 emit_testimm(temp,2);
2925 emit_testimm(temp,1);
2929 if (opcode[i]==0x2A) { // SWL
2930 emit_writeword_indexed(tl,0,temp);
2932 else if (opcode[i]==0x2E) { // SWR
2933 emit_writebyte_indexed(tl,3,temp);
2940 set_jump_target(case1, out);
2941 if (opcode[i]==0x2A) { // SWL
2942 // Write 3 msb into three least significant bytes
2943 if(rs2[i]) emit_rorimm(tl,8,tl);
2944 emit_writehword_indexed(tl,-1,temp);
2945 if(rs2[i]) emit_rorimm(tl,16,tl);
2946 emit_writebyte_indexed(tl,1,temp);
2947 if(rs2[i]) emit_rorimm(tl,8,tl);
2949 else if (opcode[i]==0x2E) { // SWR
2950 // Write two lsb into two most significant bytes
2951 emit_writehword_indexed(tl,1,temp);
2956 set_jump_target(case2, out);
2957 emit_testimm(temp,1);
2960 if (opcode[i]==0x2A) { // SWL
2961 // Write two msb into two least significant bytes
2962 if(rs2[i]) emit_rorimm(tl,16,tl);
2963 emit_writehword_indexed(tl,-2,temp);
2964 if(rs2[i]) emit_rorimm(tl,16,tl);
2966 else if (opcode[i]==0x2E) { // SWR
2967 // Write 3 lsb into three most significant bytes
2968 emit_writebyte_indexed(tl,-1,temp);
2969 if(rs2[i]) emit_rorimm(tl,8,tl);
2970 emit_writehword_indexed(tl,0,temp);
2971 if(rs2[i]) emit_rorimm(tl,24,tl);
2976 set_jump_target(case3, out);
2977 if (opcode[i]==0x2A) { // SWL
2978 // Write msb into least significant byte
2979 if(rs2[i]) emit_rorimm(tl,24,tl);
2980 emit_writebyte_indexed(tl,-3,temp);
2981 if(rs2[i]) emit_rorimm(tl,8,tl);
2983 else if (opcode[i]==0x2E) { // SWR
2984 // Write entire word
2985 emit_writeword_indexed(tl,-3,temp);
2987 set_jump_target(done0, out);
2988 set_jump_target(done1, out);
2989 set_jump_target(done2, out);
2991 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj[i],reglist);
2992 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
2993 emit_addimm_no_flags(-ram_offset,temp);
2994 #if defined(HOST_IMM8)
2995 int ir=get_reg(i_regs->regmap,INVCP);
2997 emit_cmpmem_indexedsr12_reg(ir,temp,1);
2999 emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
3001 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3002 emit_callne(invalidate_addr_reg[temp]);
3006 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3011 static void cop0_assemble(int i,struct regstat *i_regs)
3013 if(opcode2[i]==0) // MFC0
3015 signed char t=get_reg(i_regs->regmap,rt1[i]);
3016 u_int copr=(source[i]>>11)&0x1f;
3017 //assert(t>=0); // Why does this happen? OOT is weird
3018 if(t>=0&&rt1[i]!=0) {
3019 emit_readword(®_cop0[copr],t);
3022 else if(opcode2[i]==4) // MTC0
3024 signed char s=get_reg(i_regs->regmap,rs1[i]);
3025 char copr=(source[i]>>11)&0x1f;
3027 wb_register(rs1[i],i_regs->regmap,i_regs->dirty);
3028 if(copr==9||copr==11||copr==12||copr==13) {
3029 emit_readword(&last_count,HOST_TEMPREG);
3030 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3031 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3032 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3033 emit_writeword(HOST_CCREG,&Count);
3035 // What a mess. The status register (12) can enable interrupts,
3036 // so needs a special case to handle a pending interrupt.
3037 // The interrupt must be taken immediately, because a subsequent
3038 // instruction might disable interrupts again.
3039 if(copr==12||copr==13) {
3041 // burn cycles to cause cc_interrupt, which will
3042 // reschedule next_interupt. Relies on CCREG from above.
3043 assem_debug("MTC0 DS %d\n", copr);
3044 emit_writeword(HOST_CCREG,&last_count);
3045 emit_movimm(0,HOST_CCREG);
3046 emit_storereg(CCREG,HOST_CCREG);
3047 emit_loadreg(rs1[i],1);
3048 emit_movimm(copr,0);
3049 emit_call(pcsx_mtc0_ds);
3050 emit_loadreg(rs1[i],s);
3053 emit_movimm(start+i*4+4,HOST_TEMPREG);
3054 emit_writeword(HOST_TEMPREG,&pcaddr);
3055 emit_movimm(0,HOST_TEMPREG);
3056 emit_writeword(HOST_TEMPREG,&pending_exception);
3058 //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
3061 emit_loadreg(rs1[i],1);
3064 emit_movimm(copr,0);
3065 emit_call(pcsx_mtc0);
3066 if(copr==9||copr==11||copr==12||copr==13) {
3067 emit_readword(&Count,HOST_CCREG);
3068 emit_readword(&next_interupt,HOST_TEMPREG);
3069 emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3070 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3071 emit_writeword(HOST_TEMPREG,&last_count);
3072 emit_storereg(CCREG,HOST_CCREG);
3074 if(copr==12||copr==13) {
3075 assert(!is_delayslot);
3076 emit_readword(&pending_exception,14);
3080 emit_readword(&pcaddr, 0);
3081 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3082 emit_call(get_addr_ht);
3084 set_jump_target(jaddr, out);
3086 emit_loadreg(rs1[i],s);
3090 assert(opcode2[i]==0x10);
3091 //if((source[i]&0x3f)==0x10) // RFE
3093 emit_readword(&Status,0);
3094 emit_andimm(0,0x3c,1);
3095 emit_andimm(0,~0xf,0);
3096 emit_orrshr_imm(1,2,0);
3097 emit_writeword(0,&Status);
3102 static void cop1_unusable(int i,struct regstat *i_regs)
3104 // XXX: should just just do the exception instead
3109 add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3113 static void cop1_assemble(int i,struct regstat *i_regs)
3115 cop1_unusable(i, i_regs);
3118 static void c1ls_assemble(int i,struct regstat *i_regs)
3120 cop1_unusable(i, i_regs);
3124 static void do_cop1stub(int n)
3127 assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3128 set_jump_target(stubs[n].addr, out);
3130 // int rs=stubs[n].b;
3131 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3134 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3135 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3137 //else {printf("fp exception in delay slot\n");}
3138 wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3139 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3140 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3141 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3142 emit_jmp(ds?fp_exception_ds:fp_exception);
3145 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3155 emit_readword(®_cop2d[copr],tl);
3156 emit_signextend16(tl,tl);
3157 emit_writeword(tl,®_cop2d[copr]); // hmh
3164 emit_readword(®_cop2d[copr],tl);
3165 emit_andimm(tl,0xffff,tl);
3166 emit_writeword(tl,®_cop2d[copr]);
3169 emit_readword(®_cop2d[14],tl); // SXY2
3170 emit_writeword(tl,®_cop2d[copr]);
3174 c2op_mfc2_29_assemble(tl,temp);
3177 emit_readword(®_cop2d[copr],tl);
3182 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3186 emit_readword(®_cop2d[13],temp); // SXY1
3187 emit_writeword(sl,®_cop2d[copr]);
3188 emit_writeword(temp,®_cop2d[12]); // SXY0
3189 emit_readword(®_cop2d[14],temp); // SXY2
3190 emit_writeword(sl,®_cop2d[14]);
3191 emit_writeword(temp,®_cop2d[13]); // SXY1
3194 emit_andimm(sl,0x001f,temp);
3195 emit_shlimm(temp,7,temp);
3196 emit_writeword(temp,®_cop2d[9]);
3197 emit_andimm(sl,0x03e0,temp);
3198 emit_shlimm(temp,2,temp);
3199 emit_writeword(temp,®_cop2d[10]);
3200 emit_andimm(sl,0x7c00,temp);
3201 emit_shrimm(temp,3,temp);
3202 emit_writeword(temp,®_cop2d[11]);
3203 emit_writeword(sl,®_cop2d[28]);
3206 emit_xorsar_imm(sl,sl,31,temp);
3207 #if defined(HAVE_ARMV5) || defined(__aarch64__)
3208 emit_clz(temp,temp);
3210 emit_movs(temp,HOST_TEMPREG);
3211 emit_movimm(0,temp);
3212 emit_jeq((int)out+4*4);
3213 emit_addpl_imm(temp,1,temp);
3214 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3215 emit_jns((int)out-2*4);
3217 emit_writeword(sl,®_cop2d[30]);
3218 emit_writeword(temp,®_cop2d[31]);
3223 emit_writeword(sl,®_cop2d[copr]);
3228 static void c2ls_assemble(int i,struct regstat *i_regs)
3233 int memtarget=0,c=0;
3235 enum stub_type type;
3236 int agr=AGEN1+(i&1);
3237 int fastio_reg_override=-1;
3239 u_int copr=(source[i]>>16)&0x1f;
3240 s=get_reg(i_regs->regmap,rs1[i]);
3241 tl=get_reg(i_regs->regmap,FTEMP);
3246 for(hr=0;hr<HOST_REGS;hr++) {
3247 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3249 if(i_regs->regmap[HOST_CCREG]==CCREG)
3250 reglist&=~(1<<HOST_CCREG);
3253 if (opcode[i]==0x3a) { // SWC2
3254 ar=get_reg(i_regs->regmap,agr);
3255 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3260 if(s>=0) c=(i_regs->wasconst>>s)&1;
3261 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3262 if (!offset&&!c&&s>=0) ar=s;
3265 if (opcode[i]==0x3a) { // SWC2
3266 cop2_get_dreg(copr,tl,-1);
3274 emit_jmp(0); // inline_readstub/inline_writestub?
3278 jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3280 else if(ram_offset&&memtarget) {
3281 host_tempreg_acquire();
3282 emit_addimm(ar,ram_offset,HOST_TEMPREG);
3283 fastio_reg_override=HOST_TEMPREG;
3285 if (opcode[i]==0x32) { // LWC2
3287 if(fastio_reg_override>=0) a=fastio_reg_override;
3288 emit_readword_indexed(0,a,tl);
3290 if (opcode[i]==0x3a) { // SWC2
3291 #ifdef DESTRUCTIVE_SHIFT
3292 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3295 if(fastio_reg_override>=0) a=fastio_reg_override;
3296 emit_writeword_indexed(tl,0,a);
3299 if(fastio_reg_override==HOST_TEMPREG)
3300 host_tempreg_release();
3302 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj[i],reglist);
3303 if(opcode[i]==0x3a) // SWC2
3304 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3305 #if defined(HOST_IMM8)
3306 int ir=get_reg(i_regs->regmap,INVCP);
3308 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3310 emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
3312 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3313 emit_callne(invalidate_addr_reg[ar]);
3317 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3320 if (opcode[i]==0x32) { // LWC2
3321 host_tempreg_acquire();
3322 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3323 host_tempreg_release();
3327 static void cop2_assemble(int i,struct regstat *i_regs)
3329 u_int copr=(source[i]>>11)&0x1f;
3330 signed char temp=get_reg(i_regs->regmap,-1);
3331 if (opcode2[i]==0) { // MFC2
3332 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3333 if(tl>=0&&rt1[i]!=0)
3334 cop2_get_dreg(copr,tl,temp);
3336 else if (opcode2[i]==4) { // MTC2
3337 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3338 cop2_put_dreg(copr,sl,temp);
3340 else if (opcode2[i]==2) // CFC2
3342 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3343 if(tl>=0&&rt1[i]!=0)
3344 emit_readword(®_cop2c[copr],tl);
3346 else if (opcode2[i]==6) // CTC2
3348 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3357 emit_signextend16(sl,temp);
3360 c2op_ctc2_31_assemble(sl,temp);
3366 emit_writeword(temp,®_cop2c[copr]);
3371 static void do_unalignedwritestub(int n)
3373 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
3375 set_jump_target(stubs[n].addr, out);
3378 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3379 int addr=stubs[n].b;
3380 u_int reglist=stubs[n].e;
3381 signed char *i_regmap=i_regs->regmap;
3382 int temp2=get_reg(i_regmap,FTEMP);
3384 rt=get_reg(i_regmap,rs2[i]);
3387 assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
3389 reglist&=~(1<<temp2);
3392 // don't bother with it and call write handler
3395 int cc=get_reg(i_regmap,CCREG);
3397 emit_loadreg(CCREG,2);
3398 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n].d+1),2);
3399 emit_call((opcode[i]==0x2a?jump_handle_swl:jump_handle_swr));
3400 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n].d+1),cc<0?2:cc);
3402 emit_storereg(CCREG,2);
3403 restore_regs(reglist);
3404 emit_jmp(stubs[n].retaddr); // return address
3406 emit_andimm(addr,0xfffffffc,temp2);
3407 emit_writeword(temp2,&address);
3410 emit_shrimm(addr,16,1);
3411 int cc=get_reg(i_regmap,CCREG);
3413 emit_loadreg(CCREG,2);
3415 emit_movimm((u_int)readmem,0);
3416 emit_addimm(cc<0?2:cc,2*stubs[n].d+2,2);
3417 emit_call((int)&indirect_jump_indexed);
3418 restore_regs(reglist);
3420 emit_readword(&readmem_dword,temp2);
3421 int temp=addr; //hmh
3422 emit_shlimm(addr,3,temp);
3423 emit_andimm(temp,24,temp);
3424 if (opcode[i]==0x2a) // SWL
3425 emit_xorimm(temp,24,temp);
3426 emit_movimm(-1,HOST_TEMPREG);
3427 if (opcode[i]==0x2a) { // SWL
3428 emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
3429 emit_orrshr(rt,temp,temp2);
3431 emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
3432 emit_orrshl(rt,temp,temp2);
3434 emit_readword(&address,addr);
3435 emit_writeword(temp2,&word);
3436 //save_regs(reglist); // don't need to, no state changes
3437 emit_shrimm(addr,16,1);
3438 emit_movimm((u_int)writemem,0);
3439 //emit_call((int)&indirect_jump_indexed);
3441 emit_readword_dualindexedx4(0,1,15);
3442 emit_readword(&Count,HOST_TEMPREG);
3443 emit_readword(&next_interupt,2);
3444 emit_addimm(HOST_TEMPREG,-2*stubs[n].d-2,HOST_TEMPREG);
3445 emit_writeword(2,&last_count);
3446 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3448 emit_storereg(CCREG,HOST_TEMPREG);
3450 restore_regs(reglist);
3451 emit_jmp(stubs[n].retaddr); // return address
3455 #ifndef multdiv_assemble
3456 void multdiv_assemble(int i,struct regstat *i_regs)
3458 printf("Need multdiv_assemble for this architecture.\n");
3463 static void mov_assemble(int i,struct regstat *i_regs)
3465 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3466 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3469 tl=get_reg(i_regs->regmap,rt1[i]);
3472 sl=get_reg(i_regs->regmap,rs1[i]);
3473 if(sl>=0) emit_mov(sl,tl);
3474 else emit_loadreg(rs1[i],tl);
3479 // call interpreter, exception handler, things that change pc/regs/cycles ...
3480 static void call_c_cpu_handler(int i, const struct regstat *i_regs, u_int pc, void *func)
3482 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3483 assert(ccreg==HOST_CCREG);
3484 assert(!is_delayslot);
3487 emit_movimm(pc,3); // Get PC
3488 emit_readword(&last_count,2);
3489 emit_writeword(3,&psxRegs.pc);
3490 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
3491 emit_add(2,HOST_CCREG,2);
3492 emit_writeword(2,&psxRegs.cycle);
3494 emit_jmp(jump_to_new_pc);
3497 static void syscall_assemble(int i,struct regstat *i_regs)
3499 emit_movimm(0x20,0); // cause code
3500 emit_movimm(0,1); // not in delay slot
3501 call_c_cpu_handler(i,i_regs,start+i*4,psxException);
3504 static void hlecall_assemble(int i,struct regstat *i_regs)
3506 void *hlefunc = psxNULL;
3507 uint32_t hleCode = source[i] & 0x03ffffff;
3508 if (hleCode < ARRAY_SIZE(psxHLEt))
3509 hlefunc = psxHLEt[hleCode];
3511 call_c_cpu_handler(i,i_regs,start+i*4+4,hlefunc);
3514 static void intcall_assemble(int i,struct regstat *i_regs)
3516 call_c_cpu_handler(i,i_regs,start+i*4,execI);
3519 static void speculate_mov(int rs,int rt)
3522 smrv_strong_next|=1<<rt;
3527 static void speculate_mov_weak(int rs,int rt)
3530 smrv_weak_next|=1<<rt;
3535 static void speculate_register_values(int i)
3538 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3539 // gp,sp are likely to stay the same throughout the block
3540 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3541 smrv_weak_next=~smrv_strong_next;
3542 //printf(" llr %08x\n", smrv[4]);
3544 smrv_strong=smrv_strong_next;
3545 smrv_weak=smrv_weak_next;
3548 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3549 else if((smrv_strong>>rs2[i])&1) speculate_mov(rs2[i],rt1[i]);
3550 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3551 else if((smrv_weak>>rs2[i])&1) speculate_mov_weak(rs2[i],rt1[i]);
3553 smrv_strong_next&=~(1<<rt1[i]);
3554 smrv_weak_next&=~(1<<rt1[i]);
3558 smrv_strong_next&=~(1<<rt1[i]);
3559 smrv_weak_next&=~(1<<rt1[i]);
3562 if(rt1[i]&&is_const(®s[i],rt1[i])) {
3563 int value,hr=get_reg(regs[i].regmap,rt1[i]);
3565 if(get_final_value(hr,i,&value))
3567 else smrv[rt1[i]]=constmap[i][hr];
3568 smrv_strong_next|=1<<rt1[i];
3572 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3573 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3577 if(start<0x2000&&(rt1[i]==26||(smrv[rt1[i]]>>24)==0xa0)) {
3578 // special case for BIOS
3579 smrv[rt1[i]]=0xa0000000;
3580 smrv_strong_next|=1<<rt1[i];
3587 smrv_strong_next&=~(1<<rt1[i]);
3588 smrv_weak_next&=~(1<<rt1[i]);
3592 if(opcode2[i]==0||opcode2[i]==2) { // MFC/CFC
3593 smrv_strong_next&=~(1<<rt1[i]);
3594 smrv_weak_next&=~(1<<rt1[i]);
3598 if (opcode[i]==0x32) { // LWC2
3599 smrv_strong_next&=~(1<<rt1[i]);
3600 smrv_weak_next&=~(1<<rt1[i]);
3606 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
3607 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
3611 static void ds_assemble(int i,struct regstat *i_regs)
3613 speculate_register_values(i);
3617 alu_assemble(i,i_regs);break;
3619 imm16_assemble(i,i_regs);break;
3621 shift_assemble(i,i_regs);break;
3623 shiftimm_assemble(i,i_regs);break;
3625 load_assemble(i,i_regs);break;
3627 loadlr_assemble(i,i_regs);break;
3629 store_assemble(i,i_regs);break;
3631 storelr_assemble(i,i_regs);break;
3633 cop0_assemble(i,i_regs);break;
3635 cop1_assemble(i,i_regs);break;
3637 c1ls_assemble(i,i_regs);break;
3639 cop2_assemble(i,i_regs);break;
3641 c2ls_assemble(i,i_regs);break;
3643 c2op_assemble(i,i_regs);break;
3645 multdiv_assemble(i,i_regs);break;
3647 mov_assemble(i,i_regs);break;
3656 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
3661 // Is the branch target a valid internal jump?
3662 static int internal_branch(int addr)
3664 if(addr&1) return 0; // Indirect (register) jump
3665 if(addr>=start && addr<start+slen*4-4)
3672 static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
3675 for(hr=0;hr<HOST_REGS;hr++) {
3676 if(hr!=EXCLUDE_REG) {
3677 if(pre[hr]!=entry[hr]) {
3680 if(get_reg(entry,pre[hr])<0) {
3682 if(!((u>>pre[hr])&1))
3683 emit_storereg(pre[hr],hr);
3690 // Move from one register to another (no writeback)
3691 for(hr=0;hr<HOST_REGS;hr++) {
3692 if(hr!=EXCLUDE_REG) {
3693 if(pre[hr]!=entry[hr]) {
3694 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3696 if((nr=get_reg(entry,pre[hr]))>=0) {
3705 // Load the specified registers
3706 // This only loads the registers given as arguments because
3707 // we don't want to load things that will be overwritten
3708 static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2)
3712 for(hr=0;hr<HOST_REGS;hr++) {
3713 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3714 if(entry[hr]!=regmap[hr]) {
3715 if(regmap[hr]==rs1||regmap[hr]==rs2)
3722 emit_loadreg(regmap[hr],hr);
3730 // Load registers prior to the start of a loop
3731 // so that they are not loaded within the loop
3732 static void loop_preload(signed char pre[],signed char entry[])
3735 for(hr=0;hr<HOST_REGS;hr++) {
3736 if(hr!=EXCLUDE_REG) {
3737 if(pre[hr]!=entry[hr]) {
3739 if(get_reg(pre,entry[hr])<0) {
3740 assem_debug("loop preload:\n");
3741 //printf("loop preload: %d\n",hr);
3745 else if(entry[hr]<TEMPREG)
3747 emit_loadreg(entry[hr],hr);
3749 else if(entry[hr]-64<TEMPREG)
3751 emit_loadreg(entry[hr],hr);
3760 // Generate address for load/store instruction
3761 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
3762 void address_generation(int i,struct regstat *i_regs,signed char entry[])
3764 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
3766 int agr=AGEN1+(i&1);
3767 if(itype[i]==LOAD) {
3768 ra=get_reg(i_regs->regmap,rt1[i]);
3769 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3772 if(itype[i]==LOADLR) {
3773 ra=get_reg(i_regs->regmap,FTEMP);
3775 if(itype[i]==STORE||itype[i]==STORELR) {
3776 ra=get_reg(i_regs->regmap,agr);
3777 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3779 if(itype[i]==C1LS||itype[i]==C2LS) {
3780 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
3781 ra=get_reg(i_regs->regmap,FTEMP);
3782 else { // SWC1/SDC1/SWC2/SDC2
3783 ra=get_reg(i_regs->regmap,agr);
3784 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3787 int rs=get_reg(i_regs->regmap,rs1[i]);
3790 int c=(i_regs->wasconst>>rs)&1;
3792 // Using r0 as a base address
3793 if(!entry||entry[ra]!=agr) {
3794 if (opcode[i]==0x22||opcode[i]==0x26) {
3795 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3796 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3797 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3799 emit_movimm(offset,ra);
3801 } // else did it in the previous cycle
3804 if(!entry||entry[ra]!=rs1[i])
3805 emit_loadreg(rs1[i],ra);
3806 //if(!entry||entry[ra]!=rs1[i])
3807 // printf("poor load scheduling!\n");
3810 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
3811 if(!entry||entry[ra]!=agr) {
3812 if (opcode[i]==0x22||opcode[i]==0x26) {
3813 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3814 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3815 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3817 emit_movimm(constmap[i][rs]+offset,ra);
3818 regs[i].loadedconst|=1<<ra;
3820 } // else did it in the previous cycle
3821 } // else load_consts already did it
3823 if(offset&&!c&&rs1[i]) {
3825 emit_addimm(rs,offset,ra);
3827 emit_addimm(ra,offset,ra);
3832 // Preload constants for next instruction
3833 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
3836 agr=AGEN1+((i+1)&1);
3837 ra=get_reg(i_regs->regmap,agr);
3839 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
3840 int offset=imm[i+1];
3841 int c=(regs[i+1].wasconst>>rs)&1;
3842 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
3843 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3844 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3845 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3846 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3848 emit_movimm(constmap[i+1][rs]+offset,ra);
3849 regs[i+1].loadedconst|=1<<ra;
3852 else if(rs1[i+1]==0) {
3853 // Using r0 as a base address
3854 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3855 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3856 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3857 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3859 emit_movimm(offset,ra);
3866 static int get_final_value(int hr, int i, int *value)
3868 int reg=regs[i].regmap[hr];
3870 if(regs[i+1].regmap[hr]!=reg) break;
3871 if(!((regs[i+1].isconst>>hr)&1)) break;
3876 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
3877 *value=constmap[i][hr];
3881 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
3882 // Load in delay slot, out-of-order execution
3883 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
3885 // Precompute load address
3886 *value=constmap[i][hr]+imm[i+2];
3890 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
3892 // Precompute load address
3893 *value=constmap[i][hr]+imm[i+1];
3894 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
3899 *value=constmap[i][hr];
3900 //printf("c=%lx\n",(long)constmap[i][hr]);
3901 if(i==slen-1) return 1;
3903 return !((unneeded_reg[i+1]>>reg)&1);
3906 // Load registers with known constants
3907 static void load_consts(signed char pre[],signed char regmap[],int i)
3910 // propagate loaded constant flags
3912 regs[i].loadedconst=0;
3914 for(hr=0;hr<HOST_REGS;hr++) {
3915 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
3916 &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
3918 regs[i].loadedconst|=1<<hr;
3923 for(hr=0;hr<HOST_REGS;hr++) {
3924 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3925 //if(entry[hr]!=regmap[hr]) {
3926 if(!((regs[i].loadedconst>>hr)&1)) {
3927 assert(regmap[hr]<64);
3928 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
3929 int value,similar=0;
3930 if(get_final_value(hr,i,&value)) {
3931 // see if some other register has similar value
3932 for(hr2=0;hr2<HOST_REGS;hr2++) {
3933 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
3934 if(is_similar_value(value,constmap[i][hr2])) {
3942 if(get_final_value(hr2,i,&value2)) // is this needed?
3943 emit_movimm_from(value2,hr2,value,hr);
3945 emit_movimm(value,hr);
3951 emit_movimm(value,hr);
3954 regs[i].loadedconst|=1<<hr;
3961 void load_all_consts(signed char regmap[], u_int dirty, int i)
3965 for(hr=0;hr<HOST_REGS;hr++) {
3966 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
3967 assert(regmap[hr] < 64);
3968 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
3969 int value=constmap[i][hr];
3974 emit_movimm(value,hr);
3981 // Write out all dirty registers (except cycle count)
3982 static void wb_dirtys(signed char i_regmap[],uint64_t i_dirty)
3985 for(hr=0;hr<HOST_REGS;hr++) {
3986 if(hr!=EXCLUDE_REG) {
3987 if(i_regmap[hr]>0) {
3988 if(i_regmap[hr]!=CCREG) {
3989 if((i_dirty>>hr)&1) {
3990 assert(i_regmap[hr]<64);
3991 emit_storereg(i_regmap[hr],hr);
3999 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4000 // This writes the registers not written by store_regs_bt
4001 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_dirty,int addr)
4004 int t=(addr-start)>>2;
4005 for(hr=0;hr<HOST_REGS;hr++) {
4006 if(hr!=EXCLUDE_REG) {
4007 if(i_regmap[hr]>0) {
4008 if(i_regmap[hr]!=CCREG) {
4009 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
4010 if((i_dirty>>hr)&1) {
4011 assert(i_regmap[hr]<64);
4012 emit_storereg(i_regmap[hr],hr);
4021 // Load all registers (except cycle count)
4022 void load_all_regs(signed char i_regmap[])
4025 for(hr=0;hr<HOST_REGS;hr++) {
4026 if(hr!=EXCLUDE_REG) {
4027 if(i_regmap[hr]==0) {
4031 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4033 emit_loadreg(i_regmap[hr],hr);
4039 // Load all current registers also needed by next instruction
4040 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4043 for(hr=0;hr<HOST_REGS;hr++) {
4044 if(hr!=EXCLUDE_REG) {
4045 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4046 if(i_regmap[hr]==0) {
4050 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4052 emit_loadreg(i_regmap[hr],hr);
4059 // Load all regs, storing cycle count if necessary
4060 void load_regs_entry(int t)
4063 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4064 else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4065 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4066 emit_storereg(CCREG,HOST_CCREG);
4069 for(hr=0;hr<HOST_REGS;hr++) {
4070 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4071 if(regs[t].regmap_entry[hr]==0) {
4074 else if(regs[t].regmap_entry[hr]!=CCREG)
4076 emit_loadreg(regs[t].regmap_entry[hr],hr);
4082 // Store dirty registers prior to branch
4083 void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4085 if(internal_branch(addr))
4087 int t=(addr-start)>>2;
4089 for(hr=0;hr<HOST_REGS;hr++) {
4090 if(hr!=EXCLUDE_REG) {
4091 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4092 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
4093 if((i_dirty>>hr)&1) {
4094 assert(i_regmap[hr]<64);
4095 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4096 emit_storereg(i_regmap[hr],hr);
4105 // Branch out of this block, write out all dirty regs
4106 wb_dirtys(i_regmap,i_dirty);
4110 // Load all needed registers for branch target
4111 static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4113 //if(addr>=start && addr<(start+slen*4))
4114 if(internal_branch(addr))
4116 int t=(addr-start)>>2;
4118 // Store the cycle count before loading something else
4119 if(i_regmap[HOST_CCREG]!=CCREG) {
4120 assert(i_regmap[HOST_CCREG]==-1);
4122 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4123 emit_storereg(CCREG,HOST_CCREG);
4126 for(hr=0;hr<HOST_REGS;hr++) {
4127 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4128 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4129 if(regs[t].regmap_entry[hr]==0) {
4132 else if(regs[t].regmap_entry[hr]!=CCREG)
4134 emit_loadreg(regs[t].regmap_entry[hr],hr);
4142 static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4144 if(addr>=start && addr<start+slen*4-4)
4146 int t=(addr-start)>>2;
4148 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4149 for(hr=0;hr<HOST_REGS;hr++)
4153 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4155 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4162 if(i_regmap[hr]<TEMPREG)
4164 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4167 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4173 else // Same register but is it 32-bit or dirty?
4176 if(!((regs[t].dirty>>hr)&1))
4180 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4182 //printf("%x: dirty no match\n",addr);
4190 // Delay slots are not valid branch targets
4191 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP)) return 0;
4192 // Delay slots require additional processing, so do not match
4193 if(is_ds[t]) return 0;
4198 for(hr=0;hr<HOST_REGS;hr++)
4204 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4219 static void drc_dbg_emit_do_cmp(int i)
4221 extern void do_insn_cmp();
4225 for(hr=0;hr<HOST_REGS;hr++)
4226 if(regs[i].regmap[hr]>=0) reglist|=1<<hr;
4228 emit_movimm(start+i*4,0);
4229 emit_writeword(0,&pcaddr);
4230 emit_call(do_insn_cmp);
4231 //emit_readword(&cycle,0);
4232 //emit_addimm(0,2,0);
4233 //emit_writeword(0,&cycle);
4235 restore_regs(reglist);
4238 #define drc_dbg_emit_do_cmp(x)
4241 // Used when a branch jumps into the delay slot of another branch
4242 static void ds_assemble_entry(int i)
4244 int t=(ba[i]-start)>>2;
4246 instr_addr[t] = out;
4247 assem_debug("Assemble delay slot at %x\n",ba[i]);
4248 assem_debug("<->\n");
4249 drc_dbg_emit_do_cmp(t);
4250 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4251 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
4252 load_regs(regs[t].regmap_entry,regs[t].regmap,rs1[t],rs2[t]);
4253 address_generation(t,®s[t],regs[t].regmap_entry);
4254 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4255 load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP);
4259 alu_assemble(t,®s[t]);break;
4261 imm16_assemble(t,®s[t]);break;
4263 shift_assemble(t,®s[t]);break;
4265 shiftimm_assemble(t,®s[t]);break;
4267 load_assemble(t,®s[t]);break;
4269 loadlr_assemble(t,®s[t]);break;
4271 store_assemble(t,®s[t]);break;
4273 storelr_assemble(t,®s[t]);break;
4275 cop0_assemble(t,®s[t]);break;
4277 cop1_assemble(t,®s[t]);break;
4279 c1ls_assemble(t,®s[t]);break;
4281 cop2_assemble(t,®s[t]);break;
4283 c2ls_assemble(t,®s[t]);break;
4285 c2op_assemble(t,®s[t]);break;
4287 multdiv_assemble(t,®s[t]);break;
4289 mov_assemble(t,®s[t]);break;
4298 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4300 store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4301 load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4302 if(internal_branch(ba[i]+4))
4303 assem_debug("branch: internal\n");
4305 assem_debug("branch: external\n");
4306 assert(internal_branch(ba[i]+4));
4307 add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
4311 static void emit_extjump(void *addr, u_int target)
4313 emit_extjump2(addr, target, dyna_linker);
4316 static void emit_extjump_ds(void *addr, u_int target)
4318 emit_extjump2(addr, target, dyna_linker_ds);
4321 // Load 2 immediates optimizing for small code size
4322 static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4324 emit_movimm(imm1,rt1);
4325 emit_movimm_from(imm1,rt1,imm2,rt2);
4328 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4338 //if(ba[i]>=start && ba[i]<(start+slen*4))
4339 if(internal_branch(ba[i]))
4342 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4350 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4352 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4354 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4355 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4359 else if(*adj==0||invert) {
4360 int cycles=CLOCK_ADJUST(count+2);
4364 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
4365 cycles=CLOCK_ADJUST(*adj)+count+2-*adj;
4367 emit_addimm_and_set_flags(cycles,HOST_CCREG);
4373 emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
4377 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4380 static void do_ccstub(int n)
4383 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
4384 set_jump_target(stubs[n].addr, out);
4386 if(stubs[n].d==NULLDS) {
4387 // Delay slot instruction is nullified ("likely" branch)
4388 wb_dirtys(regs[i].regmap,regs[i].dirty);
4390 else if(stubs[n].d!=TAKEN) {
4391 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
4394 if(internal_branch(ba[i]))
4395 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4399 // Save PC as return address
4400 emit_movimm(stubs[n].c,EAX);
4401 emit_writeword(EAX,&pcaddr);
4405 // Return address depends on which way the branch goes
4406 if(itype[i]==CJUMP||itype[i]==SJUMP)
4408 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4409 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4420 #ifdef DESTRUCTIVE_WRITEBACK
4422 if((branch_regs[i].dirty>>s1l)&&1)
4423 emit_loadreg(rs1[i],s1l);
4426 if((branch_regs[i].dirty>>s1l)&1)
4427 emit_loadreg(rs2[i],s1l);
4430 if((branch_regs[i].dirty>>s2l)&1)
4431 emit_loadreg(rs2[i],s2l);
4434 int addr=-1,alt=-1,ntaddr=-1;
4437 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4438 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4439 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4447 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4448 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4449 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4455 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4459 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4460 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4461 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4467 assert(hr<HOST_REGS);
4469 if((opcode[i]&0x2f)==4) // BEQ
4471 #ifdef HAVE_CMOV_IMM
4472 if(s2l>=0) emit_cmp(s1l,s2l);
4473 else emit_test(s1l,s1l);
4474 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4476 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4477 if(s2l>=0) emit_cmp(s1l,s2l);
4478 else emit_test(s1l,s1l);
4479 emit_cmovne_reg(alt,addr);
4482 if((opcode[i]&0x2f)==5) // BNE
4484 #ifdef HAVE_CMOV_IMM
4485 if(s2l>=0) emit_cmp(s1l,s2l);
4486 else emit_test(s1l,s1l);
4487 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4489 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4490 if(s2l>=0) emit_cmp(s1l,s2l);
4491 else emit_test(s1l,s1l);
4492 emit_cmovne_reg(alt,addr);
4495 if((opcode[i]&0x2f)==6) // BLEZ
4497 //emit_movimm(ba[i],alt);
4498 //emit_movimm(start+i*4+8,addr);
4499 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4501 emit_cmovl_reg(alt,addr);
4503 if((opcode[i]&0x2f)==7) // BGTZ
4505 //emit_movimm(ba[i],addr);
4506 //emit_movimm(start+i*4+8,ntaddr);
4507 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4509 emit_cmovl_reg(ntaddr,addr);
4511 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4513 //emit_movimm(ba[i],alt);
4514 //emit_movimm(start+i*4+8,addr);
4515 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4517 emit_cmovs_reg(alt,addr);
4519 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4521 //emit_movimm(ba[i],addr);
4522 //emit_movimm(start+i*4+8,alt);
4523 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4525 emit_cmovs_reg(alt,addr);
4527 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4528 if(source[i]&0x10000) // BC1T
4530 //emit_movimm(ba[i],alt);
4531 //emit_movimm(start+i*4+8,addr);
4532 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4533 emit_testimm(s1l,0x800000);
4534 emit_cmovne_reg(alt,addr);
4538 //emit_movimm(ba[i],addr);
4539 //emit_movimm(start+i*4+8,alt);
4540 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4541 emit_testimm(s1l,0x800000);
4542 emit_cmovne_reg(alt,addr);
4545 emit_writeword(addr,&pcaddr);
4550 int r=get_reg(branch_regs[i].regmap,rs1[i]);
4551 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4552 r=get_reg(branch_regs[i].regmap,RTEMP);
4554 emit_writeword(r,&pcaddr);
4556 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
4558 // Update cycle count
4559 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4560 if(stubs[n].a) emit_addimm(HOST_CCREG,CLOCK_ADJUST((signed int)stubs[n].a),HOST_CCREG);
4561 emit_call(cc_interrupt);
4562 if(stubs[n].a) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((signed int)stubs[n].a),HOST_CCREG);
4563 if(stubs[n].d==TAKEN) {
4564 if(internal_branch(ba[i]))
4565 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4566 else if(itype[i]==RJUMP) {
4567 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4568 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4570 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4572 }else if(stubs[n].d==NOTTAKEN) {
4573 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4574 else load_all_regs(branch_regs[i].regmap);
4575 }else if(stubs[n].d==NULLDS) {
4576 // Delay slot instruction is nullified ("likely" branch)
4577 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4578 else load_all_regs(regs[i].regmap);
4580 load_all_regs(branch_regs[i].regmap);
4582 if (stubs[n].retaddr)
4583 emit_jmp(stubs[n].retaddr);
4585 do_jump_vaddr(stubs[n].e);
4588 static void add_to_linker(void *addr, u_int target, int ext)
4590 assert(linkcount < ARRAY_SIZE(link_addr));
4591 link_addr[linkcount].addr = addr;
4592 link_addr[linkcount].target = target;
4593 link_addr[linkcount].ext = ext;
4597 static void ujump_assemble_write_ra(int i)
4600 unsigned int return_address;
4601 rt=get_reg(branch_regs[i].regmap,31);
4602 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4604 return_address=start+i*4+8;
4607 if(internal_branch(return_address)&&rt1[i+1]!=31) {
4608 int temp=-1; // note: must be ds-safe
4612 if(temp>=0) do_miniht_insert(return_address,rt,temp);
4613 else emit_movimm(return_address,rt);
4621 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
4624 emit_movimm(return_address,rt); // PC into link register
4626 emit_prefetch(hash_table_get(return_address));
4632 static void ujump_assemble(int i,struct regstat *i_regs)
4635 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
4636 address_generation(i+1,i_regs,regs[i].regmap_entry);
4638 int temp=get_reg(branch_regs[i].regmap,PTEMP);
4639 if(rt1[i]==31&&temp>=0)
4641 signed char *i_regmap=i_regs->regmap;
4642 int return_address=start+i*4+8;
4643 if(get_reg(branch_regs[i].regmap,31)>0)
4644 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
4647 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
4648 ujump_assemble_write_ra(i); // writeback ra for DS
4651 ds_assemble(i+1,i_regs);
4652 uint64_t bc_unneeded=branch_regs[i].u;
4653 bc_unneeded|=1|(1LL<<rt1[i]);
4654 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
4655 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
4656 if(!ra_done&&rt1[i]==31)
4657 ujump_assemble_write_ra(i);
4659 cc=get_reg(branch_regs[i].regmap,CCREG);
4660 assert(cc==HOST_CCREG);
4661 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4663 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
4665 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
4666 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
4667 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4668 if(internal_branch(ba[i]))
4669 assem_debug("branch: internal\n");
4671 assem_debug("branch: external\n");
4672 if(internal_branch(ba[i])&&is_ds[(ba[i]-start)>>2]) {
4673 ds_assemble_entry(i);
4676 add_to_linker(out,ba[i],internal_branch(ba[i]));
4681 static void rjump_assemble_write_ra(int i)
4683 int rt,return_address;
4684 assert(rt1[i+1]!=rt1[i]);
4685 assert(rt2[i+1]!=rt1[i]);
4686 rt=get_reg(branch_regs[i].regmap,rt1[i]);
4687 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4689 return_address=start+i*4+8;
4693 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
4696 emit_movimm(return_address,rt); // PC into link register
4698 emit_prefetch(hash_table_get(return_address));
4702 static void rjump_assemble(int i,struct regstat *i_regs)
4707 rs=get_reg(branch_regs[i].regmap,rs1[i]);
4709 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4710 // Delay slot abuse, make a copy of the branch address register
4711 temp=get_reg(branch_regs[i].regmap,RTEMP);
4713 assert(regs[i].regmap[temp]==RTEMP);
4717 address_generation(i+1,i_regs,regs[i].regmap_entry);
4721 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
4722 signed char *i_regmap=i_regs->regmap;
4723 int return_address=start+i*4+8;
4724 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
4730 int rh=get_reg(regs[i].regmap,RHASH);
4731 if(rh>=0) do_preload_rhash(rh);
4734 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
4735 rjump_assemble_write_ra(i);
4738 ds_assemble(i+1,i_regs);
4739 uint64_t bc_unneeded=branch_regs[i].u;
4740 bc_unneeded|=1|(1LL<<rt1[i]);
4741 bc_unneeded&=~(1LL<<rs1[i]);
4742 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
4743 load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i],CCREG);
4744 if(!ra_done&&rt1[i]!=0)
4745 rjump_assemble_write_ra(i);
4746 cc=get_reg(branch_regs[i].regmap,CCREG);
4747 assert(cc==HOST_CCREG);
4750 int rh=get_reg(branch_regs[i].regmap,RHASH);
4751 int ht=get_reg(branch_regs[i].regmap,RHTBL);
4753 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
4754 do_preload_rhtbl(ht);
4758 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
4759 #ifdef DESTRUCTIVE_WRITEBACK
4760 if((branch_regs[i].dirty>>rs)&1) {
4761 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
4762 emit_loadreg(rs1[i],rs);
4767 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
4771 do_miniht_load(ht,rh);
4774 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
4775 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
4777 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
4778 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
4779 if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
4780 // special case for RFE
4784 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
4787 do_miniht_jump(rs,rh,ht);
4794 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4795 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
4799 static void cjump_assemble(int i,struct regstat *i_regs)
4801 signed char *i_regmap=i_regs->regmap;
4804 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4805 assem_debug("match=%d\n",match);
4807 int unconditional=0,nop=0;
4809 int internal=internal_branch(ba[i]);
4810 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
4811 if(!match) invert=1;
4812 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4813 if(i>(ba[i]-start)>>2) invert=1;
4816 invert=1; // because of near cond. branches
4820 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4821 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4824 s1l=get_reg(i_regmap,rs1[i]);
4825 s2l=get_reg(i_regmap,rs2[i]);
4827 if(rs1[i]==0&&rs2[i]==0)
4829 if(opcode[i]&1) nop=1;
4830 else unconditional=1;
4831 //assert(opcode[i]!=5);
4832 //assert(opcode[i]!=7);
4833 //assert(opcode[i]!=0x15);
4834 //assert(opcode[i]!=0x17);
4847 // Out of order execution (delay slot first)
4849 address_generation(i+1,i_regs,regs[i].regmap_entry);
4850 ds_assemble(i+1,i_regs);
4852 uint64_t bc_unneeded=branch_regs[i].u;
4853 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
4855 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
4856 load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i],rs2[i]);
4857 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
4858 cc=get_reg(branch_regs[i].regmap,CCREG);
4859 assert(cc==HOST_CCREG);
4861 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4862 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
4863 //assem_debug("cycle count (adj)\n");
4865 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
4866 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
4867 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
4868 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4870 assem_debug("branch: internal\n");
4872 assem_debug("branch: external\n");
4873 if(internal&&is_ds[(ba[i]-start)>>2]) {
4874 ds_assemble_entry(i);
4877 add_to_linker(out,ba[i],internal);
4880 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4881 if(((u_int)out)&7) emit_addnop(0);
4886 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
4889 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
4892 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
4893 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
4894 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
4896 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4898 if(opcode[i]==4) // BEQ
4900 if(s2l>=0) emit_cmp(s1l,s2l);
4901 else emit_test(s1l,s1l);
4906 add_to_linker(out,ba[i],internal);
4910 if(opcode[i]==5) // BNE
4912 if(s2l>=0) emit_cmp(s1l,s2l);
4913 else emit_test(s1l,s1l);
4918 add_to_linker(out,ba[i],internal);
4922 if(opcode[i]==6) // BLEZ
4929 add_to_linker(out,ba[i],internal);
4933 if(opcode[i]==7) // BGTZ
4940 add_to_linker(out,ba[i],internal);
4945 if(taken) set_jump_target(taken, out);
4946 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4947 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
4949 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
4950 add_to_linker(out,ba[i],internal);
4953 add_to_linker(out,ba[i],internal*2);
4959 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
4960 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4961 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4963 assem_debug("branch: internal\n");
4965 assem_debug("branch: external\n");
4966 if(internal&&is_ds[(ba[i]-start)>>2]) {
4967 ds_assemble_entry(i);
4970 add_to_linker(out,ba[i],internal);
4974 set_jump_target(nottaken, out);
4977 if(nottaken1) set_jump_target(nottaken1, out);
4979 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
4981 } // (!unconditional)
4985 // In-order execution (branch first)
4986 //if(likely[i]) printf("IOL\n");
4989 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
4990 if(!unconditional&&!nop) {
4991 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4993 if((opcode[i]&0x2f)==4) // BEQ
4995 if(s2l>=0) emit_cmp(s1l,s2l);
4996 else emit_test(s1l,s1l);
5000 if((opcode[i]&0x2f)==5) // BNE
5002 if(s2l>=0) emit_cmp(s1l,s2l);
5003 else emit_test(s1l,s1l);
5007 if((opcode[i]&0x2f)==6) // BLEZ
5013 if((opcode[i]&0x2f)==7) // BGTZ
5019 } // if(!unconditional)
5021 uint64_t ds_unneeded=branch_regs[i].u;
5022 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5026 if(taken) set_jump_target(taken, out);
5027 assem_debug("1:\n");
5028 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5030 load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i+1],rs2[i+1]);
5031 address_generation(i+1,&branch_regs[i],0);
5032 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5033 ds_assemble(i+1,&branch_regs[i]);
5034 cc=get_reg(branch_regs[i].regmap,CCREG);
5036 emit_loadreg(CCREG,cc=HOST_CCREG);
5037 // CHECK: Is the following instruction (fall thru) allocated ok?
5039 assert(cc==HOST_CCREG);
5040 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5041 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5042 assem_debug("cycle count (adj)\n");
5043 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5044 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5046 assem_debug("branch: internal\n");
5048 assem_debug("branch: external\n");
5049 if(internal&&is_ds[(ba[i]-start)>>2]) {
5050 ds_assemble_entry(i);
5053 add_to_linker(out,ba[i],internal);
5058 if(!unconditional) {
5059 if(nottaken1) set_jump_target(nottaken1, out);
5060 set_jump_target(nottaken, out);
5061 assem_debug("2:\n");
5063 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5064 load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i+1],rs2[i+1]);
5065 address_generation(i+1,&branch_regs[i],0);
5066 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5067 ds_assemble(i+1,&branch_regs[i]);
5069 cc=get_reg(branch_regs[i].regmap,CCREG);
5070 if(cc==-1&&!likely[i]) {
5071 // Cycle count isn't in a register, temporarily load it then write it out
5072 emit_loadreg(CCREG,HOST_CCREG);
5073 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5076 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5077 emit_storereg(CCREG,HOST_CCREG);
5080 cc=get_reg(i_regmap,CCREG);
5081 assert(cc==HOST_CCREG);
5082 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5085 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5091 static void sjump_assemble(int i,struct regstat *i_regs)
5093 signed char *i_regmap=i_regs->regmap;
5096 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5097 assem_debug("smatch=%d\n",match);
5099 int unconditional=0,nevertaken=0;
5101 int internal=internal_branch(ba[i]);
5102 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5103 if(!match) invert=1;
5104 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5105 if(i>(ba[i]-start)>>2) invert=1;
5108 invert=1; // because of near cond. branches
5111 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5112 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5115 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5118 s1l=get_reg(i_regmap,rs1[i]);
5122 if(opcode2[i]&1) unconditional=1;
5124 // These are never taken (r0 is never less than zero)
5125 //assert(opcode2[i]!=0);
5126 //assert(opcode2[i]!=2);
5127 //assert(opcode2[i]!=0x10);
5128 //assert(opcode2[i]!=0x12);
5132 // Out of order execution (delay slot first)
5134 address_generation(i+1,i_regs,regs[i].regmap_entry);
5135 ds_assemble(i+1,i_regs);
5137 uint64_t bc_unneeded=branch_regs[i].u;
5138 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5140 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5141 load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i],rs1[i]);
5142 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5144 int rt,return_address;
5145 rt=get_reg(branch_regs[i].regmap,31);
5146 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5148 // Save the PC even if the branch is not taken
5149 return_address=start+i*4+8;
5150 emit_movimm(return_address,rt); // PC into link register
5152 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
5156 cc=get_reg(branch_regs[i].regmap,CCREG);
5157 assert(cc==HOST_CCREG);
5159 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5160 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5161 assem_debug("cycle count (adj)\n");
5163 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5164 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5165 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5166 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5168 assem_debug("branch: internal\n");
5170 assem_debug("branch: external\n");
5171 if(internal&&is_ds[(ba[i]-start)>>2]) {
5172 ds_assemble_entry(i);
5175 add_to_linker(out,ba[i],internal);
5178 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5179 if(((u_int)out)&7) emit_addnop(0);
5183 else if(nevertaken) {
5184 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5187 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5190 void *nottaken = NULL;
5191 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5192 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5195 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5202 add_to_linker(out,ba[i],internal);
5206 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5213 add_to_linker(out,ba[i],internal);
5220 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5221 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5223 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5224 add_to_linker(out,ba[i],internal);
5227 add_to_linker(out,ba[i],internal*2);
5233 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5234 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5235 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5237 assem_debug("branch: internal\n");
5239 assem_debug("branch: external\n");
5240 if(internal&&is_ds[(ba[i]-start)>>2]) {
5241 ds_assemble_entry(i);
5244 add_to_linker(out,ba[i],internal);
5248 set_jump_target(nottaken, out);
5252 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5254 } // (!unconditional)
5258 // In-order execution (branch first)
5260 void *nottaken = NULL;
5262 int rt,return_address;
5263 rt=get_reg(branch_regs[i].regmap,31);
5265 // Save the PC even if the branch is not taken
5266 return_address=start+i*4+8;
5267 emit_movimm(return_address,rt); // PC into link register
5269 emit_prefetch(hash_table_get(return_address));
5273 if(!unconditional) {
5274 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5276 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5282 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5288 } // if(!unconditional)
5290 uint64_t ds_unneeded=branch_regs[i].u;
5291 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5295 //assem_debug("1:\n");
5296 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5298 load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i+1],rs2[i+1]);
5299 address_generation(i+1,&branch_regs[i],0);
5300 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5301 ds_assemble(i+1,&branch_regs[i]);
5302 cc=get_reg(branch_regs[i].regmap,CCREG);
5304 emit_loadreg(CCREG,cc=HOST_CCREG);
5305 // CHECK: Is the following instruction (fall thru) allocated ok?
5307 assert(cc==HOST_CCREG);
5308 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5309 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5310 assem_debug("cycle count (adj)\n");
5311 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5312 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5314 assem_debug("branch: internal\n");
5316 assem_debug("branch: external\n");
5317 if(internal&&is_ds[(ba[i]-start)>>2]) {
5318 ds_assemble_entry(i);
5321 add_to_linker(out,ba[i],internal);
5326 if(!unconditional) {
5327 set_jump_target(nottaken, out);
5328 assem_debug("1:\n");
5330 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5331 load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i+1],rs2[i+1]);
5332 address_generation(i+1,&branch_regs[i],0);
5333 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5334 ds_assemble(i+1,&branch_regs[i]);
5336 cc=get_reg(branch_regs[i].regmap,CCREG);
5337 if(cc==-1&&!likely[i]) {
5338 // Cycle count isn't in a register, temporarily load it then write it out
5339 emit_loadreg(CCREG,HOST_CCREG);
5340 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5343 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5344 emit_storereg(CCREG,HOST_CCREG);
5347 cc=get_reg(i_regmap,CCREG);
5348 assert(cc==HOST_CCREG);
5349 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5352 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5358 static void pagespan_assemble(int i,struct regstat *i_regs)
5360 int s1l=get_reg(i_regs->regmap,rs1[i]);
5361 int s2l=get_reg(i_regs->regmap,rs2[i]);
5363 void *nottaken = NULL;
5364 int unconditional=0;
5375 int addr=-1,alt=-1,ntaddr=-1;
5376 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5380 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5381 (i_regs->regmap[hr]&63)!=rs1[i] &&
5382 (i_regs->regmap[hr]&63)!=rs2[i] )
5391 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5392 (i_regs->regmap[hr]&63)!=rs1[i] &&
5393 (i_regs->regmap[hr]&63)!=rs2[i] )
5399 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5403 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5404 (i_regs->regmap[hr]&63)!=rs1[i] &&
5405 (i_regs->regmap[hr]&63)!=rs2[i] )
5412 assert(hr<HOST_REGS);
5413 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
5414 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
5416 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5417 if(opcode[i]==2) // J
5421 if(opcode[i]==3) // JAL
5424 int rt=get_reg(i_regs->regmap,31);
5425 emit_movimm(start+i*4+8,rt);
5428 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
5431 if(opcode2[i]==9) // JALR
5433 int rt=get_reg(i_regs->regmap,rt1[i]);
5434 emit_movimm(start+i*4+8,rt);
5437 if((opcode[i]&0x3f)==4) // BEQ
5444 #ifdef HAVE_CMOV_IMM
5446 if(s2l>=0) emit_cmp(s1l,s2l);
5447 else emit_test(s1l,s1l);
5448 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5454 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5455 if(s2l>=0) emit_cmp(s1l,s2l);
5456 else emit_test(s1l,s1l);
5457 emit_cmovne_reg(alt,addr);
5460 if((opcode[i]&0x3f)==5) // BNE
5462 #ifdef HAVE_CMOV_IMM
5463 if(s2l>=0) emit_cmp(s1l,s2l);
5464 else emit_test(s1l,s1l);
5465 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5468 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5469 if(s2l>=0) emit_cmp(s1l,s2l);
5470 else emit_test(s1l,s1l);
5471 emit_cmovne_reg(alt,addr);
5474 if((opcode[i]&0x3f)==0x14) // BEQL
5476 if(s2l>=0) emit_cmp(s1l,s2l);
5477 else emit_test(s1l,s1l);
5478 if(nottaken) set_jump_target(nottaken, out);
5482 if((opcode[i]&0x3f)==0x15) // BNEL
5484 if(s2l>=0) emit_cmp(s1l,s2l);
5485 else emit_test(s1l,s1l);
5488 if(taken) set_jump_target(taken, out);
5490 if((opcode[i]&0x3f)==6) // BLEZ
5492 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5494 emit_cmovl_reg(alt,addr);
5496 if((opcode[i]&0x3f)==7) // BGTZ
5498 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5500 emit_cmovl_reg(ntaddr,addr);
5502 if((opcode[i]&0x3f)==0x16) // BLEZL
5504 assert((opcode[i]&0x3f)!=0x16);
5506 if((opcode[i]&0x3f)==0x17) // BGTZL
5508 assert((opcode[i]&0x3f)!=0x17);
5510 assert(opcode[i]!=1); // BLTZ/BGEZ
5512 //FIXME: Check CSREG
5513 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5514 if((source[i]&0x30000)==0) // BC1F
5516 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5517 emit_testimm(s1l,0x800000);
5518 emit_cmovne_reg(alt,addr);
5520 if((source[i]&0x30000)==0x10000) // BC1T
5522 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5523 emit_testimm(s1l,0x800000);
5524 emit_cmovne_reg(alt,addr);
5526 if((source[i]&0x30000)==0x20000) // BC1FL
5528 emit_testimm(s1l,0x800000);
5532 if((source[i]&0x30000)==0x30000) // BC1TL
5534 emit_testimm(s1l,0x800000);
5540 assert(i_regs->regmap[HOST_CCREG]==CCREG);
5541 wb_dirtys(regs[i].regmap,regs[i].dirty);
5542 if(likely[i]||unconditional)
5544 emit_movimm(ba[i],HOST_BTREG);
5546 else if(addr!=HOST_BTREG)
5548 emit_mov(addr,HOST_BTREG);
5550 void *branch_addr=out;
5552 int target_addr=start+i*4+5;
5554 void *compiled_target_addr=check_addr(target_addr);
5555 emit_extjump_ds(branch_addr, target_addr);
5556 if(compiled_target_addr) {
5557 set_jump_target(branch_addr, compiled_target_addr);
5558 add_link(target_addr,stub);
5560 else set_jump_target(branch_addr, stub);
5563 set_jump_target(nottaken, out);
5564 wb_dirtys(regs[i].regmap,regs[i].dirty);
5565 void *branch_addr=out;
5567 int target_addr=start+i*4+8;
5569 void *compiled_target_addr=check_addr(target_addr);
5570 emit_extjump_ds(branch_addr, target_addr);
5571 if(compiled_target_addr) {
5572 set_jump_target(branch_addr, compiled_target_addr);
5573 add_link(target_addr,stub);
5575 else set_jump_target(branch_addr, stub);
5579 // Assemble the delay slot for the above
5580 static void pagespan_ds()
5582 assem_debug("initial delay slot:\n");
5583 u_int vaddr=start+1;
5584 u_int page=get_page(vaddr);
5585 u_int vpage=get_vpage(vaddr);
5586 ll_add(jump_dirty+vpage,vaddr,(void *)out);
5588 ll_add(jump_in+page,vaddr,(void *)out);
5589 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
5590 if(regs[0].regmap[HOST_CCREG]!=CCREG)
5591 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty);
5592 if(regs[0].regmap[HOST_BTREG]!=BTREG)
5593 emit_writeword(HOST_BTREG,&branch_target);
5594 load_regs(regs[0].regmap_entry,regs[0].regmap,rs1[0],rs2[0]);
5595 address_generation(0,®s[0],regs[0].regmap_entry);
5596 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
5597 load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP);
5601 alu_assemble(0,®s[0]);break;
5603 imm16_assemble(0,®s[0]);break;
5605 shift_assemble(0,®s[0]);break;
5607 shiftimm_assemble(0,®s[0]);break;
5609 load_assemble(0,®s[0]);break;
5611 loadlr_assemble(0,®s[0]);break;
5613 store_assemble(0,®s[0]);break;
5615 storelr_assemble(0,®s[0]);break;
5617 cop0_assemble(0,®s[0]);break;
5619 cop1_assemble(0,®s[0]);break;
5621 c1ls_assemble(0,®s[0]);break;
5623 cop2_assemble(0,®s[0]);break;
5625 c2ls_assemble(0,®s[0]);break;
5627 c2op_assemble(0,®s[0]);break;
5629 multdiv_assemble(0,®s[0]);break;
5631 mov_assemble(0,®s[0]);break;
5640 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
5642 int btaddr=get_reg(regs[0].regmap,BTREG);
5644 btaddr=get_reg(regs[0].regmap,-1);
5645 emit_readword(&branch_target,btaddr);
5647 assert(btaddr!=HOST_CCREG);
5648 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
5650 host_tempreg_acquire();
5651 emit_movimm(start+4,HOST_TEMPREG);
5652 emit_cmp(btaddr,HOST_TEMPREG);
5653 host_tempreg_release();
5655 emit_cmpimm(btaddr,start+4);
5659 store_regs_bt(regs[0].regmap,regs[0].dirty,-1);
5660 do_jump_vaddr(btaddr);
5661 set_jump_target(branch, out);
5662 store_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
5663 load_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
5666 // Basic liveness analysis for MIPS registers
5667 void unneeded_registers(int istart,int iend,int r)
5670 uint64_t u,gte_u,b,gte_b;
5671 uint64_t temp_u,temp_gte_u=0;
5672 uint64_t gte_u_unknown=0;
5673 if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
5677 gte_u=gte_u_unknown;
5679 //u=unneeded_reg[iend+1];
5681 gte_u=gte_unneeded[iend+1];
5684 for (i=iend;i>=istart;i--)
5686 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
5687 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
5689 // If subroutine call, flag return address as a possible branch target
5690 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
5692 if(ba[i]<start || ba[i]>=(start+slen*4))
5694 // Branch out of this block, flush all regs
5696 gte_u=gte_u_unknown;
5697 branch_unneeded_reg[i]=u;
5698 // Merge in delay slot
5699 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
5700 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5703 gte_u&=~gte_rs[i+1];
5704 // If branch is "likely" (and conditional)
5705 // then we skip the delay slot on the fall-thru path
5708 u&=unneeded_reg[i+2];
5709 gte_u&=gte_unneeded[i+2];
5714 gte_u=gte_u_unknown;
5720 // Internal branch, flag target
5721 bt[(ba[i]-start)>>2]=1;
5722 if(ba[i]<=start+i*4) {
5724 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
5726 // Unconditional branch
5730 // Conditional branch (not taken case)
5731 temp_u=unneeded_reg[i+2];
5732 temp_gte_u&=gte_unneeded[i+2];
5734 // Merge in delay slot
5735 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
5736 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5738 temp_gte_u|=gte_rt[i+1];
5739 temp_gte_u&=~gte_rs[i+1];
5740 // If branch is "likely" (and conditional)
5741 // then we skip the delay slot on the fall-thru path
5744 temp_u&=unneeded_reg[i+2];
5745 temp_gte_u&=gte_unneeded[i+2];
5750 temp_gte_u=gte_u_unknown;
5753 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
5754 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5756 temp_gte_u|=gte_rt[i];
5757 temp_gte_u&=~gte_rs[i];
5758 unneeded_reg[i]=temp_u;
5759 gte_unneeded[i]=temp_gte_u;
5760 // Only go three levels deep. This recursion can take an
5761 // excessive amount of time if there are a lot of nested loops.
5763 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
5765 unneeded_reg[(ba[i]-start)>>2]=1;
5766 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
5769 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
5771 // Unconditional branch
5772 u=unneeded_reg[(ba[i]-start)>>2];
5773 gte_u=gte_unneeded[(ba[i]-start)>>2];
5774 branch_unneeded_reg[i]=u;
5775 // Merge in delay slot
5776 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
5777 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5780 gte_u&=~gte_rs[i+1];
5782 // Conditional branch
5783 b=unneeded_reg[(ba[i]-start)>>2];
5784 gte_b=gte_unneeded[(ba[i]-start)>>2];
5785 branch_unneeded_reg[i]=b;
5786 // Branch delay slot
5787 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
5788 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5791 gte_b&=~gte_rs[i+1];
5792 // If branch is "likely" then we skip the
5793 // delay slot on the fall-thru path
5798 u&=unneeded_reg[i+2];
5799 gte_u&=gte_unneeded[i+2];
5806 branch_unneeded_reg[i]&=unneeded_reg[i+2];
5808 branch_unneeded_reg[i]=1;
5814 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
5816 // SYSCALL instruction (software interrupt)
5819 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
5821 // ERET instruction (return from interrupt)
5825 // Written registers are unneeded
5829 // Accessed registers are needed
5833 if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
5834 gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
5835 // Source-target dependencies
5836 // R0 is always unneeded
5840 gte_unneeded[i]=gte_u;
5842 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
5845 for(r=1;r<=CCREG;r++) {
5846 if((unneeded_reg[i]>>r)&1) {
5847 if(r==HIREG) printf(" HI");
5848 else if(r==LOREG) printf(" LO");
5849 else printf(" r%d",r);
5857 // Write back dirty registers as soon as we will no longer modify them,
5858 // so that we don't end up with lots of writes at the branches.
5859 void clean_registers(int istart,int iend,int wr)
5863 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
5864 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
5866 will_dirty_i=will_dirty_next=0;
5867 wont_dirty_i=wont_dirty_next=0;
5869 will_dirty_i=will_dirty_next=will_dirty[iend+1];
5870 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
5872 for (i=iend;i>=istart;i--)
5874 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
5876 if(ba[i]<start || ba[i]>=(start+slen*4))
5878 // Branch out of this block, flush all regs
5879 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
5881 // Unconditional branch
5884 // Merge in delay slot (will dirty)
5885 for(r=0;r<HOST_REGS;r++) {
5886 if(r!=EXCLUDE_REG) {
5887 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
5888 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
5889 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
5890 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
5891 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
5892 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
5893 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
5894 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
5895 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
5896 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
5897 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
5898 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
5899 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
5900 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
5906 // Conditional branch
5908 wont_dirty_i=wont_dirty_next;
5909 // Merge in delay slot (will dirty)
5910 for(r=0;r<HOST_REGS;r++) {
5911 if(r!=EXCLUDE_REG) {
5913 // Might not dirty if likely branch is not taken
5914 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
5915 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
5916 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
5917 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
5918 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
5919 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
5920 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
5921 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
5922 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
5923 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
5924 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
5925 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
5926 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
5927 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
5932 // Merge in delay slot (wont dirty)
5933 for(r=0;r<HOST_REGS;r++) {
5934 if(r!=EXCLUDE_REG) {
5935 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
5936 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
5937 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
5938 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
5939 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
5940 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
5941 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
5942 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
5943 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
5944 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
5948 #ifndef DESTRUCTIVE_WRITEBACK
5949 branch_regs[i].dirty&=wont_dirty_i;
5951 branch_regs[i].dirty|=will_dirty_i;
5957 if(ba[i]<=start+i*4) {
5959 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
5961 // Unconditional branch
5964 // Merge in delay slot (will dirty)
5965 for(r=0;r<HOST_REGS;r++) {
5966 if(r!=EXCLUDE_REG) {
5967 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
5968 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
5969 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
5970 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
5971 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
5972 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
5973 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
5974 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
5975 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
5976 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
5977 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
5978 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
5979 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
5980 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
5984 // Conditional branch (not taken case)
5985 temp_will_dirty=will_dirty_next;
5986 temp_wont_dirty=wont_dirty_next;
5987 // Merge in delay slot (will dirty)
5988 for(r=0;r<HOST_REGS;r++) {
5989 if(r!=EXCLUDE_REG) {
5991 // Will not dirty if likely branch is not taken
5992 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
5993 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
5994 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
5995 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
5996 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
5997 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
5998 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
5999 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6000 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6001 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6002 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6003 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6004 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6005 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6010 // Merge in delay slot (wont dirty)
6011 for(r=0;r<HOST_REGS;r++) {
6012 if(r!=EXCLUDE_REG) {
6013 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
6014 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
6015 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
6016 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
6017 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6018 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
6019 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
6020 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
6021 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
6022 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6025 // Deal with changed mappings
6027 for(r=0;r<HOST_REGS;r++) {
6028 if(r!=EXCLUDE_REG) {
6029 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
6030 temp_will_dirty&=~(1<<r);
6031 temp_wont_dirty&=~(1<<r);
6032 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6033 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6034 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6036 temp_will_dirty|=1<<r;
6037 temp_wont_dirty|=1<<r;
6044 will_dirty[i]=temp_will_dirty;
6045 wont_dirty[i]=temp_wont_dirty;
6046 clean_registers((ba[i]-start)>>2,i-1,0);
6048 // Limit recursion. It can take an excessive amount
6049 // of time if there are a lot of nested loops.
6050 will_dirty[(ba[i]-start)>>2]=0;
6051 wont_dirty[(ba[i]-start)>>2]=-1;
6056 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6058 // Unconditional branch
6061 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6062 for(r=0;r<HOST_REGS;r++) {
6063 if(r!=EXCLUDE_REG) {
6064 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6065 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
6066 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6068 if(branch_regs[i].regmap[r]>=0) {
6069 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6070 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6075 // Merge in delay slot
6076 for(r=0;r<HOST_REGS;r++) {
6077 if(r!=EXCLUDE_REG) {
6078 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6079 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6080 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6081 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6082 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6083 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6084 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6085 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6086 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6087 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6088 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6089 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6090 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6091 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6095 // Conditional branch
6096 will_dirty_i=will_dirty_next;
6097 wont_dirty_i=wont_dirty_next;
6098 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6099 for(r=0;r<HOST_REGS;r++) {
6100 if(r!=EXCLUDE_REG) {
6101 signed char target_reg=branch_regs[i].regmap[r];
6102 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6103 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6104 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6106 else if(target_reg>=0) {
6107 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6108 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6110 // Treat delay slot as part of branch too
6111 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6112 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6113 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6117 will_dirty[i+1]&=~(1<<r);
6122 // Merge in delay slot
6123 for(r=0;r<HOST_REGS;r++) {
6124 if(r!=EXCLUDE_REG) {
6126 // Might not dirty if likely branch is not taken
6127 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6128 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6129 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6130 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6131 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6132 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6133 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6134 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6135 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6136 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6137 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6138 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6139 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6140 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6145 // Merge in delay slot (won't dirty)
6146 for(r=0;r<HOST_REGS;r++) {
6147 if(r!=EXCLUDE_REG) {
6148 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6149 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6150 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6151 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6152 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6153 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6154 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6155 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6156 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6157 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6161 #ifndef DESTRUCTIVE_WRITEBACK
6162 branch_regs[i].dirty&=wont_dirty_i;
6164 branch_regs[i].dirty|=will_dirty_i;
6169 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6171 // SYSCALL instruction (software interrupt)
6175 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6177 // ERET instruction (return from interrupt)
6181 will_dirty_next=will_dirty_i;
6182 wont_dirty_next=wont_dirty_i;
6183 for(r=0;r<HOST_REGS;r++) {
6184 if(r!=EXCLUDE_REG) {
6185 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6186 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6187 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6188 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6189 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6190 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6191 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6192 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6194 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP)
6196 // Don't store a register immediately after writing it,
6197 // may prevent dual-issue.
6198 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
6199 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
6205 will_dirty[i]=will_dirty_i;
6206 wont_dirty[i]=wont_dirty_i;
6207 // Mark registers that won't be dirtied as not dirty
6209 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
6210 for(r=0;r<HOST_REGS;r++) {
6211 if((will_dirty_i>>r)&1) {
6217 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP)) {
6218 regs[i].dirty|=will_dirty_i;
6219 #ifndef DESTRUCTIVE_WRITEBACK
6220 regs[i].dirty&=wont_dirty_i;
6221 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
6223 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
6224 for(r=0;r<HOST_REGS;r++) {
6225 if(r!=EXCLUDE_REG) {
6226 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
6227 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
6228 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6236 for(r=0;r<HOST_REGS;r++) {
6237 if(r!=EXCLUDE_REG) {
6238 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
6239 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
6240 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6248 // Deal with changed mappings
6249 temp_will_dirty=will_dirty_i;
6250 temp_wont_dirty=wont_dirty_i;
6251 for(r=0;r<HOST_REGS;r++) {
6252 if(r!=EXCLUDE_REG) {
6254 if(regs[i].regmap[r]==regmap_pre[i][r]) {
6256 #ifndef DESTRUCTIVE_WRITEBACK
6257 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6259 regs[i].wasdirty|=will_dirty_i&(1<<r);
6262 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
6263 // Register moved to a different register
6264 will_dirty_i&=~(1<<r);
6265 wont_dirty_i&=~(1<<r);
6266 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
6267 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
6269 #ifndef DESTRUCTIVE_WRITEBACK
6270 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6272 regs[i].wasdirty|=will_dirty_i&(1<<r);
6276 will_dirty_i&=~(1<<r);
6277 wont_dirty_i&=~(1<<r);
6278 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6279 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6280 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6283 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
6293 void disassemble_inst(int i)
6295 if (bt[i]) printf("*"); else printf(" ");
6298 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6300 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
6302 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
6304 if (opcode[i]==0x9&&rt1[i]!=31)
6305 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
6307 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
6310 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
6312 if(opcode[i]==0xf) //LUI
6313 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
6315 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
6319 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
6323 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
6327 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
6330 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
6333 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
6336 if((opcode2[i]&0x1d)==0x10)
6337 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
6338 else if((opcode2[i]&0x1d)==0x11)
6339 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
6341 printf (" %x: %s\n",start+i*4,insn[i]);
6345 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
6346 else if(opcode2[i]==4)
6347 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
6348 else printf (" %x: %s\n",start+i*4,insn[i]);
6352 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
6353 else if(opcode2[i]>3)
6354 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
6355 else printf (" %x: %s\n",start+i*4,insn[i]);
6359 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
6360 else if(opcode2[i]>3)
6361 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
6362 else printf (" %x: %s\n",start+i*4,insn[i]);
6365 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
6368 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
6371 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6374 //printf (" %s %8x\n",insn[i],source[i]);
6375 printf (" %x: %s\n",start+i*4,insn[i]);
6379 static void disassemble_inst(int i) {}
6382 #define DRC_TEST_VAL 0x74657374
6384 static void new_dynarec_test(void)
6386 int (*testfunc)(void);
6391 // check structure linkage
6392 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
6394 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
6397 SysPrintf("testing if we can run recompiled code...\n");
6398 ((volatile u_int *)out)[0]++; // make cache dirty
6400 for (i = 0; i < ARRAY_SIZE(ret); i++) {
6401 out = translation_cache;
6402 beginning = start_block();
6403 emit_movimm(DRC_TEST_VAL + i, 0); // test
6406 end_block(beginning);
6407 testfunc = beginning;
6408 ret[i] = testfunc();
6411 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
6412 SysPrintf("test passed.\n");
6414 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
6415 out = translation_cache;
6418 // clear the state completely, instead of just marking
6419 // things invalid like invalidate_all_pages() does
6420 void new_dynarec_clear_full()
6423 out = translation_cache;
6424 memset(invalid_code,1,sizeof(invalid_code));
6425 memset(hash_table,0xff,sizeof(hash_table));
6426 memset(mini_ht,-1,sizeof(mini_ht));
6427 memset(restore_candidate,0,sizeof(restore_candidate));
6428 memset(shadow,0,sizeof(shadow));
6430 expirep=16384; // Expiry pointer, +2 blocks
6431 pending_exception=0;
6434 inv_code_start=inv_code_end=~0;
6436 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6437 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6438 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6441 void new_dynarec_init()
6443 SysPrintf("Init new dynarec\n");
6445 // allocate/prepare a buffer for translation cache
6446 // see assem_arm.h for some explanation
6447 #if defined(BASE_ADDR_FIXED)
6448 if (mmap(translation_cache, 1 << TARGET_SIZE_2,
6449 PROT_READ | PROT_WRITE | PROT_EXEC,
6450 MAP_PRIVATE | MAP_ANONYMOUS,
6451 -1, 0) != translation_cache) {
6452 SysPrintf("mmap() failed: %s\n", strerror(errno));
6453 SysPrintf("disable BASE_ADDR_FIXED and recompile\n");
6456 #elif defined(BASE_ADDR_DYNAMIC)
6458 sceBlock = sceKernelAllocMemBlockForVM("code", 1 << TARGET_SIZE_2);
6460 SysPrintf("sceKernelAllocMemBlockForVM failed\n");
6461 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&translation_cache);
6463 SysPrintf("sceKernelGetMemBlockBase failed\n");
6465 translation_cache = mmap (NULL, 1 << TARGET_SIZE_2,
6466 PROT_READ | PROT_WRITE | PROT_EXEC,
6467 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
6468 if (translation_cache == MAP_FAILED) {
6469 SysPrintf("mmap() failed: %s\n", strerror(errno));
6474 #ifndef NO_WRITE_EXEC
6475 // not all systems allow execute in data segment by default
6476 if (mprotect(translation_cache, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
6477 SysPrintf("mprotect() failed: %s\n", strerror(errno));
6480 out = translation_cache;
6481 cycle_multiplier=200;
6482 new_dynarec_clear_full();
6484 // Copy this into local area so we don't have to put it in every literal pool
6485 invc_ptr=invalid_code;
6490 ram_offset=(uintptr_t)rdram-0x80000000;
6493 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
6496 void new_dynarec_cleanup()
6499 #if defined(BASE_ADDR_FIXED) || defined(BASE_ADDR_DYNAMIC)
6501 sceKernelFreeMemBlock(sceBlock);
6504 if (munmap(translation_cache, 1<<TARGET_SIZE_2) < 0)
6505 SysPrintf("munmap() failed\n");
6508 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6509 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6510 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6512 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
6516 static u_int *get_source_start(u_int addr, u_int *limit)
6518 if (addr < 0x00200000 ||
6519 (0xa0000000 <= addr && addr < 0xa0200000)) {
6520 // used for BIOS calls mostly?
6521 *limit = (addr&0xa0000000)|0x00200000;
6522 return (u_int *)(rdram + (addr&0x1fffff));
6524 else if (!Config.HLE && (
6525 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
6526 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
6528 *limit = (addr & 0xfff00000) | 0x80000;
6529 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
6531 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
6532 *limit = (addr & 0x80600000) + 0x00200000;
6533 return (u_int *)(rdram + (addr&0x1fffff));
6538 static u_int scan_for_ret(u_int addr)
6543 mem = get_source_start(addr, &limit);
6547 if (limit > addr + 0x1000)
6548 limit = addr + 0x1000;
6549 for (; addr < limit; addr += 4, mem++) {
6550 if (*mem == 0x03e00008) // jr $ra
6556 struct savestate_block {
6561 static int addr_cmp(const void *p1_, const void *p2_)
6563 const struct savestate_block *p1 = p1_, *p2 = p2_;
6564 return p1->addr - p2->addr;
6567 int new_dynarec_save_blocks(void *save, int size)
6569 struct savestate_block *blocks = save;
6570 int maxcount = size / sizeof(blocks[0]);
6571 struct savestate_block tmp_blocks[1024];
6572 struct ll_entry *head;
6573 int p, s, d, o, bcnt;
6577 for (p = 0; p < ARRAY_SIZE(jump_in); p++) {
6579 for (head = jump_in[p]; head != NULL; head = head->next) {
6580 tmp_blocks[bcnt].addr = head->vaddr;
6581 tmp_blocks[bcnt].regflags = head->reg_sv_flags;
6586 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6588 addr = tmp_blocks[0].addr;
6589 for (s = d = 0; s < bcnt; s++) {
6590 if (tmp_blocks[s].addr < addr)
6592 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6593 tmp_blocks[d++] = tmp_blocks[s];
6594 addr = scan_for_ret(tmp_blocks[s].addr);
6597 if (o + d > maxcount)
6599 memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
6603 return o * sizeof(blocks[0]);
6606 void new_dynarec_load_blocks(const void *save, int size)
6608 const struct savestate_block *blocks = save;
6609 int count = size / sizeof(blocks[0]);
6610 u_int regs_save[32];
6614 get_addr(psxRegs.pc);
6616 // change GPRs for speculation to at least partially work..
6617 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
6618 for (i = 1; i < 32; i++)
6619 psxRegs.GPR.r[i] = 0x80000000;
6621 for (b = 0; b < count; b++) {
6622 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
6624 psxRegs.GPR.r[i] = 0x1f800000;
6627 get_addr(blocks[b].addr);
6629 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
6631 psxRegs.GPR.r[i] = 0x80000000;
6635 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
6638 int new_recompile_block(u_int addr)
6640 u_int pagelimit = 0;
6641 u_int state_rflags = 0;
6644 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
6645 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
6647 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
6649 // this is just for speculation
6650 for (i = 1; i < 32; i++) {
6651 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
6652 state_rflags |= 1 << i;
6655 start = (u_int)addr&~3;
6656 //assert(((u_int)addr&1)==0); // start-in-delay-slot flag
6657 new_dynarec_did_compile=1;
6658 if (Config.HLE && start == 0x80001000) // hlecall
6660 // XXX: is this enough? Maybe check hleSoftCall?
6661 void *beginning=start_block();
6662 u_int page=get_page(start);
6664 invalid_code[start>>12]=0;
6665 emit_movimm(start,0);
6666 emit_writeword(0,&pcaddr);
6667 emit_jmp(new_dyna_leave);
6669 end_block(beginning);
6670 ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
6674 source = get_source_start(start, &pagelimit);
6675 if (source == NULL) {
6676 SysPrintf("Compile at bogus memory address: %08x\n", addr);
6680 /* Pass 1: disassemble */
6681 /* Pass 2: register dependencies, branch targets */
6682 /* Pass 3: register allocation */
6683 /* Pass 4: branch dependencies */
6684 /* Pass 5: pre-alloc */
6685 /* Pass 6: optimize clean/dirty state */
6686 /* Pass 7: flag 32-bit registers */
6687 /* Pass 8: assembly */
6688 /* Pass 9: linker */
6689 /* Pass 10: garbage collection / free memory */
6693 unsigned int type,op,op2;
6695 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
6697 /* Pass 1 disassembly */
6699 for(i=0;!done;i++) {
6700 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
6701 minimum_free_regs[i]=0;
6702 opcode[i]=op=source[i]>>26;
6705 case 0x00: strcpy(insn[i],"special"); type=NI;
6709 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
6710 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
6711 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
6712 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
6713 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
6714 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
6715 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
6716 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
6717 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
6718 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
6719 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
6720 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
6721 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
6722 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
6723 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
6724 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
6725 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
6726 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
6727 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
6728 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
6729 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
6730 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
6731 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
6732 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
6733 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
6734 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
6735 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
6736 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
6737 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
6738 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
6739 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
6740 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
6741 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
6742 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
6743 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
6745 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
6746 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
6747 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
6748 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
6749 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
6750 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
6751 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
6752 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
6753 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
6754 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
6755 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
6756 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
6757 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
6758 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
6759 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
6760 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
6761 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
6765 case 0x01: strcpy(insn[i],"regimm"); type=NI;
6766 op2=(source[i]>>16)&0x1f;
6769 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
6770 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
6771 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
6772 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
6773 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
6774 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
6775 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
6776 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
6777 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
6778 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
6779 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
6780 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
6781 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
6782 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
6785 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
6786 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
6787 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
6788 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
6789 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
6790 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
6791 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
6792 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
6793 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
6794 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
6795 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
6796 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
6797 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
6798 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
6799 case 0x10: strcpy(insn[i],"cop0"); type=NI;
6800 op2=(source[i]>>21)&0x1f;
6803 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
6804 case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break;
6805 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
6806 case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break;
6807 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
6810 case 0x11: strcpy(insn[i],"cop1"); type=COP1;
6811 op2=(source[i]>>21)&0x1f;
6814 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
6815 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
6816 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
6817 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
6818 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
6819 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
6820 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
6821 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
6823 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
6824 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
6825 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
6826 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
6827 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
6828 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
6829 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
6831 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
6833 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
6834 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
6835 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
6836 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
6838 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
6839 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
6841 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
6842 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
6843 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
6844 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
6846 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
6847 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
6848 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
6850 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
6851 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
6853 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
6854 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
6855 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
6857 case 0x12: strcpy(insn[i],"COP2"); type=NI;
6858 op2=(source[i]>>21)&0x1f;
6860 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
6861 if (gte_handlers[source[i]&0x3f]!=NULL) {
6862 if (gte_regnames[source[i]&0x3f]!=NULL)
6863 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
6865 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
6871 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
6872 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
6873 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
6874 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
6877 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
6878 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
6879 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
6880 default: strcpy(insn[i],"???"); type=NI;
6881 SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
6886 /* Get registers/immediates */
6890 gte_rs[i]=gte_rt[i]=0;
6893 rs1[i]=(source[i]>>21)&0x1f;
6895 rt1[i]=(source[i]>>16)&0x1f;
6897 imm[i]=(short)source[i];
6901 rs1[i]=(source[i]>>21)&0x1f;
6902 rs2[i]=(source[i]>>16)&0x1f;
6905 imm[i]=(short)source[i];
6908 // LWL/LWR only load part of the register,
6909 // therefore the target register must be treated as a source too
6910 rs1[i]=(source[i]>>21)&0x1f;
6911 rs2[i]=(source[i]>>16)&0x1f;
6912 rt1[i]=(source[i]>>16)&0x1f;
6914 imm[i]=(short)source[i];
6915 if(op==0x26) dep1[i]=rt1[i]; // LWR
6918 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
6919 else rs1[i]=(source[i]>>21)&0x1f;
6921 rt1[i]=(source[i]>>16)&0x1f;
6923 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
6924 imm[i]=(unsigned short)source[i];
6926 imm[i]=(short)source[i];
6928 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
6935 // The JAL instruction writes to r31.
6942 rs1[i]=(source[i]>>21)&0x1f;
6946 // The JALR instruction writes to rd.
6948 rt1[i]=(source[i]>>11)&0x1f;
6953 rs1[i]=(source[i]>>21)&0x1f;
6954 rs2[i]=(source[i]>>16)&0x1f;
6957 if(op&2) { // BGTZ/BLEZ
6963 rs1[i]=(source[i]>>21)&0x1f;
6967 if(op2&0x10) { // BxxAL
6969 // NOTE: If the branch is not taken, r31 is still overwritten
6971 likely[i]=(op2&2)>>1;
6974 rs1[i]=(source[i]>>21)&0x1f; // source
6975 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
6976 rt1[i]=(source[i]>>11)&0x1f; // destination
6978 if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6979 dep1[i]=rs1[i];dep2[i]=rs2[i];
6981 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
6982 dep1[i]=rs1[i];dep2[i]=rs2[i];
6986 rs1[i]=(source[i]>>21)&0x1f; // source
6987 rs2[i]=(source[i]>>16)&0x1f; // divisor
6996 if(op2==0x10) rs1[i]=HIREG; // MFHI
6997 if(op2==0x11) rt1[i]=HIREG; // MTHI
6998 if(op2==0x12) rs1[i]=LOREG; // MFLO
6999 if(op2==0x13) rt1[i]=LOREG; // MTLO
7000 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
7001 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
7005 rs1[i]=(source[i]>>16)&0x1f; // target of shift
7006 rs2[i]=(source[i]>>21)&0x1f; // shift amount
7007 rt1[i]=(source[i]>>11)&0x1f; // destination
7011 rs1[i]=(source[i]>>16)&0x1f;
7013 rt1[i]=(source[i]>>11)&0x1f;
7015 imm[i]=(source[i]>>6)&0x1f;
7016 // DSxx32 instructions
7017 if(op2>=0x3c) imm[i]|=0x20;
7024 if(op2==0||op2==2) rt1[i]=(source[i]>>16)&0x1F; // MFC0/CFC0
7025 if(op2==4||op2==6) rs1[i]=(source[i]>>16)&0x1F; // MTC0/CTC0
7026 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
7027 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
7034 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7035 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7043 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
7044 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
7046 int gr=(source[i]>>11)&0x1F;
7049 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
7050 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
7051 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
7052 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
7056 rs1[i]=(source[i]>>21)&0x1F;
7060 imm[i]=(short)source[i];
7063 rs1[i]=(source[i]>>21)&0x1F;
7067 imm[i]=(short)source[i];
7068 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7069 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7076 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7077 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7078 gte_rt[i]|=1ll<<63; // every op changes flags
7079 if((source[i]&0x3f)==GTE_MVMVA) {
7080 int v = (source[i] >> 15) & 3;
7081 gte_rs[i]&=~0xe3fll;
7082 if(v==3) gte_rs[i]|=0xe00ll;
7083 else gte_rs[i]|=3ll<<(v*2);
7100 /* Calculate branch target addresses */
7102 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
7103 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
7104 ba[i]=start+i*4+8; // Ignore never taken branch
7105 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
7106 ba[i]=start+i*4+8; // Ignore never taken branch
7107 else if(type==CJUMP||type==SJUMP)
7108 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7110 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP)) {
7112 // branch in delay slot?
7113 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP) {
7114 // don't handle first branch and call interpreter if it's hit
7115 SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
7118 // basic load delay detection
7119 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
7120 int t=(ba[i-1]-start)/4;
7121 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
7122 // jump target wants DS result - potential load delay effect
7123 SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
7125 bt[t+1]=1; // expected return from interpreter
7127 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
7128 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
7129 // v0 overwrite like this is a sign of trouble, bail out
7130 SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
7136 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
7140 i--; // don't compile the DS
7143 /* Is this the end of the block? */
7144 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
7145 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
7149 if(stop_after_jal) done=1;
7151 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7153 // Don't recompile stuff that's already compiled
7154 if(check_addr(start+i*4+4)) done=1;
7155 // Don't get too close to the limit
7156 if(i>MAXBLOCK/2) done=1;
7158 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
7159 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
7161 // Does the block continue due to a branch?
7164 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
7165 if(ba[j]==start+i*4+4) done=j=0;
7166 if(ba[j]==start+i*4+8) done=j=0;
7169 //assert(i<MAXBLOCK-1);
7170 if(start+i*4==pagelimit-4) done=1;
7171 assert(start+i*4<pagelimit);
7172 if (i==MAXBLOCK-1) done=1;
7173 // Stop if we're compiling junk
7174 if(itype[i]==NI&&opcode[i]==0x11) {
7175 done=stop_after_jal=1;
7176 SysPrintf("Disabled speculative precompilation\n");
7180 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP) {
7181 if(start+i*4==pagelimit) {
7187 /* Pass 2 - Register dependencies and branch targets */
7189 unneeded_registers(0,slen-1,0);
7191 /* Pass 3 - Register allocation */
7193 struct regstat current; // Current register allocations/status
7195 current.u=unneeded_reg[0];
7196 clear_all_regs(current.regmap);
7197 alloc_reg(¤t,0,CCREG);
7198 dirty_reg(¤t,CCREG);
7201 current.waswritten=0;
7207 // First instruction is delay slot
7212 current.regmap[HOST_BTREG]=BTREG;
7220 for(hr=0;hr<HOST_REGS;hr++)
7222 // Is this really necessary?
7223 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7226 current.waswritten=0;
7229 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7230 regs[i].wasconst=current.isconst;
7231 regs[i].wasdirty=current.dirty;
7232 regs[i].loadedconst=0;
7233 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP) {
7235 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
7242 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
7243 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
7245 } else { SysPrintf("oops, branch at end of block with no delay slot\n");abort(); }
7249 ds=0; // Skip delay slot, already allocated as part of branch
7250 // ...but we need to alloc it in case something jumps here
7252 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
7254 current.u=branch_unneeded_reg[i-1];
7256 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
7258 struct regstat temp;
7259 memcpy(&temp,¤t,sizeof(current));
7260 temp.wasdirty=temp.dirty;
7261 // TODO: Take into account unconditional branches, as below
7262 delayslot_alloc(&temp,i);
7263 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7264 regs[i].wasdirty=temp.wasdirty;
7265 regs[i].dirty=temp.dirty;
7269 // Create entry (branch target) regmap
7270 for(hr=0;hr<HOST_REGS;hr++)
7272 int r=temp.regmap[hr];
7274 if(r!=regmap_pre[i][hr]) {
7275 regs[i].regmap_entry[hr]=-1;
7280 if((current.u>>r)&1) {
7281 regs[i].regmap_entry[hr]=-1;
7282 regs[i].regmap[hr]=-1;
7283 //Don't clear regs in the delay slot as the branch might need them
7284 //current.regmap[hr]=-1;
7286 regs[i].regmap_entry[hr]=r;
7289 // First instruction expects CCREG to be allocated
7290 if(i==0&&hr==HOST_CCREG)
7291 regs[i].regmap_entry[hr]=CCREG;
7293 regs[i].regmap_entry[hr]=-1;
7297 else { // Not delay slot
7300 //current.isconst=0; // DEBUG
7301 //current.wasconst=0; // DEBUG
7302 //regs[i].wasconst=0; // DEBUG
7303 clear_const(¤t,rt1[i]);
7304 alloc_cc(¤t,i);
7305 dirty_reg(¤t,CCREG);
7307 alloc_reg(¤t,i,31);
7308 dirty_reg(¤t,31);
7309 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
7310 //assert(rt1[i+1]!=rt1[i]);
7312 alloc_reg(¤t,i,PTEMP);
7316 delayslot_alloc(¤t,i+1);
7317 //current.isconst=0; // DEBUG
7319 //printf("i=%d, isconst=%x\n",i,current.isconst);
7322 //current.isconst=0;
7323 //current.wasconst=0;
7324 //regs[i].wasconst=0;
7325 clear_const(¤t,rs1[i]);
7326 clear_const(¤t,rt1[i]);
7327 alloc_cc(¤t,i);
7328 dirty_reg(¤t,CCREG);
7329 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
7330 alloc_reg(¤t,i,rs1[i]);
7332 alloc_reg(¤t,i,rt1[i]);
7333 dirty_reg(¤t,rt1[i]);
7334 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
7335 assert(rt1[i+1]!=rt1[i]);
7337 alloc_reg(¤t,i,PTEMP);
7341 if(rs1[i]==31) { // JALR
7342 alloc_reg(¤t,i,RHASH);
7343 alloc_reg(¤t,i,RHTBL);
7346 delayslot_alloc(¤t,i+1);
7348 // The delay slot overwrites our source register,
7349 // allocate a temporary register to hold the old value.
7353 delayslot_alloc(¤t,i+1);
7355 alloc_reg(¤t,i,RTEMP);
7357 //current.isconst=0; // DEBUG
7362 //current.isconst=0;
7363 //current.wasconst=0;
7364 //regs[i].wasconst=0;
7365 clear_const(¤t,rs1[i]);
7366 clear_const(¤t,rs2[i]);
7367 if((opcode[i]&0x3E)==4) // BEQ/BNE
7369 alloc_cc(¤t,i);
7370 dirty_reg(¤t,CCREG);
7371 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
7372 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
7373 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
7374 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
7375 // The delay slot overwrites one of our conditions.
7376 // Allocate the branch condition registers instead.
7380 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
7381 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
7386 delayslot_alloc(¤t,i+1);
7390 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
7392 alloc_cc(¤t,i);
7393 dirty_reg(¤t,CCREG);
7394 alloc_reg(¤t,i,rs1[i]);
7395 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
7396 // The delay slot overwrites one of our conditions.
7397 // Allocate the branch condition registers instead.
7401 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
7406 delayslot_alloc(¤t,i+1);
7410 // Don't alloc the delay slot yet because we might not execute it
7411 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
7416 alloc_cc(¤t,i);
7417 dirty_reg(¤t,CCREG);
7418 alloc_reg(¤t,i,rs1[i]);
7419 alloc_reg(¤t,i,rs2[i]);
7422 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
7427 alloc_cc(¤t,i);
7428 dirty_reg(¤t,CCREG);
7429 alloc_reg(¤t,i,rs1[i]);
7432 //current.isconst=0;
7435 //current.isconst=0;
7436 //current.wasconst=0;
7437 //regs[i].wasconst=0;
7438 clear_const(¤t,rs1[i]);
7439 clear_const(¤t,rt1[i]);
7440 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
7441 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
7443 alloc_cc(¤t,i);
7444 dirty_reg(¤t,CCREG);
7445 alloc_reg(¤t,i,rs1[i]);
7446 if (rt1[i]==31) { // BLTZAL/BGEZAL
7447 alloc_reg(¤t,i,31);
7448 dirty_reg(¤t,31);
7449 //#ifdef REG_PREFETCH
7450 //alloc_reg(¤t,i,PTEMP);
7453 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
7454 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
7455 // Allocate the branch condition registers instead.
7459 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
7464 delayslot_alloc(¤t,i+1);
7468 // Don't alloc the delay slot yet because we might not execute it
7469 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
7474 alloc_cc(¤t,i);
7475 dirty_reg(¤t,CCREG);
7476 alloc_reg(¤t,i,rs1[i]);
7479 //current.isconst=0;
7482 imm16_alloc(¤t,i);
7486 load_alloc(¤t,i);
7490 store_alloc(¤t,i);
7493 alu_alloc(¤t,i);
7496 shift_alloc(¤t,i);
7499 multdiv_alloc(¤t,i);
7502 shiftimm_alloc(¤t,i);
7505 mov_alloc(¤t,i);
7508 cop0_alloc(¤t,i);
7512 cop12_alloc(¤t,i);
7515 c1ls_alloc(¤t,i);
7518 c2ls_alloc(¤t,i);
7521 c2op_alloc(¤t,i);
7526 syscall_alloc(¤t,i);
7529 pagespan_alloc(¤t,i);
7533 // Create entry (branch target) regmap
7534 for(hr=0;hr<HOST_REGS;hr++)
7537 r=current.regmap[hr];
7539 if(r!=regmap_pre[i][hr]) {
7540 // TODO: delay slot (?)
7541 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
7542 if(or<0||(r&63)>=TEMPREG){
7543 regs[i].regmap_entry[hr]=-1;
7547 // Just move it to a different register
7548 regs[i].regmap_entry[hr]=r;
7549 // If it was dirty before, it's still dirty
7550 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
7557 regs[i].regmap_entry[hr]=0;
7562 if((current.u>>r)&1) {
7563 regs[i].regmap_entry[hr]=-1;
7564 //regs[i].regmap[hr]=-1;
7565 current.regmap[hr]=-1;
7567 regs[i].regmap_entry[hr]=r;
7571 // Branches expect CCREG to be allocated at the target
7572 if(regmap_pre[i][hr]==CCREG)
7573 regs[i].regmap_entry[hr]=CCREG;
7575 regs[i].regmap_entry[hr]=-1;
7578 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
7581 if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
7582 current.waswritten|=1<<rs1[i-1];
7583 current.waswritten&=~(1<<rt1[i]);
7584 current.waswritten&=~(1<<rt2[i]);
7585 if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
7586 current.waswritten&=~(1<<rs1[i]);
7588 /* Branch post-alloc */
7591 current.wasdirty=current.dirty;
7592 switch(itype[i-1]) {
7594 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7595 branch_regs[i-1].isconst=0;
7596 branch_regs[i-1].wasconst=0;
7597 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
7598 alloc_cc(&branch_regs[i-1],i-1);
7599 dirty_reg(&branch_regs[i-1],CCREG);
7600 if(rt1[i-1]==31) { // JAL
7601 alloc_reg(&branch_regs[i-1],i-1,31);
7602 dirty_reg(&branch_regs[i-1],31);
7604 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7605 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
7608 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7609 branch_regs[i-1].isconst=0;
7610 branch_regs[i-1].wasconst=0;
7611 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
7612 alloc_cc(&branch_regs[i-1],i-1);
7613 dirty_reg(&branch_regs[i-1],CCREG);
7614 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
7615 if(rt1[i-1]!=0) { // JALR
7616 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
7617 dirty_reg(&branch_regs[i-1],rt1[i-1]);
7620 if(rs1[i-1]==31) { // JALR
7621 alloc_reg(&branch_regs[i-1],i-1,RHASH);
7622 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
7625 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7626 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
7629 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
7631 alloc_cc(¤t,i-1);
7632 dirty_reg(¤t,CCREG);
7633 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
7634 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
7635 // The delay slot overwrote one of our conditions
7636 // Delay slot goes after the test (in order)
7637 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
7639 delayslot_alloc(¤t,i);
7644 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
7645 // Alloc the branch condition registers
7646 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
7647 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
7649 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7650 branch_regs[i-1].isconst=0;
7651 branch_regs[i-1].wasconst=0;
7652 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7653 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
7656 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
7658 alloc_cc(¤t,i-1);
7659 dirty_reg(¤t,CCREG);
7660 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
7661 // The delay slot overwrote the branch condition
7662 // Delay slot goes after the test (in order)
7663 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
7665 delayslot_alloc(¤t,i);
7670 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
7671 // Alloc the branch condition register
7672 alloc_reg(¤t,i-1,rs1[i-1]);
7674 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7675 branch_regs[i-1].isconst=0;
7676 branch_regs[i-1].wasconst=0;
7677 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7678 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
7681 // Alloc the delay slot in case the branch is taken
7682 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
7684 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7685 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
7686 alloc_cc(&branch_regs[i-1],i);
7687 dirty_reg(&branch_regs[i-1],CCREG);
7688 delayslot_alloc(&branch_regs[i-1],i);
7689 branch_regs[i-1].isconst=0;
7690 alloc_reg(¤t,i,CCREG); // Not taken path
7691 dirty_reg(¤t,CCREG);
7692 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7695 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
7697 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7698 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
7699 alloc_cc(&branch_regs[i-1],i);
7700 dirty_reg(&branch_regs[i-1],CCREG);
7701 delayslot_alloc(&branch_regs[i-1],i);
7702 branch_regs[i-1].isconst=0;
7703 alloc_reg(¤t,i,CCREG); // Not taken path
7704 dirty_reg(¤t,CCREG);
7705 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7709 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
7710 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
7712 alloc_cc(¤t,i-1);
7713 dirty_reg(¤t,CCREG);
7714 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
7715 // The delay slot overwrote the branch condition
7716 // Delay slot goes after the test (in order)
7717 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
7719 delayslot_alloc(¤t,i);
7724 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
7725 // Alloc the branch condition register
7726 alloc_reg(¤t,i-1,rs1[i-1]);
7728 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7729 branch_regs[i-1].isconst=0;
7730 branch_regs[i-1].wasconst=0;
7731 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7732 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
7735 // Alloc the delay slot in case the branch is taken
7736 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
7738 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7739 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
7740 alloc_cc(&branch_regs[i-1],i);
7741 dirty_reg(&branch_regs[i-1],CCREG);
7742 delayslot_alloc(&branch_regs[i-1],i);
7743 branch_regs[i-1].isconst=0;
7744 alloc_reg(¤t,i,CCREG); // Not taken path
7745 dirty_reg(¤t,CCREG);
7746 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7748 // FIXME: BLTZAL/BGEZAL
7749 if(opcode2[i-1]&0x10) { // BxxZAL
7750 alloc_reg(&branch_regs[i-1],i-1,31);
7751 dirty_reg(&branch_regs[i-1],31);
7756 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7758 if(rt1[i-1]==31) // JAL/JALR
7760 // Subroutine call will return here, don't alloc any registers
7762 clear_all_regs(current.regmap);
7763 alloc_reg(¤t,i,CCREG);
7764 dirty_reg(¤t,CCREG);
7768 // Internal branch will jump here, match registers to caller
7770 clear_all_regs(current.regmap);
7771 alloc_reg(¤t,i,CCREG);
7772 dirty_reg(¤t,CCREG);
7775 if(ba[j]==start+i*4+4) {
7776 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
7777 current.dirty=branch_regs[j].dirty;
7782 if(ba[j]==start+i*4+4) {
7783 for(hr=0;hr<HOST_REGS;hr++) {
7784 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
7785 current.regmap[hr]=-1;
7787 current.dirty&=branch_regs[j].dirty;
7796 // Count cycles in between branches
7798 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
7802 #if !defined(DRC_DBG)
7803 else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2)
7805 // GTE runs in parallel until accessed, divide by 2 for a rough guess
7806 cc+=gte_cycletab[source[i]&0x3f]/2;
7808 else if(/*itype[i]==LOAD||itype[i]==STORE||*/itype[i]==C1LS) // load,store causes weird timing issues
7810 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
7812 else if(i>1&&itype[i]==STORE&&itype[i-1]==STORE&&itype[i-2]==STORE&&!bt[i])
7816 else if(itype[i]==C2LS)
7827 regs[i].dirty=current.dirty;
7828 regs[i].isconst=current.isconst;
7829 memcpy(constmap[i],current_constmap,sizeof(current_constmap));
7831 for(hr=0;hr<HOST_REGS;hr++) {
7832 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
7833 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
7834 regs[i].wasconst&=~(1<<hr);
7838 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
7839 regs[i].waswritten=current.waswritten;
7842 /* Pass 4 - Cull unused host registers */
7846 for (i=slen-1;i>=0;i--)
7849 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
7851 if(ba[i]<start || ba[i]>=(start+slen*4))
7853 // Branch out of this block, don't need anything
7859 // Need whatever matches the target
7861 int t=(ba[i]-start)>>2;
7862 for(hr=0;hr<HOST_REGS;hr++)
7864 if(regs[i].regmap_entry[hr]>=0) {
7865 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
7869 // Conditional branch may need registers for following instructions
7870 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7873 nr|=needed_reg[i+2];
7874 for(hr=0;hr<HOST_REGS;hr++)
7876 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
7877 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
7881 // Don't need stuff which is overwritten
7882 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7883 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7884 // Merge in delay slot
7885 for(hr=0;hr<HOST_REGS;hr++)
7888 // These are overwritten unless the branch is "likely"
7889 // and the delay slot is nullified if not taken
7890 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
7891 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
7893 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
7894 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
7895 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
7896 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
7897 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
7898 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
7899 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
7903 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7905 // SYSCALL instruction (software interrupt)
7908 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7910 // ERET instruction (return from interrupt)
7916 for(hr=0;hr<HOST_REGS;hr++) {
7917 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
7918 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
7919 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7920 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7924 for(hr=0;hr<HOST_REGS;hr++)
7926 // Overwritten registers are not needed
7927 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
7928 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
7929 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
7930 // Source registers are needed
7931 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
7932 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
7933 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
7934 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
7935 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
7936 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
7937 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
7939 // Don't store a register immediately after writing it,
7940 // may prevent dual-issue.
7941 // But do so if this is a branch target, otherwise we
7942 // might have to load the register before the branch.
7943 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
7944 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
7945 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
7946 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
7948 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
7949 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
7950 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
7954 // Cycle count is needed at branches. Assume it is needed at the target too.
7955 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==SPAN) {
7956 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7957 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7962 // Deallocate unneeded registers
7963 for(hr=0;hr<HOST_REGS;hr++)
7966 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
7967 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
7968 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
7969 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
7971 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7974 regs[i].regmap[hr]=-1;
7975 regs[i].isconst&=~(1<<hr);
7977 regmap_pre[i+2][hr]=-1;
7978 regs[i+2].wasconst&=~(1<<hr);
7983 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
7986 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
7987 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
7990 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
7991 itype[i+1]==C1LS || itype[i+1]==C2LS)
7993 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
7994 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
7995 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
7996 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
7997 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
7998 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
7999 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
8000 regs[i].regmap[hr]!=map )
8002 regs[i].regmap[hr]=-1;
8003 regs[i].isconst&=~(1<<hr);
8004 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
8005 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
8006 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
8007 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
8008 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
8009 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8010 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
8011 branch_regs[i].regmap[hr]!=map)
8013 branch_regs[i].regmap[hr]=-1;
8014 branch_regs[i].regmap_entry[hr]=-1;
8015 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
8017 if(!likely[i]&&i<slen-2) {
8018 regmap_pre[i+2][hr]=-1;
8019 regs[i+2].wasconst&=~(1<<hr);
8031 if(itype[i]==STORE || itype[i]==STORELR ||
8032 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
8035 if(itype[i]==LOADLR || itype[i]==STORELR ||
8036 itype[i]==C1LS || itype[i]==C2LS)
8038 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
8039 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
8040 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
8041 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
8043 if(i<slen-1&&!is_ds[i]) {
8044 assert(regs[i].regmap[hr]<64);
8045 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
8046 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
8048 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
8049 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8051 regmap_pre[i+1][hr]=-1;
8052 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
8053 regs[i+1].wasconst&=~(1<<hr);
8055 regs[i].regmap[hr]=-1;
8056 regs[i].isconst&=~(1<<hr);
8064 /* Pass 5 - Pre-allocate registers */
8066 // If a register is allocated during a loop, try to allocate it for the
8067 // entire loop, if possible. This avoids loading/storing registers
8068 // inside of the loop.
8070 signed char f_regmap[HOST_REGS];
8071 clear_all_regs(f_regmap);
8072 for(i=0;i<slen-1;i++)
8074 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
8076 if(ba[i]>=start && ba[i]<(start+i*4))
8077 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
8078 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
8079 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
8080 ||itype[i+1]==SHIFT||itype[i+1]==COP1
8081 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
8083 int t=(ba[i]-start)>>2;
8084 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP)) // loop_preload can't handle jumps into delay slots
8085 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
8086 for(hr=0;hr<HOST_REGS;hr++)
8088 if(regs[i].regmap[hr]>=0) {
8089 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8090 // dealloc old register
8092 for(n=0;n<HOST_REGS;n++)
8094 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8096 // and alloc new one
8097 f_regmap[hr]=regs[i].regmap[hr];
8100 if(branch_regs[i].regmap[hr]>=0) {
8101 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8102 // dealloc old register
8104 for(n=0;n<HOST_REGS;n++)
8106 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8108 // and alloc new one
8109 f_regmap[hr]=branch_regs[i].regmap[hr];
8113 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
8114 f_regmap[hr]=branch_regs[i].regmap[hr];
8116 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
8117 f_regmap[hr]=branch_regs[i].regmap[hr];
8119 // Avoid dirty->clean transition
8120 #ifdef DESTRUCTIVE_WRITEBACK
8121 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
8123 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8124 // case above, however it's always a good idea. We can't hoist the
8125 // load if the register was already allocated, so there's no point
8126 // wasting time analyzing most of these cases. It only "succeeds"
8127 // when the mapping was different and the load can be replaced with
8128 // a mov, which is of negligible benefit. So such cases are
8130 if(f_regmap[hr]>0) {
8131 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
8135 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8136 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
8138 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
8139 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8141 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8142 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8144 if(get_reg(regs[i].regmap,r&63)<0) break;
8145 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
8148 while(k>1&®s[k-1].regmap[hr]==-1) {
8149 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8150 //printf("no free regs for store %x\n",start+(k-1)*4);
8153 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8154 //printf("no-match due to different register\n");
8157 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP) {
8158 //printf("no-match due to branch\n");
8161 // call/ret fast path assumes no registers allocated
8162 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
8168 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
8169 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8171 regs[k].regmap_entry[hr]=f_regmap[hr];
8172 regs[k].regmap[hr]=f_regmap[hr];
8173 regmap_pre[k+1][hr]=f_regmap[hr];
8174 regs[k].wasdirty&=~(1<<hr);
8175 regs[k].dirty&=~(1<<hr);
8176 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
8177 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
8178 regs[k].wasconst&=~(1<<hr);
8179 regs[k].isconst&=~(1<<hr);
8184 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8187 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8188 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
8189 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8190 regs[i].regmap_entry[hr]=f_regmap[hr];
8191 regs[i].regmap[hr]=f_regmap[hr];
8192 regs[i].wasdirty&=~(1<<hr);
8193 regs[i].dirty&=~(1<<hr);
8194 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
8195 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
8196 regs[i].wasconst&=~(1<<hr);
8197 regs[i].isconst&=~(1<<hr);
8198 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8199 branch_regs[i].wasdirty&=~(1<<hr);
8200 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
8201 branch_regs[i].regmap[hr]=f_regmap[hr];
8202 branch_regs[i].dirty&=~(1<<hr);
8203 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
8204 branch_regs[i].wasconst&=~(1<<hr);
8205 branch_regs[i].isconst&=~(1<<hr);
8206 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
8207 regmap_pre[i+2][hr]=f_regmap[hr];
8208 regs[i+2].wasdirty&=~(1<<hr);
8209 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
8214 // Alloc register clean at beginning of loop,
8215 // but may dirty it in pass 6
8216 regs[k].regmap_entry[hr]=f_regmap[hr];
8217 regs[k].regmap[hr]=f_regmap[hr];
8218 regs[k].dirty&=~(1<<hr);
8219 regs[k].wasconst&=~(1<<hr);
8220 regs[k].isconst&=~(1<<hr);
8221 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP) {
8222 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8223 branch_regs[k].regmap[hr]=f_regmap[hr];
8224 branch_regs[k].dirty&=~(1<<hr);
8225 branch_regs[k].wasconst&=~(1<<hr);
8226 branch_regs[k].isconst&=~(1<<hr);
8227 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
8228 regmap_pre[k+2][hr]=f_regmap[hr];
8229 regs[k+2].wasdirty&=~(1<<hr);
8234 regmap_pre[k+1][hr]=f_regmap[hr];
8235 regs[k+1].wasdirty&=~(1<<hr);
8238 if(regs[j].regmap[hr]==f_regmap[hr])
8239 regs[j].regmap_entry[hr]=f_regmap[hr];
8243 if(regs[j].regmap[hr]>=0)
8245 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8246 //printf("no-match due to different register\n");
8249 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
8251 // Stop on unconditional branch
8254 if(itype[j]==CJUMP||itype[j]==SJUMP)
8257 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
8260 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
8263 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8264 //printf("no-match due to different register (branch)\n");
8268 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8269 //printf("No free regs for store %x\n",start+j*4);
8272 assert(f_regmap[hr]<64);
8279 // Non branch or undetermined branch target
8280 for(hr=0;hr<HOST_REGS;hr++)
8282 if(hr!=EXCLUDE_REG) {
8283 if(regs[i].regmap[hr]>=0) {
8284 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8285 // dealloc old register
8287 for(n=0;n<HOST_REGS;n++)
8289 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8291 // and alloc new one
8292 f_regmap[hr]=regs[i].regmap[hr];
8297 // Try to restore cycle count at branch targets
8299 for(j=i;j<slen-1;j++) {
8300 if(regs[j].regmap[HOST_CCREG]!=-1) break;
8301 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8302 //printf("no free regs for store %x\n",start+j*4);
8306 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8308 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8310 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8311 regs[k].regmap[HOST_CCREG]=CCREG;
8312 regmap_pre[k+1][HOST_CCREG]=CCREG;
8313 regs[k+1].wasdirty|=1<<HOST_CCREG;
8314 regs[k].dirty|=1<<HOST_CCREG;
8315 regs[k].wasconst&=~(1<<HOST_CCREG);
8316 regs[k].isconst&=~(1<<HOST_CCREG);
8319 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8321 // Work backwards from the branch target
8322 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8324 //printf("Extend backwards\n");
8327 while(regs[k-1].regmap[HOST_CCREG]==-1) {
8328 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8329 //printf("no free regs for store %x\n",start+(k-1)*4);
8334 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8335 //printf("Extend CC, %x ->\n",start+k*4);
8337 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8338 regs[k].regmap[HOST_CCREG]=CCREG;
8339 regmap_pre[k+1][HOST_CCREG]=CCREG;
8340 regs[k+1].wasdirty|=1<<HOST_CCREG;
8341 regs[k].dirty|=1<<HOST_CCREG;
8342 regs[k].wasconst&=~(1<<HOST_CCREG);
8343 regs[k].isconst&=~(1<<HOST_CCREG);
8348 //printf("Fail Extend CC, %x ->\n",start+k*4);
8352 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
8353 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
8354 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1)
8356 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8361 // This allocates registers (if possible) one instruction prior
8362 // to use, which can avoid a load-use penalty on certain CPUs.
8363 for(i=0;i<slen-1;i++)
8365 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP))
8369 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
8370 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
8373 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
8375 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8377 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8378 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8379 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8380 regs[i].isconst&=~(1<<hr);
8381 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8382 constmap[i][hr]=constmap[i+1][hr];
8383 regs[i+1].wasdirty&=~(1<<hr);
8384 regs[i].dirty&=~(1<<hr);
8389 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
8391 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8393 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8394 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8395 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8396 regs[i].isconst&=~(1<<hr);
8397 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8398 constmap[i][hr]=constmap[i+1][hr];
8399 regs[i+1].wasdirty&=~(1<<hr);
8400 regs[i].dirty&=~(1<<hr);
8404 // Preload target address for load instruction (non-constant)
8405 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
8406 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
8408 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8410 regs[i].regmap[hr]=rs1[i+1];
8411 regmap_pre[i+1][hr]=rs1[i+1];
8412 regs[i+1].regmap_entry[hr]=rs1[i+1];
8413 regs[i].isconst&=~(1<<hr);
8414 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8415 constmap[i][hr]=constmap[i+1][hr];
8416 regs[i+1].wasdirty&=~(1<<hr);
8417 regs[i].dirty&=~(1<<hr);
8421 // Load source into target register
8422 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
8423 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
8425 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8427 regs[i].regmap[hr]=rs1[i+1];
8428 regmap_pre[i+1][hr]=rs1[i+1];
8429 regs[i+1].regmap_entry[hr]=rs1[i+1];
8430 regs[i].isconst&=~(1<<hr);
8431 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8432 constmap[i][hr]=constmap[i+1][hr];
8433 regs[i+1].wasdirty&=~(1<<hr);
8434 regs[i].dirty&=~(1<<hr);
8438 // Address for store instruction (non-constant)
8439 if(itype[i+1]==STORE||itype[i+1]==STORELR
8440 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
8441 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
8442 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8443 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8444 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
8446 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8448 regs[i].regmap[hr]=rs1[i+1];
8449 regmap_pre[i+1][hr]=rs1[i+1];
8450 regs[i+1].regmap_entry[hr]=rs1[i+1];
8451 regs[i].isconst&=~(1<<hr);
8452 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8453 constmap[i][hr]=constmap[i+1][hr];
8454 regs[i+1].wasdirty&=~(1<<hr);
8455 regs[i].dirty&=~(1<<hr);
8459 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
8460 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
8462 hr=get_reg(regs[i+1].regmap,FTEMP);
8464 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8466 regs[i].regmap[hr]=rs1[i+1];
8467 regmap_pre[i+1][hr]=rs1[i+1];
8468 regs[i+1].regmap_entry[hr]=rs1[i+1];
8469 regs[i].isconst&=~(1<<hr);
8470 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8471 constmap[i][hr]=constmap[i+1][hr];
8472 regs[i+1].wasdirty&=~(1<<hr);
8473 regs[i].dirty&=~(1<<hr);
8475 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8477 // move it to another register
8478 regs[i+1].regmap[hr]=-1;
8479 regmap_pre[i+2][hr]=-1;
8480 regs[i+1].regmap[nr]=FTEMP;
8481 regmap_pre[i+2][nr]=FTEMP;
8482 regs[i].regmap[nr]=rs1[i+1];
8483 regmap_pre[i+1][nr]=rs1[i+1];
8484 regs[i+1].regmap_entry[nr]=rs1[i+1];
8485 regs[i].isconst&=~(1<<nr);
8486 regs[i+1].isconst&=~(1<<nr);
8487 regs[i].dirty&=~(1<<nr);
8488 regs[i+1].wasdirty&=~(1<<nr);
8489 regs[i+1].dirty&=~(1<<nr);
8490 regs[i+2].wasdirty&=~(1<<nr);
8494 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
8495 if(itype[i+1]==LOAD)
8496 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
8497 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
8498 hr=get_reg(regs[i+1].regmap,FTEMP);
8499 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
8500 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8501 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8503 if(hr>=0&®s[i].regmap[hr]<0) {
8504 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
8505 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8506 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8507 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8508 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8509 regs[i].isconst&=~(1<<hr);
8510 regs[i+1].wasdirty&=~(1<<hr);
8511 regs[i].dirty&=~(1<<hr);
8520 /* Pass 6 - Optimize clean/dirty state */
8521 clean_registers(0,slen-1,1);
8523 /* Pass 7 - Identify 32-bit registers */
8524 for (i=slen-1;i>=0;i--)
8526 if(itype[i]==CJUMP||itype[i]==SJUMP)
8528 // Conditional branch
8529 if((source[i]>>16)!=0x1000&&i<slen-2) {
8530 // Mark this address as a branch target since it may be called
8531 // upon return from interrupt
8537 if(itype[slen-1]==SPAN) {
8538 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
8542 /* Debug/disassembly */
8547 for(r=1;r<=CCREG;r++) {
8548 if((unneeded_reg[i]>>r)&1) {
8549 if(r==HIREG) printf(" HI");
8550 else if(r==LOREG) printf(" LO");
8551 else printf(" r%d",r);
8555 #if defined(__i386__) || defined(__x86_64__)
8556 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
8559 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
8561 #if defined(__i386__) || defined(__x86_64__)
8563 if(needed_reg[i]&1) printf("eax ");
8564 if((needed_reg[i]>>1)&1) printf("ecx ");
8565 if((needed_reg[i]>>2)&1) printf("edx ");
8566 if((needed_reg[i]>>3)&1) printf("ebx ");
8567 if((needed_reg[i]>>5)&1) printf("ebp ");
8568 if((needed_reg[i]>>6)&1) printf("esi ");
8569 if((needed_reg[i]>>7)&1) printf("edi ");
8571 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
8573 if(regs[i].wasdirty&1) printf("eax ");
8574 if((regs[i].wasdirty>>1)&1) printf("ecx ");
8575 if((regs[i].wasdirty>>2)&1) printf("edx ");
8576 if((regs[i].wasdirty>>3)&1) printf("ebx ");
8577 if((regs[i].wasdirty>>5)&1) printf("ebp ");
8578 if((regs[i].wasdirty>>6)&1) printf("esi ");
8579 if((regs[i].wasdirty>>7)&1) printf("edi ");
8582 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
8584 if(regs[i].wasdirty&1) printf("r0 ");
8585 if((regs[i].wasdirty>>1)&1) printf("r1 ");
8586 if((regs[i].wasdirty>>2)&1) printf("r2 ");
8587 if((regs[i].wasdirty>>3)&1) printf("r3 ");
8588 if((regs[i].wasdirty>>4)&1) printf("r4 ");
8589 if((regs[i].wasdirty>>5)&1) printf("r5 ");
8590 if((regs[i].wasdirty>>6)&1) printf("r6 ");
8591 if((regs[i].wasdirty>>7)&1) printf("r7 ");
8592 if((regs[i].wasdirty>>8)&1) printf("r8 ");
8593 if((regs[i].wasdirty>>9)&1) printf("r9 ");
8594 if((regs[i].wasdirty>>10)&1) printf("r10 ");
8595 if((regs[i].wasdirty>>12)&1) printf("r12 ");
8598 disassemble_inst(i);
8599 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
8600 #if defined(__i386__) || defined(__x86_64__)
8601 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
8602 if(regs[i].dirty&1) printf("eax ");
8603 if((regs[i].dirty>>1)&1) printf("ecx ");
8604 if((regs[i].dirty>>2)&1) printf("edx ");
8605 if((regs[i].dirty>>3)&1) printf("ebx ");
8606 if((regs[i].dirty>>5)&1) printf("ebp ");
8607 if((regs[i].dirty>>6)&1) printf("esi ");
8608 if((regs[i].dirty>>7)&1) printf("edi ");
8611 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
8612 if(regs[i].dirty&1) printf("r0 ");
8613 if((regs[i].dirty>>1)&1) printf("r1 ");
8614 if((regs[i].dirty>>2)&1) printf("r2 ");
8615 if((regs[i].dirty>>3)&1) printf("r3 ");
8616 if((regs[i].dirty>>4)&1) printf("r4 ");
8617 if((regs[i].dirty>>5)&1) printf("r5 ");
8618 if((regs[i].dirty>>6)&1) printf("r6 ");
8619 if((regs[i].dirty>>7)&1) printf("r7 ");
8620 if((regs[i].dirty>>8)&1) printf("r8 ");
8621 if((regs[i].dirty>>9)&1) printf("r9 ");
8622 if((regs[i].dirty>>10)&1) printf("r10 ");
8623 if((regs[i].dirty>>12)&1) printf("r12 ");
8626 if(regs[i].isconst) {
8627 printf("constants: ");
8628 #if defined(__i386__) || defined(__x86_64__)
8629 if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]);
8630 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]);
8631 if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]);
8632 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]);
8633 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]);
8634 if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]);
8635 if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]);
8637 #if defined(__arm__) || defined(__aarch64__)
8639 for (r = 0; r < ARRAY_SIZE(constmap[i]); r++)
8640 if ((regs[i].isconst >> r) & 1)
8641 printf(" r%d=%x", r, (u_int)constmap[i][r]);
8645 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
8646 #if defined(__i386__) || defined(__x86_64__)
8647 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
8648 if(branch_regs[i].dirty&1) printf("eax ");
8649 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
8650 if((branch_regs[i].dirty>>2)&1) printf("edx ");
8651 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
8652 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
8653 if((branch_regs[i].dirty>>6)&1) printf("esi ");
8654 if((branch_regs[i].dirty>>7)&1) printf("edi ");
8657 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
8658 if(branch_regs[i].dirty&1) printf("r0 ");
8659 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
8660 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
8661 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
8662 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
8663 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
8664 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
8665 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
8666 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
8667 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
8668 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
8669 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
8675 /* Pass 8 - Assembly */
8676 linkcount=0;stubcount=0;
8677 ds=0;is_delayslot=0;
8679 void *beginning=start_block();
8684 void *instr_addr0_override = NULL;
8686 if (start == 0x80030000) {
8687 // nasty hack for the fastbios thing
8688 // override block entry to this code
8689 instr_addr0_override = out;
8690 emit_movimm(start,0);
8691 // abuse io address var as a flag that we
8692 // have already returned here once
8693 emit_readword(&address,1);
8694 emit_writeword(0,&pcaddr);
8695 emit_writeword(0,&address);
8698 emit_jeq(out + 4*2);
8699 emit_jmp(new_dyna_leave);
8701 emit_jne(new_dyna_leave);
8706 //if(ds) printf("ds: ");
8707 disassemble_inst(i);
8709 ds=0; // Skip delay slot
8710 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
8711 instr_addr[i] = NULL;
8713 speculate_register_values(i);
8714 #ifndef DESTRUCTIVE_WRITEBACK
8715 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
8717 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
8719 if((itype[i]==CJUMP||itype[i]==SJUMP)&&!likely[i]) {
8720 dirty_pre=branch_regs[i].dirty;
8722 dirty_pre=regs[i].dirty;
8726 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
8728 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
8729 loop_preload(regmap_pre[i],regs[i].regmap_entry);
8731 // branch target entry point
8732 instr_addr[i] = out;
8733 assem_debug("<->\n");
8734 drc_dbg_emit_do_cmp(i);
8737 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
8738 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
8739 load_regs(regs[i].regmap_entry,regs[i].regmap,rs1[i],rs2[i]);
8740 address_generation(i,®s[i],regs[i].regmap_entry);
8741 load_consts(regmap_pre[i],regs[i].regmap,i);
8742 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
8744 // Load the delay slot registers if necessary
8745 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
8746 load_regs(regs[i].regmap_entry,regs[i].regmap,rs1[i+1],rs1[i+1]);
8747 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
8748 load_regs(regs[i].regmap_entry,regs[i].regmap,rs2[i+1],rs2[i+1]);
8749 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
8750 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
8754 // Preload registers for following instruction
8755 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
8756 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
8757 load_regs(regs[i].regmap_entry,regs[i].regmap,rs1[i+1],rs1[i+1]);
8758 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
8759 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
8760 load_regs(regs[i].regmap_entry,regs[i].regmap,rs2[i+1],rs2[i+1]);
8762 // TODO: if(is_ooo(i)) address_generation(i+1);
8764 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
8765 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
8766 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
8770 alu_assemble(i,®s[i]);break;
8772 imm16_assemble(i,®s[i]);break;
8774 shift_assemble(i,®s[i]);break;
8776 shiftimm_assemble(i,®s[i]);break;
8778 load_assemble(i,®s[i]);break;
8780 loadlr_assemble(i,®s[i]);break;
8782 store_assemble(i,®s[i]);break;
8784 storelr_assemble(i,®s[i]);break;
8786 cop0_assemble(i,®s[i]);break;
8788 cop1_assemble(i,®s[i]);break;
8790 c1ls_assemble(i,®s[i]);break;
8792 cop2_assemble(i,®s[i]);break;
8794 c2ls_assemble(i,®s[i]);break;
8796 c2op_assemble(i,®s[i]);break;
8798 multdiv_assemble(i,®s[i]);break;
8800 mov_assemble(i,®s[i]);break;
8802 syscall_assemble(i,®s[i]);break;
8804 hlecall_assemble(i,®s[i]);break;
8806 intcall_assemble(i,®s[i]);break;
8808 ujump_assemble(i,®s[i]);ds=1;break;
8810 rjump_assemble(i,®s[i]);ds=1;break;
8812 cjump_assemble(i,®s[i]);ds=1;break;
8814 sjump_assemble(i,®s[i]);ds=1;break;
8816 pagespan_assemble(i,®s[i]);break;
8818 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
8821 literal_pool_jumpover(256);
8824 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
8825 // If the block did not end with an unconditional branch,
8826 // add a jump to the next instruction.
8828 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
8829 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP);
8831 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP) {
8832 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
8833 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
8834 emit_loadreg(CCREG,HOST_CCREG);
8835 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
8837 else if(!likely[i-2])
8839 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
8840 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
8844 store_regs_bt(regs[i-2].regmap,regs[i-2].dirty,start+i*4);
8845 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
8847 add_to_linker(out,start+i*4,0);
8854 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP);
8855 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
8856 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
8857 emit_loadreg(CCREG,HOST_CCREG);
8858 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
8859 add_to_linker(out,start+i*4,0);
8863 // TODO: delay slot stubs?
8865 for(i=0;i<stubcount;i++)
8867 switch(stubs[i].type)
8875 do_readstub(i);break;
8880 do_writestub(i);break;
8884 do_invstub(i);break;
8886 do_cop1stub(i);break;
8888 do_unalignedwritestub(i);break;
8892 if (instr_addr0_override)
8893 instr_addr[0] = instr_addr0_override;
8895 /* Pass 9 - Linker */
8896 for(i=0;i<linkcount;i++)
8898 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
8900 if (!link_addr[i].ext)
8903 void *addr = check_addr(link_addr[i].target);
8904 emit_extjump(link_addr[i].addr, link_addr[i].target);
8906 set_jump_target(link_addr[i].addr, addr);
8907 add_link(link_addr[i].target,stub);
8910 set_jump_target(link_addr[i].addr, stub);
8915 int target=(link_addr[i].target-start)>>2;
8916 assert(target>=0&&target<slen);
8917 assert(instr_addr[target]);
8918 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
8919 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
8921 set_jump_target(link_addr[i].addr, instr_addr[target]);
8925 // External Branch Targets (jump_in)
8926 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
8931 if(instr_addr[i]) // TODO - delay slots (=null)
8933 u_int vaddr=start+i*4;
8934 u_int page=get_page(vaddr);
8935 u_int vpage=get_vpage(vaddr);
8938 assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4);
8939 assem_debug("jump_in: %x\n",start+i*4);
8940 ll_add(jump_dirty+vpage,vaddr,out);
8941 void *entry_point = do_dirty_stub(i);
8942 ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point);
8943 // If there was an existing entry in the hash table,
8944 // replace it with the new address.
8945 // Don't add new entries. We'll insert the
8946 // ones that actually get used in check_addr().
8947 struct ht_entry *ht_bin = hash_table_get(vaddr);
8948 if (ht_bin->vaddr[0] == vaddr)
8949 ht_bin->tcaddr[0] = entry_point;
8950 if (ht_bin->vaddr[1] == vaddr)
8951 ht_bin->tcaddr[1] = entry_point;
8956 // Write out the literal pool if necessary
8958 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
8960 if(((u_int)out)&7) emit_addnop(13);
8962 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
8963 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
8964 memcpy(copy,source,slen*4);
8967 end_block(beginning);
8969 // If we're within 256K of the end of the buffer,
8970 // start over from the beginning. (Is 256K enough?)
8971 if (out > translation_cache+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE)
8972 out = translation_cache;
8974 // Trap writes to any of the pages we compiled
8975 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
8978 inv_code_start=inv_code_end=~0;
8980 // for PCSX we need to mark all mirrors too
8981 if(get_page(start)<(RAM_SIZE>>12))
8982 for(i=start>>12;i<=(start+slen*4)>>12;i++)
8983 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
8984 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
8985 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
8987 /* Pass 10 - Free memory by expiring oldest blocks */
8989 int end=(((out-translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535;
8992 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
8993 uintptr_t base=(uintptr_t)translation_cache+((expirep>>13)<<shift); // Base address of this block
8994 inv_debug("EXP: Phase %d\n",expirep);
8995 switch((expirep>>11)&3)
8998 // Clear jump_in and jump_dirty
8999 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
9000 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
9001 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
9002 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
9006 ll_kill_pointers(jump_out[expirep&2047],base,shift);
9007 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
9012 struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i];
9013 if (((uintptr_t)ht_bin->tcaddr[1]>>shift) == (base>>shift) ||
9014 (((uintptr_t)ht_bin->tcaddr[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
9015 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]);
9016 ht_bin->vaddr[1] = -1;
9017 ht_bin->tcaddr[1] = NULL;
9019 if (((uintptr_t)ht_bin->tcaddr[0]>>shift) == (base>>shift) ||
9020 (((uintptr_t)ht_bin->tcaddr[0]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
9021 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]);
9022 ht_bin->vaddr[0] = ht_bin->vaddr[1];
9023 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
9024 ht_bin->vaddr[1] = -1;
9025 ht_bin->tcaddr[1] = NULL;
9031 #if defined(__arm__) || defined(__aarch64__)
9032 if((expirep&2047)==0)
9035 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
9036 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
9039 expirep=(expirep+1)&65535;
9044 // vim:shiftwidth=2:expandtab