1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
26 #include "emu_if.h" //emulator interface
29 //#define assem_debug printf
30 //#define inv_debug printf
31 #define assem_debug(...)
32 #define inv_debug(...)
35 #include "assem_x86.h"
38 #include "assem_x64.h"
41 #include "assem_arm.h"
45 #define MAX_OUTPUT_BLOCK_SIZE 262144
47 int cycle_multiplier; // 100 for 1.0
48 #define CLOCK_ADJUST(x) (((x) * cycle_multiplier + 50) / 100)
52 signed char regmap_entry[HOST_REGS];
53 signed char regmap[HOST_REGS];
62 u_int waswritten; // regs that were used as store base before
63 uint64_t constmap[HOST_REGS];
71 struct ll_entry *next;
77 char insn[MAXBLOCK][10];
78 u_char itype[MAXBLOCK];
79 u_char opcode[MAXBLOCK];
80 u_char opcode2[MAXBLOCK];
88 u_char dep1[MAXBLOCK];
89 u_char dep2[MAXBLOCK];
91 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
92 static uint64_t gte_rt[MAXBLOCK];
93 static uint64_t gte_unneeded[MAXBLOCK];
94 static int gte_reads_flags; // gte flag read encountered
95 static u_int smrv[32]; // speculated MIPS register values
96 static u_int smrv_strong; // mask or regs that are likely to have correct values
97 static u_int smrv_weak; // same, but somewhat less likely
98 static u_int smrv_strong_next; // same, but after current insn executes
99 static u_int smrv_weak_next;
102 char likely[MAXBLOCK];
103 char is_ds[MAXBLOCK];
105 uint64_t unneeded_reg[MAXBLOCK];
106 uint64_t unneeded_reg_upper[MAXBLOCK];
107 uint64_t branch_unneeded_reg[MAXBLOCK];
108 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
109 uint64_t p32[MAXBLOCK];
110 uint64_t pr32[MAXBLOCK];
111 signed char regmap_pre[MAXBLOCK][HOST_REGS];
112 signed char regmap[MAXBLOCK][HOST_REGS];
113 signed char regmap_entry[MAXBLOCK][HOST_REGS];
114 uint64_t constmap[MAXBLOCK][HOST_REGS];
115 struct regstat regs[MAXBLOCK];
116 struct regstat branch_regs[MAXBLOCK];
117 signed char minimum_free_regs[MAXBLOCK];
118 u_int needed_reg[MAXBLOCK];
119 uint64_t requires_32bit[MAXBLOCK];
120 u_int wont_dirty[MAXBLOCK];
121 u_int will_dirty[MAXBLOCK];
124 u_int instr_addr[MAXBLOCK];
125 u_int link_addr[MAXBLOCK][3];
127 u_int stubs[MAXBLOCK*3][8];
129 u_int literals[1024][2];
134 struct ll_entry *jump_in[4096];
135 struct ll_entry *jump_out[4096];
136 struct ll_entry *jump_dirty[4096];
137 u_int hash_table[65536][4] __attribute__((aligned(16)));
138 char shadow[1048576] __attribute__((aligned(16)));
144 static const u_int using_tlb=0;
146 int new_dynarec_did_compile;
147 u_int stop_after_jal;
148 extern u_char restore_candidate[512];
149 extern int cycle_count;
151 /* registers that may be allocated */
153 #define HIREG 32 // hi
154 #define LOREG 33 // lo
155 #define FSREG 34 // FPU status (FCSR)
156 #define CSREG 35 // Coprocessor status
157 #define CCREG 36 // Cycle count
158 #define INVCP 37 // Pointer to invalid_code
159 #define MMREG 38 // Pointer to memory_map
160 #define ROREG 39 // ram offset (if rdram!=0x80000000)
162 #define FTEMP 40 // FPU temporary register
163 #define PTEMP 41 // Prefetch temporary register
164 #define TLREG 42 // TLB mapping offset
165 #define RHASH 43 // Return address hash
166 #define RHTBL 44 // Return address hash table address
167 #define RTEMP 45 // JR/JALR address register
169 #define AGEN1 46 // Address generation temporary register
170 #define AGEN2 47 // Address generation temporary register
171 #define MGEN1 48 // Maptable address generation temporary register
172 #define MGEN2 49 // Maptable address generation temporary register
173 #define BTREG 50 // Branch target temporary register
175 /* instruction types */
176 #define NOP 0 // No operation
177 #define LOAD 1 // Load
178 #define STORE 2 // Store
179 #define LOADLR 3 // Unaligned load
180 #define STORELR 4 // Unaligned store
181 #define MOV 5 // Move
182 #define ALU 6 // Arithmetic/logic
183 #define MULTDIV 7 // Multiply/divide
184 #define SHIFT 8 // Shift by register
185 #define SHIFTIMM 9// Shift by immediate
186 #define IMM16 10 // 16-bit immediate
187 #define RJUMP 11 // Unconditional jump to register
188 #define UJUMP 12 // Unconditional jump
189 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
190 #define SJUMP 14 // Conditional branch (regimm format)
191 #define COP0 15 // Coprocessor 0
192 #define COP1 16 // Coprocessor 1
193 #define C1LS 17 // Coprocessor 1 load/store
194 #define FJUMP 18 // Conditional branch (floating point)
195 #define FLOAT 19 // Floating point unit
196 #define FCONV 20 // Convert integer to float
197 #define FCOMP 21 // Floating point compare (sets FSREG)
198 #define SYSCALL 22// SYSCALL
199 #define OTHER 23 // Other
200 #define SPAN 24 // Branch/delay slot spans 2 pages
201 #define NI 25 // Not implemented
202 #define HLECALL 26// PCSX fake opcodes for HLE
203 #define COP2 27 // Coprocessor 2 move
204 #define C2LS 28 // Coprocessor 2 load/store
205 #define C2OP 29 // Coprocessor 2 operation
206 #define INTCALL 30// Call interpreter to handle rare corner cases
215 #define LOADBU_STUB 7
216 #define LOADHU_STUB 8
217 #define STOREB_STUB 9
218 #define STOREH_STUB 10
219 #define STOREW_STUB 11
220 #define STORED_STUB 12
221 #define STORELR_STUB 13
222 #define INVCODE_STUB 14
230 int new_recompile_block(int addr);
231 void *get_addr_ht(u_int vaddr);
232 void invalidate_block(u_int block);
233 void invalidate_addr(u_int addr);
234 void remove_hash(int vaddr);
237 void dyna_linker_ds();
239 void verify_code_vm();
240 void verify_code_ds();
243 void fp_exception_ds();
245 void jump_syscall_hle();
249 void new_dyna_leave();
254 void read_nomem_new();
255 void read_nomemb_new();
256 void read_nomemh_new();
257 void read_nomemd_new();
258 void write_nomem_new();
259 void write_nomemb_new();
260 void write_nomemh_new();
261 void write_nomemd_new();
262 void write_rdram_new();
263 void write_rdramb_new();
264 void write_rdramh_new();
265 void write_rdramd_new();
266 extern u_int memory_map[1048576];
268 // Needed by assembler
269 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
270 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
271 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
272 void load_all_regs(signed char i_regmap[]);
273 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
274 void load_regs_entry(int t);
275 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
279 //#define DEBUG_CYCLE_COUNT 1
281 static void tlb_hacks()
285 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
289 switch (ROM_HEADER->Country_code&0xFF)
301 // Unknown country code
305 u_int rom_addr=(u_int)rom;
307 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
308 // in the lower 4G of memory to use this hack. Copy it if necessary.
309 if((void *)rom>(void *)0xffffffff) {
310 munmap(ROM_COPY, 67108864);
311 if(mmap(ROM_COPY, 12582912,
312 PROT_READ | PROT_WRITE,
313 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
314 -1, 0) <= 0) {printf("mmap() failed\n");}
315 memcpy(ROM_COPY,rom,12582912);
316 rom_addr=(u_int)ROM_COPY;
320 for(n=0x7F000;n<0x80000;n++) {
321 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
328 static u_int get_page(u_int vaddr)
331 u_int page=(vaddr^0x80000000)>>12;
333 u_int page=vaddr&~0xe0000000;
334 if (page < 0x1000000)
335 page &= ~0x0e00000; // RAM mirrors
339 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
341 if(page>2048) page=2048+(page&2047);
345 static u_int get_vpage(u_int vaddr)
347 u_int vpage=(vaddr^0x80000000)>>12;
349 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
351 if(vpage>2048) vpage=2048+(vpage&2047);
355 // Get address from virtual address
356 // This is called from the recompiled JR/JALR instructions
357 void *get_addr(u_int vaddr)
359 u_int page=get_page(vaddr);
360 u_int vpage=get_vpage(vaddr);
361 struct ll_entry *head;
362 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
365 if(head->vaddr==vaddr&&head->reg32==0) {
366 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
367 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
370 ht_bin[1]=(int)head->addr;
376 head=jump_dirty[vpage];
378 if(head->vaddr==vaddr&&head->reg32==0) {
379 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
380 // Don't restore blocks which are about to expire from the cache
381 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
382 if(verify_dirty(head->addr)) {
383 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
384 invalid_code[vaddr>>12]=0;
385 inv_code_start=inv_code_end=~0;
387 memory_map[vaddr>>12]|=0x40000000;
391 if(tlb_LUT_r[vaddr>>12]) {
392 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
393 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
396 restore_candidate[vpage>>3]|=1<<(vpage&7);
398 else restore_candidate[page>>3]|=1<<(page&7);
399 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
400 if(ht_bin[0]==vaddr) {
401 ht_bin[1]=(int)head->addr; // Replace existing entry
407 ht_bin[1]=(int)head->addr;
415 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
416 int r=new_recompile_block(vaddr);
417 if(r==0) return get_addr(vaddr);
418 // Execute in unmapped page, generate pagefault execption
420 Cause=(vaddr<<31)|0x8;
421 EPC=(vaddr&1)?vaddr-5:vaddr;
423 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
424 EntryHi=BadVAddr&0xFFFFE000;
425 return get_addr_ht(0x80000000);
427 // Look up address in hash table first
428 void *get_addr_ht(u_int vaddr)
430 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
431 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
432 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
433 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
434 return get_addr(vaddr);
437 void *get_addr_32(u_int vaddr,u_int flags)
440 return get_addr(vaddr);
442 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
443 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
444 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
445 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
446 u_int page=get_page(vaddr);
447 u_int vpage=get_vpage(vaddr);
448 struct ll_entry *head;
451 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
452 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
454 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
456 ht_bin[1]=(int)head->addr;
458 }else if(ht_bin[2]==-1) {
459 ht_bin[3]=(int)head->addr;
462 //ht_bin[3]=ht_bin[1];
463 //ht_bin[2]=ht_bin[0];
464 //ht_bin[1]=(int)head->addr;
471 head=jump_dirty[vpage];
473 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
474 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
475 // Don't restore blocks which are about to expire from the cache
476 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
477 if(verify_dirty(head->addr)) {
478 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
479 invalid_code[vaddr>>12]=0;
480 inv_code_start=inv_code_end=~0;
481 memory_map[vaddr>>12]|=0x40000000;
484 if(tlb_LUT_r[vaddr>>12]) {
485 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
486 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
489 restore_candidate[vpage>>3]|=1<<(vpage&7);
491 else restore_candidate[page>>3]|=1<<(page&7);
493 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
495 ht_bin[1]=(int)head->addr;
497 }else if(ht_bin[2]==-1) {
498 ht_bin[3]=(int)head->addr;
501 //ht_bin[3]=ht_bin[1];
502 //ht_bin[2]=ht_bin[0];
503 //ht_bin[1]=(int)head->addr;
511 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
512 int r=new_recompile_block(vaddr);
513 if(r==0) return get_addr(vaddr);
514 // Execute in unmapped page, generate pagefault execption
516 Cause=(vaddr<<31)|0x8;
517 EPC=(vaddr&1)?vaddr-5:vaddr;
519 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
520 EntryHi=BadVAddr&0xFFFFE000;
521 return get_addr_ht(0x80000000);
525 void clear_all_regs(signed char regmap[])
528 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
531 signed char get_reg(signed char regmap[],int r)
534 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
538 // Find a register that is available for two consecutive cycles
539 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
542 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
546 int count_free_regs(signed char regmap[])
550 for(hr=0;hr<HOST_REGS;hr++)
552 if(hr!=EXCLUDE_REG) {
553 if(regmap[hr]<0) count++;
559 void dirty_reg(struct regstat *cur,signed char reg)
563 for (hr=0;hr<HOST_REGS;hr++) {
564 if((cur->regmap[hr]&63)==reg) {
570 // If we dirty the lower half of a 64 bit register which is now being
571 // sign-extended, we need to dump the upper half.
572 // Note: Do this only after completion of the instruction, because
573 // some instructions may need to read the full 64-bit value even if
574 // overwriting it (eg SLTI, DSRA32).
575 static void flush_dirty_uppers(struct regstat *cur)
578 for (hr=0;hr<HOST_REGS;hr++) {
579 if((cur->dirty>>hr)&1) {
582 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
587 void set_const(struct regstat *cur,signed char reg,uint64_t value)
591 for (hr=0;hr<HOST_REGS;hr++) {
592 if(cur->regmap[hr]==reg) {
594 cur->constmap[hr]=value;
596 else if((cur->regmap[hr]^64)==reg) {
598 cur->constmap[hr]=value>>32;
603 void clear_const(struct regstat *cur,signed char reg)
607 for (hr=0;hr<HOST_REGS;hr++) {
608 if((cur->regmap[hr]&63)==reg) {
609 cur->isconst&=~(1<<hr);
614 int is_const(struct regstat *cur,signed char reg)
619 for (hr=0;hr<HOST_REGS;hr++) {
620 if((cur->regmap[hr]&63)==reg) {
621 return (cur->isconst>>hr)&1;
626 uint64_t get_const(struct regstat *cur,signed char reg)
630 for (hr=0;hr<HOST_REGS;hr++) {
631 if(cur->regmap[hr]==reg) {
632 return cur->constmap[hr];
635 printf("Unknown constant in r%d\n",reg);
639 // Least soon needed registers
640 // Look at the next ten instructions and see which registers
641 // will be used. Try not to reallocate these.
642 void lsn(u_char hsn[], int i, int *preferred_reg)
652 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
654 // Don't go past an unconditonal jump
661 if(rs1[i+j]) hsn[rs1[i+j]]=j;
662 if(rs2[i+j]) hsn[rs2[i+j]]=j;
663 if(rt1[i+j]) hsn[rt1[i+j]]=j;
664 if(rt2[i+j]) hsn[rt2[i+j]]=j;
665 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
666 // Stores can allocate zero
670 // On some architectures stores need invc_ptr
671 #if defined(HOST_IMM8)
672 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
676 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
684 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
686 // Follow first branch
687 int t=(ba[i+b]-start)>>2;
688 j=7-b;if(t+j>=slen) j=slen-t-1;
691 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
692 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
693 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
694 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
697 // TODO: preferred register based on backward branch
699 // Delay slot should preferably not overwrite branch conditions or cycle count
700 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
701 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
702 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
708 // Coprocessor load/store needs FTEMP, even if not declared
709 if(itype[i]==C1LS||itype[i]==C2LS) {
712 // Load L/R also uses FTEMP as a temporary register
713 if(itype[i]==LOADLR) {
716 // Also SWL/SWR/SDL/SDR
717 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
720 // Don't remove the TLB registers either
721 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
724 // Don't remove the miniht registers
725 if(itype[i]==UJUMP||itype[i]==RJUMP)
732 // We only want to allocate registers if we're going to use them again soon
733 int needed_again(int r, int i)
739 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
741 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
742 return 0; // Don't need any registers if exiting the block
750 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
752 // Don't go past an unconditonal jump
756 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
763 if(rs1[i+j]==r) rn=j;
764 if(rs2[i+j]==r) rn=j;
765 if((unneeded_reg[i+j]>>r)&1) rn=10;
766 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
774 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
776 // Follow first branch
778 int t=(ba[i+b]-start)>>2;
779 j=7-b;if(t+j>=slen) j=slen-t-1;
782 if(!((unneeded_reg[t+j]>>r)&1)) {
783 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
784 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
794 // Try to match register allocations at the end of a loop with those
796 int loop_reg(int i, int r, int hr)
805 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
807 // Don't go past an unconditonal jump
814 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
819 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
820 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
821 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
823 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
825 int t=(ba[i+k]-start)>>2;
826 int reg=get_reg(regs[t].regmap_entry,r);
827 if(reg>=0) return reg;
828 //reg=get_reg(regs[t+1].regmap_entry,r);
829 //if(reg>=0) return reg;
837 // Allocate every register, preserving source/target regs
838 void alloc_all(struct regstat *cur,int i)
842 for(hr=0;hr<HOST_REGS;hr++) {
843 if(hr!=EXCLUDE_REG) {
844 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
845 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
848 cur->dirty&=~(1<<hr);
851 if((cur->regmap[hr]&63)==0)
854 cur->dirty&=~(1<<hr);
861 void div64(int64_t dividend,int64_t divisor)
865 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
866 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
868 void divu64(uint64_t dividend,uint64_t divisor)
872 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
873 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
876 void mult64(uint64_t m1,uint64_t m2)
878 unsigned long long int op1, op2, op3, op4;
879 unsigned long long int result1, result2, result3, result4;
880 unsigned long long int temp1, temp2, temp3, temp4;
896 op1 = op2 & 0xFFFFFFFF;
897 op2 = (op2 >> 32) & 0xFFFFFFFF;
898 op3 = op4 & 0xFFFFFFFF;
899 op4 = (op4 >> 32) & 0xFFFFFFFF;
902 temp2 = (temp1 >> 32) + op1 * op4;
904 temp4 = (temp3 >> 32) + op2 * op4;
906 result1 = temp1 & 0xFFFFFFFF;
907 result2 = temp2 + (temp3 & 0xFFFFFFFF);
908 result3 = (result2 >> 32) + temp4;
909 result4 = (result3 >> 32);
911 lo = result1 | (result2 << 32);
912 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
921 void multu64(uint64_t m1,uint64_t m2)
923 unsigned long long int op1, op2, op3, op4;
924 unsigned long long int result1, result2, result3, result4;
925 unsigned long long int temp1, temp2, temp3, temp4;
927 op1 = m1 & 0xFFFFFFFF;
928 op2 = (m1 >> 32) & 0xFFFFFFFF;
929 op3 = m2 & 0xFFFFFFFF;
930 op4 = (m2 >> 32) & 0xFFFFFFFF;
933 temp2 = (temp1 >> 32) + op1 * op4;
935 temp4 = (temp3 >> 32) + op2 * op4;
937 result1 = temp1 & 0xFFFFFFFF;
938 result2 = temp2 + (temp3 & 0xFFFFFFFF);
939 result3 = (result2 >> 32) + temp4;
940 result4 = (result3 >> 32);
942 lo = result1 | (result2 << 32);
943 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
945 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
946 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
949 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
957 else original=loaded;
960 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
963 original>>=64-(bits^56);
964 original<<=64-(bits^56);
968 else original=loaded;
974 #include "assem_x86.c"
977 #include "assem_x64.c"
980 #include "assem_arm.c"
983 // Add virtual address mapping to linked list
984 void ll_add(struct ll_entry **head,int vaddr,void *addr)
986 struct ll_entry *new_entry;
987 new_entry=malloc(sizeof(struct ll_entry));
988 assert(new_entry!=NULL);
989 new_entry->vaddr=vaddr;
991 new_entry->addr=addr;
992 new_entry->next=*head;
996 // Add virtual address mapping for 32-bit compiled block
997 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
999 ll_add(head,vaddr,addr);
1001 (*head)->reg32=reg32;
1005 // Check if an address is already compiled
1006 // but don't return addresses which are about to expire from the cache
1007 void *check_addr(u_int vaddr)
1009 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1010 if(ht_bin[0]==vaddr) {
1011 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1012 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1014 if(ht_bin[2]==vaddr) {
1015 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1016 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1018 u_int page=get_page(vaddr);
1019 struct ll_entry *head;
1022 if(head->vaddr==vaddr&&head->reg32==0) {
1023 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1024 // Update existing entry with current address
1025 if(ht_bin[0]==vaddr) {
1026 ht_bin[1]=(int)head->addr;
1029 if(ht_bin[2]==vaddr) {
1030 ht_bin[3]=(int)head->addr;
1033 // Insert into hash table with low priority.
1034 // Don't evict existing entries, as they are probably
1035 // addresses that are being accessed frequently.
1037 ht_bin[1]=(int)head->addr;
1039 }else if(ht_bin[2]==-1) {
1040 ht_bin[3]=(int)head->addr;
1051 void remove_hash(int vaddr)
1053 //printf("remove hash: %x\n",vaddr);
1054 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1055 if(ht_bin[2]==vaddr) {
1056 ht_bin[2]=ht_bin[3]=-1;
1058 if(ht_bin[0]==vaddr) {
1059 ht_bin[0]=ht_bin[2];
1060 ht_bin[1]=ht_bin[3];
1061 ht_bin[2]=ht_bin[3]=-1;
1065 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1067 struct ll_entry *next;
1069 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1070 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1072 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1073 remove_hash((*head)->vaddr);
1080 head=&((*head)->next);
1085 // Remove all entries from linked list
1086 void ll_clear(struct ll_entry **head)
1088 struct ll_entry *cur;
1089 struct ll_entry *next;
1100 // Dereference the pointers and remove if it matches
1101 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1104 int ptr=get_pointer(head->addr);
1105 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1106 if(((ptr>>shift)==(addr>>shift)) ||
1107 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1109 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1110 u_int host_addr=(u_int)kill_pointer(head->addr);
1112 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1119 // This is called when we write to a compiled block (see do_invstub)
1120 void invalidate_page(u_int page)
1122 struct ll_entry *head;
1123 struct ll_entry *next;
1127 inv_debug("INVALIDATE: %x\n",head->vaddr);
1128 remove_hash(head->vaddr);
1133 head=jump_out[page];
1136 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1137 u_int host_addr=(u_int)kill_pointer(head->addr);
1139 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1147 static void invalidate_block_range(u_int block, u_int first, u_int last)
1149 u_int page=get_page(block<<12);
1150 //printf("first=%d last=%d\n",first,last);
1151 invalidate_page(page);
1152 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1153 assert(last<page+5);
1154 // Invalidate the adjacent pages if a block crosses a 4K boundary
1156 invalidate_page(first);
1159 for(first=page+1;first<last;first++) {
1160 invalidate_page(first);
1166 // Don't trap writes
1167 invalid_code[block]=1;
1169 // If there is a valid TLB entry for this page, remove write protect
1170 if(tlb_LUT_w[block]) {
1171 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1172 // CHECK: Is this right?
1173 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1174 u_int real_block=tlb_LUT_w[block]>>12;
1175 invalid_code[real_block]=1;
1176 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1178 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1182 memset(mini_ht,-1,sizeof(mini_ht));
1186 void invalidate_block(u_int block)
1188 u_int page=get_page(block<<12);
1189 u_int vpage=get_vpage(block<<12);
1190 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1191 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1194 struct ll_entry *head;
1195 head=jump_dirty[vpage];
1196 //printf("page=%d vpage=%d\n",page,vpage);
1199 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1200 get_bounds((int)head->addr,&start,&end);
1201 //printf("start: %x end: %x\n",start,end);
1202 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1203 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1204 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1205 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1209 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1210 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1211 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1212 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1219 invalidate_block_range(block,first,last);
1222 void invalidate_addr(u_int addr)
1226 // this check is done by the caller
1227 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1228 u_int page=get_page(addr);
1229 if(page<2048) { // RAM
1230 struct ll_entry *head;
1231 u_int addr_min=~0, addr_max=0;
1232 int mask=RAM_SIZE-1;
1234 inv_code_start=addr&~0xfff;
1235 inv_code_end=addr|0xfff;
1238 // must check previous page too because of spans..
1240 inv_code_start-=0x1000;
1242 for(;pg1<=page;pg1++) {
1243 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1245 get_bounds((int)head->addr,&start,&end);
1246 if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1247 if(start<addr_min) addr_min=start;
1248 if(end>addr_max) addr_max=end;
1250 else if(addr<start) {
1251 if(start<inv_code_end)
1252 inv_code_end=start-1;
1255 if(end>inv_code_start)
1261 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1262 inv_code_start=inv_code_end=~0;
1263 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1267 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);//rhits);
1270 if(page!=0) // FIXME: don't know what's up with page 0 (Klonoa)
1274 invalidate_block(addr>>12);
1277 // This is called when loading a save state.
1278 // Anything could have changed, so invalidate everything.
1279 void invalidate_all_pages()
1282 for(page=0;page<4096;page++)
1283 invalidate_page(page);
1284 for(page=0;page<1048576;page++)
1285 if(!invalid_code[page]) {
1286 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1287 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1290 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1293 memset(mini_ht,-1,sizeof(mini_ht));
1297 for(page=0;page<0x100000;page++) {
1298 if(tlb_LUT_r[page]) {
1299 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1300 if(!tlb_LUT_w[page]||!invalid_code[page])
1301 memory_map[page]|=0x40000000; // Write protect
1303 else memory_map[page]=-1;
1304 if(page==0x80000) page=0xC0000;
1310 // Add an entry to jump_out after making a link
1311 void add_link(u_int vaddr,void *src)
1313 u_int page=get_page(vaddr);
1314 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1315 int *ptr=(int *)(src+4);
1316 assert((*ptr&0x0fff0000)==0x059f0000);
1317 ll_add(jump_out+page,vaddr,src);
1318 //int ptr=get_pointer(src);
1319 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1322 // If a code block was found to be unmodified (bit was set in
1323 // restore_candidate) and it remains unmodified (bit is clear
1324 // in invalid_code) then move the entries for that 4K page from
1325 // the dirty list to the clean list.
1326 void clean_blocks(u_int page)
1328 struct ll_entry *head;
1329 inv_debug("INV: clean_blocks page=%d\n",page);
1330 head=jump_dirty[page];
1332 if(!invalid_code[head->vaddr>>12]) {
1333 // Don't restore blocks which are about to expire from the cache
1334 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1336 if(verify_dirty((int)head->addr)) {
1337 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1340 get_bounds((int)head->addr,&start,&end);
1341 if(start-(u_int)rdram<RAM_SIZE) {
1342 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1343 inv|=invalid_code[i];
1347 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1348 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1349 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1350 if(addr<start||addr>=end) inv=1;
1353 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1357 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1358 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1361 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1363 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1364 //printf("page=%x, addr=%x\n",page,head->vaddr);
1365 //assert(head->vaddr>>12==(page|0x80000));
1366 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1367 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1369 if(ht_bin[0]==head->vaddr) {
1370 ht_bin[1]=(int)clean_addr; // Replace existing entry
1372 if(ht_bin[2]==head->vaddr) {
1373 ht_bin[3]=(int)clean_addr; // Replace existing entry
1386 void mov_alloc(struct regstat *current,int i)
1388 // Note: Don't need to actually alloc the source registers
1389 if((~current->is32>>rs1[i])&1) {
1390 //alloc_reg64(current,i,rs1[i]);
1391 alloc_reg64(current,i,rt1[i]);
1392 current->is32&=~(1LL<<rt1[i]);
1394 //alloc_reg(current,i,rs1[i]);
1395 alloc_reg(current,i,rt1[i]);
1396 current->is32|=(1LL<<rt1[i]);
1398 clear_const(current,rs1[i]);
1399 clear_const(current,rt1[i]);
1400 dirty_reg(current,rt1[i]);
1403 void shiftimm_alloc(struct regstat *current,int i)
1405 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1408 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1410 alloc_reg(current,i,rt1[i]);
1411 current->is32|=1LL<<rt1[i];
1412 dirty_reg(current,rt1[i]);
1413 if(is_const(current,rs1[i])) {
1414 int v=get_const(current,rs1[i]);
1415 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1416 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1417 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1419 else clear_const(current,rt1[i]);
1424 clear_const(current,rs1[i]);
1425 clear_const(current,rt1[i]);
1428 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1431 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1432 alloc_reg64(current,i,rt1[i]);
1433 current->is32&=~(1LL<<rt1[i]);
1434 dirty_reg(current,rt1[i]);
1437 if(opcode2[i]==0x3c) // DSLL32
1440 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1441 alloc_reg64(current,i,rt1[i]);
1442 current->is32&=~(1LL<<rt1[i]);
1443 dirty_reg(current,rt1[i]);
1446 if(opcode2[i]==0x3e) // DSRL32
1449 alloc_reg64(current,i,rs1[i]);
1451 alloc_reg64(current,i,rt1[i]);
1452 current->is32&=~(1LL<<rt1[i]);
1454 alloc_reg(current,i,rt1[i]);
1455 current->is32|=1LL<<rt1[i];
1457 dirty_reg(current,rt1[i]);
1460 if(opcode2[i]==0x3f) // DSRA32
1463 alloc_reg64(current,i,rs1[i]);
1464 alloc_reg(current,i,rt1[i]);
1465 current->is32|=1LL<<rt1[i];
1466 dirty_reg(current,rt1[i]);
1471 void shift_alloc(struct regstat *current,int i)
1474 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1476 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1477 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1478 alloc_reg(current,i,rt1[i]);
1479 if(rt1[i]==rs2[i]) {
1480 alloc_reg_temp(current,i,-1);
1481 minimum_free_regs[i]=1;
1483 current->is32|=1LL<<rt1[i];
1484 } else { // DSLLV/DSRLV/DSRAV
1485 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1486 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1487 alloc_reg64(current,i,rt1[i]);
1488 current->is32&=~(1LL<<rt1[i]);
1489 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1491 alloc_reg_temp(current,i,-1);
1492 minimum_free_regs[i]=1;
1495 clear_const(current,rs1[i]);
1496 clear_const(current,rs2[i]);
1497 clear_const(current,rt1[i]);
1498 dirty_reg(current,rt1[i]);
1502 void alu_alloc(struct regstat *current,int i)
1504 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1506 if(rs1[i]&&rs2[i]) {
1507 alloc_reg(current,i,rs1[i]);
1508 alloc_reg(current,i,rs2[i]);
1511 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1512 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1514 alloc_reg(current,i,rt1[i]);
1516 current->is32|=1LL<<rt1[i];
1518 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1520 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1522 alloc_reg64(current,i,rs1[i]);
1523 alloc_reg64(current,i,rs2[i]);
1524 alloc_reg(current,i,rt1[i]);
1526 alloc_reg(current,i,rs1[i]);
1527 alloc_reg(current,i,rs2[i]);
1528 alloc_reg(current,i,rt1[i]);
1531 current->is32|=1LL<<rt1[i];
1533 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1535 if(rs1[i]&&rs2[i]) {
1536 alloc_reg(current,i,rs1[i]);
1537 alloc_reg(current,i,rs2[i]);
1541 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1542 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1544 alloc_reg(current,i,rt1[i]);
1545 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1547 if(!((current->uu>>rt1[i])&1)) {
1548 alloc_reg64(current,i,rt1[i]);
1550 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1551 if(rs1[i]&&rs2[i]) {
1552 alloc_reg64(current,i,rs1[i]);
1553 alloc_reg64(current,i,rs2[i]);
1557 // Is is really worth it to keep 64-bit values in registers?
1559 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1560 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1564 current->is32&=~(1LL<<rt1[i]);
1566 current->is32|=1LL<<rt1[i];
1570 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1572 if(rs1[i]&&rs2[i]) {
1573 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1574 alloc_reg64(current,i,rs1[i]);
1575 alloc_reg64(current,i,rs2[i]);
1576 alloc_reg64(current,i,rt1[i]);
1578 alloc_reg(current,i,rs1[i]);
1579 alloc_reg(current,i,rs2[i]);
1580 alloc_reg(current,i,rt1[i]);
1584 alloc_reg(current,i,rt1[i]);
1585 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1586 // DADD used as move, or zeroing
1587 // If we have a 64-bit source, then make the target 64 bits too
1588 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1589 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1590 alloc_reg64(current,i,rt1[i]);
1591 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1592 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1593 alloc_reg64(current,i,rt1[i]);
1595 if(opcode2[i]>=0x2e&&rs2[i]) {
1596 // DSUB used as negation - 64-bit result
1597 // If we have a 32-bit register, extend it to 64 bits
1598 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1599 alloc_reg64(current,i,rt1[i]);
1603 if(rs1[i]&&rs2[i]) {
1604 current->is32&=~(1LL<<rt1[i]);
1606 current->is32&=~(1LL<<rt1[i]);
1607 if((current->is32>>rs1[i])&1)
1608 current->is32|=1LL<<rt1[i];
1610 current->is32&=~(1LL<<rt1[i]);
1611 if((current->is32>>rs2[i])&1)
1612 current->is32|=1LL<<rt1[i];
1614 current->is32|=1LL<<rt1[i];
1618 clear_const(current,rs1[i]);
1619 clear_const(current,rs2[i]);
1620 clear_const(current,rt1[i]);
1621 dirty_reg(current,rt1[i]);
1624 void imm16_alloc(struct regstat *current,int i)
1626 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1628 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1629 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1630 current->is32&=~(1LL<<rt1[i]);
1631 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1632 // TODO: Could preserve the 32-bit flag if the immediate is zero
1633 alloc_reg64(current,i,rt1[i]);
1634 alloc_reg64(current,i,rs1[i]);
1636 clear_const(current,rs1[i]);
1637 clear_const(current,rt1[i]);
1639 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1640 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1641 current->is32|=1LL<<rt1[i];
1642 clear_const(current,rs1[i]);
1643 clear_const(current,rt1[i]);
1645 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1646 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1647 if(rs1[i]!=rt1[i]) {
1648 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1649 alloc_reg64(current,i,rt1[i]);
1650 current->is32&=~(1LL<<rt1[i]);
1653 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1654 if(is_const(current,rs1[i])) {
1655 int v=get_const(current,rs1[i]);
1656 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1657 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1658 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1660 else clear_const(current,rt1[i]);
1662 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1663 if(is_const(current,rs1[i])) {
1664 int v=get_const(current,rs1[i]);
1665 set_const(current,rt1[i],v+imm[i]);
1667 else clear_const(current,rt1[i]);
1668 current->is32|=1LL<<rt1[i];
1671 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1672 current->is32|=1LL<<rt1[i];
1674 dirty_reg(current,rt1[i]);
1677 void load_alloc(struct regstat *current,int i)
1679 clear_const(current,rt1[i]);
1680 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1681 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1682 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1683 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1684 alloc_reg(current,i,rt1[i]);
1685 assert(get_reg(current->regmap,rt1[i])>=0);
1686 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1688 current->is32&=~(1LL<<rt1[i]);
1689 alloc_reg64(current,i,rt1[i]);
1691 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1693 current->is32&=~(1LL<<rt1[i]);
1694 alloc_reg64(current,i,rt1[i]);
1695 alloc_all(current,i);
1696 alloc_reg64(current,i,FTEMP);
1697 minimum_free_regs[i]=HOST_REGS;
1699 else current->is32|=1LL<<rt1[i];
1700 dirty_reg(current,rt1[i]);
1701 // If using TLB, need a register for pointer to the mapping table
1702 if(using_tlb) alloc_reg(current,i,TLREG);
1703 // LWL/LWR need a temporary register for the old value
1704 if(opcode[i]==0x22||opcode[i]==0x26)
1706 alloc_reg(current,i,FTEMP);
1707 alloc_reg_temp(current,i,-1);
1708 minimum_free_regs[i]=1;
1713 // Load to r0 or unneeded register (dummy load)
1714 // but we still need a register to calculate the address
1715 if(opcode[i]==0x22||opcode[i]==0x26)
1717 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1719 // If using TLB, need a register for pointer to the mapping table
1720 if(using_tlb) alloc_reg(current,i,TLREG);
1721 alloc_reg_temp(current,i,-1);
1722 minimum_free_regs[i]=1;
1723 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1725 alloc_all(current,i);
1726 alloc_reg64(current,i,FTEMP);
1727 minimum_free_regs[i]=HOST_REGS;
1732 void store_alloc(struct regstat *current,int i)
1734 clear_const(current,rs2[i]);
1735 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1736 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1737 alloc_reg(current,i,rs2[i]);
1738 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1739 alloc_reg64(current,i,rs2[i]);
1740 if(rs2[i]) alloc_reg(current,i,FTEMP);
1742 // If using TLB, need a register for pointer to the mapping table
1743 if(using_tlb) alloc_reg(current,i,TLREG);
1744 #if defined(HOST_IMM8)
1745 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1746 else alloc_reg(current,i,INVCP);
1748 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1749 alloc_reg(current,i,FTEMP);
1751 // We need a temporary register for address generation
1752 alloc_reg_temp(current,i,-1);
1753 minimum_free_regs[i]=1;
1756 void c1ls_alloc(struct regstat *current,int i)
1758 //clear_const(current,rs1[i]); // FIXME
1759 clear_const(current,rt1[i]);
1760 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1761 alloc_reg(current,i,CSREG); // Status
1762 alloc_reg(current,i,FTEMP);
1763 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1764 alloc_reg64(current,i,FTEMP);
1766 // If using TLB, need a register for pointer to the mapping table
1767 if(using_tlb) alloc_reg(current,i,TLREG);
1768 #if defined(HOST_IMM8)
1769 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1770 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1771 alloc_reg(current,i,INVCP);
1773 // We need a temporary register for address generation
1774 alloc_reg_temp(current,i,-1);
1777 void c2ls_alloc(struct regstat *current,int i)
1779 clear_const(current,rt1[i]);
1780 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1781 alloc_reg(current,i,FTEMP);
1782 // If using TLB, need a register for pointer to the mapping table
1783 if(using_tlb) alloc_reg(current,i,TLREG);
1784 #if defined(HOST_IMM8)
1785 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1786 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1787 alloc_reg(current,i,INVCP);
1789 // We need a temporary register for address generation
1790 alloc_reg_temp(current,i,-1);
1791 minimum_free_regs[i]=1;
1794 #ifndef multdiv_alloc
1795 void multdiv_alloc(struct regstat *current,int i)
1802 // case 0x1D: DMULTU
1805 clear_const(current,rs1[i]);
1806 clear_const(current,rs2[i]);
1809 if((opcode2[i]&4)==0) // 32-bit
1811 current->u&=~(1LL<<HIREG);
1812 current->u&=~(1LL<<LOREG);
1813 alloc_reg(current,i,HIREG);
1814 alloc_reg(current,i,LOREG);
1815 alloc_reg(current,i,rs1[i]);
1816 alloc_reg(current,i,rs2[i]);
1817 current->is32|=1LL<<HIREG;
1818 current->is32|=1LL<<LOREG;
1819 dirty_reg(current,HIREG);
1820 dirty_reg(current,LOREG);
1824 current->u&=~(1LL<<HIREG);
1825 current->u&=~(1LL<<LOREG);
1826 current->uu&=~(1LL<<HIREG);
1827 current->uu&=~(1LL<<LOREG);
1828 alloc_reg64(current,i,HIREG);
1829 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1830 alloc_reg64(current,i,rs1[i]);
1831 alloc_reg64(current,i,rs2[i]);
1832 alloc_all(current,i);
1833 current->is32&=~(1LL<<HIREG);
1834 current->is32&=~(1LL<<LOREG);
1835 dirty_reg(current,HIREG);
1836 dirty_reg(current,LOREG);
1837 minimum_free_regs[i]=HOST_REGS;
1842 // Multiply by zero is zero.
1843 // MIPS does not have a divide by zero exception.
1844 // The result is undefined, we return zero.
1845 alloc_reg(current,i,HIREG);
1846 alloc_reg(current,i,LOREG);
1847 current->is32|=1LL<<HIREG;
1848 current->is32|=1LL<<LOREG;
1849 dirty_reg(current,HIREG);
1850 dirty_reg(current,LOREG);
1855 void cop0_alloc(struct regstat *current,int i)
1857 if(opcode2[i]==0) // MFC0
1860 clear_const(current,rt1[i]);
1861 alloc_all(current,i);
1862 alloc_reg(current,i,rt1[i]);
1863 current->is32|=1LL<<rt1[i];
1864 dirty_reg(current,rt1[i]);
1867 else if(opcode2[i]==4) // MTC0
1870 clear_const(current,rs1[i]);
1871 alloc_reg(current,i,rs1[i]);
1872 alloc_all(current,i);
1875 alloc_all(current,i); // FIXME: Keep r0
1877 alloc_reg(current,i,0);
1882 // TLBR/TLBWI/TLBWR/TLBP/ERET
1883 assert(opcode2[i]==0x10);
1884 alloc_all(current,i);
1886 minimum_free_regs[i]=HOST_REGS;
1889 void cop1_alloc(struct regstat *current,int i)
1891 alloc_reg(current,i,CSREG); // Load status
1892 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1895 clear_const(current,rt1[i]);
1897 alloc_reg64(current,i,rt1[i]); // DMFC1
1898 current->is32&=~(1LL<<rt1[i]);
1900 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1901 current->is32|=1LL<<rt1[i];
1903 dirty_reg(current,rt1[i]);
1905 alloc_reg_temp(current,i,-1);
1907 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1910 clear_const(current,rs1[i]);
1912 alloc_reg64(current,i,rs1[i]); // DMTC1
1914 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1915 alloc_reg_temp(current,i,-1);
1919 alloc_reg(current,i,0);
1920 alloc_reg_temp(current,i,-1);
1923 minimum_free_regs[i]=1;
1925 void fconv_alloc(struct regstat *current,int i)
1927 alloc_reg(current,i,CSREG); // Load status
1928 alloc_reg_temp(current,i,-1);
1929 minimum_free_regs[i]=1;
1931 void float_alloc(struct regstat *current,int i)
1933 alloc_reg(current,i,CSREG); // Load status
1934 alloc_reg_temp(current,i,-1);
1935 minimum_free_regs[i]=1;
1937 void c2op_alloc(struct regstat *current,int i)
1939 alloc_reg_temp(current,i,-1);
1941 void fcomp_alloc(struct regstat *current,int i)
1943 alloc_reg(current,i,CSREG); // Load status
1944 alloc_reg(current,i,FSREG); // Load flags
1945 dirty_reg(current,FSREG); // Flag will be modified
1946 alloc_reg_temp(current,i,-1);
1947 minimum_free_regs[i]=1;
1950 void syscall_alloc(struct regstat *current,int i)
1952 alloc_cc(current,i);
1953 dirty_reg(current,CCREG);
1954 alloc_all(current,i);
1955 minimum_free_regs[i]=HOST_REGS;
1959 void delayslot_alloc(struct regstat *current,int i)
1970 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1971 printf("Disabled speculative precompilation\n");
1975 imm16_alloc(current,i);
1979 load_alloc(current,i);
1983 store_alloc(current,i);
1986 alu_alloc(current,i);
1989 shift_alloc(current,i);
1992 multdiv_alloc(current,i);
1995 shiftimm_alloc(current,i);
1998 mov_alloc(current,i);
2001 cop0_alloc(current,i);
2005 cop1_alloc(current,i);
2008 c1ls_alloc(current,i);
2011 c2ls_alloc(current,i);
2014 fconv_alloc(current,i);
2017 float_alloc(current,i);
2020 fcomp_alloc(current,i);
2023 c2op_alloc(current,i);
2028 // Special case where a branch and delay slot span two pages in virtual memory
2029 static void pagespan_alloc(struct regstat *current,int i)
2032 current->wasconst=0;
2034 minimum_free_regs[i]=HOST_REGS;
2035 alloc_all(current,i);
2036 alloc_cc(current,i);
2037 dirty_reg(current,CCREG);
2038 if(opcode[i]==3) // JAL
2040 alloc_reg(current,i,31);
2041 dirty_reg(current,31);
2043 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2045 alloc_reg(current,i,rs1[i]);
2047 alloc_reg(current,i,rt1[i]);
2048 dirty_reg(current,rt1[i]);
2051 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2053 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2054 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2055 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2057 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2058 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2062 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2064 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2065 if(!((current->is32>>rs1[i])&1))
2067 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2071 if(opcode[i]==0x11) // BC1
2073 alloc_reg(current,i,FSREG);
2074 alloc_reg(current,i,CSREG);
2079 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2081 stubs[stubcount][0]=type;
2082 stubs[stubcount][1]=addr;
2083 stubs[stubcount][2]=retaddr;
2084 stubs[stubcount][3]=a;
2085 stubs[stubcount][4]=b;
2086 stubs[stubcount][5]=c;
2087 stubs[stubcount][6]=d;
2088 stubs[stubcount][7]=e;
2092 // Write out a single register
2093 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2096 for(hr=0;hr<HOST_REGS;hr++) {
2097 if(hr!=EXCLUDE_REG) {
2098 if((regmap[hr]&63)==r) {
2101 emit_storereg(r,hr);
2103 if((is32>>regmap[hr])&1) {
2104 emit_sarimm(hr,31,hr);
2105 emit_storereg(r|64,hr);
2109 emit_storereg(r|64,hr);
2119 //if(!tracedebug) return 0;
2122 for(i=0;i<2097152;i++) {
2123 unsigned int temp=sum;
2126 sum^=((u_int *)rdram)[i];
2135 sum^=((u_int *)reg)[i];
2143 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2145 #ifndef DISABLE_COP1
2148 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2158 void memdebug(int i)
2160 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2161 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2164 //if(Count>=-2084597794) {
2165 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2167 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2168 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2169 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2172 printf("TRACE: %x\n",(&i)[-1]);
2176 printf("TRACE: %x \n",(&j)[10]);
2177 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2181 //printf("TRACE: %x\n",(&i)[-1]);
2184 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2186 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2189 void alu_assemble(int i,struct regstat *i_regs)
2191 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2193 signed char s1,s2,t;
2194 t=get_reg(i_regs->regmap,rt1[i]);
2196 s1=get_reg(i_regs->regmap,rs1[i]);
2197 s2=get_reg(i_regs->regmap,rs2[i]);
2198 if(rs1[i]&&rs2[i]) {
2201 if(opcode2[i]&2) emit_sub(s1,s2,t);
2202 else emit_add(s1,s2,t);
2205 if(s1>=0) emit_mov(s1,t);
2206 else emit_loadreg(rs1[i],t);
2210 if(opcode2[i]&2) emit_neg(s2,t);
2211 else emit_mov(s2,t);
2214 emit_loadreg(rs2[i],t);
2215 if(opcode2[i]&2) emit_neg(t,t);
2218 else emit_zeroreg(t);
2222 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2224 signed char s1l,s2l,s1h,s2h,tl,th;
2225 tl=get_reg(i_regs->regmap,rt1[i]);
2226 th=get_reg(i_regs->regmap,rt1[i]|64);
2228 s1l=get_reg(i_regs->regmap,rs1[i]);
2229 s2l=get_reg(i_regs->regmap,rs2[i]);
2230 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2231 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2232 if(rs1[i]&&rs2[i]) {
2235 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2236 else emit_adds(s1l,s2l,tl);
2238 #ifdef INVERTED_CARRY
2239 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2241 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2243 else emit_add(s1h,s2h,th);
2247 if(s1l>=0) emit_mov(s1l,tl);
2248 else emit_loadreg(rs1[i],tl);
2250 if(s1h>=0) emit_mov(s1h,th);
2251 else emit_loadreg(rs1[i]|64,th);
2256 if(opcode2[i]&2) emit_negs(s2l,tl);
2257 else emit_mov(s2l,tl);
2260 emit_loadreg(rs2[i],tl);
2261 if(opcode2[i]&2) emit_negs(tl,tl);
2264 #ifdef INVERTED_CARRY
2265 if(s2h>=0) emit_mov(s2h,th);
2266 else emit_loadreg(rs2[i]|64,th);
2268 emit_adcimm(-1,th); // x86 has inverted carry flag
2273 if(s2h>=0) emit_rscimm(s2h,0,th);
2275 emit_loadreg(rs2[i]|64,th);
2276 emit_rscimm(th,0,th);
2279 if(s2h>=0) emit_mov(s2h,th);
2280 else emit_loadreg(rs2[i]|64,th);
2287 if(th>=0) emit_zeroreg(th);
2292 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2294 signed char s1l,s1h,s2l,s2h,t;
2295 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2297 t=get_reg(i_regs->regmap,rt1[i]);
2300 s1l=get_reg(i_regs->regmap,rs1[i]);
2301 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2302 s2l=get_reg(i_regs->regmap,rs2[i]);
2303 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2304 if(rs2[i]==0) // rx<r0
2307 if(opcode2[i]==0x2a) // SLT
2308 emit_shrimm(s1h,31,t);
2309 else // SLTU (unsigned can not be less than zero)
2312 else if(rs1[i]==0) // r0<rx
2315 if(opcode2[i]==0x2a) // SLT
2316 emit_set_gz64_32(s2h,s2l,t);
2317 else // SLTU (set if not zero)
2318 emit_set_nz64_32(s2h,s2l,t);
2321 assert(s1l>=0);assert(s1h>=0);
2322 assert(s2l>=0);assert(s2h>=0);
2323 if(opcode2[i]==0x2a) // SLT
2324 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2326 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2330 t=get_reg(i_regs->regmap,rt1[i]);
2333 s1l=get_reg(i_regs->regmap,rs1[i]);
2334 s2l=get_reg(i_regs->regmap,rs2[i]);
2335 if(rs2[i]==0) // rx<r0
2338 if(opcode2[i]==0x2a) // SLT
2339 emit_shrimm(s1l,31,t);
2340 else // SLTU (unsigned can not be less than zero)
2343 else if(rs1[i]==0) // r0<rx
2346 if(opcode2[i]==0x2a) // SLT
2347 emit_set_gz32(s2l,t);
2348 else // SLTU (set if not zero)
2349 emit_set_nz32(s2l,t);
2352 assert(s1l>=0);assert(s2l>=0);
2353 if(opcode2[i]==0x2a) // SLT
2354 emit_set_if_less32(s1l,s2l,t);
2356 emit_set_if_carry32(s1l,s2l,t);
2362 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2364 signed char s1l,s1h,s2l,s2h,th,tl;
2365 tl=get_reg(i_regs->regmap,rt1[i]);
2366 th=get_reg(i_regs->regmap,rt1[i]|64);
2367 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2371 s1l=get_reg(i_regs->regmap,rs1[i]);
2372 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2373 s2l=get_reg(i_regs->regmap,rs2[i]);
2374 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2375 if(rs1[i]&&rs2[i]) {
2376 assert(s1l>=0);assert(s1h>=0);
2377 assert(s2l>=0);assert(s2h>=0);
2378 if(opcode2[i]==0x24) { // AND
2379 emit_and(s1l,s2l,tl);
2380 emit_and(s1h,s2h,th);
2382 if(opcode2[i]==0x25) { // OR
2383 emit_or(s1l,s2l,tl);
2384 emit_or(s1h,s2h,th);
2386 if(opcode2[i]==0x26) { // XOR
2387 emit_xor(s1l,s2l,tl);
2388 emit_xor(s1h,s2h,th);
2390 if(opcode2[i]==0x27) { // NOR
2391 emit_or(s1l,s2l,tl);
2392 emit_or(s1h,s2h,th);
2399 if(opcode2[i]==0x24) { // AND
2403 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2405 if(s1l>=0) emit_mov(s1l,tl);
2406 else emit_loadreg(rs1[i],tl);
2407 if(s1h>=0) emit_mov(s1h,th);
2408 else emit_loadreg(rs1[i]|64,th);
2412 if(s2l>=0) emit_mov(s2l,tl);
2413 else emit_loadreg(rs2[i],tl);
2414 if(s2h>=0) emit_mov(s2h,th);
2415 else emit_loadreg(rs2[i]|64,th);
2422 if(opcode2[i]==0x27) { // NOR
2424 if(s1l>=0) emit_not(s1l,tl);
2426 emit_loadreg(rs1[i],tl);
2429 if(s1h>=0) emit_not(s1h,th);
2431 emit_loadreg(rs1[i]|64,th);
2437 if(s2l>=0) emit_not(s2l,tl);
2439 emit_loadreg(rs2[i],tl);
2442 if(s2h>=0) emit_not(s2h,th);
2444 emit_loadreg(rs2[i]|64,th);
2460 s1l=get_reg(i_regs->regmap,rs1[i]);
2461 s2l=get_reg(i_regs->regmap,rs2[i]);
2462 if(rs1[i]&&rs2[i]) {
2465 if(opcode2[i]==0x24) { // AND
2466 emit_and(s1l,s2l,tl);
2468 if(opcode2[i]==0x25) { // OR
2469 emit_or(s1l,s2l,tl);
2471 if(opcode2[i]==0x26) { // XOR
2472 emit_xor(s1l,s2l,tl);
2474 if(opcode2[i]==0x27) { // NOR
2475 emit_or(s1l,s2l,tl);
2481 if(opcode2[i]==0x24) { // AND
2484 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2486 if(s1l>=0) emit_mov(s1l,tl);
2487 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2491 if(s2l>=0) emit_mov(s2l,tl);
2492 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2494 else emit_zeroreg(tl);
2496 if(opcode2[i]==0x27) { // NOR
2498 if(s1l>=0) emit_not(s1l,tl);
2500 emit_loadreg(rs1[i],tl);
2506 if(s2l>=0) emit_not(s2l,tl);
2508 emit_loadreg(rs2[i],tl);
2512 else emit_movimm(-1,tl);
2521 void imm16_assemble(int i,struct regstat *i_regs)
2523 if (opcode[i]==0x0f) { // LUI
2526 t=get_reg(i_regs->regmap,rt1[i]);
2529 if(!((i_regs->isconst>>t)&1))
2530 emit_movimm(imm[i]<<16,t);
2534 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2537 t=get_reg(i_regs->regmap,rt1[i]);
2538 s=get_reg(i_regs->regmap,rs1[i]);
2543 if(!((i_regs->isconst>>t)&1)) {
2545 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2546 emit_addimm(t,imm[i],t);
2548 if(!((i_regs->wasconst>>s)&1))
2549 emit_addimm(s,imm[i],t);
2551 emit_movimm(constmap[i][s]+imm[i],t);
2557 if(!((i_regs->isconst>>t)&1))
2558 emit_movimm(imm[i],t);
2563 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2565 signed char sh,sl,th,tl;
2566 th=get_reg(i_regs->regmap,rt1[i]|64);
2567 tl=get_reg(i_regs->regmap,rt1[i]);
2568 sh=get_reg(i_regs->regmap,rs1[i]|64);
2569 sl=get_reg(i_regs->regmap,rs1[i]);
2575 emit_addimm64_32(sh,sl,imm[i],th,tl);
2578 emit_addimm(sl,imm[i],tl);
2581 emit_movimm(imm[i],tl);
2582 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2587 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2589 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2590 signed char sh,sl,t;
2591 t=get_reg(i_regs->regmap,rt1[i]);
2592 sh=get_reg(i_regs->regmap,rs1[i]|64);
2593 sl=get_reg(i_regs->regmap,rs1[i]);
2597 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2598 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2599 if(opcode[i]==0x0a) { // SLTI
2601 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2602 emit_slti32(t,imm[i],t);
2604 emit_slti32(sl,imm[i],t);
2609 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2610 emit_sltiu32(t,imm[i],t);
2612 emit_sltiu32(sl,imm[i],t);
2617 if(opcode[i]==0x0a) // SLTI
2618 emit_slti64_32(sh,sl,imm[i],t);
2620 emit_sltiu64_32(sh,sl,imm[i],t);
2623 // SLTI(U) with r0 is just stupid,
2624 // nonetheless examples can be found
2625 if(opcode[i]==0x0a) // SLTI
2626 if(0<imm[i]) emit_movimm(1,t);
2627 else emit_zeroreg(t);
2630 if(imm[i]) emit_movimm(1,t);
2631 else emit_zeroreg(t);
2637 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2639 signed char sh,sl,th,tl;
2640 th=get_reg(i_regs->regmap,rt1[i]|64);
2641 tl=get_reg(i_regs->regmap,rt1[i]);
2642 sh=get_reg(i_regs->regmap,rs1[i]|64);
2643 sl=get_reg(i_regs->regmap,rs1[i]);
2644 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2645 if(opcode[i]==0x0c) //ANDI
2649 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2650 emit_andimm(tl,imm[i],tl);
2652 if(!((i_regs->wasconst>>sl)&1))
2653 emit_andimm(sl,imm[i],tl);
2655 emit_movimm(constmap[i][sl]&imm[i],tl);
2660 if(th>=0) emit_zeroreg(th);
2666 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2670 emit_loadreg(rs1[i]|64,th);
2675 if(opcode[i]==0x0d) //ORI
2677 emit_orimm(tl,imm[i],tl);
2679 if(!((i_regs->wasconst>>sl)&1))
2680 emit_orimm(sl,imm[i],tl);
2682 emit_movimm(constmap[i][sl]|imm[i],tl);
2684 if(opcode[i]==0x0e) //XORI
2686 emit_xorimm(tl,imm[i],tl);
2688 if(!((i_regs->wasconst>>sl)&1))
2689 emit_xorimm(sl,imm[i],tl);
2691 emit_movimm(constmap[i][sl]^imm[i],tl);
2695 emit_movimm(imm[i],tl);
2696 if(th>=0) emit_zeroreg(th);
2704 void shiftimm_assemble(int i,struct regstat *i_regs)
2706 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2710 t=get_reg(i_regs->regmap,rt1[i]);
2711 s=get_reg(i_regs->regmap,rs1[i]);
2713 if(t>=0&&!((i_regs->isconst>>t)&1)){
2720 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2722 if(opcode2[i]==0) // SLL
2724 emit_shlimm(s<0?t:s,imm[i],t);
2726 if(opcode2[i]==2) // SRL
2728 emit_shrimm(s<0?t:s,imm[i],t);
2730 if(opcode2[i]==3) // SRA
2732 emit_sarimm(s<0?t:s,imm[i],t);
2736 if(s>=0 && s!=t) emit_mov(s,t);
2740 //emit_storereg(rt1[i],t); //DEBUG
2743 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2746 signed char sh,sl,th,tl;
2747 th=get_reg(i_regs->regmap,rt1[i]|64);
2748 tl=get_reg(i_regs->regmap,rt1[i]);
2749 sh=get_reg(i_regs->regmap,rs1[i]|64);
2750 sl=get_reg(i_regs->regmap,rs1[i]);
2755 if(th>=0) emit_zeroreg(th);
2762 if(opcode2[i]==0x38) // DSLL
2764 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2765 emit_shlimm(sl,imm[i],tl);
2767 if(opcode2[i]==0x3a) // DSRL
2769 emit_shrdimm(sl,sh,imm[i],tl);
2770 if(th>=0) emit_shrimm(sh,imm[i],th);
2772 if(opcode2[i]==0x3b) // DSRA
2774 emit_shrdimm(sl,sh,imm[i],tl);
2775 if(th>=0) emit_sarimm(sh,imm[i],th);
2779 if(sl!=tl) emit_mov(sl,tl);
2780 if(th>=0&&sh!=th) emit_mov(sh,th);
2786 if(opcode2[i]==0x3c) // DSLL32
2789 signed char sl,tl,th;
2790 tl=get_reg(i_regs->regmap,rt1[i]);
2791 th=get_reg(i_regs->regmap,rt1[i]|64);
2792 sl=get_reg(i_regs->regmap,rs1[i]);
2801 emit_shlimm(th,imm[i]&31,th);
2806 if(opcode2[i]==0x3e) // DSRL32
2809 signed char sh,tl,th;
2810 tl=get_reg(i_regs->regmap,rt1[i]);
2811 th=get_reg(i_regs->regmap,rt1[i]|64);
2812 sh=get_reg(i_regs->regmap,rs1[i]|64);
2816 if(th>=0) emit_zeroreg(th);
2819 emit_shrimm(tl,imm[i]&31,tl);
2824 if(opcode2[i]==0x3f) // DSRA32
2828 tl=get_reg(i_regs->regmap,rt1[i]);
2829 sh=get_reg(i_regs->regmap,rs1[i]|64);
2835 emit_sarimm(tl,imm[i]&31,tl);
2842 #ifndef shift_assemble
2843 void shift_assemble(int i,struct regstat *i_regs)
2845 printf("Need shift_assemble for this architecture.\n");
2850 void load_assemble(int i,struct regstat *i_regs)
2852 int s,th,tl,addr,map=-1;
2855 int memtarget=0,c=0;
2856 int fastload_reg_override=0;
2858 th=get_reg(i_regs->regmap,rt1[i]|64);
2859 tl=get_reg(i_regs->regmap,rt1[i]);
2860 s=get_reg(i_regs->regmap,rs1[i]);
2862 for(hr=0;hr<HOST_REGS;hr++) {
2863 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2865 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2867 c=(i_regs->wasconst>>s)&1;
2869 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2870 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2873 //printf("load_assemble: c=%d\n",c);
2874 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2875 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2877 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2879 // could be FIFO, must perform the read
2881 assem_debug("(forced read)\n");
2882 tl=get_reg(i_regs->regmap,-1);
2886 if(offset||s<0||c) addr=tl;
2888 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2890 //printf("load_assemble: c=%d\n",c);
2891 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2892 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2894 if(th>=0) reglist&=~(1<<th);
2898 map=get_reg(i_regs->regmap,ROREG);
2899 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2901 //#define R29_HACK 1
2903 // Strmnnrmn's speed hack
2904 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2907 jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2912 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2913 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2914 map=get_reg(i_regs->regmap,TLREG);
2917 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2918 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2920 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2921 if (opcode[i]==0x20) { // LB
2924 #ifdef HOST_IMM_ADDR32
2926 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2930 //emit_xorimm(addr,3,tl);
2931 //gen_tlb_addr_r(tl,map);
2932 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2934 #ifdef BIG_ENDIAN_MIPS
2935 if(!c) emit_xorimm(addr,3,tl);
2936 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2940 if(fastload_reg_override) a=fastload_reg_override;
2942 emit_movsbl_indexed_tlb(x,a,map,tl);
2946 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2949 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2951 if (opcode[i]==0x21) { // LH
2954 #ifdef HOST_IMM_ADDR32
2956 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2961 #ifdef BIG_ENDIAN_MIPS
2962 if(!c) emit_xorimm(addr,2,tl);
2963 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2967 if(fastload_reg_override) a=fastload_reg_override;
2969 //emit_movswl_indexed_tlb(x,tl,map,tl);
2972 gen_tlb_addr_r(a,map);
2973 emit_movswl_indexed(x,a,tl);
2976 emit_movswl_indexed(x,a,tl);
2978 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2984 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2987 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2989 if (opcode[i]==0x23) { // LW
2993 if(fastload_reg_override) a=fastload_reg_override;
2994 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2995 #ifdef HOST_IMM_ADDR32
2997 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3000 emit_readword_indexed_tlb(0,a,map,tl);
3003 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3006 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3008 if (opcode[i]==0x24) { // LBU
3011 #ifdef HOST_IMM_ADDR32
3013 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3017 //emit_xorimm(addr,3,tl);
3018 //gen_tlb_addr_r(tl,map);
3019 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3021 #ifdef BIG_ENDIAN_MIPS
3022 if(!c) emit_xorimm(addr,3,tl);
3023 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3027 if(fastload_reg_override) a=fastload_reg_override;
3029 emit_movzbl_indexed_tlb(x,a,map,tl);
3033 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3036 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3038 if (opcode[i]==0x25) { // LHU
3041 #ifdef HOST_IMM_ADDR32
3043 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3048 #ifdef BIG_ENDIAN_MIPS
3049 if(!c) emit_xorimm(addr,2,tl);
3050 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3054 if(fastload_reg_override) a=fastload_reg_override;
3056 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3059 gen_tlb_addr_r(a,map);
3060 emit_movzwl_indexed(x,a,tl);
3063 emit_movzwl_indexed(x,a,tl);
3065 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3071 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3074 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3076 if (opcode[i]==0x27) { // LWU
3081 if(fastload_reg_override) a=fastload_reg_override;
3082 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3083 #ifdef HOST_IMM_ADDR32
3085 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3088 emit_readword_indexed_tlb(0,a,map,tl);
3091 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3094 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3098 if (opcode[i]==0x37) { // LD
3102 if(fastload_reg_override) a=fastload_reg_override;
3103 //gen_tlb_addr_r(tl,map);
3104 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3105 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3106 #ifdef HOST_IMM_ADDR32
3108 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3111 emit_readdword_indexed_tlb(0,a,map,th,tl);
3114 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3117 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3120 //emit_storereg(rt1[i],tl); // DEBUG
3121 //if(opcode[i]==0x23)
3122 //if(opcode[i]==0x24)
3123 //if(opcode[i]==0x23||opcode[i]==0x24)
3124 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3128 emit_readword((int)&last_count,ECX);
3130 if(get_reg(i_regs->regmap,CCREG)<0)
3131 emit_loadreg(CCREG,HOST_CCREG);
3132 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3133 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3134 emit_writeword(HOST_CCREG,(int)&Count);
3137 if(get_reg(i_regs->regmap,CCREG)<0)
3138 emit_loadreg(CCREG,0);
3140 emit_mov(HOST_CCREG,0);
3142 emit_addimm(0,2*ccadj[i],0);
3143 emit_writeword(0,(int)&Count);
3145 emit_call((int)memdebug);
3147 restore_regs(0x100f);
3151 #ifndef loadlr_assemble
3152 void loadlr_assemble(int i,struct regstat *i_regs)
3154 printf("Need loadlr_assemble for this architecture.\n");
3159 void store_assemble(int i,struct regstat *i_regs)
3164 int jaddr=0,jaddr2,type;
3165 int memtarget=0,c=0;
3166 int agr=AGEN1+(i&1);
3167 int faststore_reg_override=0;
3169 th=get_reg(i_regs->regmap,rs2[i]|64);
3170 tl=get_reg(i_regs->regmap,rs2[i]);
3171 s=get_reg(i_regs->regmap,rs1[i]);
3172 temp=get_reg(i_regs->regmap,agr);
3173 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3176 c=(i_regs->wasconst>>s)&1;
3178 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3179 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3184 for(hr=0;hr<HOST_REGS;hr++) {
3185 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3187 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3188 if(offset||s<0||c) addr=temp;
3194 // Strmnnrmn's speed hack
3195 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3197 emit_cmpimm(addr,RAM_SIZE);
3198 #ifdef DESTRUCTIVE_SHIFT
3199 if(s==addr) emit_mov(s,temp);
3203 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3207 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3208 // Hint to branch predictor that the branch is unlikely to be taken
3210 emit_jno_unlikely(0);
3216 jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3221 if (opcode[i]==0x28) x=3; // SB
3222 if (opcode[i]==0x29) x=2; // SH
3223 map=get_reg(i_regs->regmap,TLREG);
3226 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3227 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3230 if (opcode[i]==0x28) { // SB
3233 #ifdef BIG_ENDIAN_MIPS
3234 if(!c) emit_xorimm(addr,3,temp);
3235 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3239 if(faststore_reg_override) a=faststore_reg_override;
3240 //gen_tlb_addr_w(temp,map);
3241 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3242 emit_writebyte_indexed_tlb(tl,x,a,map,a);
3246 if (opcode[i]==0x29) { // SH
3249 #ifdef BIG_ENDIAN_MIPS
3250 if(!c) emit_xorimm(addr,2,temp);
3251 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3255 if(faststore_reg_override) a=faststore_reg_override;
3257 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3260 gen_tlb_addr_w(a,map);
3261 emit_writehword_indexed(tl,x,a);
3263 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3267 if (opcode[i]==0x2B) { // SW
3270 if(faststore_reg_override) a=faststore_reg_override;
3271 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3272 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3276 if (opcode[i]==0x3F) { // SD
3279 if(faststore_reg_override) a=faststore_reg_override;
3282 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3283 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3284 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3287 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3288 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3289 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3296 // PCSX store handlers don't check invcode again
3298 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3302 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))) {
3304 #ifdef DESTRUCTIVE_SHIFT
3305 // The x86 shift operation is 'destructive'; it overwrites the
3306 // source register, so we need to make a copy first and use that.
3309 #if defined(HOST_IMM8)
3310 int ir=get_reg(i_regs->regmap,INVCP);
3312 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3314 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3316 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3317 emit_callne(invalidate_addr_reg[addr]);
3321 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3326 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3327 } else if(c&&!memtarget) {
3328 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3330 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3331 //if(opcode[i]==0x2B || opcode[i]==0x28)
3332 //if(opcode[i]==0x2B || opcode[i]==0x29)
3333 //if(opcode[i]==0x2B)
3334 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3342 emit_readword((int)&last_count,ECX);
3344 if(get_reg(i_regs->regmap,CCREG)<0)
3345 emit_loadreg(CCREG,HOST_CCREG);
3346 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3347 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3348 emit_writeword(HOST_CCREG,(int)&Count);
3351 if(get_reg(i_regs->regmap,CCREG)<0)
3352 emit_loadreg(CCREG,0);
3354 emit_mov(HOST_CCREG,0);
3356 emit_addimm(0,2*ccadj[i],0);
3357 emit_writeword(0,(int)&Count);
3359 emit_call((int)memdebug);
3364 restore_regs(0x100f);
3369 void storelr_assemble(int i,struct regstat *i_regs)
3376 int case1,case2,case3;
3377 int done0,done1,done2;
3378 int memtarget=0,c=0;
3379 int agr=AGEN1+(i&1);
3381 th=get_reg(i_regs->regmap,rs2[i]|64);
3382 tl=get_reg(i_regs->regmap,rs2[i]);
3383 s=get_reg(i_regs->regmap,rs1[i]);
3384 temp=get_reg(i_regs->regmap,agr);
3385 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3388 c=(i_regs->isconst>>s)&1;
3390 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3391 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3395 for(hr=0;hr<HOST_REGS;hr++) {
3396 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3401 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3402 if(!offset&&s!=temp) emit_mov(s,temp);
3408 if(!memtarget||!rs1[i]) {
3414 int map=get_reg(i_regs->regmap,ROREG);
3415 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3416 gen_tlb_addr_w(temp,map);
3418 if((u_int)rdram!=0x80000000)
3419 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3422 int map=get_reg(i_regs->regmap,TLREG);
3425 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3426 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3427 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3428 if(!jaddr&&!memtarget) {
3432 gen_tlb_addr_w(temp,map);
3435 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3436 temp2=get_reg(i_regs->regmap,FTEMP);
3437 if(!rs2[i]) temp2=th=tl;
3440 #ifndef BIG_ENDIAN_MIPS
3441 emit_xorimm(temp,3,temp);
3443 emit_testimm(temp,2);
3446 emit_testimm(temp,1);
3450 if (opcode[i]==0x2A) { // SWL
3451 emit_writeword_indexed(tl,0,temp);
3453 if (opcode[i]==0x2E) { // SWR
3454 emit_writebyte_indexed(tl,3,temp);
3456 if (opcode[i]==0x2C) { // SDL
3457 emit_writeword_indexed(th,0,temp);
3458 if(rs2[i]) emit_mov(tl,temp2);
3460 if (opcode[i]==0x2D) { // SDR
3461 emit_writebyte_indexed(tl,3,temp);
3462 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3467 set_jump_target(case1,(int)out);
3468 if (opcode[i]==0x2A) { // SWL
3469 // Write 3 msb into three least significant bytes
3470 if(rs2[i]) emit_rorimm(tl,8,tl);
3471 emit_writehword_indexed(tl,-1,temp);
3472 if(rs2[i]) emit_rorimm(tl,16,tl);
3473 emit_writebyte_indexed(tl,1,temp);
3474 if(rs2[i]) emit_rorimm(tl,8,tl);
3476 if (opcode[i]==0x2E) { // SWR
3477 // Write two lsb into two most significant bytes
3478 emit_writehword_indexed(tl,1,temp);
3480 if (opcode[i]==0x2C) { // SDL
3481 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3482 // Write 3 msb into three least significant bytes
3483 if(rs2[i]) emit_rorimm(th,8,th);
3484 emit_writehword_indexed(th,-1,temp);
3485 if(rs2[i]) emit_rorimm(th,16,th);
3486 emit_writebyte_indexed(th,1,temp);
3487 if(rs2[i]) emit_rorimm(th,8,th);
3489 if (opcode[i]==0x2D) { // SDR
3490 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3491 // Write two lsb into two most significant bytes
3492 emit_writehword_indexed(tl,1,temp);
3497 set_jump_target(case2,(int)out);
3498 emit_testimm(temp,1);
3501 if (opcode[i]==0x2A) { // SWL
3502 // Write two msb into two least significant bytes
3503 if(rs2[i]) emit_rorimm(tl,16,tl);
3504 emit_writehword_indexed(tl,-2,temp);
3505 if(rs2[i]) emit_rorimm(tl,16,tl);
3507 if (opcode[i]==0x2E) { // SWR
3508 // Write 3 lsb into three most significant bytes
3509 emit_writebyte_indexed(tl,-1,temp);
3510 if(rs2[i]) emit_rorimm(tl,8,tl);
3511 emit_writehword_indexed(tl,0,temp);
3512 if(rs2[i]) emit_rorimm(tl,24,tl);
3514 if (opcode[i]==0x2C) { // SDL
3515 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3516 // Write two msb into two least significant bytes
3517 if(rs2[i]) emit_rorimm(th,16,th);
3518 emit_writehword_indexed(th,-2,temp);
3519 if(rs2[i]) emit_rorimm(th,16,th);
3521 if (opcode[i]==0x2D) { // SDR
3522 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3523 // Write 3 lsb into three most significant bytes
3524 emit_writebyte_indexed(tl,-1,temp);
3525 if(rs2[i]) emit_rorimm(tl,8,tl);
3526 emit_writehword_indexed(tl,0,temp);
3527 if(rs2[i]) emit_rorimm(tl,24,tl);
3532 set_jump_target(case3,(int)out);
3533 if (opcode[i]==0x2A) { // SWL
3534 // Write msb into least significant byte
3535 if(rs2[i]) emit_rorimm(tl,24,tl);
3536 emit_writebyte_indexed(tl,-3,temp);
3537 if(rs2[i]) emit_rorimm(tl,8,tl);
3539 if (opcode[i]==0x2E) { // SWR
3540 // Write entire word
3541 emit_writeword_indexed(tl,-3,temp);
3543 if (opcode[i]==0x2C) { // SDL
3544 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3545 // Write msb into least significant byte
3546 if(rs2[i]) emit_rorimm(th,24,th);
3547 emit_writebyte_indexed(th,-3,temp);
3548 if(rs2[i]) emit_rorimm(th,8,th);
3550 if (opcode[i]==0x2D) { // SDR
3551 if(rs2[i]) emit_mov(th,temp2);
3552 // Write entire word
3553 emit_writeword_indexed(tl,-3,temp);
3555 set_jump_target(done0,(int)out);
3556 set_jump_target(done1,(int)out);
3557 set_jump_target(done2,(int)out);
3558 if (opcode[i]==0x2C) { // SDL
3559 emit_testimm(temp,4);
3562 emit_andimm(temp,~3,temp);
3563 emit_writeword_indexed(temp2,4,temp);
3564 set_jump_target(done0,(int)out);
3566 if (opcode[i]==0x2D) { // SDR
3567 emit_testimm(temp,4);
3570 emit_andimm(temp,~3,temp);
3571 emit_writeword_indexed(temp2,-4,temp);
3572 set_jump_target(done0,(int)out);
3575 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3576 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))) {
3578 int map=get_reg(i_regs->regmap,ROREG);
3579 if(map<0) map=HOST_TEMPREG;
3580 gen_orig_addr_w(temp,map);
3582 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3584 #if defined(HOST_IMM8)
3585 int ir=get_reg(i_regs->regmap,INVCP);
3587 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3589 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3591 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3592 emit_callne(invalidate_addr_reg[temp]);
3596 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3601 //save_regs(0x100f);
3602 emit_readword((int)&last_count,ECX);
3603 if(get_reg(i_regs->regmap,CCREG)<0)
3604 emit_loadreg(CCREG,HOST_CCREG);
3605 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3606 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3607 emit_writeword(HOST_CCREG,(int)&Count);
3608 emit_call((int)memdebug);
3610 //restore_regs(0x100f);
3614 void c1ls_assemble(int i,struct regstat *i_regs)
3616 #ifndef DISABLE_COP1
3622 int jaddr,jaddr2=0,jaddr3,type;
3623 int agr=AGEN1+(i&1);
3625 th=get_reg(i_regs->regmap,FTEMP|64);
3626 tl=get_reg(i_regs->regmap,FTEMP);
3627 s=get_reg(i_regs->regmap,rs1[i]);
3628 temp=get_reg(i_regs->regmap,agr);
3629 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3634 for(hr=0;hr<HOST_REGS;hr++) {
3635 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3637 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3638 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3640 // Loads use a temporary register which we need to save
3643 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3647 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3648 //else c=(i_regs->wasconst>>s)&1;
3649 if(s>=0) c=(i_regs->wasconst>>s)&1;
3650 // Check cop1 unusable
3652 signed char rs=get_reg(i_regs->regmap,CSREG);
3654 emit_testimm(rs,0x20000000);
3657 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3660 if (opcode[i]==0x39) { // SWC1 (get float address)
3661 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3663 if (opcode[i]==0x3D) { // SDC1 (get double address)
3664 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3666 // Generate address + offset
3669 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3673 map=get_reg(i_regs->regmap,TLREG);
3676 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3677 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3679 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3680 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3683 if (opcode[i]==0x39) { // SWC1 (read float)
3684 emit_readword_indexed(0,tl,tl);
3686 if (opcode[i]==0x3D) { // SDC1 (read double)
3687 emit_readword_indexed(4,tl,th);
3688 emit_readword_indexed(0,tl,tl);
3690 if (opcode[i]==0x31) { // LWC1 (get target address)
3691 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3693 if (opcode[i]==0x35) { // LDC1 (get target address)
3694 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3701 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3703 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3705 #ifdef DESTRUCTIVE_SHIFT
3706 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3707 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3711 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3712 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3714 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3715 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3718 if (opcode[i]==0x31) { // LWC1
3719 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3720 //gen_tlb_addr_r(ar,map);
3721 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3722 #ifdef HOST_IMM_ADDR32
3723 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3726 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3729 if (opcode[i]==0x35) { // LDC1
3731 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3732 //gen_tlb_addr_r(ar,map);
3733 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3734 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3735 #ifdef HOST_IMM_ADDR32
3736 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3739 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3742 if (opcode[i]==0x39) { // SWC1
3743 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3744 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3747 if (opcode[i]==0x3D) { // SDC1
3749 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3750 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3751 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3754 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))) {
3755 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3756 #ifndef DESTRUCTIVE_SHIFT
3757 temp=offset||c||s<0?ar:s;
3759 #if defined(HOST_IMM8)
3760 int ir=get_reg(i_regs->regmap,INVCP);
3762 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3764 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3766 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3767 emit_callne(invalidate_addr_reg[temp]);
3771 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3775 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3776 if (opcode[i]==0x31) { // LWC1 (write float)
3777 emit_writeword_indexed(tl,0,temp);
3779 if (opcode[i]==0x35) { // LDC1 (write double)
3780 emit_writeword_indexed(th,4,temp);
3781 emit_writeword_indexed(tl,0,temp);
3783 //if(opcode[i]==0x39)
3784 /*if(opcode[i]==0x39||opcode[i]==0x31)
3787 emit_readword((int)&last_count,ECX);
3788 if(get_reg(i_regs->regmap,CCREG)<0)
3789 emit_loadreg(CCREG,HOST_CCREG);
3790 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3791 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3792 emit_writeword(HOST_CCREG,(int)&Count);
3793 emit_call((int)memdebug);
3797 cop1_unusable(i, i_regs);
3801 void c2ls_assemble(int i,struct regstat *i_regs)
3806 int memtarget=0,c=0;
3807 int jaddr2=0,jaddr3,type;
3808 int agr=AGEN1+(i&1);
3809 int fastio_reg_override=0;
3811 u_int copr=(source[i]>>16)&0x1f;
3812 s=get_reg(i_regs->regmap,rs1[i]);
3813 tl=get_reg(i_regs->regmap,FTEMP);
3819 for(hr=0;hr<HOST_REGS;hr++) {
3820 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3822 if(i_regs->regmap[HOST_CCREG]==CCREG)
3823 reglist&=~(1<<HOST_CCREG);
3826 if (opcode[i]==0x3a) { // SWC2
3827 ar=get_reg(i_regs->regmap,agr);
3828 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3833 if(s>=0) c=(i_regs->wasconst>>s)&1;
3834 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3835 if (!offset&&!c&&s>=0) ar=s;
3838 if (opcode[i]==0x3a) { // SWC2
3839 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3847 emit_jmp(0); // inline_readstub/inline_writestub?
3851 jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3853 if (opcode[i]==0x32) { // LWC2
3854 #ifdef HOST_IMM_ADDR32
3855 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3859 if(fastio_reg_override) a=fastio_reg_override;
3860 emit_readword_indexed(0,a,tl);
3862 if (opcode[i]==0x3a) { // SWC2
3863 #ifdef DESTRUCTIVE_SHIFT
3864 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3867 if(fastio_reg_override) a=fastio_reg_override;
3868 emit_writeword_indexed(tl,0,a);
3872 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3873 if (!(i_regs->waswritten&(1<<rs1[i]))&&opcode[i]==0x3a) { // SWC2
3874 #if defined(HOST_IMM8)
3875 int ir=get_reg(i_regs->regmap,INVCP);
3877 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3879 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3881 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3882 emit_callne(invalidate_addr_reg[ar]);
3886 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3889 if (opcode[i]==0x32) { // LWC2
3890 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3894 #ifndef multdiv_assemble
3895 void multdiv_assemble(int i,struct regstat *i_regs)
3897 printf("Need multdiv_assemble for this architecture.\n");
3902 void mov_assemble(int i,struct regstat *i_regs)
3904 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3905 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3907 signed char sh,sl,th,tl;
3908 th=get_reg(i_regs->regmap,rt1[i]|64);
3909 tl=get_reg(i_regs->regmap,rt1[i]);
3912 sh=get_reg(i_regs->regmap,rs1[i]|64);
3913 sl=get_reg(i_regs->regmap,rs1[i]);
3914 if(sl>=0) emit_mov(sl,tl);
3915 else emit_loadreg(rs1[i],tl);
3917 if(sh>=0) emit_mov(sh,th);
3918 else emit_loadreg(rs1[i]|64,th);
3924 #ifndef fconv_assemble
3925 void fconv_assemble(int i,struct regstat *i_regs)
3927 printf("Need fconv_assemble for this architecture.\n");
3933 void float_assemble(int i,struct regstat *i_regs)
3935 printf("Need float_assemble for this architecture.\n");
3940 void syscall_assemble(int i,struct regstat *i_regs)
3942 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3943 assert(ccreg==HOST_CCREG);
3944 assert(!is_delayslot);
3945 emit_movimm(start+i*4,EAX); // Get PC
3946 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3947 emit_jmp((int)jump_syscall_hle); // XXX
3950 void hlecall_assemble(int i,struct regstat *i_regs)
3952 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3953 assert(ccreg==HOST_CCREG);
3954 assert(!is_delayslot);
3955 emit_movimm(start+i*4+4,0); // Get PC
3956 emit_movimm((int)psxHLEt[source[i]&7],1);
3957 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
3958 emit_jmp((int)jump_hlecall);
3961 void intcall_assemble(int i,struct regstat *i_regs)
3963 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3964 assert(ccreg==HOST_CCREG);
3965 assert(!is_delayslot);
3966 emit_movimm(start+i*4,0); // Get PC
3967 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3968 emit_jmp((int)jump_intcall);
3971 void ds_assemble(int i,struct regstat *i_regs)
3973 speculate_register_values(i);
3977 alu_assemble(i,i_regs);break;
3979 imm16_assemble(i,i_regs);break;
3981 shift_assemble(i,i_regs);break;
3983 shiftimm_assemble(i,i_regs);break;
3985 load_assemble(i,i_regs);break;
3987 loadlr_assemble(i,i_regs);break;
3989 store_assemble(i,i_regs);break;
3991 storelr_assemble(i,i_regs);break;
3993 cop0_assemble(i,i_regs);break;
3995 cop1_assemble(i,i_regs);break;
3997 c1ls_assemble(i,i_regs);break;
3999 cop2_assemble(i,i_regs);break;
4001 c2ls_assemble(i,i_regs);break;
4003 c2op_assemble(i,i_regs);break;
4005 fconv_assemble(i,i_regs);break;
4007 float_assemble(i,i_regs);break;
4009 fcomp_assemble(i,i_regs);break;
4011 multdiv_assemble(i,i_regs);break;
4013 mov_assemble(i,i_regs);break;
4023 printf("Jump in the delay slot. This is probably a bug.\n");
4028 // Is the branch target a valid internal jump?
4029 int internal_branch(uint64_t i_is32,int addr)
4031 if(addr&1) return 0; // Indirect (register) jump
4032 if(addr>=start && addr<start+slen*4-4)
4034 int t=(addr-start)>>2;
4035 // Delay slots are not valid branch targets
4036 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4037 // 64 -> 32 bit transition requires a recompile
4038 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4040 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4041 else printf("optimizable: yes\n");
4043 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4045 if(requires_32bit[t]&~i_is32) return 0;
4053 #ifndef wb_invalidate
4054 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4055 uint64_t u,uint64_t uu)
4058 for(hr=0;hr<HOST_REGS;hr++) {
4059 if(hr!=EXCLUDE_REG) {
4060 if(pre[hr]!=entry[hr]) {
4063 if(get_reg(entry,pre[hr])<0) {
4065 if(!((u>>pre[hr])&1)) {
4066 emit_storereg(pre[hr],hr);
4067 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4068 emit_sarimm(hr,31,hr);
4069 emit_storereg(pre[hr]|64,hr);
4073 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4074 emit_storereg(pre[hr],hr);
4083 // Move from one register to another (no writeback)
4084 for(hr=0;hr<HOST_REGS;hr++) {
4085 if(hr!=EXCLUDE_REG) {
4086 if(pre[hr]!=entry[hr]) {
4087 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4089 if((nr=get_reg(entry,pre[hr]))>=0) {
4099 // Load the specified registers
4100 // This only loads the registers given as arguments because
4101 // we don't want to load things that will be overwritten
4102 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4106 for(hr=0;hr<HOST_REGS;hr++) {
4107 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4108 if(entry[hr]!=regmap[hr]) {
4109 if(regmap[hr]==rs1||regmap[hr]==rs2)
4116 emit_loadreg(regmap[hr],hr);
4123 for(hr=0;hr<HOST_REGS;hr++) {
4124 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4125 if(entry[hr]!=regmap[hr]) {
4126 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4128 assert(regmap[hr]!=64);
4129 if((is32>>(regmap[hr]&63))&1) {
4130 int lr=get_reg(regmap,regmap[hr]-64);
4132 emit_sarimm(lr,31,hr);
4134 emit_loadreg(regmap[hr],hr);
4138 emit_loadreg(regmap[hr],hr);
4146 // Load registers prior to the start of a loop
4147 // so that they are not loaded within the loop
4148 static void loop_preload(signed char pre[],signed char entry[])
4151 for(hr=0;hr<HOST_REGS;hr++) {
4152 if(hr!=EXCLUDE_REG) {
4153 if(pre[hr]!=entry[hr]) {
4155 if(get_reg(pre,entry[hr])<0) {
4156 assem_debug("loop preload:\n");
4157 //printf("loop preload: %d\n",hr);
4161 else if(entry[hr]<TEMPREG)
4163 emit_loadreg(entry[hr],hr);
4165 else if(entry[hr]-64<TEMPREG)
4167 emit_loadreg(entry[hr],hr);
4176 // Generate address for load/store instruction
4177 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4178 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4180 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4182 int agr=AGEN1+(i&1);
4183 int mgr=MGEN1+(i&1);
4184 if(itype[i]==LOAD) {
4185 ra=get_reg(i_regs->regmap,rt1[i]);
4186 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4189 if(itype[i]==LOADLR) {
4190 ra=get_reg(i_regs->regmap,FTEMP);
4192 if(itype[i]==STORE||itype[i]==STORELR) {
4193 ra=get_reg(i_regs->regmap,agr);
4194 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4196 if(itype[i]==C1LS||itype[i]==C2LS) {
4197 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4198 ra=get_reg(i_regs->regmap,FTEMP);
4199 else { // SWC1/SDC1/SWC2/SDC2
4200 ra=get_reg(i_regs->regmap,agr);
4201 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4204 int rs=get_reg(i_regs->regmap,rs1[i]);
4205 int rm=get_reg(i_regs->regmap,TLREG);
4208 int c=(i_regs->wasconst>>rs)&1;
4210 // Using r0 as a base address
4212 if(!entry||entry[rm]!=mgr) {
4213 generate_map_const(offset,rm);
4214 } // else did it in the previous cycle
4216 if(!entry||entry[ra]!=agr) {
4217 if (opcode[i]==0x22||opcode[i]==0x26) {
4218 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4219 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4220 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4222 emit_movimm(offset,ra);
4224 } // else did it in the previous cycle
4227 if(!entry||entry[ra]!=rs1[i])
4228 emit_loadreg(rs1[i],ra);
4229 //if(!entry||entry[ra]!=rs1[i])
4230 // printf("poor load scheduling!\n");
4235 if(!entry||entry[rm]!=mgr) {
4236 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4237 // Stores to memory go thru the mapper to detect self-modifying
4238 // code, loads don't.
4239 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4240 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4241 generate_map_const(constmap[i][rs]+offset,rm);
4243 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4244 generate_map_const(constmap[i][rs]+offset,rm);
4249 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4250 if(!entry||entry[ra]!=agr) {
4251 if (opcode[i]==0x22||opcode[i]==0x26) {
4252 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4253 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4254 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4256 #ifdef HOST_IMM_ADDR32
4257 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4258 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4260 emit_movimm(constmap[i][rs]+offset,ra);
4262 } // else did it in the previous cycle
4263 } // else load_consts already did it
4265 if(offset&&!c&&rs1[i]) {
4267 emit_addimm(rs,offset,ra);
4269 emit_addimm(ra,offset,ra);
4274 // Preload constants for next instruction
4275 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4277 #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
4279 agr=MGEN1+((i+1)&1);
4280 ra=get_reg(i_regs->regmap,agr);
4282 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4283 int offset=imm[i+1];
4284 int c=(regs[i+1].wasconst>>rs)&1;
4286 if(itype[i+1]==STORE||itype[i+1]==STORELR
4287 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4288 // Stores to memory go thru the mapper to detect self-modifying
4289 // code, loads don't.
4290 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4291 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4292 generate_map_const(constmap[i+1][rs]+offset,ra);
4294 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4295 generate_map_const(constmap[i+1][rs]+offset,ra);
4298 /*else if(rs1[i]==0) {
4299 generate_map_const(offset,ra);
4304 agr=AGEN1+((i+1)&1);
4305 ra=get_reg(i_regs->regmap,agr);
4307 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4308 int offset=imm[i+1];
4309 int c=(regs[i+1].wasconst>>rs)&1;
4310 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4311 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4312 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4313 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4314 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4316 #ifdef HOST_IMM_ADDR32
4317 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4318 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4320 emit_movimm(constmap[i+1][rs]+offset,ra);
4323 else if(rs1[i+1]==0) {
4324 // Using r0 as a base address
4325 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4326 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4327 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4328 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4330 emit_movimm(offset,ra);
4337 int get_final_value(int hr, int i, int *value)
4339 int reg=regs[i].regmap[hr];
4341 if(regs[i+1].regmap[hr]!=reg) break;
4342 if(!((regs[i+1].isconst>>hr)&1)) break;
4347 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4348 *value=constmap[i][hr];
4352 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4353 // Load in delay slot, out-of-order execution
4354 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4356 #ifdef HOST_IMM_ADDR32
4357 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4359 // Precompute load address
4360 *value=constmap[i][hr]+imm[i+2];
4364 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4366 #ifdef HOST_IMM_ADDR32
4367 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4369 // Precompute load address
4370 *value=constmap[i][hr]+imm[i+1];
4371 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4376 *value=constmap[i][hr];
4377 //printf("c=%x\n",(int)constmap[i][hr]);
4378 if(i==slen-1) return 1;
4380 return !((unneeded_reg[i+1]>>reg)&1);
4382 return !((unneeded_reg_upper[i+1]>>reg)&1);
4386 // Load registers with known constants
4387 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4391 for(hr=0;hr<HOST_REGS;hr++) {
4392 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4393 //if(entry[hr]!=regmap[hr]) {
4394 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4395 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4397 if(get_final_value(hr,i,&value)) {
4402 emit_movimm(value,hr);
4410 for(hr=0;hr<HOST_REGS;hr++) {
4411 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4412 //if(entry[hr]!=regmap[hr]) {
4413 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4414 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4415 if((is32>>(regmap[hr]&63))&1) {
4416 int lr=get_reg(regmap,regmap[hr]-64);
4418 emit_sarimm(lr,31,hr);
4423 if(get_final_value(hr,i,&value)) {
4428 emit_movimm(value,hr);
4437 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4441 for(hr=0;hr<HOST_REGS;hr++) {
4442 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4443 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4444 int value=constmap[i][hr];
4449 emit_movimm(value,hr);
4455 for(hr=0;hr<HOST_REGS;hr++) {
4456 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4457 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4458 if((is32>>(regmap[hr]&63))&1) {
4459 int lr=get_reg(regmap,regmap[hr]-64);
4461 emit_sarimm(lr,31,hr);
4465 int value=constmap[i][hr];
4470 emit_movimm(value,hr);
4478 // Write out all dirty registers (except cycle count)
4479 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4482 for(hr=0;hr<HOST_REGS;hr++) {
4483 if(hr!=EXCLUDE_REG) {
4484 if(i_regmap[hr]>0) {
4485 if(i_regmap[hr]!=CCREG) {
4486 if((i_dirty>>hr)&1) {
4487 if(i_regmap[hr]<64) {
4488 emit_storereg(i_regmap[hr],hr);
4490 if( ((i_is32>>i_regmap[hr])&1) ) {
4491 #ifdef DESTRUCTIVE_WRITEBACK
4492 emit_sarimm(hr,31,hr);
4493 emit_storereg(i_regmap[hr]|64,hr);
4495 emit_sarimm(hr,31,HOST_TEMPREG);
4496 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4501 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4502 emit_storereg(i_regmap[hr],hr);
4511 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4512 // This writes the registers not written by store_regs_bt
4513 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4516 int t=(addr-start)>>2;
4517 for(hr=0;hr<HOST_REGS;hr++) {
4518 if(hr!=EXCLUDE_REG) {
4519 if(i_regmap[hr]>0) {
4520 if(i_regmap[hr]!=CCREG) {
4521 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4522 if((i_dirty>>hr)&1) {
4523 if(i_regmap[hr]<64) {
4524 emit_storereg(i_regmap[hr],hr);
4526 if( ((i_is32>>i_regmap[hr])&1) ) {
4527 #ifdef DESTRUCTIVE_WRITEBACK
4528 emit_sarimm(hr,31,hr);
4529 emit_storereg(i_regmap[hr]|64,hr);
4531 emit_sarimm(hr,31,HOST_TEMPREG);
4532 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4537 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4538 emit_storereg(i_regmap[hr],hr);
4549 // Load all registers (except cycle count)
4550 void load_all_regs(signed char i_regmap[])
4553 for(hr=0;hr<HOST_REGS;hr++) {
4554 if(hr!=EXCLUDE_REG) {
4555 if(i_regmap[hr]==0) {
4559 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4561 emit_loadreg(i_regmap[hr],hr);
4567 // Load all current registers also needed by next instruction
4568 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4571 for(hr=0;hr<HOST_REGS;hr++) {
4572 if(hr!=EXCLUDE_REG) {
4573 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4574 if(i_regmap[hr]==0) {
4578 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4580 emit_loadreg(i_regmap[hr],hr);
4587 // Load all regs, storing cycle count if necessary
4588 void load_regs_entry(int t)
4591 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4592 else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4593 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4594 emit_storereg(CCREG,HOST_CCREG);
4597 for(hr=0;hr<HOST_REGS;hr++) {
4598 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4599 if(regs[t].regmap_entry[hr]==0) {
4602 else if(regs[t].regmap_entry[hr]!=CCREG)
4604 emit_loadreg(regs[t].regmap_entry[hr],hr);
4609 for(hr=0;hr<HOST_REGS;hr++) {
4610 if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4611 assert(regs[t].regmap_entry[hr]!=64);
4612 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4613 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4615 emit_loadreg(regs[t].regmap_entry[hr],hr);
4619 emit_sarimm(lr,31,hr);
4624 emit_loadreg(regs[t].regmap_entry[hr],hr);
4630 // Store dirty registers prior to branch
4631 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4633 if(internal_branch(i_is32,addr))
4635 int t=(addr-start)>>2;
4637 for(hr=0;hr<HOST_REGS;hr++) {
4638 if(hr!=EXCLUDE_REG) {
4639 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4640 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4641 if((i_dirty>>hr)&1) {
4642 if(i_regmap[hr]<64) {
4643 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4644 emit_storereg(i_regmap[hr],hr);
4645 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4646 #ifdef DESTRUCTIVE_WRITEBACK
4647 emit_sarimm(hr,31,hr);
4648 emit_storereg(i_regmap[hr]|64,hr);
4650 emit_sarimm(hr,31,HOST_TEMPREG);
4651 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4656 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4657 emit_storereg(i_regmap[hr],hr);
4668 // Branch out of this block, write out all dirty regs
4669 wb_dirtys(i_regmap,i_is32,i_dirty);
4673 // Load all needed registers for branch target
4674 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4676 //if(addr>=start && addr<(start+slen*4))
4677 if(internal_branch(i_is32,addr))
4679 int t=(addr-start)>>2;
4681 // Store the cycle count before loading something else
4682 if(i_regmap[HOST_CCREG]!=CCREG) {
4683 assert(i_regmap[HOST_CCREG]==-1);
4685 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4686 emit_storereg(CCREG,HOST_CCREG);
4689 for(hr=0;hr<HOST_REGS;hr++) {
4690 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4691 #ifdef DESTRUCTIVE_WRITEBACK
4692 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4694 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4696 if(regs[t].regmap_entry[hr]==0) {
4699 else if(regs[t].regmap_entry[hr]!=CCREG)
4701 emit_loadreg(regs[t].regmap_entry[hr],hr);
4707 for(hr=0;hr<HOST_REGS;hr++) {
4708 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4709 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4710 assert(regs[t].regmap_entry[hr]!=64);
4711 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4712 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4714 emit_loadreg(regs[t].regmap_entry[hr],hr);
4718 emit_sarimm(lr,31,hr);
4723 emit_loadreg(regs[t].regmap_entry[hr],hr);
4726 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4727 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4729 emit_sarimm(lr,31,hr);
4736 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4738 if(addr>=start && addr<start+slen*4-4)
4740 int t=(addr-start)>>2;
4742 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4743 for(hr=0;hr<HOST_REGS;hr++)
4747 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4749 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4756 if(i_regmap[hr]<TEMPREG)
4758 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4761 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4763 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4768 else // Same register but is it 32-bit or dirty?
4771 if(!((regs[t].dirty>>hr)&1))
4775 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4777 //printf("%x: dirty no match\n",addr);
4782 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4784 //printf("%x: is32 no match\n",addr);
4790 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4792 if(requires_32bit[t]&~i_is32) return 0;
4794 // Delay slots are not valid branch targets
4795 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4796 // Delay slots require additional processing, so do not match
4797 if(is_ds[t]) return 0;
4802 for(hr=0;hr<HOST_REGS;hr++)
4808 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4822 // Used when a branch jumps into the delay slot of another branch
4823 void ds_assemble_entry(int i)
4825 int t=(ba[i]-start)>>2;
4826 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4827 assem_debug("Assemble delay slot at %x\n",ba[i]);
4828 assem_debug("<->\n");
4829 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4830 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4831 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4832 address_generation(t,®s[t],regs[t].regmap_entry);
4833 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4834 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4839 alu_assemble(t,®s[t]);break;
4841 imm16_assemble(t,®s[t]);break;
4843 shift_assemble(t,®s[t]);break;
4845 shiftimm_assemble(t,®s[t]);break;
4847 load_assemble(t,®s[t]);break;
4849 loadlr_assemble(t,®s[t]);break;
4851 store_assemble(t,®s[t]);break;
4853 storelr_assemble(t,®s[t]);break;
4855 cop0_assemble(t,®s[t]);break;
4857 cop1_assemble(t,®s[t]);break;
4859 c1ls_assemble(t,®s[t]);break;
4861 cop2_assemble(t,®s[t]);break;
4863 c2ls_assemble(t,®s[t]);break;
4865 c2op_assemble(t,®s[t]);break;
4867 fconv_assemble(t,®s[t]);break;
4869 float_assemble(t,®s[t]);break;
4871 fcomp_assemble(t,®s[t]);break;
4873 multdiv_assemble(t,®s[t]);break;
4875 mov_assemble(t,®s[t]);break;
4885 printf("Jump in the delay slot. This is probably a bug.\n");
4887 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4888 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4889 if(internal_branch(regs[t].is32,ba[i]+4))
4890 assem_debug("branch: internal\n");
4892 assem_debug("branch: external\n");
4893 assert(internal_branch(regs[t].is32,ba[i]+4));
4894 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4898 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4907 //if(ba[i]>=start && ba[i]<(start+slen*4))
4908 if(internal_branch(branch_regs[i].is32,ba[i]))
4910 int t=(ba[i]-start)>>2;
4911 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4919 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4921 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4923 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4924 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4928 else if(*adj==0||invert) {
4929 emit_addimm_and_set_flags(CLOCK_ADJUST(count+2),HOST_CCREG);
4935 emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
4939 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4942 void do_ccstub(int n)
4945 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4946 set_jump_target(stubs[n][1],(int)out);
4948 if(stubs[n][6]==NULLDS) {
4949 // Delay slot instruction is nullified ("likely" branch)
4950 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4952 else if(stubs[n][6]!=TAKEN) {
4953 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4956 if(internal_branch(branch_regs[i].is32,ba[i]))
4957 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4961 // Save PC as return address
4962 emit_movimm(stubs[n][5],EAX);
4963 emit_writeword(EAX,(int)&pcaddr);
4967 // Return address depends on which way the branch goes
4968 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4970 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4971 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4972 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4973 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4983 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4987 #ifdef DESTRUCTIVE_WRITEBACK
4989 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4990 emit_loadreg(rs1[i],s1l);
4993 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4994 emit_loadreg(rs2[i],s1l);
4997 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4998 emit_loadreg(rs2[i],s2l);
5001 int addr=-1,alt=-1,ntaddr=-1;
5004 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5005 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5006 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5014 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5015 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5016 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5022 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5026 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5027 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5028 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5034 assert(hr<HOST_REGS);
5036 if((opcode[i]&0x2f)==4) // BEQ
5038 #ifdef HAVE_CMOV_IMM
5040 if(s2l>=0) emit_cmp(s1l,s2l);
5041 else emit_test(s1l,s1l);
5042 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5047 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5049 if(s2h>=0) emit_cmp(s1h,s2h);
5050 else emit_test(s1h,s1h);
5051 emit_cmovne_reg(alt,addr);
5053 if(s2l>=0) emit_cmp(s1l,s2l);
5054 else emit_test(s1l,s1l);
5055 emit_cmovne_reg(alt,addr);
5058 if((opcode[i]&0x2f)==5) // BNE
5060 #ifdef HAVE_CMOV_IMM
5062 if(s2l>=0) emit_cmp(s1l,s2l);
5063 else emit_test(s1l,s1l);
5064 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5069 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5071 if(s2h>=0) emit_cmp(s1h,s2h);
5072 else emit_test(s1h,s1h);
5073 emit_cmovne_reg(alt,addr);
5075 if(s2l>=0) emit_cmp(s1l,s2l);
5076 else emit_test(s1l,s1l);
5077 emit_cmovne_reg(alt,addr);
5080 if((opcode[i]&0x2f)==6) // BLEZ
5082 //emit_movimm(ba[i],alt);
5083 //emit_movimm(start+i*4+8,addr);
5084 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5086 if(s1h>=0) emit_mov(addr,ntaddr);
5087 emit_cmovl_reg(alt,addr);
5090 emit_cmovne_reg(ntaddr,addr);
5091 emit_cmovs_reg(alt,addr);
5094 if((opcode[i]&0x2f)==7) // BGTZ
5096 //emit_movimm(ba[i],addr);
5097 //emit_movimm(start+i*4+8,ntaddr);
5098 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5100 if(s1h>=0) emit_mov(addr,alt);
5101 emit_cmovl_reg(ntaddr,addr);
5104 emit_cmovne_reg(alt,addr);
5105 emit_cmovs_reg(ntaddr,addr);
5108 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5110 //emit_movimm(ba[i],alt);
5111 //emit_movimm(start+i*4+8,addr);
5112 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5113 if(s1h>=0) emit_test(s1h,s1h);
5114 else emit_test(s1l,s1l);
5115 emit_cmovs_reg(alt,addr);
5117 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5119 //emit_movimm(ba[i],addr);
5120 //emit_movimm(start+i*4+8,alt);
5121 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5122 if(s1h>=0) emit_test(s1h,s1h);
5123 else emit_test(s1l,s1l);
5124 emit_cmovs_reg(alt,addr);
5126 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5127 if(source[i]&0x10000) // BC1T
5129 //emit_movimm(ba[i],alt);
5130 //emit_movimm(start+i*4+8,addr);
5131 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5132 emit_testimm(s1l,0x800000);
5133 emit_cmovne_reg(alt,addr);
5137 //emit_movimm(ba[i],addr);
5138 //emit_movimm(start+i*4+8,alt);
5139 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5140 emit_testimm(s1l,0x800000);
5141 emit_cmovne_reg(alt,addr);
5144 emit_writeword(addr,(int)&pcaddr);
5149 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5150 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5151 r=get_reg(branch_regs[i].regmap,RTEMP);
5153 emit_writeword(r,(int)&pcaddr);
5155 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5157 // Update cycle count
5158 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5159 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5160 emit_call((int)cc_interrupt);
5161 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5162 if(stubs[n][6]==TAKEN) {
5163 if(internal_branch(branch_regs[i].is32,ba[i]))
5164 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5165 else if(itype[i]==RJUMP) {
5166 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5167 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5169 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5171 }else if(stubs[n][6]==NOTTAKEN) {
5172 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5173 else load_all_regs(branch_regs[i].regmap);
5174 }else if(stubs[n][6]==NULLDS) {
5175 // Delay slot instruction is nullified ("likely" branch)
5176 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5177 else load_all_regs(regs[i].regmap);
5179 load_all_regs(branch_regs[i].regmap);
5181 emit_jmp(stubs[n][2]); // return address
5183 /* This works but uses a lot of memory...
5184 emit_readword((int)&last_count,ECX);
5185 emit_add(HOST_CCREG,ECX,EAX);
5186 emit_writeword(EAX,(int)&Count);
5187 emit_call((int)gen_interupt);
5188 emit_readword((int)&Count,HOST_CCREG);
5189 emit_readword((int)&next_interupt,EAX);
5190 emit_readword((int)&pending_exception,EBX);
5191 emit_writeword(EAX,(int)&last_count);
5192 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5194 int jne_instr=(int)out;
5196 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5197 load_all_regs(branch_regs[i].regmap);
5198 emit_jmp(stubs[n][2]); // return address
5199 set_jump_target(jne_instr,(int)out);
5200 emit_readword((int)&pcaddr,EAX);
5201 // Call get_addr_ht instead of doing the hash table here.
5202 // This code is executed infrequently and takes up a lot of space
5203 // so smaller is better.
5204 emit_storereg(CCREG,HOST_CCREG);
5206 emit_call((int)get_addr_ht);
5207 emit_loadreg(CCREG,HOST_CCREG);
5208 emit_addimm(ESP,4,ESP);
5212 add_to_linker(int addr,int target,int ext)
5214 link_addr[linkcount][0]=addr;
5215 link_addr[linkcount][1]=target;
5216 link_addr[linkcount][2]=ext;
5220 static void ujump_assemble_write_ra(int i)
5223 unsigned int return_address;
5224 rt=get_reg(branch_regs[i].regmap,31);
5225 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5227 return_address=start+i*4+8;
5230 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5231 int temp=-1; // note: must be ds-safe
5235 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5236 else emit_movimm(return_address,rt);
5244 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5247 emit_movimm(return_address,rt); // PC into link register
5249 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5255 void ujump_assemble(int i,struct regstat *i_regs)
5257 signed char *i_regmap=i_regs->regmap;
5259 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5260 address_generation(i+1,i_regs,regs[i].regmap_entry);
5262 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5263 if(rt1[i]==31&&temp>=0)
5265 int return_address=start+i*4+8;
5266 if(get_reg(branch_regs[i].regmap,31)>0)
5267 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5270 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5271 ujump_assemble_write_ra(i); // writeback ra for DS
5274 ds_assemble(i+1,i_regs);
5275 uint64_t bc_unneeded=branch_regs[i].u;
5276 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5277 bc_unneeded|=1|(1LL<<rt1[i]);
5278 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5279 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5280 bc_unneeded,bc_unneeded_upper);
5281 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5282 if(!ra_done&&rt1[i]==31)
5283 ujump_assemble_write_ra(i);
5285 cc=get_reg(branch_regs[i].regmap,CCREG);
5286 assert(cc==HOST_CCREG);
5287 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5289 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5291 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5292 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5293 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5294 if(internal_branch(branch_regs[i].is32,ba[i]))
5295 assem_debug("branch: internal\n");
5297 assem_debug("branch: external\n");
5298 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5299 ds_assemble_entry(i);
5302 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5307 static void rjump_assemble_write_ra(int i)
5309 int rt,return_address;
5310 assert(rt1[i+1]!=rt1[i]);
5311 assert(rt2[i+1]!=rt1[i]);
5312 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5313 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5315 return_address=start+i*4+8;
5319 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5322 emit_movimm(return_address,rt); // PC into link register
5324 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5328 void rjump_assemble(int i,struct regstat *i_regs)
5330 signed char *i_regmap=i_regs->regmap;
5334 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5336 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5337 // Delay slot abuse, make a copy of the branch address register
5338 temp=get_reg(branch_regs[i].regmap,RTEMP);
5340 assert(regs[i].regmap[temp]==RTEMP);
5344 address_generation(i+1,i_regs,regs[i].regmap_entry);
5348 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5349 int return_address=start+i*4+8;
5350 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5356 int rh=get_reg(regs[i].regmap,RHASH);
5357 if(rh>=0) do_preload_rhash(rh);
5360 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5361 rjump_assemble_write_ra(i);
5364 ds_assemble(i+1,i_regs);
5365 uint64_t bc_unneeded=branch_regs[i].u;
5366 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5367 bc_unneeded|=1|(1LL<<rt1[i]);
5368 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5369 bc_unneeded&=~(1LL<<rs1[i]);
5370 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5371 bc_unneeded,bc_unneeded_upper);
5372 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5373 if(!ra_done&&rt1[i]!=0)
5374 rjump_assemble_write_ra(i);
5375 cc=get_reg(branch_regs[i].regmap,CCREG);
5376 assert(cc==HOST_CCREG);
5378 int rh=get_reg(branch_regs[i].regmap,RHASH);
5379 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5381 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5382 do_preload_rhtbl(ht);
5386 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5387 #ifdef DESTRUCTIVE_WRITEBACK
5388 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5389 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5390 emit_loadreg(rs1[i],rs);
5395 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5399 do_miniht_load(ht,rh);
5402 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5403 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5405 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5406 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5408 if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
5409 // special case for RFE
5414 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5417 do_miniht_jump(rs,rh,ht);
5422 //if(rs!=EAX) emit_mov(rs,EAX);
5423 //emit_jmp((int)jump_vaddr_eax);
5424 emit_jmp(jump_vaddr_reg[rs]);
5429 emit_shrimm(rs,16,rs);
5430 emit_xor(temp,rs,rs);
5431 emit_movzwl_reg(rs,rs);
5432 emit_shlimm(rs,4,rs);
5433 emit_cmpmem_indexed((int)hash_table,rs,temp);
5434 emit_jne((int)out+14);
5435 emit_readword_indexed((int)hash_table+4,rs,rs);
5437 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5438 emit_addimm_no_flags(8,rs);
5439 emit_jeq((int)out-17);
5440 // No hit on hash table, call compiler
5443 #ifdef DEBUG_CYCLE_COUNT
5444 emit_readword((int)&last_count,ECX);
5445 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5446 emit_readword((int)&next_interupt,ECX);
5447 emit_writeword(HOST_CCREG,(int)&Count);
5448 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5449 emit_writeword(ECX,(int)&last_count);
5452 emit_storereg(CCREG,HOST_CCREG);
5453 emit_call((int)get_addr);
5454 emit_loadreg(CCREG,HOST_CCREG);
5455 emit_addimm(ESP,4,ESP);
5457 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5458 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5462 void cjump_assemble(int i,struct regstat *i_regs)
5464 signed char *i_regmap=i_regs->regmap;
5467 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5468 assem_debug("match=%d\n",match);
5469 int s1h,s1l,s2h,s2l;
5470 int prev_cop1_usable=cop1_usable;
5471 int unconditional=0,nop=0;
5474 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5475 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5476 if(!match) invert=1;
5477 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5478 if(i>(ba[i]-start)>>2) invert=1;
5482 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5483 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5484 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5485 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5488 s1l=get_reg(i_regmap,rs1[i]);
5489 s1h=get_reg(i_regmap,rs1[i]|64);
5490 s2l=get_reg(i_regmap,rs2[i]);
5491 s2h=get_reg(i_regmap,rs2[i]|64);
5493 if(rs1[i]==0&&rs2[i]==0)
5495 if(opcode[i]&1) nop=1;
5496 else unconditional=1;
5497 //assert(opcode[i]!=5);
5498 //assert(opcode[i]!=7);
5499 //assert(opcode[i]!=0x15);
5500 //assert(opcode[i]!=0x17);
5506 only32=(regs[i].was32>>rs2[i])&1;
5511 only32=(regs[i].was32>>rs1[i])&1;
5514 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5518 // Out of order execution (delay slot first)
5520 address_generation(i+1,i_regs,regs[i].regmap_entry);
5521 ds_assemble(i+1,i_regs);
5523 uint64_t bc_unneeded=branch_regs[i].u;
5524 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5525 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5526 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5528 bc_unneeded_upper|=1;
5529 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5530 bc_unneeded,bc_unneeded_upper);
5531 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5532 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5533 cc=get_reg(branch_regs[i].regmap,CCREG);
5534 assert(cc==HOST_CCREG);
5536 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5537 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5538 //assem_debug("cycle count (adj)\n");
5540 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5541 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5542 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5543 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5545 assem_debug("branch: internal\n");
5547 assem_debug("branch: external\n");
5548 if(internal&&is_ds[(ba[i]-start)>>2]) {
5549 ds_assemble_entry(i);
5552 add_to_linker((int)out,ba[i],internal);
5555 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5556 if(((u_int)out)&7) emit_addnop(0);
5561 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5564 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5567 int taken=0,nottaken=0,nottaken1=0;
5568 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5569 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5573 if(opcode[i]==4) // BEQ
5575 if(s2h>=0) emit_cmp(s1h,s2h);
5576 else emit_test(s1h,s1h);
5580 if(opcode[i]==5) // BNE
5582 if(s2h>=0) emit_cmp(s1h,s2h);
5583 else emit_test(s1h,s1h);
5584 if(invert) taken=(int)out;
5585 else add_to_linker((int)out,ba[i],internal);
5588 if(opcode[i]==6) // BLEZ
5591 if(invert) taken=(int)out;
5592 else add_to_linker((int)out,ba[i],internal);
5597 if(opcode[i]==7) // BGTZ
5602 if(invert) taken=(int)out;
5603 else add_to_linker((int)out,ba[i],internal);
5608 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5610 if(opcode[i]==4) // BEQ
5612 if(s2l>=0) emit_cmp(s1l,s2l);
5613 else emit_test(s1l,s1l);
5618 add_to_linker((int)out,ba[i],internal);
5622 if(opcode[i]==5) // BNE
5624 if(s2l>=0) emit_cmp(s1l,s2l);
5625 else emit_test(s1l,s1l);
5630 add_to_linker((int)out,ba[i],internal);
5634 if(opcode[i]==6) // BLEZ
5641 add_to_linker((int)out,ba[i],internal);
5645 if(opcode[i]==7) // BGTZ
5652 add_to_linker((int)out,ba[i],internal);
5657 if(taken) set_jump_target(taken,(int)out);
5658 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5659 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5661 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5662 add_to_linker((int)out,ba[i],internal);
5665 add_to_linker((int)out,ba[i],internal*2);
5671 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5672 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5673 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5675 assem_debug("branch: internal\n");
5677 assem_debug("branch: external\n");
5678 if(internal&&is_ds[(ba[i]-start)>>2]) {
5679 ds_assemble_entry(i);
5682 add_to_linker((int)out,ba[i],internal);
5686 set_jump_target(nottaken,(int)out);
5689 if(nottaken1) set_jump_target(nottaken1,(int)out);
5691 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5693 } // (!unconditional)
5697 // In-order execution (branch first)
5698 //if(likely[i]) printf("IOL\n");
5701 int taken=0,nottaken=0,nottaken1=0;
5702 if(!unconditional&&!nop) {
5706 if((opcode[i]&0x2f)==4) // BEQ
5708 if(s2h>=0) emit_cmp(s1h,s2h);
5709 else emit_test(s1h,s1h);
5713 if((opcode[i]&0x2f)==5) // BNE
5715 if(s2h>=0) emit_cmp(s1h,s2h);
5716 else emit_test(s1h,s1h);
5720 if((opcode[i]&0x2f)==6) // BLEZ
5728 if((opcode[i]&0x2f)==7) // BGTZ
5738 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5740 if((opcode[i]&0x2f)==4) // BEQ
5742 if(s2l>=0) emit_cmp(s1l,s2l);
5743 else emit_test(s1l,s1l);
5747 if((opcode[i]&0x2f)==5) // BNE
5749 if(s2l>=0) emit_cmp(s1l,s2l);
5750 else emit_test(s1l,s1l);
5754 if((opcode[i]&0x2f)==6) // BLEZ
5760 if((opcode[i]&0x2f)==7) // BGTZ
5766 } // if(!unconditional)
5768 uint64_t ds_unneeded=branch_regs[i].u;
5769 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5770 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5771 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5772 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5774 ds_unneeded_upper|=1;
5777 if(taken) set_jump_target(taken,(int)out);
5778 assem_debug("1:\n");
5779 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5780 ds_unneeded,ds_unneeded_upper);
5782 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5783 address_generation(i+1,&branch_regs[i],0);
5784 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5785 ds_assemble(i+1,&branch_regs[i]);
5786 cc=get_reg(branch_regs[i].regmap,CCREG);
5788 emit_loadreg(CCREG,cc=HOST_CCREG);
5789 // CHECK: Is the following instruction (fall thru) allocated ok?
5791 assert(cc==HOST_CCREG);
5792 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5793 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5794 assem_debug("cycle count (adj)\n");
5795 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5796 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5798 assem_debug("branch: internal\n");
5800 assem_debug("branch: external\n");
5801 if(internal&&is_ds[(ba[i]-start)>>2]) {
5802 ds_assemble_entry(i);
5805 add_to_linker((int)out,ba[i],internal);
5810 cop1_usable=prev_cop1_usable;
5811 if(!unconditional) {
5812 if(nottaken1) set_jump_target(nottaken1,(int)out);
5813 set_jump_target(nottaken,(int)out);
5814 assem_debug("2:\n");
5816 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5817 ds_unneeded,ds_unneeded_upper);
5818 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5819 address_generation(i+1,&branch_regs[i],0);
5820 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5821 ds_assemble(i+1,&branch_regs[i]);
5823 cc=get_reg(branch_regs[i].regmap,CCREG);
5824 if(cc==-1&&!likely[i]) {
5825 // Cycle count isn't in a register, temporarily load it then write it out
5826 emit_loadreg(CCREG,HOST_CCREG);
5827 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5830 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5831 emit_storereg(CCREG,HOST_CCREG);
5834 cc=get_reg(i_regmap,CCREG);
5835 assert(cc==HOST_CCREG);
5836 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5839 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5845 void sjump_assemble(int i,struct regstat *i_regs)
5847 signed char *i_regmap=i_regs->regmap;
5850 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5851 assem_debug("smatch=%d\n",match);
5853 int prev_cop1_usable=cop1_usable;
5854 int unconditional=0,nevertaken=0;
5857 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5858 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5859 if(!match) invert=1;
5860 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5861 if(i>(ba[i]-start)>>2) invert=1;
5864 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5865 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5868 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5869 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5872 s1l=get_reg(i_regmap,rs1[i]);
5873 s1h=get_reg(i_regmap,rs1[i]|64);
5877 if(opcode2[i]&1) unconditional=1;
5879 // These are never taken (r0 is never less than zero)
5880 //assert(opcode2[i]!=0);
5881 //assert(opcode2[i]!=2);
5882 //assert(opcode2[i]!=0x10);
5883 //assert(opcode2[i]!=0x12);
5886 only32=(regs[i].was32>>rs1[i])&1;
5890 // Out of order execution (delay slot first)
5892 address_generation(i+1,i_regs,regs[i].regmap_entry);
5893 ds_assemble(i+1,i_regs);
5895 uint64_t bc_unneeded=branch_regs[i].u;
5896 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5897 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5898 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5900 bc_unneeded_upper|=1;
5901 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5902 bc_unneeded,bc_unneeded_upper);
5903 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5904 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5906 int rt,return_address;
5907 rt=get_reg(branch_regs[i].regmap,31);
5908 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5910 // Save the PC even if the branch is not taken
5911 return_address=start+i*4+8;
5912 emit_movimm(return_address,rt); // PC into link register
5914 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5918 cc=get_reg(branch_regs[i].regmap,CCREG);
5919 assert(cc==HOST_CCREG);
5921 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5922 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5923 assem_debug("cycle count (adj)\n");
5925 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5926 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5927 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5928 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5930 assem_debug("branch: internal\n");
5932 assem_debug("branch: external\n");
5933 if(internal&&is_ds[(ba[i]-start)>>2]) {
5934 ds_assemble_entry(i);
5937 add_to_linker((int)out,ba[i],internal);
5940 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5941 if(((u_int)out)&7) emit_addnop(0);
5945 else if(nevertaken) {
5946 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5949 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5953 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5954 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5958 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5965 add_to_linker((int)out,ba[i],internal);
5969 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5976 add_to_linker((int)out,ba[i],internal);
5984 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5991 add_to_linker((int)out,ba[i],internal);
5995 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6002 add_to_linker((int)out,ba[i],internal);
6009 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6010 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6012 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6013 add_to_linker((int)out,ba[i],internal);
6016 add_to_linker((int)out,ba[i],internal*2);
6022 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6023 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6024 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6026 assem_debug("branch: internal\n");
6028 assem_debug("branch: external\n");
6029 if(internal&&is_ds[(ba[i]-start)>>2]) {
6030 ds_assemble_entry(i);
6033 add_to_linker((int)out,ba[i],internal);
6037 set_jump_target(nottaken,(int)out);
6041 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6043 } // (!unconditional)
6047 // In-order execution (branch first)
6051 int rt,return_address;
6052 rt=get_reg(branch_regs[i].regmap,31);
6054 // Save the PC even if the branch is not taken
6055 return_address=start+i*4+8;
6056 emit_movimm(return_address,rt); // PC into link register
6058 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6062 if(!unconditional) {
6063 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6067 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6073 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6083 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6089 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6096 } // if(!unconditional)
6098 uint64_t ds_unneeded=branch_regs[i].u;
6099 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6100 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6101 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6102 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6104 ds_unneeded_upper|=1;
6107 //assem_debug("1:\n");
6108 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6109 ds_unneeded,ds_unneeded_upper);
6111 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6112 address_generation(i+1,&branch_regs[i],0);
6113 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6114 ds_assemble(i+1,&branch_regs[i]);
6115 cc=get_reg(branch_regs[i].regmap,CCREG);
6117 emit_loadreg(CCREG,cc=HOST_CCREG);
6118 // CHECK: Is the following instruction (fall thru) allocated ok?
6120 assert(cc==HOST_CCREG);
6121 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6122 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6123 assem_debug("cycle count (adj)\n");
6124 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6125 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6127 assem_debug("branch: internal\n");
6129 assem_debug("branch: external\n");
6130 if(internal&&is_ds[(ba[i]-start)>>2]) {
6131 ds_assemble_entry(i);
6134 add_to_linker((int)out,ba[i],internal);
6139 cop1_usable=prev_cop1_usable;
6140 if(!unconditional) {
6141 set_jump_target(nottaken,(int)out);
6142 assem_debug("1:\n");
6144 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6145 ds_unneeded,ds_unneeded_upper);
6146 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6147 address_generation(i+1,&branch_regs[i],0);
6148 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6149 ds_assemble(i+1,&branch_regs[i]);
6151 cc=get_reg(branch_regs[i].regmap,CCREG);
6152 if(cc==-1&&!likely[i]) {
6153 // Cycle count isn't in a register, temporarily load it then write it out
6154 emit_loadreg(CCREG,HOST_CCREG);
6155 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6158 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6159 emit_storereg(CCREG,HOST_CCREG);
6162 cc=get_reg(i_regmap,CCREG);
6163 assert(cc==HOST_CCREG);
6164 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6167 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6173 void fjump_assemble(int i,struct regstat *i_regs)
6175 signed char *i_regmap=i_regs->regmap;
6178 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6179 assem_debug("fmatch=%d\n",match);
6183 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6184 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6185 if(!match) invert=1;
6186 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6187 if(i>(ba[i]-start)>>2) invert=1;
6191 fs=get_reg(branch_regs[i].regmap,FSREG);
6192 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6195 fs=get_reg(i_regmap,FSREG);
6198 // Check cop1 unusable
6200 cs=get_reg(i_regmap,CSREG);
6202 emit_testimm(cs,0x20000000);
6205 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6210 // Out of order execution (delay slot first)
6212 ds_assemble(i+1,i_regs);
6214 uint64_t bc_unneeded=branch_regs[i].u;
6215 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6216 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6217 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6219 bc_unneeded_upper|=1;
6220 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6221 bc_unneeded,bc_unneeded_upper);
6222 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6223 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6224 cc=get_reg(branch_regs[i].regmap,CCREG);
6225 assert(cc==HOST_CCREG);
6226 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6227 assem_debug("cycle count (adj)\n");
6230 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6233 emit_testimm(fs,0x800000);
6234 if(source[i]&0x10000) // BC1T
6240 add_to_linker((int)out,ba[i],internal);
6249 add_to_linker((int)out,ba[i],internal);
6257 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6258 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6259 else if(match) emit_addnop(13);
6261 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6262 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6264 assem_debug("branch: internal\n");
6266 assem_debug("branch: external\n");
6267 if(internal&&is_ds[(ba[i]-start)>>2]) {
6268 ds_assemble_entry(i);
6271 add_to_linker((int)out,ba[i],internal);
6274 set_jump_target(nottaken,(int)out);
6278 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6280 } // (!unconditional)
6284 // In-order execution (branch first)
6288 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6291 emit_testimm(fs,0x800000);
6292 if(source[i]&0x10000) // BC1T
6303 } // if(!unconditional)
6305 uint64_t ds_unneeded=branch_regs[i].u;
6306 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6307 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6308 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6309 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6311 ds_unneeded_upper|=1;
6313 //assem_debug("1:\n");
6314 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6315 ds_unneeded,ds_unneeded_upper);
6317 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6318 address_generation(i+1,&branch_regs[i],0);
6319 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6320 ds_assemble(i+1,&branch_regs[i]);
6321 cc=get_reg(branch_regs[i].regmap,CCREG);
6323 emit_loadreg(CCREG,cc=HOST_CCREG);
6324 // CHECK: Is the following instruction (fall thru) allocated ok?
6326 assert(cc==HOST_CCREG);
6327 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6328 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6329 assem_debug("cycle count (adj)\n");
6330 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6331 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6333 assem_debug("branch: internal\n");
6335 assem_debug("branch: external\n");
6336 if(internal&&is_ds[(ba[i]-start)>>2]) {
6337 ds_assemble_entry(i);
6340 add_to_linker((int)out,ba[i],internal);
6345 if(1) { // <- FIXME (don't need this)
6346 set_jump_target(nottaken,(int)out);
6347 assem_debug("1:\n");
6349 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6350 ds_unneeded,ds_unneeded_upper);
6351 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6352 address_generation(i+1,&branch_regs[i],0);
6353 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6354 ds_assemble(i+1,&branch_regs[i]);
6356 cc=get_reg(branch_regs[i].regmap,CCREG);
6357 if(cc==-1&&!likely[i]) {
6358 // Cycle count isn't in a register, temporarily load it then write it out
6359 emit_loadreg(CCREG,HOST_CCREG);
6360 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6363 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6364 emit_storereg(CCREG,HOST_CCREG);
6367 cc=get_reg(i_regmap,CCREG);
6368 assert(cc==HOST_CCREG);
6369 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6372 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6378 static void pagespan_assemble(int i,struct regstat *i_regs)
6380 int s1l=get_reg(i_regs->regmap,rs1[i]);
6381 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6382 int s2l=get_reg(i_regs->regmap,rs2[i]);
6383 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6384 void *nt_branch=NULL;
6387 int unconditional=0;
6397 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6401 int addr,alt,ntaddr;
6402 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6406 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6407 (i_regs->regmap[hr]&63)!=rs1[i] &&
6408 (i_regs->regmap[hr]&63)!=rs2[i] )
6417 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6418 (i_regs->regmap[hr]&63)!=rs1[i] &&
6419 (i_regs->regmap[hr]&63)!=rs2[i] )
6425 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6429 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6430 (i_regs->regmap[hr]&63)!=rs1[i] &&
6431 (i_regs->regmap[hr]&63)!=rs2[i] )
6438 assert(hr<HOST_REGS);
6439 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6440 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6442 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6443 if(opcode[i]==2) // J
6447 if(opcode[i]==3) // JAL
6450 int rt=get_reg(i_regs->regmap,31);
6451 emit_movimm(start+i*4+8,rt);
6454 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6457 if(opcode2[i]==9) // JALR
6459 int rt=get_reg(i_regs->regmap,rt1[i]);
6460 emit_movimm(start+i*4+8,rt);
6463 if((opcode[i]&0x3f)==4) // BEQ
6470 #ifdef HAVE_CMOV_IMM
6472 if(s2l>=0) emit_cmp(s1l,s2l);
6473 else emit_test(s1l,s1l);
6474 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6480 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6482 if(s2h>=0) emit_cmp(s1h,s2h);
6483 else emit_test(s1h,s1h);
6484 emit_cmovne_reg(alt,addr);
6486 if(s2l>=0) emit_cmp(s1l,s2l);
6487 else emit_test(s1l,s1l);
6488 emit_cmovne_reg(alt,addr);
6491 if((opcode[i]&0x3f)==5) // BNE
6493 #ifdef HAVE_CMOV_IMM
6495 if(s2l>=0) emit_cmp(s1l,s2l);
6496 else emit_test(s1l,s1l);
6497 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6503 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6505 if(s2h>=0) emit_cmp(s1h,s2h);
6506 else emit_test(s1h,s1h);
6507 emit_cmovne_reg(alt,addr);
6509 if(s2l>=0) emit_cmp(s1l,s2l);
6510 else emit_test(s1l,s1l);
6511 emit_cmovne_reg(alt,addr);
6514 if((opcode[i]&0x3f)==0x14) // BEQL
6517 if(s2h>=0) emit_cmp(s1h,s2h);
6518 else emit_test(s1h,s1h);
6522 if(s2l>=0) emit_cmp(s1l,s2l);
6523 else emit_test(s1l,s1l);
6524 if(nottaken) set_jump_target(nottaken,(int)out);
6528 if((opcode[i]&0x3f)==0x15) // BNEL
6531 if(s2h>=0) emit_cmp(s1h,s2h);
6532 else emit_test(s1h,s1h);
6536 if(s2l>=0) emit_cmp(s1l,s2l);
6537 else emit_test(s1l,s1l);
6540 if(taken) set_jump_target(taken,(int)out);
6542 if((opcode[i]&0x3f)==6) // BLEZ
6544 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6546 if(s1h>=0) emit_mov(addr,ntaddr);
6547 emit_cmovl_reg(alt,addr);
6550 emit_cmovne_reg(ntaddr,addr);
6551 emit_cmovs_reg(alt,addr);
6554 if((opcode[i]&0x3f)==7) // BGTZ
6556 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6558 if(s1h>=0) emit_mov(addr,alt);
6559 emit_cmovl_reg(ntaddr,addr);
6562 emit_cmovne_reg(alt,addr);
6563 emit_cmovs_reg(ntaddr,addr);
6566 if((opcode[i]&0x3f)==0x16) // BLEZL
6568 assert((opcode[i]&0x3f)!=0x16);
6570 if((opcode[i]&0x3f)==0x17) // BGTZL
6572 assert((opcode[i]&0x3f)!=0x17);
6574 assert(opcode[i]!=1); // BLTZ/BGEZ
6576 //FIXME: Check CSREG
6577 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6578 if((source[i]&0x30000)==0) // BC1F
6580 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6581 emit_testimm(s1l,0x800000);
6582 emit_cmovne_reg(alt,addr);
6584 if((source[i]&0x30000)==0x10000) // BC1T
6586 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6587 emit_testimm(s1l,0x800000);
6588 emit_cmovne_reg(alt,addr);
6590 if((source[i]&0x30000)==0x20000) // BC1FL
6592 emit_testimm(s1l,0x800000);
6596 if((source[i]&0x30000)==0x30000) // BC1TL
6598 emit_testimm(s1l,0x800000);
6604 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6605 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6606 if(likely[i]||unconditional)
6608 emit_movimm(ba[i],HOST_BTREG);
6610 else if(addr!=HOST_BTREG)
6612 emit_mov(addr,HOST_BTREG);
6614 void *branch_addr=out;
6616 int target_addr=start+i*4+5;
6618 void *compiled_target_addr=check_addr(target_addr);
6619 emit_extjump_ds((int)branch_addr,target_addr);
6620 if(compiled_target_addr) {
6621 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6622 add_link(target_addr,stub);
6624 else set_jump_target((int)branch_addr,(int)stub);
6627 set_jump_target((int)nottaken,(int)out);
6628 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6629 void *branch_addr=out;
6631 int target_addr=start+i*4+8;
6633 void *compiled_target_addr=check_addr(target_addr);
6634 emit_extjump_ds((int)branch_addr,target_addr);
6635 if(compiled_target_addr) {
6636 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6637 add_link(target_addr,stub);
6639 else set_jump_target((int)branch_addr,(int)stub);
6643 // Assemble the delay slot for the above
6644 static void pagespan_ds()
6646 assem_debug("initial delay slot:\n");
6647 u_int vaddr=start+1;
6648 u_int page=get_page(vaddr);
6649 u_int vpage=get_vpage(vaddr);
6650 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6652 ll_add(jump_in+page,vaddr,(void *)out);
6653 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6654 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6655 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6656 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6657 emit_writeword(HOST_BTREG,(int)&branch_target);
6658 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6659 address_generation(0,®s[0],regs[0].regmap_entry);
6660 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6661 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6666 alu_assemble(0,®s[0]);break;
6668 imm16_assemble(0,®s[0]);break;
6670 shift_assemble(0,®s[0]);break;
6672 shiftimm_assemble(0,®s[0]);break;
6674 load_assemble(0,®s[0]);break;
6676 loadlr_assemble(0,®s[0]);break;
6678 store_assemble(0,®s[0]);break;
6680 storelr_assemble(0,®s[0]);break;
6682 cop0_assemble(0,®s[0]);break;
6684 cop1_assemble(0,®s[0]);break;
6686 c1ls_assemble(0,®s[0]);break;
6688 cop2_assemble(0,®s[0]);break;
6690 c2ls_assemble(0,®s[0]);break;
6692 c2op_assemble(0,®s[0]);break;
6694 fconv_assemble(0,®s[0]);break;
6696 float_assemble(0,®s[0]);break;
6698 fcomp_assemble(0,®s[0]);break;
6700 multdiv_assemble(0,®s[0]);break;
6702 mov_assemble(0,®s[0]);break;
6712 printf("Jump in the delay slot. This is probably a bug.\n");
6714 int btaddr=get_reg(regs[0].regmap,BTREG);
6716 btaddr=get_reg(regs[0].regmap,-1);
6717 emit_readword((int)&branch_target,btaddr);
6719 assert(btaddr!=HOST_CCREG);
6720 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6722 emit_movimm(start+4,HOST_TEMPREG);
6723 emit_cmp(btaddr,HOST_TEMPREG);
6725 emit_cmpimm(btaddr,start+4);
6727 int branch=(int)out;
6729 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6730 emit_jmp(jump_vaddr_reg[btaddr]);
6731 set_jump_target(branch,(int)out);
6732 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6733 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6736 // Basic liveness analysis for MIPS registers
6737 void unneeded_registers(int istart,int iend,int r)
6740 uint64_t u,uu,gte_u,b,bu,gte_bu;
6741 uint64_t temp_u,temp_uu,temp_gte_u;
6746 u=unneeded_reg[iend+1];
6747 uu=unneeded_reg_upper[iend+1];
6752 for (i=iend;i>=istart;i--)
6754 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6755 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6757 // If subroutine call, flag return address as a possible branch target
6758 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6760 if(ba[i]<start || ba[i]>=(start+slen*4))
6762 // Branch out of this block, flush all regs
6767 if(itype[i]==UJUMP&&rt1[i]==31)
6769 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6771 if(itype[i]==RJUMP&&rs1[i]==31)
6773 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6775 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6776 if(itype[i]==UJUMP&&rt1[i]==31)
6778 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6779 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6781 if(itype[i]==RJUMP&&rs1[i]==31)
6783 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6784 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6787 branch_unneeded_reg[i]=u;
6788 branch_unneeded_reg_upper[i]=uu;
6789 // Merge in delay slot
6790 tdep=(~uu>>rt1[i+1])&1;
6791 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6792 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6793 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6794 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6795 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6798 gte_u&=~gte_rs[i+1];
6799 // If branch is "likely" (and conditional)
6800 // then we skip the delay slot on the fall-thru path
6803 u&=unneeded_reg[i+2];
6804 uu&=unneeded_reg_upper[i+2];
6805 gte_u&=gte_unneeded[i+2];
6817 // Internal branch, flag target
6818 bt[(ba[i]-start)>>2]=1;
6819 if(ba[i]<=start+i*4) {
6821 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6823 // Unconditional branch
6827 // Conditional branch (not taken case)
6828 temp_u=unneeded_reg[i+2];
6829 temp_uu=unneeded_reg_upper[i+2];
6830 temp_gte_u&=gte_unneeded[i+2];
6832 // Merge in delay slot
6833 tdep=(~temp_uu>>rt1[i+1])&1;
6834 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6835 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6836 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6837 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6838 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6839 temp_u|=1;temp_uu|=1;
6840 temp_gte_u|=gte_rt[i+1];
6841 temp_gte_u&=~gte_rs[i+1];
6842 // If branch is "likely" (and conditional)
6843 // then we skip the delay slot on the fall-thru path
6846 temp_u&=unneeded_reg[i+2];
6847 temp_uu&=unneeded_reg_upper[i+2];
6848 temp_gte_u&=gte_unneeded[i+2];
6857 tdep=(~temp_uu>>rt1[i])&1;
6858 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6859 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6860 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6861 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6862 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6863 temp_u|=1;temp_uu|=1;
6864 temp_gte_u|=gte_rt[i];
6865 temp_gte_u&=~gte_rs[i];
6866 unneeded_reg[i]=temp_u;
6867 unneeded_reg_upper[i]=temp_uu;
6868 gte_unneeded[i]=temp_gte_u;
6869 // Only go three levels deep. This recursion can take an
6870 // excessive amount of time if there are a lot of nested loops.
6872 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6874 unneeded_reg[(ba[i]-start)>>2]=1;
6875 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6876 gte_unneeded[(ba[i]-start)>>2]=0;
6879 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6881 // Unconditional branch
6882 u=unneeded_reg[(ba[i]-start)>>2];
6883 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6884 gte_u=gte_unneeded[(ba[i]-start)>>2];
6885 branch_unneeded_reg[i]=u;
6886 branch_unneeded_reg_upper[i]=uu;
6889 //branch_unneeded_reg[i]=u;
6890 //branch_unneeded_reg_upper[i]=uu;
6891 // Merge in delay slot
6892 tdep=(~uu>>rt1[i+1])&1;
6893 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6894 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6895 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6896 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6897 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6900 gte_u&=~gte_rs[i+1];
6902 // Conditional branch
6903 b=unneeded_reg[(ba[i]-start)>>2];
6904 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6905 gte_bu=gte_unneeded[(ba[i]-start)>>2];
6906 branch_unneeded_reg[i]=b;
6907 branch_unneeded_reg_upper[i]=bu;
6910 //branch_unneeded_reg[i]=b;
6911 //branch_unneeded_reg_upper[i]=bu;
6912 // Branch delay slot
6913 tdep=(~uu>>rt1[i+1])&1;
6914 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6915 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6916 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6917 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6918 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6920 gte_bu|=gte_rt[i+1];
6921 gte_bu&=~gte_rs[i+1];
6922 // If branch is "likely" then we skip the
6923 // delay slot on the fall-thru path
6929 u&=unneeded_reg[i+2];
6930 uu&=unneeded_reg_upper[i+2];
6931 gte_u&=gte_unneeded[i+2];
6943 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6944 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6945 //branch_unneeded_reg[i]=1;
6946 //branch_unneeded_reg_upper[i]=1;
6948 branch_unneeded_reg[i]=1;
6949 branch_unneeded_reg_upper[i]=1;
6955 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6957 // SYSCALL instruction (software interrupt)
6961 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6963 // ERET instruction (return from interrupt)
6968 tdep=(~uu>>rt1[i])&1;
6969 // Written registers are unneeded
6975 // Accessed registers are needed
6981 // Source-target dependencies
6982 uu&=~(tdep<<dep1[i]);
6983 uu&=~(tdep<<dep2[i]);
6984 // R0 is always unneeded
6988 unneeded_reg_upper[i]=uu;
6989 gte_unneeded[i]=gte_u;
6991 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6994 for(r=1;r<=CCREG;r++) {
6995 if((unneeded_reg[i]>>r)&1) {
6996 if(r==HIREG) printf(" HI");
6997 else if(r==LOREG) printf(" LO");
6998 else printf(" r%d",r);
7002 for(r=1;r<=CCREG;r++) {
7003 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
7004 if(r==HIREG) printf(" HI");
7005 else if(r==LOREG) printf(" LO");
7006 else printf(" r%d",r);
7012 for (i=iend;i>=istart;i--)
7014 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7019 // Identify registers which are likely to contain 32-bit values
7020 // This is used to predict whether any branches will jump to a
7021 // location with 64-bit values in registers.
7022 static void provisional_32bit()
7026 uint64_t lastbranch=1;
7031 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7032 if(i>1) is32=lastbranch;
7038 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7040 if(i>2) is32=lastbranch;
7044 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7046 if(rs1[i-2]==0||rs2[i-2]==0)
7049 is32|=1LL<<rs1[i-2];
7052 is32|=1LL<<rs2[i-2];
7057 // If something jumps here with 64-bit values
7058 // then promote those registers to 64 bits
7061 uint64_t temp_is32=is32;
7064 if(ba[j]==start+i*4)
7065 //temp_is32&=branch_regs[j].is32;
7070 if(ba[j]==start+i*4)
7081 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7082 // Branches don't write registers, consider the delay slot instead.
7093 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7094 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7103 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7104 if(op==0x22) is32|=1LL<<rt; // LWL
7107 if (op==0x08||op==0x09|| // ADDI/ADDIU
7108 op==0x0a||op==0x0b|| // SLTI/SLTIU
7114 if(op==0x18||op==0x19) { // DADDI/DADDIU
7117 // is32|=((is32>>s1)&1LL)<<rt;
7119 if(op==0x0d||op==0x0e) { // ORI/XORI
7120 uint64_t sr=((is32>>s1)&1LL);
7136 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7139 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7142 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7143 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7147 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7152 uint64_t sr=((is32>>s1)&1LL);
7157 uint64_t sr=((is32>>s2)&1LL);
7165 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7170 uint64_t sr=((is32>>s1)&1LL);
7180 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7181 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7184 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7189 uint64_t sr=((is32>>s1)&1LL);
7195 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7196 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7200 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7201 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7204 if(op2==0) is32|=1LL<<rt; // MFC0
7208 if(op2==0) is32|=1LL<<rt; // MFC1
7209 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7210 if(op2==2) is32|=1LL<<rt; // CFC1
7232 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7234 if(rt1[i-1]==31) // JAL/JALR
7236 // Subroutine call will return here, don't alloc any registers
7241 // Internal branch will jump here, match registers to caller
7249 // Identify registers which may be assumed to contain 32-bit values
7250 // and where optimizations will rely on this.
7251 // This is used to determine whether backward branches can safely
7252 // jump to a location with 64-bit values in registers.
7253 static void provisional_r32()
7258 for (i=slen-1;i>=0;i--)
7261 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7263 if(ba[i]<start || ba[i]>=(start+slen*4))
7265 // Branch out of this block, don't need anything
7271 // Need whatever matches the target
7272 // (and doesn't get overwritten by the delay slot instruction)
7274 int t=(ba[i]-start)>>2;
7275 if(ba[i]>start+i*4) {
7277 //if(!(requires_32bit[t]&~regs[i].was32))
7278 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7279 if(!(pr32[t]&~regs[i].was32))
7280 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7283 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7284 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7287 // Conditional branch may need registers for following instructions
7288 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7291 //r32|=requires_32bit[i+2];
7294 // Mark this address as a branch target since it may be called
7295 // upon return from interrupt
7299 // Merge in delay slot
7301 // These are overwritten unless the branch is "likely"
7302 // and the delay slot is nullified if not taken
7303 r32&=~(1LL<<rt1[i+1]);
7304 r32&=~(1LL<<rt2[i+1]);
7306 // Assume these are needed (delay slot)
7309 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7313 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7315 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7317 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7319 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7321 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7324 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7326 // SYSCALL instruction (software interrupt)
7329 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7331 // ERET instruction (return from interrupt)
7335 r32&=~(1LL<<rt1[i]);
7336 r32&=~(1LL<<rt2[i]);
7339 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7343 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7345 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7347 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7349 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7351 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7353 //requires_32bit[i]=r32;
7356 // Dirty registers which are 32-bit, require 32-bit input
7357 // as they will be written as 32-bit values
7358 for(hr=0;hr<HOST_REGS;hr++)
7360 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7361 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7362 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7363 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7364 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7371 // Write back dirty registers as soon as we will no longer modify them,
7372 // so that we don't end up with lots of writes at the branches.
7373 void clean_registers(int istart,int iend,int wr)
7377 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7378 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7380 will_dirty_i=will_dirty_next=0;
7381 wont_dirty_i=wont_dirty_next=0;
7383 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7384 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7386 for (i=iend;i>=istart;i--)
7388 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7390 if(ba[i]<start || ba[i]>=(start+slen*4))
7392 // Branch out of this block, flush all regs
7393 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7395 // Unconditional branch
7398 // Merge in delay slot (will dirty)
7399 for(r=0;r<HOST_REGS;r++) {
7400 if(r!=EXCLUDE_REG) {
7401 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7402 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7403 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7404 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7405 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7406 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7407 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7408 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7409 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7410 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7411 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7412 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7413 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7414 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7420 // Conditional branch
7422 wont_dirty_i=wont_dirty_next;
7423 // Merge in delay slot (will dirty)
7424 for(r=0;r<HOST_REGS;r++) {
7425 if(r!=EXCLUDE_REG) {
7427 // Might not dirty if likely branch is not taken
7428 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7429 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7430 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7431 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7432 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7433 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7434 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7435 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7436 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7437 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7438 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7439 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7440 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7441 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7446 // Merge in delay slot (wont dirty)
7447 for(r=0;r<HOST_REGS;r++) {
7448 if(r!=EXCLUDE_REG) {
7449 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7450 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7451 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7452 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7453 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7454 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7455 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7456 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7457 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7458 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7462 #ifndef DESTRUCTIVE_WRITEBACK
7463 branch_regs[i].dirty&=wont_dirty_i;
7465 branch_regs[i].dirty|=will_dirty_i;
7471 if(ba[i]<=start+i*4) {
7473 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7475 // Unconditional branch
7478 // Merge in delay slot (will dirty)
7479 for(r=0;r<HOST_REGS;r++) {
7480 if(r!=EXCLUDE_REG) {
7481 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7482 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7483 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7484 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7485 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7486 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7487 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7488 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7489 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7490 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7491 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7492 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7493 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7494 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7498 // Conditional branch (not taken case)
7499 temp_will_dirty=will_dirty_next;
7500 temp_wont_dirty=wont_dirty_next;
7501 // Merge in delay slot (will dirty)
7502 for(r=0;r<HOST_REGS;r++) {
7503 if(r!=EXCLUDE_REG) {
7505 // Will not dirty if likely branch is not taken
7506 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7507 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7508 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7509 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7510 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7511 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7512 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7513 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7514 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7515 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7516 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7517 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7518 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7519 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7524 // Merge in delay slot (wont dirty)
7525 for(r=0;r<HOST_REGS;r++) {
7526 if(r!=EXCLUDE_REG) {
7527 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7528 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7529 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7530 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7531 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7532 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7533 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7534 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7535 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7536 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7539 // Deal with changed mappings
7541 for(r=0;r<HOST_REGS;r++) {
7542 if(r!=EXCLUDE_REG) {
7543 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7544 temp_will_dirty&=~(1<<r);
7545 temp_wont_dirty&=~(1<<r);
7546 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7547 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7548 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7550 temp_will_dirty|=1<<r;
7551 temp_wont_dirty|=1<<r;
7558 will_dirty[i]=temp_will_dirty;
7559 wont_dirty[i]=temp_wont_dirty;
7560 clean_registers((ba[i]-start)>>2,i-1,0);
7562 // Limit recursion. It can take an excessive amount
7563 // of time if there are a lot of nested loops.
7564 will_dirty[(ba[i]-start)>>2]=0;
7565 wont_dirty[(ba[i]-start)>>2]=-1;
7570 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7572 // Unconditional branch
7575 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7576 for(r=0;r<HOST_REGS;r++) {
7577 if(r!=EXCLUDE_REG) {
7578 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7579 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7580 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7582 if(branch_regs[i].regmap[r]>=0) {
7583 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7584 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7589 // Merge in delay slot
7590 for(r=0;r<HOST_REGS;r++) {
7591 if(r!=EXCLUDE_REG) {
7592 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7593 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7594 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7595 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7596 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7597 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7598 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7599 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7600 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7601 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7602 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7603 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7604 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7605 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7609 // Conditional branch
7610 will_dirty_i=will_dirty_next;
7611 wont_dirty_i=wont_dirty_next;
7612 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7613 for(r=0;r<HOST_REGS;r++) {
7614 if(r!=EXCLUDE_REG) {
7615 signed char target_reg=branch_regs[i].regmap[r];
7616 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7617 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7618 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7620 else if(target_reg>=0) {
7621 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7622 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7624 // Treat delay slot as part of branch too
7625 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7626 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7627 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7631 will_dirty[i+1]&=~(1<<r);
7636 // Merge in delay slot
7637 for(r=0;r<HOST_REGS;r++) {
7638 if(r!=EXCLUDE_REG) {
7640 // Might not dirty if likely branch is not taken
7641 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7642 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7643 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7644 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7645 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7646 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7647 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7648 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7649 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7650 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7651 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7652 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7653 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7654 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7659 // Merge in delay slot (won't dirty)
7660 for(r=0;r<HOST_REGS;r++) {
7661 if(r!=EXCLUDE_REG) {
7662 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7663 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7664 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7665 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7666 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7667 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7668 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7669 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7670 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7671 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7675 #ifndef DESTRUCTIVE_WRITEBACK
7676 branch_regs[i].dirty&=wont_dirty_i;
7678 branch_regs[i].dirty|=will_dirty_i;
7683 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7685 // SYSCALL instruction (software interrupt)
7689 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7691 // ERET instruction (return from interrupt)
7695 will_dirty_next=will_dirty_i;
7696 wont_dirty_next=wont_dirty_i;
7697 for(r=0;r<HOST_REGS;r++) {
7698 if(r!=EXCLUDE_REG) {
7699 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7700 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7701 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7702 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7703 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7704 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7705 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7706 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7708 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7710 // Don't store a register immediately after writing it,
7711 // may prevent dual-issue.
7712 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7713 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7719 will_dirty[i]=will_dirty_i;
7720 wont_dirty[i]=wont_dirty_i;
7721 // Mark registers that won't be dirtied as not dirty
7723 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7724 for(r=0;r<HOST_REGS;r++) {
7725 if((will_dirty_i>>r)&1) {
7731 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7732 regs[i].dirty|=will_dirty_i;
7733 #ifndef DESTRUCTIVE_WRITEBACK
7734 regs[i].dirty&=wont_dirty_i;
7735 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7737 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7738 for(r=0;r<HOST_REGS;r++) {
7739 if(r!=EXCLUDE_REG) {
7740 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7741 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7742 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7750 for(r=0;r<HOST_REGS;r++) {
7751 if(r!=EXCLUDE_REG) {
7752 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7753 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7754 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7762 // Deal with changed mappings
7763 temp_will_dirty=will_dirty_i;
7764 temp_wont_dirty=wont_dirty_i;
7765 for(r=0;r<HOST_REGS;r++) {
7766 if(r!=EXCLUDE_REG) {
7768 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7770 #ifndef DESTRUCTIVE_WRITEBACK
7771 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7773 regs[i].wasdirty|=will_dirty_i&(1<<r);
7776 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7777 // Register moved to a different register
7778 will_dirty_i&=~(1<<r);
7779 wont_dirty_i&=~(1<<r);
7780 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7781 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7783 #ifndef DESTRUCTIVE_WRITEBACK
7784 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7786 regs[i].wasdirty|=will_dirty_i&(1<<r);
7790 will_dirty_i&=~(1<<r);
7791 wont_dirty_i&=~(1<<r);
7792 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7793 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7794 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7797 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7807 void disassemble_inst(int i)
7809 if (bt[i]) printf("*"); else printf(" ");
7812 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7814 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7816 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7818 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7820 if (opcode[i]==0x9&&rt1[i]!=31)
7821 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7823 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7826 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7828 if(opcode[i]==0xf) //LUI
7829 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7831 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7835 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7839 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7843 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7846 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7849 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7852 if((opcode2[i]&0x1d)==0x10)
7853 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7854 else if((opcode2[i]&0x1d)==0x11)
7855 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7857 printf (" %x: %s\n",start+i*4,insn[i]);
7861 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7862 else if(opcode2[i]==4)
7863 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7864 else printf (" %x: %s\n",start+i*4,insn[i]);
7868 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7869 else if(opcode2[i]>3)
7870 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7871 else printf (" %x: %s\n",start+i*4,insn[i]);
7875 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7876 else if(opcode2[i]>3)
7877 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7878 else printf (" %x: %s\n",start+i*4,insn[i]);
7881 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7884 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7887 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7890 //printf (" %s %8x\n",insn[i],source[i]);
7891 printf (" %x: %s\n",start+i*4,insn[i]);
7895 static void disassemble_inst(int i) {}
7898 // clear the state completely, instead of just marking
7899 // things invalid like invalidate_all_pages() does
7900 void new_dynarec_clear_full()
7903 out=(u_char *)BASE_ADDR;
7904 memset(invalid_code,1,sizeof(invalid_code));
7905 memset(hash_table,0xff,sizeof(hash_table));
7906 memset(mini_ht,-1,sizeof(mini_ht));
7907 memset(restore_candidate,0,sizeof(restore_candidate));
7908 memset(shadow,0,sizeof(shadow));
7910 expirep=16384; // Expiry pointer, +2 blocks
7911 pending_exception=0;
7914 inv_code_start=inv_code_end=~0;
7919 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7921 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7922 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7923 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7926 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7927 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7928 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7931 void new_dynarec_init()
7933 printf("Init new dynarec\n");
7934 out=(u_char *)BASE_ADDR;
7935 if (mmap (out, 1<<TARGET_SIZE_2,
7936 PROT_READ | PROT_WRITE | PROT_EXEC,
7937 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7938 -1, 0) <= 0) {printf("mmap() failed\n");}
7940 rdword=&readmem_dword;
7941 fake_pc.f.r.rs=&readmem_dword;
7942 fake_pc.f.r.rt=&readmem_dword;
7943 fake_pc.f.r.rd=&readmem_dword;
7946 cycle_multiplier=200;
7947 new_dynarec_clear_full();
7949 // Copy this into local area so we don't have to put it in every literal pool
7950 invc_ptr=invalid_code;
7953 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7954 writemem[n] = write_nomem_new;
7955 writememb[n] = write_nomemb_new;
7956 writememh[n] = write_nomemh_new;
7958 writememd[n] = write_nomemd_new;
7960 readmem[n] = read_nomem_new;
7961 readmemb[n] = read_nomemb_new;
7962 readmemh[n] = read_nomemh_new;
7964 readmemd[n] = read_nomemd_new;
7967 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7968 writemem[n] = write_rdram_new;
7969 writememb[n] = write_rdramb_new;
7970 writememh[n] = write_rdramh_new;
7972 writememd[n] = write_rdramd_new;
7975 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7976 writemem[n] = write_nomem_new;
7977 writememb[n] = write_nomemb_new;
7978 writememh[n] = write_nomemh_new;
7980 writememd[n] = write_nomemd_new;
7982 readmem[n] = read_nomem_new;
7983 readmemb[n] = read_nomemb_new;
7984 readmemh[n] = read_nomemh_new;
7986 readmemd[n] = read_nomemd_new;
7994 void new_dynarec_cleanup()
7997 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7998 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7999 for(n=0;n<4096;n++) ll_clear(jump_out+n);
8000 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8002 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
8006 int new_recompile_block(int addr)
8009 if(addr==0x800cd050) {
8011 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
8013 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8016 //if(Count==365117028) tracedebug=1;
8017 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8018 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8019 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8021 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8022 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8023 /*if(Count>=312978186) {
8027 start = (u_int)addr&~3;
8028 //assert(((u_int)addr&1)==0);
8029 new_dynarec_did_compile=1;
8031 if (Config.HLE && start == 0x80001000) // hlecall
8033 // XXX: is this enough? Maybe check hleSoftCall?
8034 u_int beginning=(u_int)out;
8035 u_int page=get_page(start);
8036 invalid_code[start>>12]=0;
8037 emit_movimm(start,0);
8038 emit_writeword(0,(int)&pcaddr);
8039 emit_jmp((int)new_dyna_leave);
8042 __clear_cache((void *)beginning,out);
8044 ll_add(jump_in+page,start,(void *)beginning);
8047 else if ((u_int)addr < 0x00200000 ||
8048 (0xa0000000 <= addr && addr < 0xa0200000)) {
8049 // used for BIOS calls mostly?
8050 source = (u_int *)((u_int)rdram+(start&0x1fffff));
8051 pagelimit = (addr&0xa0000000)|0x00200000;
8053 else if (!Config.HLE && (
8054 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8055 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8057 source = (u_int *)((u_int)psxR+(start&0x7ffff));
8058 pagelimit = (addr&0xfff00000)|0x80000;
8063 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8064 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8065 pagelimit = 0xa4001000;
8069 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8070 source = (u_int *)((u_int)rdram+start-0x80000000);
8071 pagelimit = 0x80000000+RAM_SIZE;
8074 else if ((signed int)addr >= (signed int)0xC0000000) {
8075 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8076 //if(tlb_LUT_r[start>>12])
8077 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8078 if((signed int)memory_map[start>>12]>=0) {
8079 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8080 pagelimit=(start+4096)&0xFFFFF000;
8081 int map=memory_map[start>>12];
8084 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8085 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8087 assem_debug("pagelimit=%x\n",pagelimit);
8088 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8091 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8092 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8093 return -1; // Caller will invoke exception handler
8095 //printf("source= %x\n",(int)source);
8099 printf("Compile at bogus memory address: %x \n", (int)addr);
8103 /* Pass 1: disassemble */
8104 /* Pass 2: register dependencies, branch targets */
8105 /* Pass 3: register allocation */
8106 /* Pass 4: branch dependencies */
8107 /* Pass 5: pre-alloc */
8108 /* Pass 6: optimize clean/dirty state */
8109 /* Pass 7: flag 32-bit registers */
8110 /* Pass 8: assembly */
8111 /* Pass 9: linker */
8112 /* Pass 10: garbage collection / free memory */
8116 unsigned int type,op,op2;
8118 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8120 /* Pass 1 disassembly */
8122 for(i=0;!done;i++) {
8123 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8124 minimum_free_regs[i]=0;
8125 opcode[i]=op=source[i]>>26;
8128 case 0x00: strcpy(insn[i],"special"); type=NI;
8132 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8133 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8134 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8135 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8136 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8137 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8138 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8139 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8140 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8141 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8142 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8143 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8144 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8145 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8146 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8147 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8148 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8149 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8150 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8151 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8152 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8153 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8154 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8155 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8156 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8157 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8158 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8159 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8160 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8161 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8162 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8163 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8164 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8165 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8166 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8168 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8169 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8170 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8171 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8172 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8173 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8174 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8175 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8176 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8177 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8178 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8179 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8180 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8181 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8182 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8183 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8184 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8188 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8189 op2=(source[i]>>16)&0x1f;
8192 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8193 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8194 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8195 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8196 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8197 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8198 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8199 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8200 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8201 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8202 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8203 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8204 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8205 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8208 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8209 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8210 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8211 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8212 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8213 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8214 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8215 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8216 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8217 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8218 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8219 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8220 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8221 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8222 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8223 op2=(source[i]>>21)&0x1f;
8226 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8227 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8228 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8229 switch(source[i]&0x3f)
8231 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8232 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8233 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8234 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8236 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8238 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8243 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8244 op2=(source[i]>>21)&0x1f;
8247 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8248 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8249 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8250 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8251 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8252 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8253 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8254 switch((source[i]>>16)&0x3)
8256 case 0x00: strcpy(insn[i],"BC1F"); break;
8257 case 0x01: strcpy(insn[i],"BC1T"); break;
8258 case 0x02: strcpy(insn[i],"BC1FL"); break;
8259 case 0x03: strcpy(insn[i],"BC1TL"); break;
8262 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8263 switch(source[i]&0x3f)
8265 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8266 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8267 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8268 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8269 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8270 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8271 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8272 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8273 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8274 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8275 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8276 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8277 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8278 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8279 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8280 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8281 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8282 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8283 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8284 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8285 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8286 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8287 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8288 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8289 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8290 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8291 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8292 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8293 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8294 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8295 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8296 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8297 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8298 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8299 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8302 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8303 switch(source[i]&0x3f)
8305 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8306 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8307 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8308 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8309 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8310 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8311 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8312 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8313 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8314 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8315 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8316 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8317 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8318 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8319 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8320 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8321 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8322 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8323 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8324 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8325 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8326 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8327 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8328 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8329 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8330 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8331 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8332 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8333 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8334 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8335 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8336 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8337 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8338 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8339 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8342 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8343 switch(source[i]&0x3f)
8345 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8346 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8349 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8350 switch(source[i]&0x3f)
8352 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8353 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8359 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8360 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8361 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8362 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8363 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8364 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8365 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8366 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8368 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8369 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8370 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8371 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8372 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8373 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8374 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8376 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8378 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8379 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8380 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8381 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8383 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8384 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8386 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8387 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8388 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8389 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8391 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8392 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8393 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8395 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8396 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8398 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8399 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8400 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8403 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8404 op2=(source[i]>>21)&0x1f;
8406 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8407 if (gte_handlers[source[i]&0x3f]!=NULL) {
8408 if (gte_regnames[source[i]&0x3f]!=NULL)
8409 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8411 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8417 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8418 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8419 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8420 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8423 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8424 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8425 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8427 default: strcpy(insn[i],"???"); type=NI;
8428 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8433 /* Get registers/immediates */
8439 gte_rs[i]=gte_rt[i]=0;
8442 rs1[i]=(source[i]>>21)&0x1f;
8444 rt1[i]=(source[i]>>16)&0x1f;
8446 imm[i]=(short)source[i];
8450 rs1[i]=(source[i]>>21)&0x1f;
8451 rs2[i]=(source[i]>>16)&0x1f;
8454 imm[i]=(short)source[i];
8455 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8458 // LWL/LWR only load part of the register,
8459 // therefore the target register must be treated as a source too
8460 rs1[i]=(source[i]>>21)&0x1f;
8461 rs2[i]=(source[i]>>16)&0x1f;
8462 rt1[i]=(source[i]>>16)&0x1f;
8464 imm[i]=(short)source[i];
8465 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8466 if(op==0x26) dep1[i]=rt1[i]; // LWR
8469 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8470 else rs1[i]=(source[i]>>21)&0x1f;
8472 rt1[i]=(source[i]>>16)&0x1f;
8474 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8475 imm[i]=(unsigned short)source[i];
8477 imm[i]=(short)source[i];
8479 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8480 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8481 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8488 // The JAL instruction writes to r31.
8495 rs1[i]=(source[i]>>21)&0x1f;
8499 // The JALR instruction writes to rd.
8501 rt1[i]=(source[i]>>11)&0x1f;
8506 rs1[i]=(source[i]>>21)&0x1f;
8507 rs2[i]=(source[i]>>16)&0x1f;
8510 if(op&2) { // BGTZ/BLEZ
8518 rs1[i]=(source[i]>>21)&0x1f;
8523 if(op2&0x10) { // BxxAL
8525 // NOTE: If the branch is not taken, r31 is still overwritten
8527 likely[i]=(op2&2)>>1;
8534 likely[i]=((source[i])>>17)&1;
8537 rs1[i]=(source[i]>>21)&0x1f; // source
8538 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8539 rt1[i]=(source[i]>>11)&0x1f; // destination
8541 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8542 us1[i]=rs1[i];us2[i]=rs2[i];
8544 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8545 dep1[i]=rs1[i];dep2[i]=rs2[i];
8547 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8548 dep1[i]=rs1[i];dep2[i]=rs2[i];
8552 rs1[i]=(source[i]>>21)&0x1f; // source
8553 rs2[i]=(source[i]>>16)&0x1f; // divisor
8556 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8557 us1[i]=rs1[i];us2[i]=rs2[i];
8565 if(op2==0x10) rs1[i]=HIREG; // MFHI
8566 if(op2==0x11) rt1[i]=HIREG; // MTHI
8567 if(op2==0x12) rs1[i]=LOREG; // MFLO
8568 if(op2==0x13) rt1[i]=LOREG; // MTLO
8569 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8570 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8574 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8575 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8576 rt1[i]=(source[i]>>11)&0x1f; // destination
8578 // DSLLV/DSRLV/DSRAV are 64-bit
8579 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8582 rs1[i]=(source[i]>>16)&0x1f;
8584 rt1[i]=(source[i]>>11)&0x1f;
8586 imm[i]=(source[i]>>6)&0x1f;
8587 // DSxx32 instructions
8588 if(op2>=0x3c) imm[i]|=0x20;
8589 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8590 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8597 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8598 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8599 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8600 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8607 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8608 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8609 if(op2==5) us1[i]=rs1[i]; // DMTC1
8617 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8618 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8620 int gr=(source[i]>>11)&0x1F;
8623 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8624 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8625 case 0x02: gte_rs[i]=1ll<<(gr+32); // CFC2
8626 if(gr==31&&!gte_reads_flags) {
8627 assem_debug("gte flag read encountered @%08x\n",addr + i*4);
8631 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8635 rs1[i]=(source[i]>>21)&0x1F;
8639 imm[i]=(short)source[i];
8642 rs1[i]=(source[i]>>21)&0x1F;
8646 imm[i]=(short)source[i];
8647 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8648 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8655 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
8656 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
8657 gte_rt[i]|=1ll<<63; // every op changes flags
8686 /* Calculate branch target addresses */
8688 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8689 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8690 ba[i]=start+i*4+8; // Ignore never taken branch
8691 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8692 ba[i]=start+i*4+8; // Ignore never taken branch
8693 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8694 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8697 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8699 // branch in delay slot?
8700 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8701 // don't handle first branch and call interpreter if it's hit
8702 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8705 // basic load delay detection
8706 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8707 int t=(ba[i-1]-start)/4;
8708 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8709 // jump target wants DS result - potential load delay effect
8710 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8712 bt[t+1]=1; // expected return from interpreter
8714 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8715 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8716 // v0 overwrite like this is a sign of trouble, bail out
8717 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8723 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8727 i--; // don't compile the DS
8731 /* Is this the end of the block? */
8732 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8733 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8737 if(stop_after_jal) done=1;
8739 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8741 // Don't recompile stuff that's already compiled
8742 if(check_addr(start+i*4+4)) done=1;
8743 // Don't get too close to the limit
8744 if(i>MAXBLOCK/2) done=1;
8746 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8747 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8749 // Does the block continue due to a branch?
8752 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8753 if(ba[j]==start+i*4+4) done=j=0;
8754 if(ba[j]==start+i*4+8) done=j=0;
8757 //assert(i<MAXBLOCK-1);
8758 if(start+i*4==pagelimit-4) done=1;
8759 assert(start+i*4<pagelimit);
8760 if (i==MAXBLOCK-1) done=1;
8761 // Stop if we're compiling junk
8762 if(itype[i]==NI&&opcode[i]==0x11) {
8763 done=stop_after_jal=1;
8764 printf("Disabled speculative precompilation\n");
8768 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8769 if(start+i*4==pagelimit) {
8775 /* Pass 2 - Register dependencies and branch targets */
8777 unneeded_registers(0,slen-1,0);
8779 /* Pass 3 - Register allocation */
8781 struct regstat current; // Current register allocations/status
8784 current.u=unneeded_reg[0];
8785 current.uu=unneeded_reg_upper[0];
8786 clear_all_regs(current.regmap);
8787 alloc_reg(¤t,0,CCREG);
8788 dirty_reg(¤t,CCREG);
8791 current.waswritten=0;
8797 provisional_32bit();
8800 // First instruction is delay slot
8805 unneeded_reg_upper[0]=1;
8806 current.regmap[HOST_BTREG]=BTREG;
8814 for(hr=0;hr<HOST_REGS;hr++)
8816 // Is this really necessary?
8817 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8820 current.waswritten=0;
8824 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8826 if(rs1[i-2]==0||rs2[i-2]==0)
8829 current.is32|=1LL<<rs1[i-2];
8830 int hr=get_reg(current.regmap,rs1[i-2]|64);
8831 if(hr>=0) current.regmap[hr]=-1;
8834 current.is32|=1LL<<rs2[i-2];
8835 int hr=get_reg(current.regmap,rs2[i-2]|64);
8836 if(hr>=0) current.regmap[hr]=-1;
8842 // If something jumps here with 64-bit values
8843 // then promote those registers to 64 bits
8846 uint64_t temp_is32=current.is32;
8849 if(ba[j]==start+i*4)
8850 temp_is32&=branch_regs[j].is32;
8854 if(ba[j]==start+i*4)
8858 if(temp_is32!=current.is32) {
8859 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8860 #ifndef DESTRUCTIVE_WRITEBACK
8863 for(hr=0;hr<HOST_REGS;hr++)
8865 int r=current.regmap[hr];
8868 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8870 //printf("restore %d\n",r);
8874 current.is32=temp_is32;
8881 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8882 regs[i].wasconst=current.isconst;
8883 regs[i].was32=current.is32;
8884 regs[i].wasdirty=current.dirty;
8885 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8886 // To change a dirty register from 32 to 64 bits, we must write
8887 // it out during the previous cycle (for branches, 2 cycles)
8888 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8890 uint64_t temp_is32=current.is32;
8893 if(ba[j]==start+i*4+4)
8894 temp_is32&=branch_regs[j].is32;
8898 if(ba[j]==start+i*4+4)
8902 if(temp_is32!=current.is32) {
8903 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8904 for(hr=0;hr<HOST_REGS;hr++)
8906 int r=current.regmap[hr];
8909 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8910 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8912 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8914 //printf("dump %d/r%d\n",hr,r);
8915 current.regmap[hr]=-1;
8916 if(get_reg(current.regmap,r|64)>=0)
8917 current.regmap[get_reg(current.regmap,r|64)]=-1;
8925 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8927 uint64_t temp_is32=current.is32;
8930 if(ba[j]==start+i*4+8)
8931 temp_is32&=branch_regs[j].is32;
8935 if(ba[j]==start+i*4+8)
8939 if(temp_is32!=current.is32) {
8940 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8941 for(hr=0;hr<HOST_REGS;hr++)
8943 int r=current.regmap[hr];
8946 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8947 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8949 //printf("dump %d/r%d\n",hr,r);
8950 current.regmap[hr]=-1;
8951 if(get_reg(current.regmap,r|64)>=0)
8952 current.regmap[get_reg(current.regmap,r|64)]=-1;
8960 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8962 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8963 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8964 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8973 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8974 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8975 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8976 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8977 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8980 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8984 ds=0; // Skip delay slot, already allocated as part of branch
8985 // ...but we need to alloc it in case something jumps here
8987 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8988 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8990 current.u=branch_unneeded_reg[i-1];
8991 current.uu=branch_unneeded_reg_upper[i-1];
8993 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8994 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8995 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8998 struct regstat temp;
8999 memcpy(&temp,¤t,sizeof(current));
9000 temp.wasdirty=temp.dirty;
9001 temp.was32=temp.is32;
9002 // TODO: Take into account unconditional branches, as below
9003 delayslot_alloc(&temp,i);
9004 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
9005 regs[i].wasdirty=temp.wasdirty;
9006 regs[i].was32=temp.was32;
9007 regs[i].dirty=temp.dirty;
9008 regs[i].is32=temp.is32;
9012 // Create entry (branch target) regmap
9013 for(hr=0;hr<HOST_REGS;hr++)
9015 int r=temp.regmap[hr];
9017 if(r!=regmap_pre[i][hr]) {
9018 regs[i].regmap_entry[hr]=-1;
9023 if((current.u>>r)&1) {
9024 regs[i].regmap_entry[hr]=-1;
9025 regs[i].regmap[hr]=-1;
9026 //Don't clear regs in the delay slot as the branch might need them
9027 //current.regmap[hr]=-1;
9029 regs[i].regmap_entry[hr]=r;
9032 if((current.uu>>(r&63))&1) {
9033 regs[i].regmap_entry[hr]=-1;
9034 regs[i].regmap[hr]=-1;
9035 //Don't clear regs in the delay slot as the branch might need them
9036 //current.regmap[hr]=-1;
9038 regs[i].regmap_entry[hr]=r;
9042 // First instruction expects CCREG to be allocated
9043 if(i==0&&hr==HOST_CCREG)
9044 regs[i].regmap_entry[hr]=CCREG;
9046 regs[i].regmap_entry[hr]=-1;
9050 else { // Not delay slot
9053 //current.isconst=0; // DEBUG
9054 //current.wasconst=0; // DEBUG
9055 //regs[i].wasconst=0; // DEBUG
9056 clear_const(¤t,rt1[i]);
9057 alloc_cc(¤t,i);
9058 dirty_reg(¤t,CCREG);
9060 alloc_reg(¤t,i,31);
9061 dirty_reg(¤t,31);
9062 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9063 //assert(rt1[i+1]!=rt1[i]);
9065 alloc_reg(¤t,i,PTEMP);
9067 //current.is32|=1LL<<rt1[i];
9070 delayslot_alloc(¤t,i+1);
9071 //current.isconst=0; // DEBUG
9073 //printf("i=%d, isconst=%x\n",i,current.isconst);
9076 //current.isconst=0;
9077 //current.wasconst=0;
9078 //regs[i].wasconst=0;
9079 clear_const(¤t,rs1[i]);
9080 clear_const(¤t,rt1[i]);
9081 alloc_cc(¤t,i);
9082 dirty_reg(¤t,CCREG);
9083 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9084 alloc_reg(¤t,i,rs1[i]);
9086 alloc_reg(¤t,i,rt1[i]);
9087 dirty_reg(¤t,rt1[i]);
9088 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9089 assert(rt1[i+1]!=rt1[i]);
9091 alloc_reg(¤t,i,PTEMP);
9095 if(rs1[i]==31) { // JALR
9096 alloc_reg(¤t,i,RHASH);
9097 #ifndef HOST_IMM_ADDR32
9098 alloc_reg(¤t,i,RHTBL);
9102 delayslot_alloc(¤t,i+1);
9104 // The delay slot overwrites our source register,
9105 // allocate a temporary register to hold the old value.
9109 delayslot_alloc(¤t,i+1);
9111 alloc_reg(¤t,i,RTEMP);
9113 //current.isconst=0; // DEBUG
9118 //current.isconst=0;
9119 //current.wasconst=0;
9120 //regs[i].wasconst=0;
9121 clear_const(¤t,rs1[i]);
9122 clear_const(¤t,rs2[i]);
9123 if((opcode[i]&0x3E)==4) // BEQ/BNE
9125 alloc_cc(¤t,i);
9126 dirty_reg(¤t,CCREG);
9127 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9128 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9129 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9131 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9132 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9134 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9135 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9136 // The delay slot overwrites one of our conditions.
9137 // Allocate the branch condition registers instead.
9141 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9142 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9143 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9145 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9146 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9152 delayslot_alloc(¤t,i+1);
9156 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9158 alloc_cc(¤t,i);
9159 dirty_reg(¤t,CCREG);
9160 alloc_reg(¤t,i,rs1[i]);
9161 if(!(current.is32>>rs1[i]&1))
9163 alloc_reg64(¤t,i,rs1[i]);
9165 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9166 // The delay slot overwrites one of our conditions.
9167 // Allocate the branch condition registers instead.
9171 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9172 if(!((current.is32>>rs1[i])&1))
9174 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9180 delayslot_alloc(¤t,i+1);
9184 // Don't alloc the delay slot yet because we might not execute it
9185 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9190 alloc_cc(¤t,i);
9191 dirty_reg(¤t,CCREG);
9192 alloc_reg(¤t,i,rs1[i]);
9193 alloc_reg(¤t,i,rs2[i]);
9194 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9196 alloc_reg64(¤t,i,rs1[i]);
9197 alloc_reg64(¤t,i,rs2[i]);
9201 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9206 alloc_cc(¤t,i);
9207 dirty_reg(¤t,CCREG);
9208 alloc_reg(¤t,i,rs1[i]);
9209 if(!(current.is32>>rs1[i]&1))
9211 alloc_reg64(¤t,i,rs1[i]);
9215 //current.isconst=0;
9218 //current.isconst=0;
9219 //current.wasconst=0;
9220 //regs[i].wasconst=0;
9221 clear_const(¤t,rs1[i]);
9222 clear_const(¤t,rt1[i]);
9223 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9224 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9226 alloc_cc(¤t,i);
9227 dirty_reg(¤t,CCREG);
9228 alloc_reg(¤t,i,rs1[i]);
9229 if(!(current.is32>>rs1[i]&1))
9231 alloc_reg64(¤t,i,rs1[i]);
9233 if (rt1[i]==31) { // BLTZAL/BGEZAL
9234 alloc_reg(¤t,i,31);
9235 dirty_reg(¤t,31);
9236 //#ifdef REG_PREFETCH
9237 //alloc_reg(¤t,i,PTEMP);
9239 //current.is32|=1LL<<rt1[i];
9241 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9242 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9243 // Allocate the branch condition registers instead.
9247 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9248 if(!((current.is32>>rs1[i])&1))
9250 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9256 delayslot_alloc(¤t,i+1);
9260 // Don't alloc the delay slot yet because we might not execute it
9261 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9266 alloc_cc(¤t,i);
9267 dirty_reg(¤t,CCREG);
9268 alloc_reg(¤t,i,rs1[i]);
9269 if(!(current.is32>>rs1[i]&1))
9271 alloc_reg64(¤t,i,rs1[i]);
9275 //current.isconst=0;
9281 if(likely[i]==0) // BC1F/BC1T
9283 // TODO: Theoretically we can run out of registers here on x86.
9284 // The delay slot can allocate up to six, and we need to check
9285 // CSREG before executing the delay slot. Possibly we can drop
9286 // the cycle count and then reload it after checking that the
9287 // FPU is in a usable state, or don't do out-of-order execution.
9288 alloc_cc(¤t,i);
9289 dirty_reg(¤t,CCREG);
9290 alloc_reg(¤t,i,FSREG);
9291 alloc_reg(¤t,i,CSREG);
9292 if(itype[i+1]==FCOMP) {
9293 // The delay slot overwrites the branch condition.
9294 // Allocate the branch condition registers instead.
9295 alloc_cc(¤t,i);
9296 dirty_reg(¤t,CCREG);
9297 alloc_reg(¤t,i,CSREG);
9298 alloc_reg(¤t,i,FSREG);
9302 delayslot_alloc(¤t,i+1);
9303 alloc_reg(¤t,i+1,CSREG);
9307 // Don't alloc the delay slot yet because we might not execute it
9308 if(likely[i]) // BC1FL/BC1TL
9310 alloc_cc(¤t,i);
9311 dirty_reg(¤t,CCREG);
9312 alloc_reg(¤t,i,CSREG);
9313 alloc_reg(¤t,i,FSREG);
9319 imm16_alloc(¤t,i);
9323 load_alloc(¤t,i);
9327 store_alloc(¤t,i);
9330 alu_alloc(¤t,i);
9333 shift_alloc(¤t,i);
9336 multdiv_alloc(¤t,i);
9339 shiftimm_alloc(¤t,i);
9342 mov_alloc(¤t,i);
9345 cop0_alloc(¤t,i);
9349 cop1_alloc(¤t,i);
9352 c1ls_alloc(¤t,i);
9355 c2ls_alloc(¤t,i);
9358 c2op_alloc(¤t,i);
9361 fconv_alloc(¤t,i);
9364 float_alloc(¤t,i);
9367 fcomp_alloc(¤t,i);
9372 syscall_alloc(¤t,i);
9375 pagespan_alloc(¤t,i);
9379 // Drop the upper half of registers that have become 32-bit
9380 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9381 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9382 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9383 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9386 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9387 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9388 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9389 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9393 // Create entry (branch target) regmap
9394 for(hr=0;hr<HOST_REGS;hr++)
9397 r=current.regmap[hr];
9399 if(r!=regmap_pre[i][hr]) {
9400 // TODO: delay slot (?)
9401 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9402 if(or<0||(r&63)>=TEMPREG){
9403 regs[i].regmap_entry[hr]=-1;
9407 // Just move it to a different register
9408 regs[i].regmap_entry[hr]=r;
9409 // If it was dirty before, it's still dirty
9410 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9417 regs[i].regmap_entry[hr]=0;
9421 if((current.u>>r)&1) {
9422 regs[i].regmap_entry[hr]=-1;
9423 //regs[i].regmap[hr]=-1;
9424 current.regmap[hr]=-1;
9426 regs[i].regmap_entry[hr]=r;
9429 if((current.uu>>(r&63))&1) {
9430 regs[i].regmap_entry[hr]=-1;
9431 //regs[i].regmap[hr]=-1;
9432 current.regmap[hr]=-1;
9434 regs[i].regmap_entry[hr]=r;
9438 // Branches expect CCREG to be allocated at the target
9439 if(regmap_pre[i][hr]==CCREG)
9440 regs[i].regmap_entry[hr]=CCREG;
9442 regs[i].regmap_entry[hr]=-1;
9445 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9448 if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
9449 current.waswritten|=1<<rs1[i-1];
9450 current.waswritten&=~(1<<rt1[i]);
9451 current.waswritten&=~(1<<rt2[i]);
9452 if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
9453 current.waswritten&=~(1<<rs1[i]);
9455 /* Branch post-alloc */
9458 current.was32=current.is32;
9459 current.wasdirty=current.dirty;
9460 switch(itype[i-1]) {
9462 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9463 branch_regs[i-1].isconst=0;
9464 branch_regs[i-1].wasconst=0;
9465 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9466 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9467 alloc_cc(&branch_regs[i-1],i-1);
9468 dirty_reg(&branch_regs[i-1],CCREG);
9469 if(rt1[i-1]==31) { // JAL
9470 alloc_reg(&branch_regs[i-1],i-1,31);
9471 dirty_reg(&branch_regs[i-1],31);
9472 branch_regs[i-1].is32|=1LL<<31;
9474 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9475 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9478 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9479 branch_regs[i-1].isconst=0;
9480 branch_regs[i-1].wasconst=0;
9481 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9482 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9483 alloc_cc(&branch_regs[i-1],i-1);
9484 dirty_reg(&branch_regs[i-1],CCREG);
9485 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9486 if(rt1[i-1]!=0) { // JALR
9487 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9488 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9489 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9492 if(rs1[i-1]==31) { // JALR
9493 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9494 #ifndef HOST_IMM_ADDR32
9495 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9499 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9500 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9503 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9505 alloc_cc(¤t,i-1);
9506 dirty_reg(¤t,CCREG);
9507 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9508 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9509 // The delay slot overwrote one of our conditions
9510 // Delay slot goes after the test (in order)
9511 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9512 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9513 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9516 delayslot_alloc(¤t,i);
9521 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9522 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9523 // Alloc the branch condition registers
9524 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9525 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9526 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9528 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9529 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9532 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9533 branch_regs[i-1].isconst=0;
9534 branch_regs[i-1].wasconst=0;
9535 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9536 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9539 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9541 alloc_cc(¤t,i-1);
9542 dirty_reg(¤t,CCREG);
9543 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9544 // The delay slot overwrote the branch condition
9545 // Delay slot goes after the test (in order)
9546 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9547 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9548 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9551 delayslot_alloc(¤t,i);
9556 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9557 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9558 // Alloc the branch condition register
9559 alloc_reg(¤t,i-1,rs1[i-1]);
9560 if(!(current.is32>>rs1[i-1]&1))
9562 alloc_reg64(¤t,i-1,rs1[i-1]);
9565 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9566 branch_regs[i-1].isconst=0;
9567 branch_regs[i-1].wasconst=0;
9568 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9569 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9572 // Alloc the delay slot in case the branch is taken
9573 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9575 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9576 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9577 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9578 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9579 alloc_cc(&branch_regs[i-1],i);
9580 dirty_reg(&branch_regs[i-1],CCREG);
9581 delayslot_alloc(&branch_regs[i-1],i);
9582 branch_regs[i-1].isconst=0;
9583 alloc_reg(¤t,i,CCREG); // Not taken path
9584 dirty_reg(¤t,CCREG);
9585 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9588 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9590 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9591 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9592 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9593 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9594 alloc_cc(&branch_regs[i-1],i);
9595 dirty_reg(&branch_regs[i-1],CCREG);
9596 delayslot_alloc(&branch_regs[i-1],i);
9597 branch_regs[i-1].isconst=0;
9598 alloc_reg(¤t,i,CCREG); // Not taken path
9599 dirty_reg(¤t,CCREG);
9600 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9604 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9605 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9607 alloc_cc(¤t,i-1);
9608 dirty_reg(¤t,CCREG);
9609 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9610 // The delay slot overwrote the branch condition
9611 // Delay slot goes after the test (in order)
9612 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9613 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9614 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9617 delayslot_alloc(¤t,i);
9622 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9623 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9624 // Alloc the branch condition register
9625 alloc_reg(¤t,i-1,rs1[i-1]);
9626 if(!(current.is32>>rs1[i-1]&1))
9628 alloc_reg64(¤t,i-1,rs1[i-1]);
9631 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9632 branch_regs[i-1].isconst=0;
9633 branch_regs[i-1].wasconst=0;
9634 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9635 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9638 // Alloc the delay slot in case the branch is taken
9639 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9641 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9642 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9643 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9644 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9645 alloc_cc(&branch_regs[i-1],i);
9646 dirty_reg(&branch_regs[i-1],CCREG);
9647 delayslot_alloc(&branch_regs[i-1],i);
9648 branch_regs[i-1].isconst=0;
9649 alloc_reg(¤t,i,CCREG); // Not taken path
9650 dirty_reg(¤t,CCREG);
9651 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9653 // FIXME: BLTZAL/BGEZAL
9654 if(opcode2[i-1]&0x10) { // BxxZAL
9655 alloc_reg(&branch_regs[i-1],i-1,31);
9656 dirty_reg(&branch_regs[i-1],31);
9657 branch_regs[i-1].is32|=1LL<<31;
9661 if(likely[i-1]==0) // BC1F/BC1T
9663 alloc_cc(¤t,i-1);
9664 dirty_reg(¤t,CCREG);
9665 if(itype[i]==FCOMP) {
9666 // The delay slot overwrote the branch condition
9667 // Delay slot goes after the test (in order)
9668 delayslot_alloc(¤t,i);
9673 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9674 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9675 // Alloc the branch condition register
9676 alloc_reg(¤t,i-1,FSREG);
9678 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9679 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9683 // Alloc the delay slot in case the branch is taken
9684 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9685 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9686 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9687 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9688 alloc_cc(&branch_regs[i-1],i);
9689 dirty_reg(&branch_regs[i-1],CCREG);
9690 delayslot_alloc(&branch_regs[i-1],i);
9691 branch_regs[i-1].isconst=0;
9692 alloc_reg(¤t,i,CCREG); // Not taken path
9693 dirty_reg(¤t,CCREG);
9694 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9699 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9701 if(rt1[i-1]==31) // JAL/JALR
9703 // Subroutine call will return here, don't alloc any registers
9706 clear_all_regs(current.regmap);
9707 alloc_reg(¤t,i,CCREG);
9708 dirty_reg(¤t,CCREG);
9712 // Internal branch will jump here, match registers to caller
9713 current.is32=0x3FFFFFFFFLL;
9715 clear_all_regs(current.regmap);
9716 alloc_reg(¤t,i,CCREG);
9717 dirty_reg(¤t,CCREG);
9720 if(ba[j]==start+i*4+4) {
9721 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9722 current.is32=branch_regs[j].is32;
9723 current.dirty=branch_regs[j].dirty;
9728 if(ba[j]==start+i*4+4) {
9729 for(hr=0;hr<HOST_REGS;hr++) {
9730 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9731 current.regmap[hr]=-1;
9733 current.is32&=branch_regs[j].is32;
9734 current.dirty&=branch_regs[j].dirty;
9743 // Count cycles in between branches
9745 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9750 else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2)
9752 // GTE runs in parallel until accessed, divide by 2 for a rough guess
9753 cc+=gte_cycletab[source[i]&0x3f]/2;
9755 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9757 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9759 else if(itype[i]==C2LS)
9769 flush_dirty_uppers(¤t);
9771 regs[i].is32=current.is32;
9772 regs[i].dirty=current.dirty;
9773 regs[i].isconst=current.isconst;
9774 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9776 for(hr=0;hr<HOST_REGS;hr++) {
9777 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9778 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9779 regs[i].wasconst&=~(1<<hr);
9783 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9784 regs[i].waswritten=current.waswritten;
9787 /* Pass 4 - Cull unused host registers */
9791 for (i=slen-1;i>=0;i--)
9794 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9796 if(ba[i]<start || ba[i]>=(start+slen*4))
9798 // Branch out of this block, don't need anything
9804 // Need whatever matches the target
9806 int t=(ba[i]-start)>>2;
9807 for(hr=0;hr<HOST_REGS;hr++)
9809 if(regs[i].regmap_entry[hr]>=0) {
9810 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9814 // Conditional branch may need registers for following instructions
9815 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9818 nr|=needed_reg[i+2];
9819 for(hr=0;hr<HOST_REGS;hr++)
9821 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9822 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9826 // Don't need stuff which is overwritten
9827 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9828 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9829 // Merge in delay slot
9830 for(hr=0;hr<HOST_REGS;hr++)
9833 // These are overwritten unless the branch is "likely"
9834 // and the delay slot is nullified if not taken
9835 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9836 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9838 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9839 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9840 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9841 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9842 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9843 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9844 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9845 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9846 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9847 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9848 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9850 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9851 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9852 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9854 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9855 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9856 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9860 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9862 // SYSCALL instruction (software interrupt)
9865 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9867 // ERET instruction (return from interrupt)
9873 for(hr=0;hr<HOST_REGS;hr++) {
9874 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9875 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9876 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9877 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9881 for(hr=0;hr<HOST_REGS;hr++)
9883 // Overwritten registers are not needed
9884 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9885 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9886 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9887 // Source registers are needed
9888 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9889 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9890 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9891 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9892 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9893 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9894 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9895 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9896 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9897 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9898 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9900 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9901 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9902 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9904 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9905 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9906 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9908 // Don't store a register immediately after writing it,
9909 // may prevent dual-issue.
9910 // But do so if this is a branch target, otherwise we
9911 // might have to load the register before the branch.
9912 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9913 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9914 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9915 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9916 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9918 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9919 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9920 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9921 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9925 // Cycle count is needed at branches. Assume it is needed at the target too.
9926 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9927 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9928 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9933 // Deallocate unneeded registers
9934 for(hr=0;hr<HOST_REGS;hr++)
9937 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9938 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9939 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9940 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9942 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9945 regs[i].regmap[hr]=-1;
9946 regs[i].isconst&=~(1<<hr);
9948 regmap_pre[i+2][hr]=-1;
9949 regs[i+2].wasconst&=~(1<<hr);
9954 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9956 int d1=0,d2=0,map=0,temp=0;
9957 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9963 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9964 itype[i+1]==STORE || itype[i+1]==STORELR ||
9965 itype[i+1]==C1LS || itype[i+1]==C2LS)
9968 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9969 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9972 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9973 itype[i+1]==C1LS || itype[i+1]==C2LS)
9975 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9976 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9977 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9978 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9979 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9980 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9981 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9982 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9983 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9984 regs[i].regmap[hr]!=map )
9986 regs[i].regmap[hr]=-1;
9987 regs[i].isconst&=~(1<<hr);
9988 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9989 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9990 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9991 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9992 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9993 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9994 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9995 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9996 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9997 branch_regs[i].regmap[hr]!=map)
9999 branch_regs[i].regmap[hr]=-1;
10000 branch_regs[i].regmap_entry[hr]=-1;
10001 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10003 if(!likely[i]&&i<slen-2) {
10004 regmap_pre[i+2][hr]=-1;
10005 regs[i+2].wasconst&=~(1<<hr);
10016 int d1=0,d2=0,map=-1,temp=-1;
10017 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
10023 if(itype[i]==LOAD || itype[i]==LOADLR ||
10024 itype[i]==STORE || itype[i]==STORELR ||
10025 itype[i]==C1LS || itype[i]==C2LS)
10027 } else if(itype[i]==STORE || itype[i]==STORELR ||
10028 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10031 if(itype[i]==LOADLR || itype[i]==STORELR ||
10032 itype[i]==C1LS || itype[i]==C2LS)
10034 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10035 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10036 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10037 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10038 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10039 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10041 if(i<slen-1&&!is_ds[i]) {
10042 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10043 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10044 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10046 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10047 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10049 regmap_pre[i+1][hr]=-1;
10050 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10051 regs[i+1].wasconst&=~(1<<hr);
10053 regs[i].regmap[hr]=-1;
10054 regs[i].isconst&=~(1<<hr);
10062 /* Pass 5 - Pre-allocate registers */
10064 // If a register is allocated during a loop, try to allocate it for the
10065 // entire loop, if possible. This avoids loading/storing registers
10066 // inside of the loop.
10068 signed char f_regmap[HOST_REGS];
10069 clear_all_regs(f_regmap);
10070 for(i=0;i<slen-1;i++)
10072 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10074 if(ba[i]>=start && ba[i]<(start+i*4))
10075 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10076 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10077 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10078 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10079 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10080 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10082 int t=(ba[i]-start)>>2;
10083 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10084 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10085 for(hr=0;hr<HOST_REGS;hr++)
10087 if(regs[i].regmap[hr]>64) {
10088 if(!((regs[i].dirty>>hr)&1))
10089 f_regmap[hr]=regs[i].regmap[hr];
10090 else f_regmap[hr]=-1;
10092 else if(regs[i].regmap[hr]>=0) {
10093 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10094 // dealloc old register
10096 for(n=0;n<HOST_REGS;n++)
10098 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10100 // and alloc new one
10101 f_regmap[hr]=regs[i].regmap[hr];
10104 if(branch_regs[i].regmap[hr]>64) {
10105 if(!((branch_regs[i].dirty>>hr)&1))
10106 f_regmap[hr]=branch_regs[i].regmap[hr];
10107 else f_regmap[hr]=-1;
10109 else if(branch_regs[i].regmap[hr]>=0) {
10110 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10111 // dealloc old register
10113 for(n=0;n<HOST_REGS;n++)
10115 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10117 // and alloc new one
10118 f_regmap[hr]=branch_regs[i].regmap[hr];
10122 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10123 f_regmap[hr]=branch_regs[i].regmap[hr];
10125 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10126 f_regmap[hr]=branch_regs[i].regmap[hr];
10128 // Avoid dirty->clean transition
10129 #ifdef DESTRUCTIVE_WRITEBACK
10130 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10132 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10133 // case above, however it's always a good idea. We can't hoist the
10134 // load if the register was already allocated, so there's no point
10135 // wasting time analyzing most of these cases. It only "succeeds"
10136 // when the mapping was different and the load can be replaced with
10137 // a mov, which is of negligible benefit. So such cases are
10139 if(f_regmap[hr]>0) {
10140 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10141 int r=f_regmap[hr];
10144 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10145 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10146 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10148 // NB This can exclude the case where the upper-half
10149 // register is lower numbered than the lower-half
10150 // register. Not sure if it's worth fixing...
10151 if(get_reg(regs[j].regmap,r&63)<0) break;
10152 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10153 if(regs[j].is32&(1LL<<(r&63))) break;
10155 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10156 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10158 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10159 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10161 if(get_reg(regs[i].regmap,r&63)<0) break;
10162 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10165 while(k>1&®s[k-1].regmap[hr]==-1) {
10166 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10167 //printf("no free regs for store %x\n",start+(k-1)*4);
10170 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10171 //printf("no-match due to different register\n");
10174 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10175 //printf("no-match due to branch\n");
10178 // call/ret fast path assumes no registers allocated
10179 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10183 // NB This can exclude the case where the upper-half
10184 // register is lower numbered than the lower-half
10185 // register. Not sure if it's worth fixing...
10186 if(get_reg(regs[k-1].regmap,r&63)<0) break;
10187 if(regs[k-1].is32&(1LL<<(r&63))) break;
10192 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10193 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10194 //printf("bad match after branch\n");
10198 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
10199 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10201 regs[k].regmap_entry[hr]=f_regmap[hr];
10202 regs[k].regmap[hr]=f_regmap[hr];
10203 regmap_pre[k+1][hr]=f_regmap[hr];
10204 regs[k].wasdirty&=~(1<<hr);
10205 regs[k].dirty&=~(1<<hr);
10206 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
10207 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
10208 regs[k].wasconst&=~(1<<hr);
10209 regs[k].isconst&=~(1<<hr);
10214 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10217 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10218 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
10219 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10220 regs[i].regmap_entry[hr]=f_regmap[hr];
10221 regs[i].regmap[hr]=f_regmap[hr];
10222 regs[i].wasdirty&=~(1<<hr);
10223 regs[i].dirty&=~(1<<hr);
10224 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
10225 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
10226 regs[i].wasconst&=~(1<<hr);
10227 regs[i].isconst&=~(1<<hr);
10228 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10229 branch_regs[i].wasdirty&=~(1<<hr);
10230 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
10231 branch_regs[i].regmap[hr]=f_regmap[hr];
10232 branch_regs[i].dirty&=~(1<<hr);
10233 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
10234 branch_regs[i].wasconst&=~(1<<hr);
10235 branch_regs[i].isconst&=~(1<<hr);
10236 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10237 regmap_pre[i+2][hr]=f_regmap[hr];
10238 regs[i+2].wasdirty&=~(1<<hr);
10239 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
10240 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10241 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10246 // Alloc register clean at beginning of loop,
10247 // but may dirty it in pass 6
10248 regs[k].regmap_entry[hr]=f_regmap[hr];
10249 regs[k].regmap[hr]=f_regmap[hr];
10250 regs[k].dirty&=~(1<<hr);
10251 regs[k].wasconst&=~(1<<hr);
10252 regs[k].isconst&=~(1<<hr);
10253 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10254 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10255 branch_regs[k].regmap[hr]=f_regmap[hr];
10256 branch_regs[k].dirty&=~(1<<hr);
10257 branch_regs[k].wasconst&=~(1<<hr);
10258 branch_regs[k].isconst&=~(1<<hr);
10259 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10260 regmap_pre[k+2][hr]=f_regmap[hr];
10261 regs[k+2].wasdirty&=~(1<<hr);
10262 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10263 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10268 regmap_pre[k+1][hr]=f_regmap[hr];
10269 regs[k+1].wasdirty&=~(1<<hr);
10272 if(regs[j].regmap[hr]==f_regmap[hr])
10273 regs[j].regmap_entry[hr]=f_regmap[hr];
10277 if(regs[j].regmap[hr]>=0)
10279 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10280 //printf("no-match due to different register\n");
10283 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10284 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10287 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10289 // Stop on unconditional branch
10292 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10295 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10298 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10301 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10302 //printf("no-match due to different register (branch)\n");
10306 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10307 //printf("No free regs for store %x\n",start+j*4);
10310 if(f_regmap[hr]>=64) {
10311 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10316 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10327 // Non branch or undetermined branch target
10328 for(hr=0;hr<HOST_REGS;hr++)
10330 if(hr!=EXCLUDE_REG) {
10331 if(regs[i].regmap[hr]>64) {
10332 if(!((regs[i].dirty>>hr)&1))
10333 f_regmap[hr]=regs[i].regmap[hr];
10335 else if(regs[i].regmap[hr]>=0) {
10336 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10337 // dealloc old register
10339 for(n=0;n<HOST_REGS;n++)
10341 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10343 // and alloc new one
10344 f_regmap[hr]=regs[i].regmap[hr];
10349 // Try to restore cycle count at branch targets
10351 for(j=i;j<slen-1;j++) {
10352 if(regs[j].regmap[HOST_CCREG]!=-1) break;
10353 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10354 //printf("no free regs for store %x\n",start+j*4);
10358 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10360 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10362 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10363 regs[k].regmap[HOST_CCREG]=CCREG;
10364 regmap_pre[k+1][HOST_CCREG]=CCREG;
10365 regs[k+1].wasdirty|=1<<HOST_CCREG;
10366 regs[k].dirty|=1<<HOST_CCREG;
10367 regs[k].wasconst&=~(1<<HOST_CCREG);
10368 regs[k].isconst&=~(1<<HOST_CCREG);
10371 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10373 // Work backwards from the branch target
10374 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10376 //printf("Extend backwards\n");
10379 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10380 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10381 //printf("no free regs for store %x\n",start+(k-1)*4);
10386 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10387 //printf("Extend CC, %x ->\n",start+k*4);
10389 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10390 regs[k].regmap[HOST_CCREG]=CCREG;
10391 regmap_pre[k+1][HOST_CCREG]=CCREG;
10392 regs[k+1].wasdirty|=1<<HOST_CCREG;
10393 regs[k].dirty|=1<<HOST_CCREG;
10394 regs[k].wasconst&=~(1<<HOST_CCREG);
10395 regs[k].isconst&=~(1<<HOST_CCREG);
10400 //printf("Fail Extend CC, %x ->\n",start+k*4);
10404 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10405 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10406 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10407 itype[i]!=FCONV&&itype[i]!=FCOMP)
10409 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10414 // Cache memory offset or tlb map pointer if a register is available
10415 #ifndef HOST_IMM_ADDR32
10420 int earliest_available[HOST_REGS];
10421 int loop_start[HOST_REGS];
10422 int score[HOST_REGS];
10423 int end[HOST_REGS];
10424 int reg=using_tlb?MMREG:ROREG;
10427 for(hr=0;hr<HOST_REGS;hr++) {
10428 score[hr]=0;earliest_available[hr]=0;
10429 loop_start[hr]=MAXBLOCK;
10431 for(i=0;i<slen-1;i++)
10433 // Can't do anything if no registers are available
10434 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10435 for(hr=0;hr<HOST_REGS;hr++) {
10436 score[hr]=0;earliest_available[hr]=i+1;
10437 loop_start[hr]=MAXBLOCK;
10440 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10442 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10443 for(hr=0;hr<HOST_REGS;hr++) {
10444 score[hr]=0;earliest_available[hr]=i+1;
10445 loop_start[hr]=MAXBLOCK;
10449 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10450 for(hr=0;hr<HOST_REGS;hr++) {
10451 score[hr]=0;earliest_available[hr]=i+1;
10452 loop_start[hr]=MAXBLOCK;
10457 // Mark unavailable registers
10458 for(hr=0;hr<HOST_REGS;hr++) {
10459 if(regs[i].regmap[hr]>=0) {
10460 score[hr]=0;earliest_available[hr]=i+1;
10461 loop_start[hr]=MAXBLOCK;
10463 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10464 if(branch_regs[i].regmap[hr]>=0) {
10465 score[hr]=0;earliest_available[hr]=i+2;
10466 loop_start[hr]=MAXBLOCK;
10470 // No register allocations after unconditional jumps
10471 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10473 for(hr=0;hr<HOST_REGS;hr++) {
10474 score[hr]=0;earliest_available[hr]=i+2;
10475 loop_start[hr]=MAXBLOCK;
10477 i++; // Skip delay slot too
10478 //printf("skip delay slot: %x\n",start+i*4);
10482 if(itype[i]==LOAD||itype[i]==LOADLR||
10483 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10484 for(hr=0;hr<HOST_REGS;hr++) {
10485 if(hr!=EXCLUDE_REG) {
10487 for(j=i;j<slen-1;j++) {
10488 if(regs[j].regmap[hr]>=0) break;
10489 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10490 if(branch_regs[j].regmap[hr]>=0) break;
10492 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10494 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10497 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10498 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10499 int t=(ba[j]-start)>>2;
10500 if(t<j&&t>=earliest_available[hr]) {
10501 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10502 // Score a point for hoisting loop invariant
10503 if(t<loop_start[hr]) loop_start[hr]=t;
10504 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10510 if(regs[t].regmap[hr]==reg) {
10511 // Score a point if the branch target matches this register
10516 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10517 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10522 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10524 // Stop on unconditional branch
10528 if(itype[j]==LOAD||itype[j]==LOADLR||
10529 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10536 // Find highest score and allocate that register
10538 for(hr=0;hr<HOST_REGS;hr++) {
10539 if(hr!=EXCLUDE_REG) {
10540 if(score[hr]>score[maxscore]) {
10542 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10546 if(score[maxscore]>1)
10548 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10549 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10550 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10551 assert(regs[j].regmap[maxscore]<0);
10552 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10553 regs[j].regmap[maxscore]=reg;
10554 regs[j].dirty&=~(1<<maxscore);
10555 regs[j].wasconst&=~(1<<maxscore);
10556 regs[j].isconst&=~(1<<maxscore);
10557 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10558 branch_regs[j].regmap[maxscore]=reg;
10559 branch_regs[j].wasdirty&=~(1<<maxscore);
10560 branch_regs[j].dirty&=~(1<<maxscore);
10561 branch_regs[j].wasconst&=~(1<<maxscore);
10562 branch_regs[j].isconst&=~(1<<maxscore);
10563 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10564 regmap_pre[j+2][maxscore]=reg;
10565 regs[j+2].wasdirty&=~(1<<maxscore);
10567 // loop optimization (loop_preload)
10568 int t=(ba[j]-start)>>2;
10569 if(t==loop_start[maxscore]) {
10570 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10571 regs[t].regmap_entry[maxscore]=reg;
10576 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10577 regmap_pre[j+1][maxscore]=reg;
10578 regs[j+1].wasdirty&=~(1<<maxscore);
10583 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10584 for(hr=0;hr<HOST_REGS;hr++) {
10585 score[hr]=0;earliest_available[hr]=i+i;
10586 loop_start[hr]=MAXBLOCK;
10594 // This allocates registers (if possible) one instruction prior
10595 // to use, which can avoid a load-use penalty on certain CPUs.
10596 for(i=0;i<slen-1;i++)
10598 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10602 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10603 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10606 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10608 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10610 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10611 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10612 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10613 regs[i].isconst&=~(1<<hr);
10614 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10615 constmap[i][hr]=constmap[i+1][hr];
10616 regs[i+1].wasdirty&=~(1<<hr);
10617 regs[i].dirty&=~(1<<hr);
10622 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10624 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10626 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10627 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10628 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10629 regs[i].isconst&=~(1<<hr);
10630 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10631 constmap[i][hr]=constmap[i+1][hr];
10632 regs[i+1].wasdirty&=~(1<<hr);
10633 regs[i].dirty&=~(1<<hr);
10637 // Preload target address for load instruction (non-constant)
10638 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10639 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10641 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10643 regs[i].regmap[hr]=rs1[i+1];
10644 regmap_pre[i+1][hr]=rs1[i+1];
10645 regs[i+1].regmap_entry[hr]=rs1[i+1];
10646 regs[i].isconst&=~(1<<hr);
10647 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10648 constmap[i][hr]=constmap[i+1][hr];
10649 regs[i+1].wasdirty&=~(1<<hr);
10650 regs[i].dirty&=~(1<<hr);
10654 // Load source into target register
10655 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10656 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10658 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10660 regs[i].regmap[hr]=rs1[i+1];
10661 regmap_pre[i+1][hr]=rs1[i+1];
10662 regs[i+1].regmap_entry[hr]=rs1[i+1];
10663 regs[i].isconst&=~(1<<hr);
10664 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10665 constmap[i][hr]=constmap[i+1][hr];
10666 regs[i+1].wasdirty&=~(1<<hr);
10667 regs[i].dirty&=~(1<<hr);
10671 // Preload map address
10672 #ifndef HOST_IMM_ADDR32
10673 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10674 hr=get_reg(regs[i+1].regmap,TLREG);
10676 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10677 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10679 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10681 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10682 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10683 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10684 regs[i].isconst&=~(1<<hr);
10685 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10686 constmap[i][hr]=constmap[i+1][hr];
10687 regs[i+1].wasdirty&=~(1<<hr);
10688 regs[i].dirty&=~(1<<hr);
10690 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10692 // move it to another register
10693 regs[i+1].regmap[hr]=-1;
10694 regmap_pre[i+2][hr]=-1;
10695 regs[i+1].regmap[nr]=TLREG;
10696 regmap_pre[i+2][nr]=TLREG;
10697 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10698 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10699 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10700 regs[i].isconst&=~(1<<nr);
10701 regs[i+1].isconst&=~(1<<nr);
10702 regs[i].dirty&=~(1<<nr);
10703 regs[i+1].wasdirty&=~(1<<nr);
10704 regs[i+1].dirty&=~(1<<nr);
10705 regs[i+2].wasdirty&=~(1<<nr);
10711 // Address for store instruction (non-constant)
10712 if(itype[i+1]==STORE||itype[i+1]==STORELR
10713 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10714 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10715 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10716 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10717 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10719 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10721 regs[i].regmap[hr]=rs1[i+1];
10722 regmap_pre[i+1][hr]=rs1[i+1];
10723 regs[i+1].regmap_entry[hr]=rs1[i+1];
10724 regs[i].isconst&=~(1<<hr);
10725 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10726 constmap[i][hr]=constmap[i+1][hr];
10727 regs[i+1].wasdirty&=~(1<<hr);
10728 regs[i].dirty&=~(1<<hr);
10732 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10733 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10735 hr=get_reg(regs[i+1].regmap,FTEMP);
10737 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10739 regs[i].regmap[hr]=rs1[i+1];
10740 regmap_pre[i+1][hr]=rs1[i+1];
10741 regs[i+1].regmap_entry[hr]=rs1[i+1];
10742 regs[i].isconst&=~(1<<hr);
10743 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10744 constmap[i][hr]=constmap[i+1][hr];
10745 regs[i+1].wasdirty&=~(1<<hr);
10746 regs[i].dirty&=~(1<<hr);
10748 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10750 // move it to another register
10751 regs[i+1].regmap[hr]=-1;
10752 regmap_pre[i+2][hr]=-1;
10753 regs[i+1].regmap[nr]=FTEMP;
10754 regmap_pre[i+2][nr]=FTEMP;
10755 regs[i].regmap[nr]=rs1[i+1];
10756 regmap_pre[i+1][nr]=rs1[i+1];
10757 regs[i+1].regmap_entry[nr]=rs1[i+1];
10758 regs[i].isconst&=~(1<<nr);
10759 regs[i+1].isconst&=~(1<<nr);
10760 regs[i].dirty&=~(1<<nr);
10761 regs[i+1].wasdirty&=~(1<<nr);
10762 regs[i+1].dirty&=~(1<<nr);
10763 regs[i+2].wasdirty&=~(1<<nr);
10767 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10768 if(itype[i+1]==LOAD)
10769 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10770 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10771 hr=get_reg(regs[i+1].regmap,FTEMP);
10772 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10773 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10774 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10776 if(hr>=0&®s[i].regmap[hr]<0) {
10777 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10778 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10779 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10780 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10781 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10782 regs[i].isconst&=~(1<<hr);
10783 regs[i+1].wasdirty&=~(1<<hr);
10784 regs[i].dirty&=~(1<<hr);
10793 /* Pass 6 - Optimize clean/dirty state */
10794 clean_registers(0,slen-1,1);
10796 /* Pass 7 - Identify 32-bit registers */
10802 for (i=slen-1;i>=0;i--)
10805 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10807 if(ba[i]<start || ba[i]>=(start+slen*4))
10809 // Branch out of this block, don't need anything
10815 // Need whatever matches the target
10816 // (and doesn't get overwritten by the delay slot instruction)
10818 int t=(ba[i]-start)>>2;
10819 if(ba[i]>start+i*4) {
10821 if(!(requires_32bit[t]&~regs[i].was32))
10822 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10825 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10826 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10827 if(!(pr32[t]&~regs[i].was32))
10828 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10831 // Conditional branch may need registers for following instructions
10832 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10835 r32|=requires_32bit[i+2];
10836 r32&=regs[i].was32;
10837 // Mark this address as a branch target since it may be called
10838 // upon return from interrupt
10842 // Merge in delay slot
10844 // These are overwritten unless the branch is "likely"
10845 // and the delay slot is nullified if not taken
10846 r32&=~(1LL<<rt1[i+1]);
10847 r32&=~(1LL<<rt2[i+1]);
10849 // Assume these are needed (delay slot)
10852 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10856 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10858 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10860 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10862 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10864 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10867 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10869 // SYSCALL instruction (software interrupt)
10872 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10874 // ERET instruction (return from interrupt)
10878 r32&=~(1LL<<rt1[i]);
10879 r32&=~(1LL<<rt2[i]);
10882 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10886 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10888 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10890 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10892 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10894 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10896 requires_32bit[i]=r32;
10898 // Dirty registers which are 32-bit, require 32-bit input
10899 // as they will be written as 32-bit values
10900 for(hr=0;hr<HOST_REGS;hr++)
10902 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
10903 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10904 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10905 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10909 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10912 for (i=slen-1;i>=0;i--)
10914 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10916 // Conditional branch
10917 if((source[i]>>16)!=0x1000&&i<slen-2) {
10918 // Mark this address as a branch target since it may be called
10919 // upon return from interrupt
10926 if(itype[slen-1]==SPAN) {
10927 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10931 /* Debug/disassembly */
10932 for(i=0;i<slen;i++)
10936 for(r=1;r<=CCREG;r++) {
10937 if((unneeded_reg[i]>>r)&1) {
10938 if(r==HIREG) printf(" HI");
10939 else if(r==LOREG) printf(" LO");
10940 else printf(" r%d",r);
10945 for(r=1;r<=CCREG;r++) {
10946 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10947 if(r==HIREG) printf(" HI");
10948 else if(r==LOREG) printf(" LO");
10949 else printf(" r%d",r);
10953 for(r=0;r<=CCREG;r++) {
10954 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10955 if((regs[i].was32>>r)&1) {
10956 if(r==CCREG) printf(" CC");
10957 else if(r==HIREG) printf(" HI");
10958 else if(r==LOREG) printf(" LO");
10959 else printf(" r%d",r);
10964 #if defined(__i386__) || defined(__x86_64__)
10965 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10968 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10971 if(needed_reg[i]&1) printf("eax ");
10972 if((needed_reg[i]>>1)&1) printf("ecx ");
10973 if((needed_reg[i]>>2)&1) printf("edx ");
10974 if((needed_reg[i]>>3)&1) printf("ebx ");
10975 if((needed_reg[i]>>5)&1) printf("ebp ");
10976 if((needed_reg[i]>>6)&1) printf("esi ");
10977 if((needed_reg[i]>>7)&1) printf("edi ");
10979 for(r=0;r<=CCREG;r++) {
10980 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10981 if((requires_32bit[i]>>r)&1) {
10982 if(r==CCREG) printf(" CC");
10983 else if(r==HIREG) printf(" HI");
10984 else if(r==LOREG) printf(" LO");
10985 else printf(" r%d",r);
10990 for(r=0;r<=CCREG;r++) {
10991 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10992 if((pr32[i]>>r)&1) {
10993 if(r==CCREG) printf(" CC");
10994 else if(r==HIREG) printf(" HI");
10995 else if(r==LOREG) printf(" LO");
10996 else printf(" r%d",r);
10999 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
11001 #if defined(__i386__) || defined(__x86_64__)
11002 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
11004 if(regs[i].wasdirty&1) printf("eax ");
11005 if((regs[i].wasdirty>>1)&1) printf("ecx ");
11006 if((regs[i].wasdirty>>2)&1) printf("edx ");
11007 if((regs[i].wasdirty>>3)&1) printf("ebx ");
11008 if((regs[i].wasdirty>>5)&1) printf("ebp ");
11009 if((regs[i].wasdirty>>6)&1) printf("esi ");
11010 if((regs[i].wasdirty>>7)&1) printf("edi ");
11013 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
11015 if(regs[i].wasdirty&1) printf("r0 ");
11016 if((regs[i].wasdirty>>1)&1) printf("r1 ");
11017 if((regs[i].wasdirty>>2)&1) printf("r2 ");
11018 if((regs[i].wasdirty>>3)&1) printf("r3 ");
11019 if((regs[i].wasdirty>>4)&1) printf("r4 ");
11020 if((regs[i].wasdirty>>5)&1) printf("r5 ");
11021 if((regs[i].wasdirty>>6)&1) printf("r6 ");
11022 if((regs[i].wasdirty>>7)&1) printf("r7 ");
11023 if((regs[i].wasdirty>>8)&1) printf("r8 ");
11024 if((regs[i].wasdirty>>9)&1) printf("r9 ");
11025 if((regs[i].wasdirty>>10)&1) printf("r10 ");
11026 if((regs[i].wasdirty>>12)&1) printf("r12 ");
11029 disassemble_inst(i);
11030 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11031 #if defined(__i386__) || defined(__x86_64__)
11032 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11033 if(regs[i].dirty&1) printf("eax ");
11034 if((regs[i].dirty>>1)&1) printf("ecx ");
11035 if((regs[i].dirty>>2)&1) printf("edx ");
11036 if((regs[i].dirty>>3)&1) printf("ebx ");
11037 if((regs[i].dirty>>5)&1) printf("ebp ");
11038 if((regs[i].dirty>>6)&1) printf("esi ");
11039 if((regs[i].dirty>>7)&1) printf("edi ");
11042 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11043 if(regs[i].dirty&1) printf("r0 ");
11044 if((regs[i].dirty>>1)&1) printf("r1 ");
11045 if((regs[i].dirty>>2)&1) printf("r2 ");
11046 if((regs[i].dirty>>3)&1) printf("r3 ");
11047 if((regs[i].dirty>>4)&1) printf("r4 ");
11048 if((regs[i].dirty>>5)&1) printf("r5 ");
11049 if((regs[i].dirty>>6)&1) printf("r6 ");
11050 if((regs[i].dirty>>7)&1) printf("r7 ");
11051 if((regs[i].dirty>>8)&1) printf("r8 ");
11052 if((regs[i].dirty>>9)&1) printf("r9 ");
11053 if((regs[i].dirty>>10)&1) printf("r10 ");
11054 if((regs[i].dirty>>12)&1) printf("r12 ");
11057 if(regs[i].isconst) {
11058 printf("constants: ");
11059 #if defined(__i386__) || defined(__x86_64__)
11060 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11061 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11062 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11063 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11064 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11065 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11066 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11069 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11070 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11071 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11072 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11073 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11074 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11075 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11076 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11077 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11078 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11079 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11080 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11086 for(r=0;r<=CCREG;r++) {
11087 if((regs[i].is32>>r)&1) {
11088 if(r==CCREG) printf(" CC");
11089 else if(r==HIREG) printf(" HI");
11090 else if(r==LOREG) printf(" LO");
11091 else printf(" r%d",r);
11097 for(r=0;r<=CCREG;r++) {
11098 if((p32[i]>>r)&1) {
11099 if(r==CCREG) printf(" CC");
11100 else if(r==HIREG) printf(" HI");
11101 else if(r==LOREG) printf(" LO");
11102 else printf(" r%d",r);
11105 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11106 else printf("\n");*/
11107 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11108 #if defined(__i386__) || defined(__x86_64__)
11109 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11110 if(branch_regs[i].dirty&1) printf("eax ");
11111 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11112 if((branch_regs[i].dirty>>2)&1) printf("edx ");
11113 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11114 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11115 if((branch_regs[i].dirty>>6)&1) printf("esi ");
11116 if((branch_regs[i].dirty>>7)&1) printf("edi ");
11119 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11120 if(branch_regs[i].dirty&1) printf("r0 ");
11121 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11122 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11123 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11124 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11125 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11126 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11127 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11128 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11129 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11130 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11131 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11135 for(r=0;r<=CCREG;r++) {
11136 if((branch_regs[i].is32>>r)&1) {
11137 if(r==CCREG) printf(" CC");
11138 else if(r==HIREG) printf(" HI");
11139 else if(r==LOREG) printf(" LO");
11140 else printf(" r%d",r);
11149 /* Pass 8 - Assembly */
11150 linkcount=0;stubcount=0;
11151 ds=0;is_delayslot=0;
11153 uint64_t is32_pre=0;
11155 u_int beginning=(u_int)out;
11156 if((u_int)addr&1) {
11160 u_int instr_addr0_override=0;
11163 if (start == 0x80030000) {
11164 // nasty hack for fastbios thing
11165 // override block entry to this code
11166 instr_addr0_override=(u_int)out;
11167 emit_movimm(start,0);
11168 // abuse io address var as a flag that we
11169 // have already returned here once
11170 emit_readword((int)&address,1);
11171 emit_writeword(0,(int)&pcaddr);
11172 emit_writeword(0,(int)&address);
11174 emit_jne((int)new_dyna_leave);
11177 for(i=0;i<slen;i++)
11179 //if(ds) printf("ds: ");
11180 disassemble_inst(i);
11182 ds=0; // Skip delay slot
11183 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11186 speculate_register_values(i);
11187 #ifndef DESTRUCTIVE_WRITEBACK
11188 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11190 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11191 unneeded_reg[i],unneeded_reg_upper[i]);
11192 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11193 unneeded_reg[i],unneeded_reg_upper[i]);
11195 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11196 is32_pre=branch_regs[i].is32;
11197 dirty_pre=branch_regs[i].dirty;
11199 is32_pre=regs[i].is32;
11200 dirty_pre=regs[i].dirty;
11204 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11206 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11207 unneeded_reg[i],unneeded_reg_upper[i]);
11208 loop_preload(regmap_pre[i],regs[i].regmap_entry);
11210 // branch target entry point
11211 instr_addr[i]=(u_int)out;
11212 assem_debug("<->\n");
11214 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
11215 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11216 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11217 address_generation(i,®s[i],regs[i].regmap_entry);
11218 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11219 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11221 // Load the delay slot registers if necessary
11222 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11223 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11224 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11225 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11226 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11227 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11231 // Preload registers for following instruction
11232 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11233 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11234 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11235 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11236 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11237 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11239 // TODO: if(is_ooo(i)) address_generation(i+1);
11240 if(itype[i]==CJUMP||itype[i]==FJUMP)
11241 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11242 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11243 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11244 if(bt[i]) cop1_usable=0;
11248 alu_assemble(i,®s[i]);break;
11250 imm16_assemble(i,®s[i]);break;
11252 shift_assemble(i,®s[i]);break;
11254 shiftimm_assemble(i,®s[i]);break;
11256 load_assemble(i,®s[i]);break;
11258 loadlr_assemble(i,®s[i]);break;
11260 store_assemble(i,®s[i]);break;
11262 storelr_assemble(i,®s[i]);break;
11264 cop0_assemble(i,®s[i]);break;
11266 cop1_assemble(i,®s[i]);break;
11268 c1ls_assemble(i,®s[i]);break;
11270 cop2_assemble(i,®s[i]);break;
11272 c2ls_assemble(i,®s[i]);break;
11274 c2op_assemble(i,®s[i]);break;
11276 fconv_assemble(i,®s[i]);break;
11278 float_assemble(i,®s[i]);break;
11280 fcomp_assemble(i,®s[i]);break;
11282 multdiv_assemble(i,®s[i]);break;
11284 mov_assemble(i,®s[i]);break;
11286 syscall_assemble(i,®s[i]);break;
11288 hlecall_assemble(i,®s[i]);break;
11290 intcall_assemble(i,®s[i]);break;
11292 ujump_assemble(i,®s[i]);ds=1;break;
11294 rjump_assemble(i,®s[i]);ds=1;break;
11296 cjump_assemble(i,®s[i]);ds=1;break;
11298 sjump_assemble(i,®s[i]);ds=1;break;
11300 fjump_assemble(i,®s[i]);ds=1;break;
11302 pagespan_assemble(i,®s[i]);break;
11304 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11305 literal_pool(1024);
11307 literal_pool_jumpover(256);
11310 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11311 // If the block did not end with an unconditional branch,
11312 // add a jump to the next instruction.
11314 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11315 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11317 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11318 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11319 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11320 emit_loadreg(CCREG,HOST_CCREG);
11321 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11323 else if(!likely[i-2])
11325 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11326 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11330 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11331 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11333 add_to_linker((int)out,start+i*4,0);
11340 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11341 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11342 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11343 emit_loadreg(CCREG,HOST_CCREG);
11344 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11345 add_to_linker((int)out,start+i*4,0);
11349 // TODO: delay slot stubs?
11351 for(i=0;i<stubcount;i++)
11353 switch(stubs[i][0])
11361 do_readstub(i);break;
11366 do_writestub(i);break;
11368 do_ccstub(i);break;
11370 do_invstub(i);break;
11372 do_cop1stub(i);break;
11374 do_unalignedwritestub(i);break;
11378 if (instr_addr0_override)
11379 instr_addr[0] = instr_addr0_override;
11381 /* Pass 9 - Linker */
11382 for(i=0;i<linkcount;i++)
11384 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11386 if(!link_addr[i][2])
11389 void *addr=check_addr(link_addr[i][1]);
11390 emit_extjump(link_addr[i][0],link_addr[i][1]);
11392 set_jump_target(link_addr[i][0],(int)addr);
11393 add_link(link_addr[i][1],stub);
11395 else set_jump_target(link_addr[i][0],(int)stub);
11400 int target=(link_addr[i][1]-start)>>2;
11401 assert(target>=0&&target<slen);
11402 assert(instr_addr[target]);
11403 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11404 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11406 set_jump_target(link_addr[i][0],instr_addr[target]);
11410 // External Branch Targets (jump_in)
11411 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11412 for(i=0;i<slen;i++)
11416 if(instr_addr[i]) // TODO - delay slots (=null)
11418 u_int vaddr=start+i*4;
11419 u_int page=get_page(vaddr);
11420 u_int vpage=get_vpage(vaddr);
11422 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11424 if(!requires_32bit[i])
11429 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11430 assem_debug("jump_in: %x\n",start+i*4);
11431 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11432 int entry_point=do_dirty_stub(i);
11433 ll_add(jump_in+page,vaddr,(void *)entry_point);
11434 // If there was an existing entry in the hash table,
11435 // replace it with the new address.
11436 // Don't add new entries. We'll insert the
11437 // ones that actually get used in check_addr().
11438 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11439 if(ht_bin[0]==vaddr) {
11440 ht_bin[1]=entry_point;
11442 if(ht_bin[2]==vaddr) {
11443 ht_bin[3]=entry_point;
11448 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11449 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11450 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11451 //int entry_point=(int)out;
11452 ////assem_debug("entry_point: %x\n",entry_point);
11453 //load_regs_entry(i);
11454 //if(entry_point==(int)out)
11455 // entry_point=instr_addr[i];
11457 // emit_jmp(instr_addr[i]);
11458 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11459 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11460 int entry_point=do_dirty_stub(i);
11461 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11466 // Write out the literal pool if necessary
11468 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11470 if(((u_int)out)&7) emit_addnop(13);
11472 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11473 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11474 memcpy(copy,source,slen*4);
11478 __clear_cache((void *)beginning,out);
11481 // If we're within 256K of the end of the buffer,
11482 // start over from the beginning. (Is 256K enough?)
11483 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11485 // Trap writes to any of the pages we compiled
11486 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11488 #ifndef DISABLE_TLB
11489 memory_map[i]|=0x40000000;
11490 if((signed int)start>=(signed int)0xC0000000) {
11492 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11494 memory_map[j]|=0x40000000;
11495 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11499 inv_code_start=inv_code_end=~0;
11501 // for PCSX we need to mark all mirrors too
11502 if(get_page(start)<(RAM_SIZE>>12))
11503 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11504 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11505 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11506 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11509 /* Pass 10 - Free memory by expiring oldest blocks */
11511 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11512 while(expirep!=end)
11514 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11515 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11516 inv_debug("EXP: Phase %d\n",expirep);
11517 switch((expirep>>11)&3)
11520 // Clear jump_in and jump_dirty
11521 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11522 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11523 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11524 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11528 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11529 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11532 // Clear hash table
11533 for(i=0;i<32;i++) {
11534 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11535 if((ht_bin[3]>>shift)==(base>>shift) ||
11536 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11537 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11538 ht_bin[2]=ht_bin[3]=-1;
11540 if((ht_bin[1]>>shift)==(base>>shift) ||
11541 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11542 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11543 ht_bin[0]=ht_bin[2];
11544 ht_bin[1]=ht_bin[3];
11545 ht_bin[2]=ht_bin[3]=-1;
11552 if((expirep&2047)==0)
11555 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11556 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11559 expirep=(expirep+1)&65535;
11564 // vim:shiftwidth=2:expandtab