3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
8 #include "../pico_int.h"
9 #include "../sound/ym2612.h"
10 #include "../../cpu/sh2/compiler.h"
12 struct Pico32x Pico32x;
15 static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
17 if (sh2->pending_irl > sh2->pending_int_irq) {
18 elprintf(EL_32X, "%csh2 ack/irl %d @ %08x",
19 sh2->is_slave ? 's' : 'm', level, sh2->pc);
20 return 64 + sh2->pending_irl / 2;
22 elprintf(EL_32X, "%csh2 ack/int %d/%d @ %08x",
23 sh2->is_slave ? 's' : 'm', level, sh2->pending_int_vector, sh2->pc);
24 sh2->pending_int_irq = 0; // auto-clear
25 sh2->pending_level = sh2->pending_irl;
26 return sh2->pending_int_vector;
30 // if !nested_call, must sync CPUs before calling this
31 void p32x_update_irls(int nested_call)
33 int irqs, mlvl = 0, slvl = 0;
37 irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES);
43 irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES);
48 mrun = sh2_irl_irq(&msh2, mlvl, nested_call);
49 srun = sh2_irl_irq(&ssh2, slvl, nested_call);
50 p32x_poll_event(mrun | (srun << 1), 0);
51 elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
54 void Pico32xStartup(void)
56 elprintf(EL_STATUS|EL_32X, "32X startup");
61 msh2.irq_callback = sh2_irq_cb;
63 ssh2.irq_callback = sh2_irq_cb;
69 Pico32x.vdp_regs[0] |= P32XV_nPAL;
71 PREG8(Pico32xMem->sh2_peri_regs[0], 4) =
72 PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR
79 #define HWSWAP(x) (((x) << 16) | ((x) >> 16))
80 void p32x_reset_sh2s(void)
82 elprintf(EL_32X, "sh2 reset");
87 // if we don't have BIOS set, perform it's work here.
89 if (p32x_bios_m == NULL) {
90 unsigned int idl_src, idl_dst, idl_size; // initial data load
94 idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000;
95 idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000;
96 idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc));
97 if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize ||
98 idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) {
99 elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x",
100 idl_src, idl_dst, idl_size);
103 memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size);
106 vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8));
107 sh2_set_gbr(0, 0x20004000);
111 Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e);
112 // program will set M_OK
116 if (p32x_bios_s == NULL) {
120 vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec));
121 sh2_set_gbr(1, 0x20004000);
123 // program will set S_OK
126 msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDoneT();
129 void Pico32xInit(void)
131 if (msh2.mult_m68k_to_sh2 == 0 || msh2.mult_sh2_to_m68k == 0)
132 Pico32xSetClocks(PICO_MSH2_HZ, 0);
133 if (ssh2.mult_m68k_to_sh2 == 0 || ssh2.mult_sh2_to_m68k == 0)
134 Pico32xSetClocks(0, PICO_MSH2_HZ);
137 void PicoPower32x(void)
139 memset(&Pico32x, 0, sizeof(Pico32x));
141 Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified
142 Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_HBLK|P32XV_PEN;
143 Pico32x.sh2_regs[0] = P32XS2_ADEN;
146 void PicoUnload32x(void)
148 if (Pico32xMem != NULL)
149 plat_munmap(Pico32xMem, sizeof(*Pico32xMem));
154 PicoAHW &= ~PAHW_32X;
157 void PicoReset32x(void)
159 if (PicoAHW & PAHW_32X) {
160 Pico32x.sh2irqs |= P32XI_VRES;
162 p32x_poll_event(3, 0);
163 p32x_timers_recalc();
167 static void p32x_start_blank(void)
169 if (Pico32xDrawMode != PDM32X_OFF && !PicoSkipFrame) {
174 offs = 8; lines = 224;
175 if ((Pico.video.reg[1] & 8) && !(PicoOpt & POPT_ALT_RENDERER)) {
180 // XXX: no proper handling of 32col mode..
181 if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking
182 (Pico.video.reg[12] & 1) && // 40col mode
183 (PicoDrawMask & PDRAW_32X_ON))
185 int md_bg = Pico.video.reg[7] & 0x3f;
187 // we draw full layer (not line-by-line)
188 PicoDraw32xLayer(offs, lines, md_bg);
190 else if (Pico32xDrawMode != PDM32X_32X_ONLY)
191 PicoDraw32xLayerMdOnly(offs, lines);
197 Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN;
199 // FB swap waits until vblank
200 if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) {
201 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS;
202 Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb;
203 Pico32xSwapDRAM(Pico32x.pending_fb ^ 1);
206 Pico32x.sh2irqs |= P32XI_VINT;
208 p32x_poll_event(3, 1);
212 static void pwm_irq_event(unsigned int now)
214 Pico32x.emu_flags &= ~P32XF_PWM_PEND;
215 p32x_pwm_schedule(now);
217 Pico32x.sh2irqs |= P32XI_PWM;
221 static void fillend_event(unsigned int now)
223 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_nFEN;
224 p32x_poll_event(3, 1);
227 typedef void (event_cb)(unsigned int now);
229 unsigned int event_times[P32X_EVENT_COUNT];
230 static unsigned int event_time_next;
231 static event_cb *event_cbs[] = {
232 [P32X_EVENT_PWM] = pwm_irq_event,
233 [P32X_EVENT_FILLEND] = fillend_event,
236 // schedule event at some time (in m68k clocks)
237 void p32x_event_schedule(enum p32x_event event, unsigned int now, int after)
239 unsigned int when = (now + after) | 1;
241 elprintf(EL_32X, "new event #%u %u->%u", event, now, when);
242 event_times[event] = when;
244 if (event_time_next == 0 || (int)(event_time_next - now) > after)
245 event_time_next = when;
248 static void run_events(unsigned int until)
250 int oldest, oldest_diff, time;
254 oldest = -1, oldest_diff = 0x7fffffff;
256 for (i = 0; i < P32X_EVENT_COUNT; i++) {
257 if (event_times[i]) {
258 diff = event_times[i] - until;
259 if (diff < oldest_diff) {
266 if (oldest_diff <= 0) {
267 time = event_times[oldest];
268 event_times[oldest] = 0;
269 elprintf(EL_32X, "run event #%d %u", oldest, time);
270 event_cbs[oldest](time);
272 else if (oldest_diff < 0x7fffffff) {
273 event_time_next = event_times[oldest];
283 elprintf(EL_32X, "next event #%d at %u", oldest, event_time_next);
286 // compare cycles, handling overflows
288 #define CYCLES_GT(a, b) \
289 ((int)((a) - (b)) > 0)
291 #define CYCLES_GE(a, b) \
292 ((int)((a) - (b)) >= 0)
294 #define sync_sh2s_normal p32x_sync_sh2s
295 //#define sync_sh2s_lockstep p32x_sync_sh2s
297 /* most timing is in 68k clock */
298 void sync_sh2s_normal(unsigned int m68k_target)
300 unsigned int now, target, timer_cycles;
303 elprintf(EL_32X, "sh2 sync to %u", m68k_target);
305 if (!(Pico32x.regs[0] & P32XS_nRES)) {
306 msh2.m68krcycles_done = ssh2.m68krcycles_done = m68k_target;
310 now = msh2.m68krcycles_done;
311 if (CYCLES_GT(now, ssh2.m68krcycles_done))
312 now = ssh2.m68krcycles_done;
315 while (CYCLES_GT(m68k_target, now))
317 if (event_time_next && CYCLES_GE(now, event_time_next))
320 target = m68k_target;
321 if (event_time_next && CYCLES_GT(target, event_time_next))
322 target = event_time_next;
324 while (CYCLES_GT(target, now))
326 elprintf(EL_32X, "sh2 exec to %u %d,%d/%d, flags %x", target,
327 target - msh2.m68krcycles_done, target - ssh2.m68krcycles_done,
328 m68k_target - now, Pico32x.emu_flags);
330 if (Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL)) {
331 ssh2.m68krcycles_done = target;
334 cycles = target - ssh2.m68krcycles_done;
336 done = sh2_execute(&ssh2, C_M68K_TO_SH2(ssh2, cycles));
337 ssh2.m68krcycles_done += C_SH2_TO_M68K(ssh2, done);
339 if (event_time_next && CYCLES_GT(target, event_time_next))
340 target = event_time_next;
344 if (Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL)) {
345 msh2.m68krcycles_done = target;
348 cycles = target - msh2.m68krcycles_done;
350 done = sh2_execute(&msh2, C_M68K_TO_SH2(msh2, cycles));
351 msh2.m68krcycles_done += C_SH2_TO_M68K(msh2, done);
353 if (event_time_next && CYCLES_GT(target, event_time_next))
354 target = event_time_next;
358 now = msh2.m68krcycles_done;
359 if (CYCLES_GT(now, ssh2.m68krcycles_done))
360 now = ssh2.m68krcycles_done;
363 p32x_timers_do(now - timer_cycles);
370 void sync_sh2s_lockstep(unsigned int m68k_target)
372 unsigned int mcycles;
374 mcycles = msh2.m68krcycles_done;
375 if (ssh2.m68krcycles_done < mcycles)
376 mcycles = ssh2.m68krcycles_done;
378 while (mcycles < m68k_target) {
380 sync_sh2s_normal(mcycles);
384 #define CPUS_RUN(m68k_cycles,s68k_cycles) do { \
385 SekRunM68k(m68k_cycles); \
386 if (Pico32x.emu_flags & P32XF_68KPOLL) \
387 p32x_sync_sh2s(SekCycleCntT + SekCycleCnt); \
391 #include "../pico_cmn.c"
393 void PicoFrame32x(void)
395 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank
396 if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking
397 Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access
399 p32x_poll_event(3, 1);
405 elprintf(EL_32X, "poll: %02x", Pico32x.emu_flags);
408 // calculate multipliers against 68k clock (7670442)
409 // normally * 3, but effectively slower due to high latencies everywhere
410 // however using something lower breaks MK2 animations
411 void Pico32xSetClocks(int msh2_hz, int ssh2_hz)
413 float m68k_clk = (float)(OSC_NTSC / 7);
415 msh2.mult_m68k_to_sh2 = (int)((float)msh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
416 msh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)msh2_hz);
419 ssh2.mult_m68k_to_sh2 = (int)((float)ssh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk);
420 ssh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)ssh2_hz);
424 void Pico32xStateLoaded(int is_early)
427 Pico32xMemStateLoaded();
431 sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCycleCntT;
433 p32x_poll_event(3, 0);
434 p32x_timers_recalc();
435 run_events(SekCycleCntT);
438 // vim:shiftwidth=2:ts=2:expandtab