\r
#include "app.h"\r
\r
+// trashes r0\r
+const char *TestCond(int m68k_cc, int invert)\r
+{\r
+ const char *cond="";\r
+ const char *icond="";\r
+\r
+ // ARM: NZCV\r
+ switch (m68k_cc)\r
+ {\r
+ case 0x00: // T\r
+ case 0x01: // F\r
+ break;\r
+ case 0x02: // hi\r
+ ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
+ cond="eq", icond="ne";\r
+ break;\r
+ case 0x03: // ls\r
+ ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r
+ cond="ne", icond="eq";\r
+ break;\r
+ case 0x04: // cc\r
+ ot(" tst r10,#0x20000000 ;@ cc: !C\n");\r
+ cond="eq", icond="ne";\r
+ break;\r
+ case 0x05: // cs\r
+ ot(" tst r10,#0x20000000 ;@ cs: C\n");\r
+ cond="ne", icond="eq";\r
+ break;\r
+ case 0x06: // ne\r
+ ot(" tst r10,#0x40000000 ;@ ne: !Z\n");\r
+ cond="eq", icond="ne";\r
+ break;\r
+ case 0x07: // eq\r
+ ot(" tst r10,#0x40000000 ;@ eq: Z\n");\r
+ cond="ne", icond="eq";\r
+ break;\r
+ case 0x08: // vc\r
+ ot(" tst r10,#0x10000000 ;@ vc: !V\n");\r
+ cond="eq", icond="ne";\r
+ break;\r
+ case 0x09: // vs\r
+ ot(" tst r10,#0x10000000 ;@ vs: V\n");\r
+ cond="ne", icond="eq";\r
+ break;\r
+ case 0x0a: // pl\r
+ ot(" tst r10,r10 ;@ pl: !N\n");\r
+ cond="pl", icond="mi";\r
+ break;\r
+ case 0x0b: // mi\r
+ ot(" tst r10,r10 ;@ mi: N\n");\r
+ cond="mi", icond="pl";\r
+ break;\r
+ case 0x0c: // ge\r
+ ot(" teq r10,r10,lsl #3 ;@ ge: N == V\n");\r
+ cond="pl", icond="mi";\r
+ break;\r
+ case 0x0d: // lt\r
+ ot(" teq r10,r10,lsl #3 ;@ lt: N != V\n");\r
+ cond="mi", icond="pl";\r
+ break;\r
+ case 0x0e: // gt\r
+ ot(" eor r0,r10,r10,lsl #3 ;@ gt: !Z && N == V\n");\r
+ ot(" orrs r0,r10,lsl #1\n");\r
+ cond="pl", icond="mi";\r
+ break;\r
+ case 0x0f: // le\r
+ ot(" eor r0,r10,r10,lsl #3 ;@ le: Z || N != V\n");\r
+ ot(" orrs r0,r10,lsl #1\n");\r
+ cond="mi", icond="pl";\r
+ break;\r
+ default:\r
+ printf("invalid m68k_cc: %x\n", m68k_cc);\r
+ exit(1);\r
+ break;\r
+ }\r
+ return invert?icond:cond;\r
+}\r
+\r
// --------------------- Opcodes 0x0100+ ---------------------\r
// Emit a Btst (Register) opcode 0000nnn1 ttaaaaaa\r
int OpBtstReg(int op)\r
if(size>=2) Cycles+=2;\r
}\r
\r
- EaCalcReadNoSE(-1,11,sea,0,0x0e00);\r
+ EaCalcRead(-1,11,sea,0,0x0e00,earwt_msb_dont_care);\r
\r
- EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);\r
+ EaCalcRead((type>0)?8:-1,0,tea,size,0x003f,earwt_msb_dont_care);\r
\r
if (tea>=0x10)\r
ot(" and r11,r11,#7 ;@ mem - do mod 8\n"); // size always 0\r
if (type==2) ot(" bic r1,r0,r1,lsl r11 ;@ Clear bit\n");\r
if (type==3) ot(" orr r1,r0,r1,lsl r11 ;@ Set bit\n");\r
ot("\n");\r
- EaWrite(8,1,tea,size,0x003f,0,0);\r
+ EaWrite(8,1,tea,size,0x003f,earwt_msb_dont_care);\r
}\r
OpEnd(tea);\r
\r
OpStart(op,sea,tea);\r
\r
ot("\n");\r
- EaCalcReadNoSE(-1,0,sea,0,0);\r
+ EaCalcRead(-1,0,sea,0,0,earwt_msb_dont_care);\r
ot(" mov r11,#1\n");\r
ot(" bic r10,r10,#0x40000000 ;@ Blank Z flag\n");\r
if (tea>=0x10)\r
if(size>=2) Cycles+=2;\r
}\r
\r
- EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);\r
+ EaCalcRead((type>0)?8:-1,0,tea,size,0x003f,earwt_msb_dont_care);\r
ot(" tst r0,r11 ;@ Do arithmetic\n");\r
ot(" orreq r10,r10,#0x40000000 ;@ Get Z flag\n");\r
ot("\n");\r
if (type==2) ot(" bic r1,r0,r11 ;@ Clear bit\n");\r
if (type==3) ot(" orr r1,r0,r11 ;@ Set bit\n");\r
ot("\n");\r
- EaWrite(8, 1,tea,size,0x003f,0,0);\r
+ EaWrite(8, 1,tea,size,0x003f,earwt_msb_dont_care);\r
#if CYCLONE_FOR_GENESIS && !MEMHANDLERS_CHANGE_CYCLES\r
// this is a bit hacky (device handlers might modify cycles)\r
if (tea==0x38||tea==0x39)\r
OpStart(op,ea); Cycles=size<2?4:6;\r
if(ea >= 0x10) Cycles*=2;\r
\r
- EaCalc (11,0x003f,ea,size,0,0);\r
+ EaCalc (11,0x003f,ea,size,earwt_msb_dont_care);\r
\r
- if (type!=1) EaRead (11,0,ea,size,0x003f,0,0); // Don't need to read for 'clr' (or do we, for a dummy read?)\r
+ if (type!=1) EaRead (11,0,ea,size,0x003f,earwt_msb_dont_care); // Don't need to read for 'clr' (or do we, for a dummy read?)\r
if (type==1) ot("\n");\r
\r
if (type==0)\r
ot(";@ Not:\n");\r
if(size!=2) {\r
ot(" mov r0,r0,asl #%i\n",size?16:24);\r
- ot(" mvn r1,r0,asr #%i\n",size?16:24);\r
+ ot(" mvns r1,r0,asr #%i\n",size?16:24);\r
}\r
else\r
- ot(" mvn r1,r0\n");\r
- ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
- OpGetFlags(0,0);\r
+ ot(" mvns r1,r0\n");\r
+ OpGetFlagsNZ(1);\r
ot("\n");\r
}\r
\r
if (type==1) eawrite_check_addrerr=1;\r
- EaWrite(11, 1,ea,size,0x003f,0,0);\r
+ EaWrite(11, 1,ea,size,0x003f,earwt_msb_dont_care);\r
\r
OpEnd(ea);\r
\r
\r
OpStart(op); Cycles=4;\r
\r
- EaCalc (11,0x0007,ea,2,1);\r
- EaRead (11, 0,ea,2,0x0007,1);\r
+ EaCalc (11,0x0007,ea,2,earwt_shifted_up);\r
+ EaRead (11, 0,ea,2,0x0007,earwt_shifted_up);\r
\r
- ot(" mov r1,r0,ror #16\n");\r
- ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
- OpGetFlags(0,0);\r
+ ot(" movs r1,r0,ror #16\n");\r
+ OpGetFlagsNZ(1);\r
\r
- EaWrite(11, 1,8,2,0x0007,1);\r
+ EaWrite(11, 1,8,2,0x0007,earwt_shifted_up);\r
\r
OpEnd();\r
\r
\r
OpStart(op,sea); Cycles=4;\r
\r
- EaCalc ( 0,0x003f,sea,size,1);\r
- EaRead ( 0, 0,sea,size,0x003f,1);\r
+ EaCalc (0,0x003f,sea,size,earwt_shifted_up);\r
+ EaRead (0, 0,sea,size,0x003f,earwt_shifted_up,1);\r
\r
- ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
- ot(" mrs r10,cpsr ;@ r10=flags\n");\r
+ OpGetFlagsNZ(0);\r
ot("\n");\r
\r
OpEnd(sea);\r
\r
OpStart(op); Cycles=4;\r
\r
- EaCalc (11,0x0007,ea,size+1,0,0);\r
- EaRead (11, 0,ea,size+1,0x0007,0,0);\r
+ EaCalc (11,0x0007,ea,size+1,earwt_msb_dont_care);\r
+ EaRead (11, 0,ea,size+1,0x0007,earwt_msb_dont_care);\r
\r
- ot(" mov r0,r0,asl #%d\n",shift);\r
- ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
- ot(" mrs r10,cpsr ;@ r10=flags\n");\r
+ ot(" movs r0,r0,asl #%d\n",shift);\r
+ OpGetFlagsNZ(0);\r
ot(" mov r1,r0,asr #%d\n",shift);\r
ot("\n");\r
\r
- EaWrite(11, 1,ea,size+1,0x0007,0,0);\r
+ EaWrite(11, 1,ea,size+1,0x0007,earwt_msb_dont_care);\r
\r
OpEnd();\r
return 0;\r
{\r
int cc=0,ea=0;\r
int size=0,use=0,changed_cycles=0;\r
- static const char * const cond[16]=\r
- {\r
- "al","", "hi","ls","cc","cs","ne","eq",\r
- "vc","vs","pl","mi","ge","lt","gt","le"\r
- };\r
+ const char *cond;\r
\r
cc=(op>>8)&15;\r
ea=op&0x003f;\r
OpStart(op,ea,0,changed_cycles); Cycles=8;\r
if (ea<8) Cycles=4;\r
\r
- if (cc)\r
- ot(" mov r1,#0\n");\r
-\r
switch (cc)\r
{\r
- case 0: // T\r
+ case 0x00: // T\r
ot(" mvn r1,#0\n");\r
if (ea<8) Cycles+=2;\r
break;\r
- case 1: // F\r
- break;\r
- case 2: // hi\r
- ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
- ot(" mvneq r1,r1\n");\r
- if (ea<8) ot(" subeq r5,r5,#2 ;@ Extra cycles\n");\r
- break;\r
- case 3: // ls\r
- ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r
- ot(" mvnne r1,r1\n");\r
- if (ea<8) ot(" subne r5,r5,#2 ;@ Extra cycles\n");\r
+ case 0x01: // F\r
+ ot(" mov r1,#0\n");\r
break;\r
default:\r
- ot(";@ Is the condition true?\n");\r
- ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
- ot(" mvn%s r1,r1\n",cond[cc]);\r
- if (ea<8) ot(" sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);\r
+ ot(" mov r1,#0\n");\r
+ cond=TestCond(cc);\r
+ ot(" mvn%s r1,#0\n",cond);\r
+ if (ea<8) ot(" sub%s r5,r5,#2 ;@ Extra cycles\n",cond);\r
break;\r
}\r
\r
ot("\n");\r
\r
eawrite_check_addrerr=1;\r
- EaCalc (0,0x003f, ea,size,0,0);\r
- EaWrite(0, 1, ea,size,0x003f,0,0);\r
+ EaCalc (0,0x003f, ea,size,earwt_msb_dont_care);\r
+ EaWrite(0, 1, ea,size,0x003f,earwt_msb_dont_care);\r
\r
opend_op_changes_cycles=changed_cycles;\r
OpEnd(ea,0);\r
ot(" b nozerox%.4x\n",op);\r
ot("norotx_%.4x%s\n",op,ms?"":":");\r
ot(" ldr r2,[r7,#0x4c]\n");\r
- ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
- OpGetFlags(0,0);\r
+ ot(" adds r0,r0,#0 ;@ Define flags\n");\r
+ OpGetFlagsNZ(0);\r
ot(" and r2,r2,#0x20000000\n");\r
ot(" orr r10,r10,r2 ;@ C = old_X\n");\r
ot("nozerox%.4x%s\n",op,ms?"":":");\r
\r
OpStart(op,ea,0,count<0); Cycles=size<2?6:8;\r
\r
- EaCalc(11,0x0007, ea,size,1);\r
- EaRead(11, 0, ea,size,0x0007,1);\r
+ EaCalc(11,0x0007, ea,size,earwt_shifted_up);\r
+ EaRead(11, 0, ea,size,0x0007,earwt_shifted_up);\r
\r
EmitAsr(op,type,dir,count, size,usereg);\r
\r
- EaWrite(11, 0, ea,size,0x0007,1);\r
+ EaWrite(11, 0, ea,size,0x0007,earwt_shifted_up);\r
\r
opend_op_changes_cycles = (count<0);\r
OpEnd(ea,0);\r
\r
OpStart(op,ea); Cycles=6; // EmitAsr() will add 2\r
\r
- EaCalc (11,0x003f,ea,size,1);\r
- EaRead (11, 0,ea,size,0x003f,1);\r
+ EaCalc (11,0x003f,ea,size,earwt_shifted_up);\r
+ EaRead (11, 0,ea,size,0x003f,earwt_shifted_up);\r
\r
EmitAsr(op,type,dir,1,size,0);\r
\r
- EaWrite(11, 0,ea,size,0x003f,1);\r
+ EaWrite(11, 0,ea,size,0x003f,earwt_shifted_up);\r
\r
OpEnd(ea);\r
return 0;\r
Cycles=4;\r
if(ea>=8) Cycles+=10;\r
\r
- EaCalc (11,0x003f,ea,0,1);\r
- EaRead (11, 1,ea,0,0x003f,1);\r
+ EaCalc (11,0x003f,ea,0,earwt_shifted_up);\r
+ EaRead (11, 1,ea,0,0x003f,earwt_shifted_up,1);\r
\r
- ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
- OpGetFlags(0,0);\r
+ OpGetFlagsNZ(1);\r
ot("\n");\r
\r
#if CYCLONE_FOR_GENESIS\r
#endif\r
ot(" orr r1,r1,#0x80000000 ;@ set bit7\n");\r
\r
- EaWrite(11, 1,ea,0,0x003f,1);\r
+ EaWrite(11, 1,ea,0,0x003f,earwt_shifted_up);\r
#if CYCLONE_FOR_GENESIS\r
}\r
#endif\r