MTC0(&psxRegs, reg, val);
}
-void new_dyna_before_save(void)
-{
- psxRegs.interrupt &= ~(1 << PSXINT_RCNT); // old savestate compat
-
- // psxRegs.intCycle is always maintained, no need to convert
-}
-
-void new_dyna_after_save(void)
-{
- psxRegs.interrupt |= 1 << PSXINT_RCNT;
-}
-
static void new_dyna_restore(void)
{
int i;
static void ari64_reset()
{
- printf("ari64_reset\n");
new_dyna_pcsx_mem_reset();
new_dynarec_invalidate_all_pages();
new_dyna_restore();
new_dynarec_invalidate_range(addr, addr + size);
}
-static void ari64_notify(int note, void *data) {
- /*
- Should be fixed when ARM dynarec has proper icache emulation.
+static void ari64_notify(enum R3000Anote note, void *data) {
switch (note)
{
- case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
- break;
- case R3000ACPU_NOTIFY_CACHE_ISOLATED:
- Sent from psxDma3().
- case R3000ACPU_NOTIFY_DMA3_EXE_LOAD:
- default:
- break;
+ case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
+ case R3000ACPU_NOTIFY_CACHE_ISOLATED:
+ new_dyna_pcsx_mem_isolate(note == R3000ACPU_NOTIFY_CACHE_ISOLATED);
+ break;
+ case R3000ACPU_NOTIFY_BEFORE_SAVE:
+ break;
+ case R3000ACPU_NOTIFY_AFTER_LOAD:
+ ari64_reset();
+ break;
}
- */
}
static void ari64_apply_config()
int new_dynarec_hacks;
void *psxH_ptr;
void *zeromem_ptr;
-u8 zero_mem[0x1000];
+u32 zero_mem[0x1000/4];
void *mem_rtab;
void *scratch_buf_ptr;
void new_dynarec_init() {}
void new_dyna_pcsx_mem_init(void) {}
void new_dyna_pcsx_mem_reset(void) {}
void new_dyna_pcsx_mem_load_state(void) {}
+void new_dyna_pcsx_mem_isolate(int enable) {}
void new_dyna_pcsx_mem_shutdown(void) {}
int new_dynarec_save_blocks(void *save, int size) { return 0; }
void new_dynarec_load_blocks(const void *save, int size) {}