void exception(const struct exc_frame *f)
{
+ u32 *sp, sp_add;
int i;
while (read16(VDP_CTRL_PORT) & 2)
printf(" \n");
if (f->ecxnum < 4) {
- printf(" PC: %08x SR: %04x \n", f->bae.pc, f->bae.sr);
+ printf(" PC: %08x SR: %04x \n", f->bae.pc, f->bae.sr);
printf("addr: %08x IR: %04x FC: %02x \n",
f->bae.addr, f->bae.ir, f->bae.fc);
+ sp_add = 14;
}
else {
- printf(" PC: %08x SR: %04x \n", f->g.pc, f->g.sr);
+ printf(" PC: %08x SR: %04x \n", f->g.pc, f->g.sr);
+ sp_add = 6;
}
for (i = 0; i < 8; i++)
printf(" D%d: %08x A%d: %08x \n", i, f->dr[i], i, f->ar[i]);
- printf(" \n");
+ printf(" \n");
+ sp = (u32 *)(f->ar[7] + sp_add);
+ printf(" %08x %08x %08x %08x\n", sp[0], sp[1], sp[2], sp[3]);
+ printf(" %08x %08x %08x %08x\n", sp[4], sp[5], sp[6], sp[7]);
}
// ---
z80_read_loop(zram, 0x7f08);
expect(ok, zram[0x1000], 0);
-#ifndef PICO
expect_range(ok, zram[0x1100], 0x91, 0x91);
-#else
- expect_range(ok, zram[0x1100], 0x8e, 0x91);
-#endif
return ok;
}
z80_read_loop(zram, 0x8000);
expect(ok, zram[0x1000], 0);
-#ifndef PICO
expect_range(ok, zram[0x1100], 0x95, 0x96);
-#else
- expect_range(ok, zram[0x1100], 0x93, 0x96);
-#endif
return ok;
}
test_hb();
VDP_setReg(VDP_MODE4, 0x81);
-#ifndef PICO
expect_bits(ok, r[0], 0, SR_HB);
-#endif
// set: 1-4
expect_bits(ok, r[4], SR_HB, SR_HB);
expect_bits(ok, r[5], SR_HB, SR_HB);
setup_default_palette();
-#ifndef PICO
expect(ok, vcnt, 112);
-#else
- expect_range(ok, vcnt, 111, 112);
-#endif
return ok;
}
+struct irq_test {
+ u16 cnt;
+ union {
+ u16 hv;
+ u8 v;
+ } first, last;
+ u16 pad;
+};
+
static int t_irq_hint(void)
{
- u16 *ram = (u16 *)0xfff000;
- u8 *ram8 = (u8 *)0xfff000;
- u16 v_p, cnt_p;
+ struct irq_test *it = (void *)0xfff000;
int ok = 1;
// for more fun, disable the display
VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
- ram[0] = ram[1] = ram[2] = 0;
+ it->cnt = it->first.hv = it->last.hv = 0;
memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
VDP_setReg(10, 0);
while (read8(VDP_HV_COUNTER) != 100)
move_sr(0x2000);
burn10(488 * 2 / 10);
move_sr(0x2700);
- v_p = ram8[2];
- cnt_p = ram[0];
- ram[0] = ram[1] = ram[2] = 0;
+ expect(ok, it->first.v, 229); // pending irq trigger
+ expect(ok, it->cnt, 1);
+
// count irqs
+ it->cnt = it->first.hv = it->last.hv = 0;
move_sr(0x2000);
while (read8(VDP_HV_COUNTER) != 4)
;
while (read8(VDP_HV_COUNTER) != 228)
;
move_sr(0x2700);
+ expect(ok, it->cnt, 225);
+ expect(ok, it->first.v, 0);
+ expect(ok, it->last.v, 224);
+
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
+
+ // detect reload line
+ it->cnt = it->first.hv = it->last.hv = 0;
+ VDP_setReg(10, 17);
+ move_sr(0x2000);
+ while (read16(VDP_CTRL_PORT) & 8)
+ /* blanking */;
+ VDP_setReg(10, 255);
+ while (read8(VDP_HV_COUNTER) != 228)
+ ;
+ move_sr(0x2700);
+ expect(ok, it->cnt, 1);
+ expect(ok, it->first.v, 17);
+ expect(ok, it->last.v, 17);
+
+ VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
+
+ return ok;
+}
+
+static int t_irq_both_cpu_unmask(void)
+{
+ struct irq_test *ith = (void *)0xfff000;
+ struct irq_test *itv = ith + 1;
+ u16 s0, s1;
+ int ok = 1;
+
+ memset_(ith, 0, sizeof(*ith) * 2);
+ memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
+ memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
+ VDP_setReg(10, 0);
+ while (read8(VDP_HV_COUNTER) != 100)
+ ;
+ while (read8(VDP_HV_COUNTER) != 226)
+ ;
+ VDP_setReg(10, 99);
+ VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
+ VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0 | VDP_MODE2_DISP);
+ /* go to active display line 100 */
+ while (read8(VDP_HV_COUNTER) != 100)
+ ;
+ s0 = read16(VDP_CTRL_PORT);
+ s1 = move_sr_and_read(0x2000, VDP_CTRL_PORT);
+ move_sr(0x2700);
VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
- expect(ok, v_p, 229); // pending irq trigger
- expect(ok, cnt_p, 1);
- expect(ok, ram[0], 225); // count
- expect(ok, ram8[2], 0); // first line
- expect(ok, ram8[4], 224); // last line
+ expect(ok, itv->cnt, 1); // vint count
+ expect(ok, itv->first.v, 100); // vint line
+ expect(ok, ith->cnt, 1); // hint count
+ expect(ok, ith->first.v, 100); // hint line
+ expect_bits(ok, s0, SR_F, SR_F);
+ expect_bits(ok, s1, 0, SR_F);
return ok;
}
static int t_irq_ack_v_h(void)
{
- u16 *ram = (u16 *)0xfff000;
- u8 *ram8 = (u8 *)0xfff000;
+ struct irq_test *ith = (void *)0xfff000;
+ struct irq_test *itv = ith + 1;
u16 s0, s1, s2;
int ok = 1;
- ram[0] = ram[1] = ram[2] =
- ram[4] = ram[5] = ram[6] = 0;
+ memset_(ith, 0, sizeof(*ith) * 2);
memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
VDP_setReg(10, 0);
+ /* ensure hcnt reload */
+ while (!(read16(VDP_CTRL_PORT) & 8))
+ /* not blanking */;
+ while (read16(VDP_CTRL_PORT) & 8)
+ /* blanking */;
VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0);
while (read8(VDP_HV_COUNTER) != 100)
VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
- expect(ok, ram[4], 1); // vint count
- expect(ok, ram8[10], 226); // vint line
- expect(ok, ram[0], 1); // hint count
- expect(ok, ram8[2], 228); // hint line
+ expect(ok, itv->cnt, 1); // vint count
+ expect(ok, itv->first.v, 226); // vint line
+ expect(ok, ith->cnt, 1); // hint count
+ expect(ok, ith->first.v, 228); // hint line
expect_bits(ok, s0, SR_F, SR_F);
expect_bits(ok, s1, 0, SR_F);
expect_bits(ok, s2, 0, SR_F);
static int t_irq_ack_v_h_2(void)
{
- u16 *ram = (u16 *)0xfff000;
- u8 *ram8 = (u8 *)0xfff000;
+ struct irq_test *ith = (void *)0xfff000;
+ struct irq_test *itv = ith + 1;
u16 s0, s1;
int ok = 1;
- ram[0] = ram[1] = ram[2] =
- ram[4] = ram[5] = ram[6] = 0;
+ memset_(ith, 0, sizeof(*ith) * 2);
memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
VDP_setReg(10, 0);
VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
- expect(ok, ram[4], 2); // vint count
- expect(ok, ram8[10], 226); // vint line
- expect(ok, ram[0], 1); // hint count
- expect(ok, ram8[2], 227); // hint line
+ expect(ok, itv->cnt, 2); // vint count
+ expect(ok, itv->first.v, 226); // vint line
+ expect(ok, ith->cnt, 1); // hint count
+ expect(ok, ith->first.v, 227); // hint line
expect_bits(ok, s0, SR_F, SR_F);
expect_bits(ok, s1, 0, SR_F);
return ok;
while (!read16(&r16[0x24/2]))
;
expect(ok, r[0x24/4], S_OK);
+ write32(&r[0x20/4], 0);
return ok;
}
-static void x32_cmd(enum x32x_cmd cmd, u16 is_slave)
+static void x32_cmd(enum x32x_cmd cmd, u32 a0, u32 a1, u16 is_slave)
{
u16 v, *r = (u16 *)0xa15120;
u16 cmd_s = cmd | (is_slave << 15);
int i;
+
+ write32(&r[4/2], a0);
+ write32(&r[8/2], a1);
+ mem_barrier();
write16(r, cmd_s);
mem_barrier();
for (i = 0; i < 10000 && (v = read16(r)) == cmd_s; i++)
burn10(1);
if (v != 0) {
printf("cmd clr: %x\n", v);
+ mem_barrier();
+ printf("c, e: %02x %02x\n", r[0x0c/2], r[0x0e/2]);
write16(r, 0);
}
+ v = read16(&r[1]);
+ if (v != 0) {
+ printf("cmd err: %x\n", v);
+ write16(&r[1], 0);
+ }
}
static int t_32x_echo(void)
u16 *r = (u16 *)0xa15120;
int ok = 1;
- write16(&r[0x02/2], 0x1234);
- x32_cmd(CMD_ECHO, 0);
- expect(ok, r[0x04/2], 0x1234);
- write16(&r[0x02/2], 0x2345);
- write16(&r[0x04/2], 0);
- x32_cmd(CMD_ECHO, 1);
- expect(ok, r[0x04/2], 0xa345);
- expect(ok, r[0x0c/2], 0);
- expect(ok, r[0x0e/2], 0);
+ x32_cmd(CMD_ECHO, 0x12340000, 0, 0);
+ expect(ok, r[0x06/2], 0x1234);
+ x32_cmd(CMD_ECHO, 0x23450000, 0, 1);
+ expect(ok, r[0x06/2], 0xa345);
+ return ok;
+}
+
+static int t_32x_md_bios(void)
+{
+ void (*do_call_c0)(int a, int d) = (void *)0xff0040;
+ u8 *rmb = (u8 *)0xff0000;
+ u32 *rl = (u32 *)0;
+ int ok = 1;
+
+ memcpy_(do_call_c0, test_32x_b_c0,
+ test_32x_b_c0_end - test_32x_b_c0);
+ write8(rmb, 0);
+ do_call_c0(0xff0000, 0x5a);
+
+ expect(ok, rmb[0], 0x5a);
+ expect(ok, rl[0x04/4], 0x880200);
+ expect(ok, rl[0x10/4], 0x880212);
+ expect(ok, rl[0x94/4], 0x8802d8);
return ok;
}
return ok;
}
+static int t_32x_md_fb(void)
+{
+ u8 *fbb = (u8 *)0x840000;
+ u16 *fbw = (u16 *)fbb;
+ u32 *fbl = (u32 *)fbb;
+ u8 *fob = (u8 *)0x860000;
+ u16 *fow = (u16 *)fob;
+ u32 *fol = (u32 *)fob;
+ int ok = 1;
+
+ fbl[0] = 0x12345678;
+ fol[1] = 0x89abcdef;
+ mem_barrier();
+ expect(ok, fbw[1], 0x5678);
+ expect(ok, fow[2], 0x89ab);
+ fbb[0] = 0;
+ fob[1] = 0;
+ fbw[1] = 0;
+ fow[2] = 0;
+ fow[3] = 1;
+ mem_barrier();
+ fow[3] = 0x200;
+ mem_barrier();
+ expect(ok, fol[0], 0x12340000);
+ expect(ok, fbl[1], 0x89ab0201);
+ return ok;
+}
+
+static int t_32x_sh_fb(void)
+{
+ u32 *fbl = (u32 *)0x840000;
+ int ok = 1;
+
+ fbl[0] = 0x12345678;
+ fbl[1] = 0x89abcdef;
+ mem_barrier();
+ write8(0xa15100, 0x80); // FM=1
+ x32_cmd(CMD_WRITE8, 0x24000000, 0, 0);
+ x32_cmd(CMD_WRITE8, 0x24020001, 0, 0);
+ x32_cmd(CMD_WRITE16, 0x24000002, 0, 0);
+ x32_cmd(CMD_WRITE16, 0x24020000, 0, 0);
+ x32_cmd(CMD_WRITE32, 0x24020004, 0x5a0000a5, 1);
+ write8(0xa15100, 0x00); // FM=0
+ mem_barrier();
+ expect(ok, fbl[0], 0x12340000);
+ expect(ok, fbl[1], 0x5aabcda5);
+ return ok;
+}
+
+static int t_32x_disable(void)
+{
+ void (*do_32x_disable)(void) = (void *)0xff0040;
+ u32 *r = (u32 *)0xa15100;
+ u16 *r16 = (u16 *)r;
+ u32 *rl = (u32 *)0;
+ int ok = 1;
+
+ expect(ok, r16[0x00/2], 0x83);
+
+ memcpy_(do_32x_disable, x32x_disable,
+ x32x_disable_end - x32x_disable);
+ do_32x_disable();
+
+ expect(ok, r16[0x00/2], 0x82);
+ expect(ok, r16[0x02/2], 0);
+ expect(ok, r16[0x04/2], 0);
+ expect(ok, r16[0x06/2], 1); // RV
+ expect(ok, r[0x14/4], 0);
+ expect(ok, r[0x18/4], 0);
+ expect(ok, r[0x1c/4], 0);
+ expect(ok, rl[0x04/4], 0x000800);
+
+ write16(&r16[0x06/2], 0); // can just set without ADEN
+ mem_barrier();
+ expect(ok, r16[0x06/2], 0); // RV
+ return ok;
+}
+
enum {
T_MD = 0,
T_32 = 1, // 32X
{ T_MD, t_dma_short_cmd, "dma short cmd" },
{ T_MD, t_dma_fill3_odd, "dma fill3 odd" },
{ T_MD, t_dma_fill3_even, "dma fill3 even" },
-#ifndef PICO // later
{ T_MD, t_dma_fill3_vsram, "dma fill3 vsram" },
-#endif
{ T_MD, t_dma_fill_dis, "dma fill disabled" },
{ T_MD, t_dma_fill_src, "dma fill src incr" },
{ T_MD, t_dma_128k, "dma 128k mode" },
{ T_MD, t_tim_vdp_as_vram_w, "time vdp vram w" },
{ T_MD, t_tim_vdp_as_cram_w, "time vdp cram w" },
{ T_MD, t_irq_hint, "irq4 / line" },
+ { T_MD, t_irq_both_cpu_unmask, "irq both umask" },
{ T_MD, t_irq_ack_v_h, "irq ack v-h" },
{ T_MD, t_irq_ack_v_h_2, "irq ack v-h 2" },
{ T_MD, t_irq_ack_h_v, "irq ack h-v" },
{ T_MD, t_irq_f_flag_h40, "irq f flag h40" },
{ T_MD, t_irq_f_flag_h32, "irq f flag h32" },
- // the first one enables 32X, so should be kept
+ // the first one enables 32X, so must be kept
+ // all tests assume RV=1 FM=0
{ T_32, t_32x_init, "32x init" },
{ T_32, t_32x_echo, "32x echo" },
- { T_32, t_32x_md_rom, "32x rom" },
+ { T_32, t_32x_md_bios, "32x md bios" },
+ { T_32, t_32x_md_rom, "32x md rom" },
+ { T_32, t_32x_md_fb, "32x md fb" },
+ { T_32, t_32x_sh_fb, "32x sh fb" },
+ { T_32, t_32x_disable, "32x disable" }, // must be last 32x
};
static void setup_z80(void)
int passed = 0;
int skipped = 0;
int have_32x;
+ int en_32x;
int ret;
u8 v8;
int i;
VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
have_32x = read32(0xa130ec) == MKLONG('M','A','R','S');
+ en_32x = have_32x && (read32(0xa15100) & 1);
v8 = read8(0xa10001);
- printf("MD version: %02x %s %s %s\n", v8,
+ printf("MD version: %02x %s %s %s%s\n", v8,
(v8 & 0x80) ? "world" : "jap",
(v8 & 0x40) ? "pal" : "ntsc",
- have_32x ? "32X" : "");
+ have_32x ? "32X" : "",
+ en_32x ? "+" : "");
for (i = 0; i < ARRAY_SIZE(g_tests); i++) {
// print test number if we haven't scrolled away
notaz.gp2x.de / megadrive.git / blobdiff