X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=libpcsxcore%2Fpsxinterpreter.c;h=cf3de7985a3df639a4644e02bfdcd2151a31edf0;hb=HEAD;hp=e3c5baf44b494267327e076e95a62adfe9b68132;hpb=7c3332fbf8ea98bf43f5de9e966bbae77dd9f61d;p=pcsx_rearmed.git diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c index e3c5baf4..68d79321 100644 --- a/libpcsxcore/psxinterpreter.c +++ b/libpcsxcore/psxinterpreter.c @@ -36,8 +36,6 @@ #define DO_EXCEPTION_RESERVEDI #define HANDLE_LOAD_DELAY -static int branchSeen = 0; - #ifdef __i386__ #define INT_ATTR __attribute__((regparm(2))) #else @@ -128,6 +126,19 @@ static void intExceptionInsn(psxRegisters *regs, u32 cause) intException(regs, regs->pc - 4, cause); } +static noinline void intExceptionReservedInsn(psxRegisters *regs) +{ +#ifdef DO_EXCEPTION_RESERVEDI + static u32 ppc_ = ~0u; + if (regs->pc != ppc_) { + SysPrintf("reserved instruction %08x @%08x ra=%08x\n", + regs->code, regs->pc - 4, regs->GPR.n.ra); + ppc_ = regs->pc; + } + intExceptionInsn(regs, R3000E_RI << 2); +#endif +} + // 29 Enable for 80000000-ffffffff // 30 Enable for 00000000-7fffffff // 31 Enable exception @@ -143,7 +154,7 @@ static void intExceptionDebugBp(psxRegisters *regs, u32 pc) cp0->n.Cause |= (regs->branching << 30) | (R3000E_Bp << 2); cp0->n.SR = (cp0->n.SR & ~0x3f) | ((cp0->n.SR & 0x0f) << 2); cp0->n.EPC = regs->branching ? pc - 4 : pc; - psxRegs.pc = 0x80000040; + regs->pc = 0x80000040; } static int execBreakCheck(psxRegisters *regs, u32 pc) @@ -163,25 +174,21 @@ static int execBreakCheck(psxRegisters *regs, u32 pc) // get an opcode without triggering exceptions or affecting cache u32 intFakeFetch(u32 pc) { - u8 *base = psxMemRLUT[pc >> 16]; - u32 *code; - if (unlikely(base == INVALID_PTR)) + u32 *code = (u32 *)psxm(pc & ~0x3, 0); + if (unlikely(code == INVALID_PTR)) return 0; // nop - code = (u32 *)(base + (pc & 0xfffc)); return SWAP32(*code); } static u32 INT_ATTR fetchNoCache(psxRegisters *regs, u8 **memRLUT, u32 pc) { - u8 *base = memRLUT[pc >> 16]; - u32 *code; - if (unlikely(base == INVALID_PTR)) { + u32 *code = (u32 *)psxm_lut(pc & ~0x3, 0, memRLUT); + if (unlikely(code == INVALID_PTR)) { SysPrintf("game crash @%08x, ra=%08x\n", pc, regs->GPR.n.ra); intException(regs, pc, R3000E_IBE << 2); return 0; // execute as nop } - code = (u32 *)(base + (pc & 0xfffc)); return SWAP32(*code); } @@ -204,14 +211,12 @@ static u32 INT_ATTR fetchICache(psxRegisters *regs, u8 **memRLUT, u32 pc) if (((entry->tag ^ pc) & 0xfffffff0) != 0 || pc < entry->tag) { - const u8 *base = memRLUT[pc >> 16]; - const u32 *code; - if (unlikely(base == INVALID_PTR)) { + const u32 *code = (u32 *)psxm_lut(pc & ~0xf, 0, memRLUT); + if (unlikely(code == INVALID_PTR)) { SysPrintf("game crash @%08x, ra=%08x\n", pc, regs->GPR.n.ra); intException(regs, pc, R3000E_IBE << 2); return 0; // execute as nop } - code = (u32 *)(base + (pc & 0xfff0)); entry->tag = pc; // treat as 4 words, although other configurations are said to be possible @@ -405,7 +410,7 @@ static void psxDoDelayBranch(psxRegisters *regs, u32 tar1, u32 code1) { static void doBranch(psxRegisters *regs, u32 tar, enum R3000Abdt taken) { u32 code, pc, pc_final; - branchSeen = regs->branching = taken; + regs->branchSeen = regs->branching = taken; pc_final = taken == R3000A_BRANCH_TAKEN ? tar : regs->pc + 4; // fetch the delay slot @@ -751,6 +756,8 @@ static inline int checkLD(psxRegisters *regs, u32 addr, u32 m) { return 0; } if (unlikely(BUS_LOCKED_ADDR(addr))) { + log_unhandled("bus error read addr=%08x @%08x ra=%08x\n", + addr, regs->pc - 4, regs->GPR.n.ra); intException(regs, regs->pc - 4, R3000E_DBE << 2); return 0; } @@ -774,6 +781,8 @@ static inline int checkST(psxRegisters *regs, u32 addr, u32 m) { return 0; } if (unlikely(BUS_LOCKED_ADDR(addr))) { + log_unhandled("bus error write addr=%08x @%08x ra=%08x\n", + addr, regs->pc - 4, regs->GPR.n.ra); intException(regs, regs->pc - 4, R3000E_DBE << 2); return 0; } @@ -862,12 +871,12 @@ OP(psxLWR) { doLWR(regs_, _Rt_, _oB_); } OP(psxLWLe) { if (checkLD(regs_, _oB_ & ~3, 0)) doLWL(regs_, _Rt_, _oB_); } OP(psxLWRe) { if (checkLD(regs_, _oB_ , 0)) doLWR(regs_, _Rt_, _oB_); } -OP(psxSB) { psxMemWrite8 (_oB_, _rRt_ & 0xff); } -OP(psxSH) { psxMemWrite16(_oB_, _rRt_ & 0xffff); } +OP(psxSB) { psxMemWrite8 (_oB_, _rRt_); } +OP(psxSH) { psxMemWrite16(_oB_, _rRt_); } OP(psxSW) { psxMemWrite32(_oB_, _rRt_); } -OP(psxSBe) { if (checkST(regs_, _oB_, 0)) psxMemWrite8 (_oB_, _rRt_ & 0xff); } -OP(psxSHe) { if (checkST(regs_, _oB_, 1)) psxMemWrite16(_oB_, _rRt_ & 0xffff); } +OP(psxSBe) { if (checkST(regs_, _oB_, 0)) psxMemWrite8 (_oB_, _rRt_); } +OP(psxSHe) { if (checkST(regs_, _oB_, 1)) psxMemWrite16(_oB_, _rRt_); } OP(psxSWe) { if (checkST(regs_, _oB_, 3)) psxMemWrite32(_oB_, _rRt_); } static void doSWL(psxRegisters *regs, u32 rt, u32 addr) { @@ -923,10 +932,8 @@ OP(psxSWRe) { if (checkST(regs_, _oB_ , 0)) doSWR(regs_, _Rt_, _oB_); } *********************************************************/ OP(psxMFC0) { u32 r = _Rd_; -#ifdef DO_EXCEPTION_RESERVEDI if (unlikely(0x00000417u & (1u << r))) - intExceptionInsn(regs_, R3000E_RI << 2); -#endif + intExceptionReservedInsn(regs_); doLoad(regs_, _Rt_, regs_->CP0.r[r]); } @@ -936,9 +943,9 @@ void MTC0(psxRegisters *regs_, int reg, u32 val) { // SysPrintf("MTC0 %d: %x\n", reg, val); switch (reg) { case 12: // SR - if (unlikely((regs_->CP0.n.SR ^ val) & (1 << 16))) + if (unlikely((regs_->CP0.n.SR ^ val) & (1u << 16))) psxMemOnIsolate((val >> 16) & 1); - if (unlikely((regs_->CP0.n.SR ^ val) & (7 << 29))) + if (unlikely((regs_->CP0.n.SR ^ val) & (7u << 29))) setupCop(val); regs_->CP0.n.SR = val; psxTestSWInts(regs_, 1); @@ -953,8 +960,14 @@ void MTC0(psxRegisters *regs_, int reg, u32 val) { case 7: if ((regs_->CP0.n.DCIC ^ val) & 0xff800000) log_unhandled("DCIC: %08x->%08x\n", regs_->CP0.n.DCIC, val); - // fallthrough + goto default_; + case 3: + if (regs_->CP0.n.BPC != val) + log_unhandled("BPC: %08x->%08x\n", regs_->CP0.n.BPC, val); + goto default_; + default: + default_: regs_->CP0.r[reg] = val; break; } @@ -974,9 +987,7 @@ static inline void psxNULLne(psxRegisters *regs) { OP(psxNULL) { psxNULLne(regs_); -#ifdef DO_EXCEPTION_RESERVEDI - intExceptionInsn(regs_, R3000E_RI << 2); -#endif + intExceptionReservedInsn(regs_); } void gteNULL(struct psxCP2Regs *regs) { @@ -1120,7 +1131,7 @@ OP(psxHLE) { } dloadFlush(regs_); psxHLEt[hleCode](); - branchSeen = 1; + regs_->branchSeen = 1; } static void (INT_ATTR *psxBSC[64])(psxRegisters *regs_, u32 code) = { @@ -1159,6 +1170,7 @@ void (*psxCP2[64])(struct psxCP2Regs *regs) = { /////////////////////////////////////////// static int intInit() { + intApplyConfig(); return 0; } @@ -1192,31 +1204,34 @@ static inline void execIbp(u8 **memRLUT, psxRegisters *regs) { psxBSC[regs->code >> 26](regs, regs->code); } -static void intExecute() { - psxRegisters *regs_ = &psxRegs; +static void intExecute(psxRegisters *regs) { u8 **memRLUT = psxMemRLUT; - extern int stop; - while (!stop) - execI_(memRLUT, regs_); + while (!regs->stop) + execI_(memRLUT, regs); } -static void intExecuteBp() { - psxRegisters *regs_ = &psxRegs; +static void intExecuteBp(psxRegisters *regs) { u8 **memRLUT = psxMemRLUT; - extern int stop; - while (!stop) - execIbp(memRLUT, regs_); + while (!regs->stop) + execIbp(memRLUT, regs); } -void intExecuteBlock(enum blockExecCaller caller) { - psxRegisters *regs_ = &psxRegs; +static void intExecuteBlock(psxRegisters *regs, enum blockExecCaller caller) { u8 **memRLUT = psxMemRLUT; - branchSeen = 0; - while (!branchSeen) - execI_(memRLUT, regs_); + regs->branchSeen = 0; + while (!regs->branchSeen) + execI_(memRLUT, regs); +} + +static void intExecuteBlockBp(psxRegisters *regs, enum blockExecCaller caller) { + u8 **memRLUT = psxMemRLUT; + + regs->branchSeen = 0; + while (!regs->branchSeen) + execIbp(memRLUT, regs); } static void intClear(u32 Addr, u32 Size) { @@ -1233,7 +1248,8 @@ static void intNotify(enum R3000Anote note, void *data) { setupCop(psxRegs.CP0.n.SR); // fallthrough case R3000ACPU_NOTIFY_CACHE_ISOLATED: // Armored Core? - memset(&ICache, 0xff, sizeof(ICache)); + if (fetch == fetchICache) + memset(&ICache, 0xff, sizeof(ICache)); break; case R3000ACPU_NOTIFY_CACHE_UNISOLATED: break; @@ -1307,6 +1323,7 @@ void intApplyConfig() { psxSPC[0x08] = psxJRe; psxSPC[0x09] = psxJALRe; psxInt.Execute = intExecuteBp; + psxInt.ExecuteBlock = intExecuteBlockBp; } else { psxBSC[0x20] = psxLB; psxBSC[0x21] = psxLH; @@ -1324,12 +1341,15 @@ void intApplyConfig() { psxSPC[0x08] = psxJR; psxSPC[0x09] = psxJALR; psxInt.Execute = intExecute; + psxInt.ExecuteBlock = intExecuteBlock; } // the dynarec may occasionally call the interpreter, in such a case the // cache won't work (cache only works right if all fetches go through it) - if (!Config.icache_emulation || psxCpu != &psxInt) + if (!Config.icache_emulation || psxCpu != &psxInt) { fetch = fetchNoCache; + memset(&ICache, 0xff, sizeof(ICache)); + } else fetch = fetchICache;