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inline | side by side (from parent 1:
4b1c7cd)
CCREG was always manually loaded by *jump_assemble and few other
places, however when I added more CCREG allocs I expected loading
to be handled automatically, but turns out it wasn't.
static void mov_alloc(struct regstat *current,int i)
{
if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
static void mov_alloc(struct regstat *current,int i)
{
if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
- // logically this is needed but just won't work, no idea why
- //alloc_cc(current,i); // for stalls
- //dirty_reg(current,CCREG);
+ alloc_cc(current,i); // for stalls
+ dirty_reg(current,CCREG);
}
// Note: Don't need to actually alloc the source registers
}
// Note: Don't need to actually alloc the source registers
load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
}
// TODO: if(is_ooo(i)) address_generation(i+1);
load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
}
// TODO: if(is_ooo(i)) address_generation(i+1);
- if (dops[i].itype == CJUMP)
+ if (!dops[i].is_jump || dops[i].itype == CJUMP)
load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
if (ram_offset && (dops[i].is_load || dops[i].is_store))
load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
if (ram_offset && (dops[i].is_load || dops[i].is_store))
load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);