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drc: merge Ari64's patch: 13_dummy_loads
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
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57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
3d624f89 25#include "emu_if.h" //emulator interface
57871462 26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
e1190b87 87 char ooo[MAXBLOCK];
57871462 88 uint64_t unneeded_reg[MAXBLOCK];
89 uint64_t unneeded_reg_upper[MAXBLOCK];
90 uint64_t branch_unneeded_reg[MAXBLOCK];
91 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
92 uint64_t p32[MAXBLOCK];
93 uint64_t pr32[MAXBLOCK];
94 signed char regmap_pre[MAXBLOCK][HOST_REGS];
95 signed char regmap[MAXBLOCK][HOST_REGS];
96 signed char regmap_entry[MAXBLOCK][HOST_REGS];
97 uint64_t constmap[MAXBLOCK][HOST_REGS];
57871462 98 struct regstat regs[MAXBLOCK];
99 struct regstat branch_regs[MAXBLOCK];
e1190b87 100 signed char minimum_free_regs[MAXBLOCK];
57871462 101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
af4ee1fe 124#ifndef PCSX
57871462 125 u_int using_tlb;
af4ee1fe 126#else
127 static const u_int using_tlb=0;
128#endif
dadf55f2 129 static u_int sp_in_mirror;
57871462 130 u_int stop_after_jal;
131 extern u_char restore_candidate[512];
132 extern int cycle_count;
133
134 /* registers that may be allocated */
135 /* 1-31 gpr */
136#define HIREG 32 // hi
137#define LOREG 33 // lo
138#define FSREG 34 // FPU status (FCSR)
139#define CSREG 35 // Coprocessor status
140#define CCREG 36 // Cycle count
141#define INVCP 37 // Pointer to invalid_code
619e5ded 142#define MMREG 38 // Pointer to memory_map
143#define ROREG 39 // ram offset (if rdram!=0x80000000)
144#define TEMPREG 40
145#define FTEMP 40 // FPU temporary register
146#define PTEMP 41 // Prefetch temporary register
147#define TLREG 42 // TLB mapping offset
148#define RHASH 43 // Return address hash
149#define RHTBL 44 // Return address hash table address
150#define RTEMP 45 // JR/JALR address register
151#define MAXREG 45
152#define AGEN1 46 // Address generation temporary register
153#define AGEN2 47 // Address generation temporary register
154#define MGEN1 48 // Maptable address generation temporary register
155#define MGEN2 49 // Maptable address generation temporary register
156#define BTREG 50 // Branch target temporary register
57871462 157
158 /* instruction types */
159#define NOP 0 // No operation
160#define LOAD 1 // Load
161#define STORE 2 // Store
162#define LOADLR 3 // Unaligned load
163#define STORELR 4 // Unaligned store
164#define MOV 5 // Move
165#define ALU 6 // Arithmetic/logic
166#define MULTDIV 7 // Multiply/divide
167#define SHIFT 8 // Shift by register
168#define SHIFTIMM 9// Shift by immediate
169#define IMM16 10 // 16-bit immediate
170#define RJUMP 11 // Unconditional jump to register
171#define UJUMP 12 // Unconditional jump
172#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
173#define SJUMP 14 // Conditional branch (regimm format)
174#define COP0 15 // Coprocessor 0
175#define COP1 16 // Coprocessor 1
176#define C1LS 17 // Coprocessor 1 load/store
177#define FJUMP 18 // Conditional branch (floating point)
178#define FLOAT 19 // Floating point unit
179#define FCONV 20 // Convert integer to float
180#define FCOMP 21 // Floating point compare (sets FSREG)
181#define SYSCALL 22// SYSCALL
182#define OTHER 23 // Other
183#define SPAN 24 // Branch/delay slot spans 2 pages
184#define NI 25 // Not implemented
7139f3c8 185#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 186#define COP2 27 // Coprocessor 2 move
187#define C2LS 28 // Coprocessor 2 load/store
188#define C2OP 29 // Coprocessor 2 operation
1e973cb0 189#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 190
191 /* stubs */
192#define CC_STUB 1
193#define FP_STUB 2
194#define LOADB_STUB 3
195#define LOADH_STUB 4
196#define LOADW_STUB 5
197#define LOADD_STUB 6
198#define LOADBU_STUB 7
199#define LOADHU_STUB 8
200#define STOREB_STUB 9
201#define STOREH_STUB 10
202#define STOREW_STUB 11
203#define STORED_STUB 12
204#define STORELR_STUB 13
205#define INVCODE_STUB 14
206
207 /* branch codes */
208#define TAKEN 1
209#define NOTTAKEN 2
210#define NULLDS 3
211
212// asm linkage
213int new_recompile_block(int addr);
214void *get_addr_ht(u_int vaddr);
215void invalidate_block(u_int block);
216void invalidate_addr(u_int addr);
217void remove_hash(int vaddr);
218void jump_vaddr();
219void dyna_linker();
220void dyna_linker_ds();
221void verify_code();
222void verify_code_vm();
223void verify_code_ds();
224void cc_interrupt();
225void fp_exception();
226void fp_exception_ds();
227void jump_syscall();
7139f3c8 228void jump_syscall_hle();
57871462 229void jump_eret();
7139f3c8 230void jump_hlecall();
1e973cb0 231void jump_intcall();
7139f3c8 232void new_dyna_leave();
57871462 233
234// TLB
235void TLBWI_new();
236void TLBWR_new();
237void read_nomem_new();
238void read_nomemb_new();
239void read_nomemh_new();
240void read_nomemd_new();
241void write_nomem_new();
242void write_nomemb_new();
243void write_nomemh_new();
244void write_nomemd_new();
245void write_rdram_new();
246void write_rdramb_new();
247void write_rdramh_new();
248void write_rdramd_new();
249extern u_int memory_map[1048576];
250
251// Needed by assembler
252void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
253void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
254void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
255void load_all_regs(signed char i_regmap[]);
256void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
257void load_regs_entry(int t);
258void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
259
260int tracedebug=0;
261
262//#define DEBUG_CYCLE_COUNT 1
263
264void nullf() {}
265//#define assem_debug printf
266//#define inv_debug printf
267#define assem_debug nullf
268#define inv_debug nullf
269
94d23bb9 270static void tlb_hacks()
57871462 271{
94d23bb9 272#ifndef DISABLE_TLB
57871462 273 // Goldeneye hack
274 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
275 {
276 u_int addr;
277 int n;
278 switch (ROM_HEADER->Country_code&0xFF)
279 {
280 case 0x45: // U
281 addr=0x34b30;
282 break;
283 case 0x4A: // J
284 addr=0x34b70;
285 break;
286 case 0x50: // E
287 addr=0x329f0;
288 break;
289 default:
290 // Unknown country code
291 addr=0;
292 break;
293 }
294 u_int rom_addr=(u_int)rom;
295 #ifdef ROM_COPY
296 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
297 // in the lower 4G of memory to use this hack. Copy it if necessary.
298 if((void *)rom>(void *)0xffffffff) {
299 munmap(ROM_COPY, 67108864);
300 if(mmap(ROM_COPY, 12582912,
301 PROT_READ | PROT_WRITE,
302 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
303 -1, 0) <= 0) {printf("mmap() failed\n");}
304 memcpy(ROM_COPY,rom,12582912);
305 rom_addr=(u_int)ROM_COPY;
306 }
307 #endif
308 if(addr) {
309 for(n=0x7F000;n<0x80000;n++) {
310 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
311 }
312 }
313 }
94d23bb9 314#endif
57871462 315}
316
94d23bb9 317static u_int get_page(u_int vaddr)
57871462 318{
0ce47d46 319#ifndef PCSX
57871462 320 u_int page=(vaddr^0x80000000)>>12;
0ce47d46 321#else
322 u_int page=vaddr&~0xe0000000;
323 if (page < 0x1000000)
324 page &= ~0x0e00000; // RAM mirrors
325 page>>=12;
326#endif
94d23bb9 327#ifndef DISABLE_TLB
57871462 328 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 329#endif
57871462 330 if(page>2048) page=2048+(page&2047);
94d23bb9 331 return page;
332}
333
334static u_int get_vpage(u_int vaddr)
335{
336 u_int vpage=(vaddr^0x80000000)>>12;
337#ifndef DISABLE_TLB
57871462 338 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 339#endif
57871462 340 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 341 return vpage;
342}
343
344// Get address from virtual address
345// This is called from the recompiled JR/JALR instructions
346void *get_addr(u_int vaddr)
347{
348 u_int page=get_page(vaddr);
349 u_int vpage=get_vpage(vaddr);
57871462 350 struct ll_entry *head;
351 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
352 head=jump_in[page];
353 while(head!=NULL) {
354 if(head->vaddr==vaddr&&head->reg32==0) {
355 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
356 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
357 ht_bin[3]=ht_bin[1];
358 ht_bin[2]=ht_bin[0];
359 ht_bin[1]=(int)head->addr;
360 ht_bin[0]=vaddr;
361 return head->addr;
362 }
363 head=head->next;
364 }
365 head=jump_dirty[vpage];
366 while(head!=NULL) {
367 if(head->vaddr==vaddr&&head->reg32==0) {
368 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
369 // Don't restore blocks which are about to expire from the cache
370 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
371 if(verify_dirty(head->addr)) {
372 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
373 invalid_code[vaddr>>12]=0;
374 memory_map[vaddr>>12]|=0x40000000;
375 if(vpage<2048) {
94d23bb9 376#ifndef DISABLE_TLB
57871462 377 if(tlb_LUT_r[vaddr>>12]) {
378 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
379 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
380 }
94d23bb9 381#endif
57871462 382 restore_candidate[vpage>>3]|=1<<(vpage&7);
383 }
384 else restore_candidate[page>>3]|=1<<(page&7);
385 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
386 if(ht_bin[0]==vaddr) {
387 ht_bin[1]=(int)head->addr; // Replace existing entry
388 }
389 else
390 {
391 ht_bin[3]=ht_bin[1];
392 ht_bin[2]=ht_bin[0];
393 ht_bin[1]=(int)head->addr;
394 ht_bin[0]=vaddr;
395 }
396 return head->addr;
397 }
398 }
399 head=head->next;
400 }
401 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
402 int r=new_recompile_block(vaddr);
403 if(r==0) return get_addr(vaddr);
404 // Execute in unmapped page, generate pagefault execption
405 Status|=2;
406 Cause=(vaddr<<31)|0x8;
407 EPC=(vaddr&1)?vaddr-5:vaddr;
408 BadVAddr=(vaddr&~1);
409 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
410 EntryHi=BadVAddr&0xFFFFE000;
411 return get_addr_ht(0x80000000);
412}
413// Look up address in hash table first
414void *get_addr_ht(u_int vaddr)
415{
416 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
417 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
418 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
419 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
420 return get_addr(vaddr);
421}
422
423void *get_addr_32(u_int vaddr,u_int flags)
424{
7139f3c8 425#ifdef FORCE32
426 return get_addr(vaddr);
560e4a12 427#else
57871462 428 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
429 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
430 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
431 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 432 u_int page=get_page(vaddr);
433 u_int vpage=get_vpage(vaddr);
57871462 434 struct ll_entry *head;
435 head=jump_in[page];
436 while(head!=NULL) {
437 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
438 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
439 if(head->reg32==0) {
440 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
441 if(ht_bin[0]==-1) {
442 ht_bin[1]=(int)head->addr;
443 ht_bin[0]=vaddr;
444 }else if(ht_bin[2]==-1) {
445 ht_bin[3]=(int)head->addr;
446 ht_bin[2]=vaddr;
447 }
448 //ht_bin[3]=ht_bin[1];
449 //ht_bin[2]=ht_bin[0];
450 //ht_bin[1]=(int)head->addr;
451 //ht_bin[0]=vaddr;
452 }
453 return head->addr;
454 }
455 head=head->next;
456 }
457 head=jump_dirty[vpage];
458 while(head!=NULL) {
459 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
460 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
461 // Don't restore blocks which are about to expire from the cache
462 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
463 if(verify_dirty(head->addr)) {
464 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
465 invalid_code[vaddr>>12]=0;
466 memory_map[vaddr>>12]|=0x40000000;
467 if(vpage<2048) {
94d23bb9 468#ifndef DISABLE_TLB
57871462 469 if(tlb_LUT_r[vaddr>>12]) {
470 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
471 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
472 }
94d23bb9 473#endif
57871462 474 restore_candidate[vpage>>3]|=1<<(vpage&7);
475 }
476 else restore_candidate[page>>3]|=1<<(page&7);
477 if(head->reg32==0) {
478 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
479 if(ht_bin[0]==-1) {
480 ht_bin[1]=(int)head->addr;
481 ht_bin[0]=vaddr;
482 }else if(ht_bin[2]==-1) {
483 ht_bin[3]=(int)head->addr;
484 ht_bin[2]=vaddr;
485 }
486 //ht_bin[3]=ht_bin[1];
487 //ht_bin[2]=ht_bin[0];
488 //ht_bin[1]=(int)head->addr;
489 //ht_bin[0]=vaddr;
490 }
491 return head->addr;
492 }
493 }
494 head=head->next;
495 }
496 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
497 int r=new_recompile_block(vaddr);
498 if(r==0) return get_addr(vaddr);
499 // Execute in unmapped page, generate pagefault execption
500 Status|=2;
501 Cause=(vaddr<<31)|0x8;
502 EPC=(vaddr&1)?vaddr-5:vaddr;
503 BadVAddr=(vaddr&~1);
504 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
505 EntryHi=BadVAddr&0xFFFFE000;
506 return get_addr_ht(0x80000000);
560e4a12 507#endif
57871462 508}
509
510void clear_all_regs(signed char regmap[])
511{
512 int hr;
513 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
514}
515
516signed char get_reg(signed char regmap[],int r)
517{
518 int hr;
519 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
520 return -1;
521}
522
523// Find a register that is available for two consecutive cycles
524signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
525{
526 int hr;
527 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
528 return -1;
529}
530
531int count_free_regs(signed char regmap[])
532{
533 int count=0;
534 int hr;
535 for(hr=0;hr<HOST_REGS;hr++)
536 {
537 if(hr!=EXCLUDE_REG) {
538 if(regmap[hr]<0) count++;
539 }
540 }
541 return count;
542}
543
544void dirty_reg(struct regstat *cur,signed char reg)
545{
546 int hr;
547 if(!reg) return;
548 for (hr=0;hr<HOST_REGS;hr++) {
549 if((cur->regmap[hr]&63)==reg) {
550 cur->dirty|=1<<hr;
551 }
552 }
553}
554
555// If we dirty the lower half of a 64 bit register which is now being
556// sign-extended, we need to dump the upper half.
557// Note: Do this only after completion of the instruction, because
558// some instructions may need to read the full 64-bit value even if
559// overwriting it (eg SLTI, DSRA32).
560static void flush_dirty_uppers(struct regstat *cur)
561{
562 int hr,reg;
563 for (hr=0;hr<HOST_REGS;hr++) {
564 if((cur->dirty>>hr)&1) {
565 reg=cur->regmap[hr];
566 if(reg>=64)
567 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
568 }
569 }
570}
571
572void set_const(struct regstat *cur,signed char reg,uint64_t value)
573{
574 int hr;
575 if(!reg) return;
576 for (hr=0;hr<HOST_REGS;hr++) {
577 if(cur->regmap[hr]==reg) {
578 cur->isconst|=1<<hr;
579 cur->constmap[hr]=value;
580 }
581 else if((cur->regmap[hr]^64)==reg) {
582 cur->isconst|=1<<hr;
583 cur->constmap[hr]=value>>32;
584 }
585 }
586}
587
588void clear_const(struct regstat *cur,signed char reg)
589{
590 int hr;
591 if(!reg) return;
592 for (hr=0;hr<HOST_REGS;hr++) {
593 if((cur->regmap[hr]&63)==reg) {
594 cur->isconst&=~(1<<hr);
595 }
596 }
597}
598
599int is_const(struct regstat *cur,signed char reg)
600{
601 int hr;
79c75f1b 602 if(reg<0) return 0;
57871462 603 if(!reg) return 1;
604 for (hr=0;hr<HOST_REGS;hr++) {
605 if((cur->regmap[hr]&63)==reg) {
606 return (cur->isconst>>hr)&1;
607 }
608 }
609 return 0;
610}
611uint64_t get_const(struct regstat *cur,signed char reg)
612{
613 int hr;
614 if(!reg) return 0;
615 for (hr=0;hr<HOST_REGS;hr++) {
616 if(cur->regmap[hr]==reg) {
617 return cur->constmap[hr];
618 }
619 }
620 printf("Unknown constant in r%d\n",reg);
621 exit(1);
622}
623
624// Least soon needed registers
625// Look at the next ten instructions and see which registers
626// will be used. Try not to reallocate these.
627void lsn(u_char hsn[], int i, int *preferred_reg)
628{
629 int j;
630 int b=-1;
631 for(j=0;j<9;j++)
632 {
633 if(i+j>=slen) {
634 j=slen-i-1;
635 break;
636 }
637 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
638 {
639 // Don't go past an unconditonal jump
640 j++;
641 break;
642 }
643 }
644 for(;j>=0;j--)
645 {
646 if(rs1[i+j]) hsn[rs1[i+j]]=j;
647 if(rs2[i+j]) hsn[rs2[i+j]]=j;
648 if(rt1[i+j]) hsn[rt1[i+j]]=j;
649 if(rt2[i+j]) hsn[rt2[i+j]]=j;
650 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
651 // Stores can allocate zero
652 hsn[rs1[i+j]]=j;
653 hsn[rs2[i+j]]=j;
654 }
655 // On some architectures stores need invc_ptr
656 #if defined(HOST_IMM8)
b9b61529 657 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 658 hsn[INVCP]=j;
659 }
660 #endif
661 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
662 {
663 hsn[CCREG]=j;
664 b=j;
665 }
666 }
667 if(b>=0)
668 {
669 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
670 {
671 // Follow first branch
672 int t=(ba[i+b]-start)>>2;
673 j=7-b;if(t+j>=slen) j=slen-t-1;
674 for(;j>=0;j--)
675 {
676 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
677 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
678 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
679 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
680 }
681 }
682 // TODO: preferred register based on backward branch
683 }
684 // Delay slot should preferably not overwrite branch conditions or cycle count
685 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
686 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
687 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
688 hsn[CCREG]=1;
689 // ...or hash tables
690 hsn[RHASH]=1;
691 hsn[RHTBL]=1;
692 }
693 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 694 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 695 hsn[FTEMP]=0;
696 }
697 // Load L/R also uses FTEMP as a temporary register
698 if(itype[i]==LOADLR) {
699 hsn[FTEMP]=0;
700 }
b7918751 701 // Also SWL/SWR/SDL/SDR
702 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 703 hsn[FTEMP]=0;
704 }
705 // Don't remove the TLB registers either
b9b61529 706 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 707 hsn[TLREG]=0;
708 }
709 // Don't remove the miniht registers
710 if(itype[i]==UJUMP||itype[i]==RJUMP)
711 {
712 hsn[RHASH]=0;
713 hsn[RHTBL]=0;
714 }
715}
716
717// We only want to allocate registers if we're going to use them again soon
718int needed_again(int r, int i)
719{
720 int j;
721 int b=-1;
722 int rn=10;
57871462 723
724 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
725 {
726 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
727 return 0; // Don't need any registers if exiting the block
728 }
729 for(j=0;j<9;j++)
730 {
731 if(i+j>=slen) {
732 j=slen-i-1;
733 break;
734 }
735 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
736 {
737 // Don't go past an unconditonal jump
738 j++;
739 break;
740 }
1e973cb0 741 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 742 {
743 break;
744 }
745 }
746 for(;j>=1;j--)
747 {
748 if(rs1[i+j]==r) rn=j;
749 if(rs2[i+j]==r) rn=j;
750 if((unneeded_reg[i+j]>>r)&1) rn=10;
751 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
752 {
753 b=j;
754 }
755 }
756 /*
757 if(b>=0)
758 {
759 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
760 {
761 // Follow first branch
762 int o=rn;
763 int t=(ba[i+b]-start)>>2;
764 j=7-b;if(t+j>=slen) j=slen-t-1;
765 for(;j>=0;j--)
766 {
767 if(!((unneeded_reg[t+j]>>r)&1)) {
768 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
769 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
770 }
771 else rn=o;
772 }
773 }
774 }*/
b7217e13 775 if(rn<10) return 1;
57871462 776 return 0;
777}
778
779// Try to match register allocations at the end of a loop with those
780// at the beginning
781int loop_reg(int i, int r, int hr)
782{
783 int j,k;
784 for(j=0;j<9;j++)
785 {
786 if(i+j>=slen) {
787 j=slen-i-1;
788 break;
789 }
790 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
791 {
792 // Don't go past an unconditonal jump
793 j++;
794 break;
795 }
796 }
797 k=0;
798 if(i>0){
799 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
800 k--;
801 }
802 for(;k<j;k++)
803 {
804 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
805 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
806 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
807 {
808 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
809 {
810 int t=(ba[i+k]-start)>>2;
811 int reg=get_reg(regs[t].regmap_entry,r);
812 if(reg>=0) return reg;
813 //reg=get_reg(regs[t+1].regmap_entry,r);
814 //if(reg>=0) return reg;
815 }
816 }
817 }
818 return hr;
819}
820
821
822// Allocate every register, preserving source/target regs
823void alloc_all(struct regstat *cur,int i)
824{
825 int hr;
826
827 for(hr=0;hr<HOST_REGS;hr++) {
828 if(hr!=EXCLUDE_REG) {
829 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
830 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
831 {
832 cur->regmap[hr]=-1;
833 cur->dirty&=~(1<<hr);
834 }
835 // Don't need zeros
836 if((cur->regmap[hr]&63)==0)
837 {
838 cur->regmap[hr]=-1;
839 cur->dirty&=~(1<<hr);
840 }
841 }
842 }
843}
844
845
846void div64(int64_t dividend,int64_t divisor)
847{
848 lo=dividend/divisor;
849 hi=dividend%divisor;
850 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
851 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
852}
853void divu64(uint64_t dividend,uint64_t divisor)
854{
855 lo=dividend/divisor;
856 hi=dividend%divisor;
857 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
858 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
859}
860
861void mult64(uint64_t m1,uint64_t m2)
862{
863 unsigned long long int op1, op2, op3, op4;
864 unsigned long long int result1, result2, result3, result4;
865 unsigned long long int temp1, temp2, temp3, temp4;
866 int sign = 0;
867
868 if (m1 < 0)
869 {
870 op2 = -m1;
871 sign = 1 - sign;
872 }
873 else op2 = m1;
874 if (m2 < 0)
875 {
876 op4 = -m2;
877 sign = 1 - sign;
878 }
879 else op4 = m2;
880
881 op1 = op2 & 0xFFFFFFFF;
882 op2 = (op2 >> 32) & 0xFFFFFFFF;
883 op3 = op4 & 0xFFFFFFFF;
884 op4 = (op4 >> 32) & 0xFFFFFFFF;
885
886 temp1 = op1 * op3;
887 temp2 = (temp1 >> 32) + op1 * op4;
888 temp3 = op2 * op3;
889 temp4 = (temp3 >> 32) + op2 * op4;
890
891 result1 = temp1 & 0xFFFFFFFF;
892 result2 = temp2 + (temp3 & 0xFFFFFFFF);
893 result3 = (result2 >> 32) + temp4;
894 result4 = (result3 >> 32);
895
896 lo = result1 | (result2 << 32);
897 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
898 if (sign)
899 {
900 hi = ~hi;
901 if (!lo) hi++;
902 else lo = ~lo + 1;
903 }
904}
905
906void multu64(uint64_t m1,uint64_t m2)
907{
908 unsigned long long int op1, op2, op3, op4;
909 unsigned long long int result1, result2, result3, result4;
910 unsigned long long int temp1, temp2, temp3, temp4;
911
912 op1 = m1 & 0xFFFFFFFF;
913 op2 = (m1 >> 32) & 0xFFFFFFFF;
914 op3 = m2 & 0xFFFFFFFF;
915 op4 = (m2 >> 32) & 0xFFFFFFFF;
916
917 temp1 = op1 * op3;
918 temp2 = (temp1 >> 32) + op1 * op4;
919 temp3 = op2 * op3;
920 temp4 = (temp3 >> 32) + op2 * op4;
921
922 result1 = temp1 & 0xFFFFFFFF;
923 result2 = temp2 + (temp3 & 0xFFFFFFFF);
924 result3 = (result2 >> 32) + temp4;
925 result4 = (result3 >> 32);
926
927 lo = result1 | (result2 << 32);
928 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
929
930 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
931 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
932}
933
934uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
935{
936 if(bits) {
937 original<<=64-bits;
938 original>>=64-bits;
939 loaded<<=bits;
940 original|=loaded;
941 }
942 else original=loaded;
943 return original;
944}
945uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
946{
947 if(bits^56) {
948 original>>=64-(bits^56);
949 original<<=64-(bits^56);
950 loaded>>=bits^56;
951 original|=loaded;
952 }
953 else original=loaded;
954 return original;
955}
956
957#ifdef __i386__
958#include "assem_x86.c"
959#endif
960#ifdef __x86_64__
961#include "assem_x64.c"
962#endif
963#ifdef __arm__
964#include "assem_arm.c"
965#endif
966
967// Add virtual address mapping to linked list
968void ll_add(struct ll_entry **head,int vaddr,void *addr)
969{
970 struct ll_entry *new_entry;
971 new_entry=malloc(sizeof(struct ll_entry));
972 assert(new_entry!=NULL);
973 new_entry->vaddr=vaddr;
974 new_entry->reg32=0;
975 new_entry->addr=addr;
976 new_entry->next=*head;
977 *head=new_entry;
978}
979
980// Add virtual address mapping for 32-bit compiled block
981void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
982{
7139f3c8 983 ll_add(head,vaddr,addr);
984#ifndef FORCE32
985 (*head)->reg32=reg32;
986#endif
57871462 987}
988
989// Check if an address is already compiled
990// but don't return addresses which are about to expire from the cache
991void *check_addr(u_int vaddr)
992{
993 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
994 if(ht_bin[0]==vaddr) {
995 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
996 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
997 }
998 if(ht_bin[2]==vaddr) {
999 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1000 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1001 }
94d23bb9 1002 u_int page=get_page(vaddr);
57871462 1003 struct ll_entry *head;
1004 head=jump_in[page];
1005 while(head!=NULL) {
1006 if(head->vaddr==vaddr&&head->reg32==0) {
1007 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1008 // Update existing entry with current address
1009 if(ht_bin[0]==vaddr) {
1010 ht_bin[1]=(int)head->addr;
1011 return head->addr;
1012 }
1013 if(ht_bin[2]==vaddr) {
1014 ht_bin[3]=(int)head->addr;
1015 return head->addr;
1016 }
1017 // Insert into hash table with low priority.
1018 // Don't evict existing entries, as they are probably
1019 // addresses that are being accessed frequently.
1020 if(ht_bin[0]==-1) {
1021 ht_bin[1]=(int)head->addr;
1022 ht_bin[0]=vaddr;
1023 }else if(ht_bin[2]==-1) {
1024 ht_bin[3]=(int)head->addr;
1025 ht_bin[2]=vaddr;
1026 }
1027 return head->addr;
1028 }
1029 }
1030 head=head->next;
1031 }
1032 return 0;
1033}
1034
1035void remove_hash(int vaddr)
1036{
1037 //printf("remove hash: %x\n",vaddr);
1038 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1039 if(ht_bin[2]==vaddr) {
1040 ht_bin[2]=ht_bin[3]=-1;
1041 }
1042 if(ht_bin[0]==vaddr) {
1043 ht_bin[0]=ht_bin[2];
1044 ht_bin[1]=ht_bin[3];
1045 ht_bin[2]=ht_bin[3]=-1;
1046 }
1047}
1048
1049void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1050{
1051 struct ll_entry *next;
1052 while(*head) {
1053 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1054 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1055 {
1056 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1057 remove_hash((*head)->vaddr);
1058 next=(*head)->next;
1059 free(*head);
1060 *head=next;
1061 }
1062 else
1063 {
1064 head=&((*head)->next);
1065 }
1066 }
1067}
1068
1069// Remove all entries from linked list
1070void ll_clear(struct ll_entry **head)
1071{
1072 struct ll_entry *cur;
1073 struct ll_entry *next;
1074 if(cur=*head) {
1075 *head=0;
1076 while(cur) {
1077 next=cur->next;
1078 free(cur);
1079 cur=next;
1080 }
1081 }
1082}
1083
1084// Dereference the pointers and remove if it matches
1085void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1086{
1087 while(head) {
1088 int ptr=get_pointer(head->addr);
1089 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1090 if(((ptr>>shift)==(addr>>shift)) ||
1091 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1092 {
5088bb70 1093 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 1094 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1095 #ifdef __arm__
1096 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1097 #endif
57871462 1098 }
1099 head=head->next;
1100 }
1101}
1102
1103// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1104void invalidate_page(u_int page)
57871462 1105{
57871462 1106 struct ll_entry *head;
1107 struct ll_entry *next;
1108 head=jump_in[page];
1109 jump_in[page]=0;
1110 while(head!=NULL) {
1111 inv_debug("INVALIDATE: %x\n",head->vaddr);
1112 remove_hash(head->vaddr);
1113 next=head->next;
1114 free(head);
1115 head=next;
1116 }
1117 head=jump_out[page];
1118 jump_out[page]=0;
1119 while(head!=NULL) {
1120 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1121 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1122 #ifdef __arm__
1123 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1124 #endif
57871462 1125 next=head->next;
1126 free(head);
1127 head=next;
1128 }
57871462 1129}
1130void invalidate_block(u_int block)
1131{
94d23bb9 1132 u_int page=get_page(block<<12);
1133 u_int vpage=get_vpage(block<<12);
57871462 1134 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1135 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1136 u_int first,last;
1137 first=last=page;
1138 struct ll_entry *head;
1139 head=jump_dirty[vpage];
1140 //printf("page=%d vpage=%d\n",page,vpage);
1141 while(head!=NULL) {
1142 u_int start,end;
1143 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1144 get_bounds((int)head->addr,&start,&end);
1145 //printf("start: %x end: %x\n",start,end);
4cb76aa4 1146 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
57871462 1147 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1148 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1149 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1150 }
1151 }
90ae6d4e 1152#ifndef DISABLE_TLB
57871462 1153 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1154 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1155 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1156 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1157 }
1158 }
90ae6d4e 1159#endif
57871462 1160 }
1161 head=head->next;
1162 }
1163 //printf("first=%d last=%d\n",first,last);
f76eeef9 1164 invalidate_page(page);
57871462 1165 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1166 assert(last<page+5);
1167 // Invalidate the adjacent pages if a block crosses a 4K boundary
1168 while(first<page) {
1169 invalidate_page(first);
1170 first++;
1171 }
1172 for(first=page+1;first<last;first++) {
1173 invalidate_page(first);
1174 }
dd3a91a1 1175 #ifdef __arm__
1176 do_clear_cache();
1177 #endif
57871462 1178
1179 // Don't trap writes
1180 invalid_code[block]=1;
b12c9fb8 1181#ifdef PCSX
1182 invalid_code[((u_int)0x80000000>>12)|page]=1;
1183#endif
94d23bb9 1184#ifndef DISABLE_TLB
57871462 1185 // If there is a valid TLB entry for this page, remove write protect
1186 if(tlb_LUT_w[block]) {
1187 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1188 // CHECK: Is this right?
1189 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1190 u_int real_block=tlb_LUT_w[block]>>12;
1191 invalid_code[real_block]=1;
1192 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1193 }
1194 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1195#endif
f76eeef9 1196
57871462 1197 #ifdef USE_MINI_HT
1198 memset(mini_ht,-1,sizeof(mini_ht));
1199 #endif
1200}
1201void invalidate_addr(u_int addr)
1202{
1203 invalidate_block(addr>>12);
1204}
dd3a91a1 1205// This is called when loading a save state.
1206// Anything could have changed, so invalidate everything.
57871462 1207void invalidate_all_pages()
1208{
1209 u_int page,n;
1210 for(page=0;page<4096;page++)
1211 invalidate_page(page);
1212 for(page=0;page<1048576;page++)
1213 if(!invalid_code[page]) {
1214 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1215 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1216 }
1217 #ifdef __arm__
1218 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1219 #endif
1220 #ifdef USE_MINI_HT
1221 memset(mini_ht,-1,sizeof(mini_ht));
1222 #endif
94d23bb9 1223 #ifndef DISABLE_TLB
57871462 1224 // TLB
1225 for(page=0;page<0x100000;page++) {
1226 if(tlb_LUT_r[page]) {
1227 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1228 if(!tlb_LUT_w[page]||!invalid_code[page])
1229 memory_map[page]|=0x40000000; // Write protect
1230 }
1231 else memory_map[page]=-1;
1232 if(page==0x80000) page=0xC0000;
1233 }
1234 tlb_hacks();
94d23bb9 1235 #endif
57871462 1236}
1237
1238// Add an entry to jump_out after making a link
1239void add_link(u_int vaddr,void *src)
1240{
94d23bb9 1241 u_int page=get_page(vaddr);
57871462 1242 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1243 ll_add(jump_out+page,vaddr,src);
1244 //int ptr=get_pointer(src);
1245 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1246}
1247
1248// If a code block was found to be unmodified (bit was set in
1249// restore_candidate) and it remains unmodified (bit is clear
1250// in invalid_code) then move the entries for that 4K page from
1251// the dirty list to the clean list.
1252void clean_blocks(u_int page)
1253{
1254 struct ll_entry *head;
1255 inv_debug("INV: clean_blocks page=%d\n",page);
1256 head=jump_dirty[page];
1257 while(head!=NULL) {
1258 if(!invalid_code[head->vaddr>>12]) {
1259 // Don't restore blocks which are about to expire from the cache
1260 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1261 u_int start,end;
1262 if(verify_dirty((int)head->addr)) {
1263 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1264 u_int i;
1265 u_int inv=0;
1266 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1267 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1268 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1269 inv|=invalid_code[i];
1270 }
1271 }
1272 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1273 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1274 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1275 if(addr<start||addr>=end) inv=1;
1276 }
4cb76aa4 1277 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1278 inv=1;
1279 }
1280 if(!inv) {
1281 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1282 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1283 u_int ppage=page;
94d23bb9 1284#ifndef DISABLE_TLB
57871462 1285 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1286#endif
57871462 1287 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1288 //printf("page=%x, addr=%x\n",page,head->vaddr);
1289 //assert(head->vaddr>>12==(page|0x80000));
1290 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1291 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1292 if(!head->reg32) {
1293 if(ht_bin[0]==head->vaddr) {
1294 ht_bin[1]=(int)clean_addr; // Replace existing entry
1295 }
1296 if(ht_bin[2]==head->vaddr) {
1297 ht_bin[3]=(int)clean_addr; // Replace existing entry
1298 }
1299 }
1300 }
1301 }
1302 }
1303 }
1304 }
1305 head=head->next;
1306 }
1307}
1308
1309
1310void mov_alloc(struct regstat *current,int i)
1311{
1312 // Note: Don't need to actually alloc the source registers
1313 if((~current->is32>>rs1[i])&1) {
1314 //alloc_reg64(current,i,rs1[i]);
1315 alloc_reg64(current,i,rt1[i]);
1316 current->is32&=~(1LL<<rt1[i]);
1317 } else {
1318 //alloc_reg(current,i,rs1[i]);
1319 alloc_reg(current,i,rt1[i]);
1320 current->is32|=(1LL<<rt1[i]);
1321 }
1322 clear_const(current,rs1[i]);
1323 clear_const(current,rt1[i]);
1324 dirty_reg(current,rt1[i]);
1325}
1326
1327void shiftimm_alloc(struct regstat *current,int i)
1328{
1329 clear_const(current,rs1[i]);
1330 clear_const(current,rt1[i]);
1331 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1332 {
1333 if(rt1[i]) {
1334 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1335 else lt1[i]=rs1[i];
1336 alloc_reg(current,i,rt1[i]);
1337 current->is32|=1LL<<rt1[i];
1338 dirty_reg(current,rt1[i]);
1339 }
1340 }
1341 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1342 {
1343 if(rt1[i]) {
1344 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1345 alloc_reg64(current,i,rt1[i]);
1346 current->is32&=~(1LL<<rt1[i]);
1347 dirty_reg(current,rt1[i]);
1348 }
1349 }
1350 if(opcode2[i]==0x3c) // DSLL32
1351 {
1352 if(rt1[i]) {
1353 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1354 alloc_reg64(current,i,rt1[i]);
1355 current->is32&=~(1LL<<rt1[i]);
1356 dirty_reg(current,rt1[i]);
1357 }
1358 }
1359 if(opcode2[i]==0x3e) // DSRL32
1360 {
1361 if(rt1[i]) {
1362 alloc_reg64(current,i,rs1[i]);
1363 if(imm[i]==32) {
1364 alloc_reg64(current,i,rt1[i]);
1365 current->is32&=~(1LL<<rt1[i]);
1366 } else {
1367 alloc_reg(current,i,rt1[i]);
1368 current->is32|=1LL<<rt1[i];
1369 }
1370 dirty_reg(current,rt1[i]);
1371 }
1372 }
1373 if(opcode2[i]==0x3f) // DSRA32
1374 {
1375 if(rt1[i]) {
1376 alloc_reg64(current,i,rs1[i]);
1377 alloc_reg(current,i,rt1[i]);
1378 current->is32|=1LL<<rt1[i];
1379 dirty_reg(current,rt1[i]);
1380 }
1381 }
1382}
1383
1384void shift_alloc(struct regstat *current,int i)
1385{
1386 if(rt1[i]) {
1387 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1388 {
1389 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1390 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1391 alloc_reg(current,i,rt1[i]);
e1190b87 1392 if(rt1[i]==rs2[i]) {
1393 alloc_reg_temp(current,i,-1);
1394 minimum_free_regs[i]=1;
1395 }
57871462 1396 current->is32|=1LL<<rt1[i];
1397 } else { // DSLLV/DSRLV/DSRAV
1398 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1399 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1400 alloc_reg64(current,i,rt1[i]);
1401 current->is32&=~(1LL<<rt1[i]);
1402 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1403 {
57871462 1404 alloc_reg_temp(current,i,-1);
e1190b87 1405 minimum_free_regs[i]=1;
1406 }
57871462 1407 }
1408 clear_const(current,rs1[i]);
1409 clear_const(current,rs2[i]);
1410 clear_const(current,rt1[i]);
1411 dirty_reg(current,rt1[i]);
1412 }
1413}
1414
1415void alu_alloc(struct regstat *current,int i)
1416{
1417 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1418 if(rt1[i]) {
1419 if(rs1[i]&&rs2[i]) {
1420 alloc_reg(current,i,rs1[i]);
1421 alloc_reg(current,i,rs2[i]);
1422 }
1423 else {
1424 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1425 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1426 }
1427 alloc_reg(current,i,rt1[i]);
1428 }
1429 current->is32|=1LL<<rt1[i];
1430 }
1431 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1432 if(rt1[i]) {
1433 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1434 {
1435 alloc_reg64(current,i,rs1[i]);
1436 alloc_reg64(current,i,rs2[i]);
1437 alloc_reg(current,i,rt1[i]);
1438 } else {
1439 alloc_reg(current,i,rs1[i]);
1440 alloc_reg(current,i,rs2[i]);
1441 alloc_reg(current,i,rt1[i]);
1442 }
1443 }
1444 current->is32|=1LL<<rt1[i];
1445 }
1446 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1447 if(rt1[i]) {
1448 if(rs1[i]&&rs2[i]) {
1449 alloc_reg(current,i,rs1[i]);
1450 alloc_reg(current,i,rs2[i]);
1451 }
1452 else
1453 {
1454 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1455 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1456 }
1457 alloc_reg(current,i,rt1[i]);
1458 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1459 {
1460 if(!((current->uu>>rt1[i])&1)) {
1461 alloc_reg64(current,i,rt1[i]);
1462 }
1463 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1464 if(rs1[i]&&rs2[i]) {
1465 alloc_reg64(current,i,rs1[i]);
1466 alloc_reg64(current,i,rs2[i]);
1467 }
1468 else
1469 {
1470 // Is is really worth it to keep 64-bit values in registers?
1471 #ifdef NATIVE_64BIT
1472 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1473 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1474 #endif
1475 }
1476 }
1477 current->is32&=~(1LL<<rt1[i]);
1478 } else {
1479 current->is32|=1LL<<rt1[i];
1480 }
1481 }
1482 }
1483 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1484 if(rt1[i]) {
1485 if(rs1[i]&&rs2[i]) {
1486 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1487 alloc_reg64(current,i,rs1[i]);
1488 alloc_reg64(current,i,rs2[i]);
1489 alloc_reg64(current,i,rt1[i]);
1490 } else {
1491 alloc_reg(current,i,rs1[i]);
1492 alloc_reg(current,i,rs2[i]);
1493 alloc_reg(current,i,rt1[i]);
1494 }
1495 }
1496 else {
1497 alloc_reg(current,i,rt1[i]);
1498 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1499 // DADD used as move, or zeroing
1500 // If we have a 64-bit source, then make the target 64 bits too
1501 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1502 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1503 alloc_reg64(current,i,rt1[i]);
1504 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1505 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1506 alloc_reg64(current,i,rt1[i]);
1507 }
1508 if(opcode2[i]>=0x2e&&rs2[i]) {
1509 // DSUB used as negation - 64-bit result
1510 // If we have a 32-bit register, extend it to 64 bits
1511 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1512 alloc_reg64(current,i,rt1[i]);
1513 }
1514 }
1515 }
1516 if(rs1[i]&&rs2[i]) {
1517 current->is32&=~(1LL<<rt1[i]);
1518 } else if(rs1[i]) {
1519 current->is32&=~(1LL<<rt1[i]);
1520 if((current->is32>>rs1[i])&1)
1521 current->is32|=1LL<<rt1[i];
1522 } else if(rs2[i]) {
1523 current->is32&=~(1LL<<rt1[i]);
1524 if((current->is32>>rs2[i])&1)
1525 current->is32|=1LL<<rt1[i];
1526 } else {
1527 current->is32|=1LL<<rt1[i];
1528 }
1529 }
1530 }
1531 clear_const(current,rs1[i]);
1532 clear_const(current,rs2[i]);
1533 clear_const(current,rt1[i]);
1534 dirty_reg(current,rt1[i]);
1535}
1536
1537void imm16_alloc(struct regstat *current,int i)
1538{
1539 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1540 else lt1[i]=rs1[i];
1541 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1542 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1543 current->is32&=~(1LL<<rt1[i]);
1544 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1545 // TODO: Could preserve the 32-bit flag if the immediate is zero
1546 alloc_reg64(current,i,rt1[i]);
1547 alloc_reg64(current,i,rs1[i]);
1548 }
1549 clear_const(current,rs1[i]);
1550 clear_const(current,rt1[i]);
1551 }
1552 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1553 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1554 current->is32|=1LL<<rt1[i];
1555 clear_const(current,rs1[i]);
1556 clear_const(current,rt1[i]);
1557 }
1558 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1559 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1560 if(rs1[i]!=rt1[i]) {
1561 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1562 alloc_reg64(current,i,rt1[i]);
1563 current->is32&=~(1LL<<rt1[i]);
1564 }
1565 }
1566 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1567 if(is_const(current,rs1[i])) {
1568 int v=get_const(current,rs1[i]);
1569 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1570 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1571 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1572 }
1573 else clear_const(current,rt1[i]);
1574 }
1575 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1576 if(is_const(current,rs1[i])) {
1577 int v=get_const(current,rs1[i]);
1578 set_const(current,rt1[i],v+imm[i]);
1579 }
1580 else clear_const(current,rt1[i]);
1581 current->is32|=1LL<<rt1[i];
1582 }
1583 else {
1584 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1585 current->is32|=1LL<<rt1[i];
1586 }
1587 dirty_reg(current,rt1[i]);
1588}
1589
1590void load_alloc(struct regstat *current,int i)
1591{
1592 clear_const(current,rt1[i]);
1593 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1594 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1595 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
373d1d07 1596 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
57871462 1597 alloc_reg(current,i,rt1[i]);
373d1d07 1598 assert(get_reg(current->regmap,rt1[i])>=0);
57871462 1599 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1600 {
1601 current->is32&=~(1LL<<rt1[i]);
1602 alloc_reg64(current,i,rt1[i]);
1603 }
1604 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1605 {
1606 current->is32&=~(1LL<<rt1[i]);
1607 alloc_reg64(current,i,rt1[i]);
1608 alloc_all(current,i);
1609 alloc_reg64(current,i,FTEMP);
e1190b87 1610 minimum_free_regs[i]=HOST_REGS;
57871462 1611 }
1612 else current->is32|=1LL<<rt1[i];
1613 dirty_reg(current,rt1[i]);
1614 // If using TLB, need a register for pointer to the mapping table
1615 if(using_tlb) alloc_reg(current,i,TLREG);
1616 // LWL/LWR need a temporary register for the old value
1617 if(opcode[i]==0x22||opcode[i]==0x26)
1618 {
1619 alloc_reg(current,i,FTEMP);
1620 alloc_reg_temp(current,i,-1);
e1190b87 1621 minimum_free_regs[i]=1;
57871462 1622 }
1623 }
1624 else
1625 {
373d1d07 1626 // Load to r0 or unneeded register (dummy load)
57871462 1627 // but we still need a register to calculate the address
535d208a 1628 if(opcode[i]==0x22||opcode[i]==0x26)
1629 {
1630 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1631 }
373d1d07 1632 // If using TLB, need a register for pointer to the mapping table
1633 if(using_tlb) alloc_reg(current,i,TLREG);
57871462 1634 alloc_reg_temp(current,i,-1);
e1190b87 1635 minimum_free_regs[i]=1;
535d208a 1636 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1637 {
1638 alloc_all(current,i);
1639 alloc_reg64(current,i,FTEMP);
e1190b87 1640 minimum_free_regs[i]=HOST_REGS;
535d208a 1641 }
57871462 1642 }
1643}
1644
1645void store_alloc(struct regstat *current,int i)
1646{
1647 clear_const(current,rs2[i]);
1648 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1649 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1650 alloc_reg(current,i,rs2[i]);
1651 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1652 alloc_reg64(current,i,rs2[i]);
1653 if(rs2[i]) alloc_reg(current,i,FTEMP);
1654 }
1655 // If using TLB, need a register for pointer to the mapping table
1656 if(using_tlb) alloc_reg(current,i,TLREG);
1657 #if defined(HOST_IMM8)
1658 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1659 else alloc_reg(current,i,INVCP);
1660 #endif
b7918751 1661 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1662 alloc_reg(current,i,FTEMP);
1663 }
1664 // We need a temporary register for address generation
1665 alloc_reg_temp(current,i,-1);
e1190b87 1666 minimum_free_regs[i]=1;
57871462 1667}
1668
1669void c1ls_alloc(struct regstat *current,int i)
1670{
1671 //clear_const(current,rs1[i]); // FIXME
1672 clear_const(current,rt1[i]);
1673 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1674 alloc_reg(current,i,CSREG); // Status
1675 alloc_reg(current,i,FTEMP);
1676 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1677 alloc_reg64(current,i,FTEMP);
1678 }
1679 // If using TLB, need a register for pointer to the mapping table
1680 if(using_tlb) alloc_reg(current,i,TLREG);
1681 #if defined(HOST_IMM8)
1682 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1683 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1684 alloc_reg(current,i,INVCP);
1685 #endif
1686 // We need a temporary register for address generation
1687 alloc_reg_temp(current,i,-1);
1688}
1689
b9b61529 1690void c2ls_alloc(struct regstat *current,int i)
1691{
1692 clear_const(current,rt1[i]);
1693 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1694 alloc_reg(current,i,FTEMP);
1695 // If using TLB, need a register for pointer to the mapping table
1696 if(using_tlb) alloc_reg(current,i,TLREG);
1697 #if defined(HOST_IMM8)
1698 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1699 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1700 alloc_reg(current,i,INVCP);
1701 #endif
1702 // We need a temporary register for address generation
1703 alloc_reg_temp(current,i,-1);
e1190b87 1704 minimum_free_regs[i]=1;
b9b61529 1705}
1706
57871462 1707#ifndef multdiv_alloc
1708void multdiv_alloc(struct regstat *current,int i)
1709{
1710 // case 0x18: MULT
1711 // case 0x19: MULTU
1712 // case 0x1A: DIV
1713 // case 0x1B: DIVU
1714 // case 0x1C: DMULT
1715 // case 0x1D: DMULTU
1716 // case 0x1E: DDIV
1717 // case 0x1F: DDIVU
1718 clear_const(current,rs1[i]);
1719 clear_const(current,rs2[i]);
1720 if(rs1[i]&&rs2[i])
1721 {
1722 if((opcode2[i]&4)==0) // 32-bit
1723 {
1724 current->u&=~(1LL<<HIREG);
1725 current->u&=~(1LL<<LOREG);
1726 alloc_reg(current,i,HIREG);
1727 alloc_reg(current,i,LOREG);
1728 alloc_reg(current,i,rs1[i]);
1729 alloc_reg(current,i,rs2[i]);
1730 current->is32|=1LL<<HIREG;
1731 current->is32|=1LL<<LOREG;
1732 dirty_reg(current,HIREG);
1733 dirty_reg(current,LOREG);
1734 }
1735 else // 64-bit
1736 {
1737 current->u&=~(1LL<<HIREG);
1738 current->u&=~(1LL<<LOREG);
1739 current->uu&=~(1LL<<HIREG);
1740 current->uu&=~(1LL<<LOREG);
1741 alloc_reg64(current,i,HIREG);
1742 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1743 alloc_reg64(current,i,rs1[i]);
1744 alloc_reg64(current,i,rs2[i]);
1745 alloc_all(current,i);
1746 current->is32&=~(1LL<<HIREG);
1747 current->is32&=~(1LL<<LOREG);
1748 dirty_reg(current,HIREG);
1749 dirty_reg(current,LOREG);
e1190b87 1750 minimum_free_regs[i]=HOST_REGS;
57871462 1751 }
1752 }
1753 else
1754 {
1755 // Multiply by zero is zero.
1756 // MIPS does not have a divide by zero exception.
1757 // The result is undefined, we return zero.
1758 alloc_reg(current,i,HIREG);
1759 alloc_reg(current,i,LOREG);
1760 current->is32|=1LL<<HIREG;
1761 current->is32|=1LL<<LOREG;
1762 dirty_reg(current,HIREG);
1763 dirty_reg(current,LOREG);
1764 }
1765}
1766#endif
1767
1768void cop0_alloc(struct regstat *current,int i)
1769{
1770 if(opcode2[i]==0) // MFC0
1771 {
1772 if(rt1[i]) {
1773 clear_const(current,rt1[i]);
1774 alloc_all(current,i);
1775 alloc_reg(current,i,rt1[i]);
1776 current->is32|=1LL<<rt1[i];
1777 dirty_reg(current,rt1[i]);
1778 }
1779 }
1780 else if(opcode2[i]==4) // MTC0
1781 {
1782 if(rs1[i]){
1783 clear_const(current,rs1[i]);
1784 alloc_reg(current,i,rs1[i]);
1785 alloc_all(current,i);
1786 }
1787 else {
1788 alloc_all(current,i); // FIXME: Keep r0
1789 current->u&=~1LL;
1790 alloc_reg(current,i,0);
1791 }
1792 }
1793 else
1794 {
1795 // TLBR/TLBWI/TLBWR/TLBP/ERET
1796 assert(opcode2[i]==0x10);
1797 alloc_all(current,i);
1798 }
e1190b87 1799 minimum_free_regs[i]=HOST_REGS;
57871462 1800}
1801
1802void cop1_alloc(struct regstat *current,int i)
1803{
1804 alloc_reg(current,i,CSREG); // Load status
1805 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1806 {
7de557a6 1807 if(rt1[i]){
1808 clear_const(current,rt1[i]);
1809 if(opcode2[i]==1) {
1810 alloc_reg64(current,i,rt1[i]); // DMFC1
1811 current->is32&=~(1LL<<rt1[i]);
1812 }else{
1813 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1814 current->is32|=1LL<<rt1[i];
1815 }
1816 dirty_reg(current,rt1[i]);
57871462 1817 }
57871462 1818 alloc_reg_temp(current,i,-1);
1819 }
1820 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1821 {
1822 if(rs1[i]){
1823 clear_const(current,rs1[i]);
1824 if(opcode2[i]==5)
1825 alloc_reg64(current,i,rs1[i]); // DMTC1
1826 else
1827 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1828 alloc_reg_temp(current,i,-1);
1829 }
1830 else {
1831 current->u&=~1LL;
1832 alloc_reg(current,i,0);
1833 alloc_reg_temp(current,i,-1);
1834 }
1835 }
e1190b87 1836 minimum_free_regs[i]=1;
57871462 1837}
1838void fconv_alloc(struct regstat *current,int i)
1839{
1840 alloc_reg(current,i,CSREG); // Load status
1841 alloc_reg_temp(current,i,-1);
e1190b87 1842 minimum_free_regs[i]=1;
57871462 1843}
1844void float_alloc(struct regstat *current,int i)
1845{
1846 alloc_reg(current,i,CSREG); // Load status
1847 alloc_reg_temp(current,i,-1);
e1190b87 1848 minimum_free_regs[i]=1;
57871462 1849}
b9b61529 1850void c2op_alloc(struct regstat *current,int i)
1851{
1852 alloc_reg_temp(current,i,-1);
1853}
57871462 1854void fcomp_alloc(struct regstat *current,int i)
1855{
1856 alloc_reg(current,i,CSREG); // Load status
1857 alloc_reg(current,i,FSREG); // Load flags
1858 dirty_reg(current,FSREG); // Flag will be modified
1859 alloc_reg_temp(current,i,-1);
e1190b87 1860 minimum_free_regs[i]=1;
57871462 1861}
1862
1863void syscall_alloc(struct regstat *current,int i)
1864{
1865 alloc_cc(current,i);
1866 dirty_reg(current,CCREG);
1867 alloc_all(current,i);
e1190b87 1868 minimum_free_regs[i]=HOST_REGS;
57871462 1869 current->isconst=0;
1870}
1871
1872void delayslot_alloc(struct regstat *current,int i)
1873{
1874 switch(itype[i]) {
1875 case UJUMP:
1876 case CJUMP:
1877 case SJUMP:
1878 case RJUMP:
1879 case FJUMP:
1880 case SYSCALL:
7139f3c8 1881 case HLECALL:
57871462 1882 case SPAN:
1883 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1884 printf("Disabled speculative precompilation\n");
1885 stop_after_jal=1;
1886 break;
1887 case IMM16:
1888 imm16_alloc(current,i);
1889 break;
1890 case LOAD:
1891 case LOADLR:
1892 load_alloc(current,i);
1893 break;
1894 case STORE:
1895 case STORELR:
1896 store_alloc(current,i);
1897 break;
1898 case ALU:
1899 alu_alloc(current,i);
1900 break;
1901 case SHIFT:
1902 shift_alloc(current,i);
1903 break;
1904 case MULTDIV:
1905 multdiv_alloc(current,i);
1906 break;
1907 case SHIFTIMM:
1908 shiftimm_alloc(current,i);
1909 break;
1910 case MOV:
1911 mov_alloc(current,i);
1912 break;
1913 case COP0:
1914 cop0_alloc(current,i);
1915 break;
1916 case COP1:
b9b61529 1917 case COP2:
57871462 1918 cop1_alloc(current,i);
1919 break;
1920 case C1LS:
1921 c1ls_alloc(current,i);
1922 break;
b9b61529 1923 case C2LS:
1924 c2ls_alloc(current,i);
1925 break;
57871462 1926 case FCONV:
1927 fconv_alloc(current,i);
1928 break;
1929 case FLOAT:
1930 float_alloc(current,i);
1931 break;
1932 case FCOMP:
1933 fcomp_alloc(current,i);
1934 break;
b9b61529 1935 case C2OP:
1936 c2op_alloc(current,i);
1937 break;
57871462 1938 }
1939}
1940
1941// Special case where a branch and delay slot span two pages in virtual memory
1942static void pagespan_alloc(struct regstat *current,int i)
1943{
1944 current->isconst=0;
1945 current->wasconst=0;
1946 regs[i].wasconst=0;
e1190b87 1947 minimum_free_regs[i]=HOST_REGS;
57871462 1948 alloc_all(current,i);
1949 alloc_cc(current,i);
1950 dirty_reg(current,CCREG);
1951 if(opcode[i]==3) // JAL
1952 {
1953 alloc_reg(current,i,31);
1954 dirty_reg(current,31);
1955 }
1956 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1957 {
1958 alloc_reg(current,i,rs1[i]);
5067f341 1959 if (rt1[i]!=0) {
1960 alloc_reg(current,i,rt1[i]);
1961 dirty_reg(current,rt1[i]);
57871462 1962 }
1963 }
1964 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1965 {
1966 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1967 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1968 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1969 {
1970 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1971 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1972 }
1973 }
1974 else
1975 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1976 {
1977 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1978 if(!((current->is32>>rs1[i])&1))
1979 {
1980 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1981 }
1982 }
1983 else
1984 if(opcode[i]==0x11) // BC1
1985 {
1986 alloc_reg(current,i,FSREG);
1987 alloc_reg(current,i,CSREG);
1988 }
1989 //else ...
1990}
1991
1992add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1993{
1994 stubs[stubcount][0]=type;
1995 stubs[stubcount][1]=addr;
1996 stubs[stubcount][2]=retaddr;
1997 stubs[stubcount][3]=a;
1998 stubs[stubcount][4]=b;
1999 stubs[stubcount][5]=c;
2000 stubs[stubcount][6]=d;
2001 stubs[stubcount][7]=e;
2002 stubcount++;
2003}
2004
2005// Write out a single register
2006void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2007{
2008 int hr;
2009 for(hr=0;hr<HOST_REGS;hr++) {
2010 if(hr!=EXCLUDE_REG) {
2011 if((regmap[hr]&63)==r) {
2012 if((dirty>>hr)&1) {
2013 if(regmap[hr]<64) {
2014 emit_storereg(r,hr);
24385cae 2015#ifndef FORCE32
57871462 2016 if((is32>>regmap[hr])&1) {
2017 emit_sarimm(hr,31,hr);
2018 emit_storereg(r|64,hr);
2019 }
24385cae 2020#endif
57871462 2021 }else{
2022 emit_storereg(r|64,hr);
2023 }
2024 }
2025 }
2026 }
2027 }
2028}
2029
2030int mchecksum()
2031{
2032 //if(!tracedebug) return 0;
2033 int i;
2034 int sum=0;
2035 for(i=0;i<2097152;i++) {
2036 unsigned int temp=sum;
2037 sum<<=1;
2038 sum|=(~temp)>>31;
2039 sum^=((u_int *)rdram)[i];
2040 }
2041 return sum;
2042}
2043int rchecksum()
2044{
2045 int i;
2046 int sum=0;
2047 for(i=0;i<64;i++)
2048 sum^=((u_int *)reg)[i];
2049 return sum;
2050}
57871462 2051void rlist()
2052{
2053 int i;
2054 printf("TRACE: ");
2055 for(i=0;i<32;i++)
2056 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2057 printf("\n");
3d624f89 2058#ifndef DISABLE_COP1
57871462 2059 printf("TRACE: ");
2060 for(i=0;i<32;i++)
2061 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2062 printf("\n");
3d624f89 2063#endif
57871462 2064}
2065
2066void enabletrace()
2067{
2068 tracedebug=1;
2069}
2070
2071void memdebug(int i)
2072{
2073 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2074 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2075 //rlist();
2076 //if(tracedebug) {
2077 //if(Count>=-2084597794) {
2078 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2079 //if(0) {
2080 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2081 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2082 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2083 rlist();
2084 #ifdef __i386__
2085 printf("TRACE: %x\n",(&i)[-1]);
2086 #endif
2087 #ifdef __arm__
2088 int j;
2089 printf("TRACE: %x \n",(&j)[10]);
2090 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2091 #endif
2092 //fflush(stdout);
2093 }
2094 //printf("TRACE: %x\n",(&i)[-1]);
2095}
2096
2097void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2098{
2099 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2100}
2101
2102void alu_assemble(int i,struct regstat *i_regs)
2103{
2104 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2105 if(rt1[i]) {
2106 signed char s1,s2,t;
2107 t=get_reg(i_regs->regmap,rt1[i]);
2108 if(t>=0) {
2109 s1=get_reg(i_regs->regmap,rs1[i]);
2110 s2=get_reg(i_regs->regmap,rs2[i]);
2111 if(rs1[i]&&rs2[i]) {
2112 assert(s1>=0);
2113 assert(s2>=0);
2114 if(opcode2[i]&2) emit_sub(s1,s2,t);
2115 else emit_add(s1,s2,t);
2116 }
2117 else if(rs1[i]) {
2118 if(s1>=0) emit_mov(s1,t);
2119 else emit_loadreg(rs1[i],t);
2120 }
2121 else if(rs2[i]) {
2122 if(s2>=0) {
2123 if(opcode2[i]&2) emit_neg(s2,t);
2124 else emit_mov(s2,t);
2125 }
2126 else {
2127 emit_loadreg(rs2[i],t);
2128 if(opcode2[i]&2) emit_neg(t,t);
2129 }
2130 }
2131 else emit_zeroreg(t);
2132 }
2133 }
2134 }
2135 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2136 if(rt1[i]) {
2137 signed char s1l,s2l,s1h,s2h,tl,th;
2138 tl=get_reg(i_regs->regmap,rt1[i]);
2139 th=get_reg(i_regs->regmap,rt1[i]|64);
2140 if(tl>=0) {
2141 s1l=get_reg(i_regs->regmap,rs1[i]);
2142 s2l=get_reg(i_regs->regmap,rs2[i]);
2143 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2144 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2145 if(rs1[i]&&rs2[i]) {
2146 assert(s1l>=0);
2147 assert(s2l>=0);
2148 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2149 else emit_adds(s1l,s2l,tl);
2150 if(th>=0) {
2151 #ifdef INVERTED_CARRY
2152 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2153 #else
2154 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2155 #endif
2156 else emit_add(s1h,s2h,th);
2157 }
2158 }
2159 else if(rs1[i]) {
2160 if(s1l>=0) emit_mov(s1l,tl);
2161 else emit_loadreg(rs1[i],tl);
2162 if(th>=0) {
2163 if(s1h>=0) emit_mov(s1h,th);
2164 else emit_loadreg(rs1[i]|64,th);
2165 }
2166 }
2167 else if(rs2[i]) {
2168 if(s2l>=0) {
2169 if(opcode2[i]&2) emit_negs(s2l,tl);
2170 else emit_mov(s2l,tl);
2171 }
2172 else {
2173 emit_loadreg(rs2[i],tl);
2174 if(opcode2[i]&2) emit_negs(tl,tl);
2175 }
2176 if(th>=0) {
2177 #ifdef INVERTED_CARRY
2178 if(s2h>=0) emit_mov(s2h,th);
2179 else emit_loadreg(rs2[i]|64,th);
2180 if(opcode2[i]&2) {
2181 emit_adcimm(-1,th); // x86 has inverted carry flag
2182 emit_not(th,th);
2183 }
2184 #else
2185 if(opcode2[i]&2) {
2186 if(s2h>=0) emit_rscimm(s2h,0,th);
2187 else {
2188 emit_loadreg(rs2[i]|64,th);
2189 emit_rscimm(th,0,th);
2190 }
2191 }else{
2192 if(s2h>=0) emit_mov(s2h,th);
2193 else emit_loadreg(rs2[i]|64,th);
2194 }
2195 #endif
2196 }
2197 }
2198 else {
2199 emit_zeroreg(tl);
2200 if(th>=0) emit_zeroreg(th);
2201 }
2202 }
2203 }
2204 }
2205 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2206 if(rt1[i]) {
2207 signed char s1l,s1h,s2l,s2h,t;
2208 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2209 {
2210 t=get_reg(i_regs->regmap,rt1[i]);
2211 //assert(t>=0);
2212 if(t>=0) {
2213 s1l=get_reg(i_regs->regmap,rs1[i]);
2214 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2215 s2l=get_reg(i_regs->regmap,rs2[i]);
2216 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2217 if(rs2[i]==0) // rx<r0
2218 {
2219 assert(s1h>=0);
2220 if(opcode2[i]==0x2a) // SLT
2221 emit_shrimm(s1h,31,t);
2222 else // SLTU (unsigned can not be less than zero)
2223 emit_zeroreg(t);
2224 }
2225 else if(rs1[i]==0) // r0<rx
2226 {
2227 assert(s2h>=0);
2228 if(opcode2[i]==0x2a) // SLT
2229 emit_set_gz64_32(s2h,s2l,t);
2230 else // SLTU (set if not zero)
2231 emit_set_nz64_32(s2h,s2l,t);
2232 }
2233 else {
2234 assert(s1l>=0);assert(s1h>=0);
2235 assert(s2l>=0);assert(s2h>=0);
2236 if(opcode2[i]==0x2a) // SLT
2237 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2238 else // SLTU
2239 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2240 }
2241 }
2242 } else {
2243 t=get_reg(i_regs->regmap,rt1[i]);
2244 //assert(t>=0);
2245 if(t>=0) {
2246 s1l=get_reg(i_regs->regmap,rs1[i]);
2247 s2l=get_reg(i_regs->regmap,rs2[i]);
2248 if(rs2[i]==0) // rx<r0
2249 {
2250 assert(s1l>=0);
2251 if(opcode2[i]==0x2a) // SLT
2252 emit_shrimm(s1l,31,t);
2253 else // SLTU (unsigned can not be less than zero)
2254 emit_zeroreg(t);
2255 }
2256 else if(rs1[i]==0) // r0<rx
2257 {
2258 assert(s2l>=0);
2259 if(opcode2[i]==0x2a) // SLT
2260 emit_set_gz32(s2l,t);
2261 else // SLTU (set if not zero)
2262 emit_set_nz32(s2l,t);
2263 }
2264 else{
2265 assert(s1l>=0);assert(s2l>=0);
2266 if(opcode2[i]==0x2a) // SLT
2267 emit_set_if_less32(s1l,s2l,t);
2268 else // SLTU
2269 emit_set_if_carry32(s1l,s2l,t);
2270 }
2271 }
2272 }
2273 }
2274 }
2275 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2276 if(rt1[i]) {
2277 signed char s1l,s1h,s2l,s2h,th,tl;
2278 tl=get_reg(i_regs->regmap,rt1[i]);
2279 th=get_reg(i_regs->regmap,rt1[i]|64);
2280 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2281 {
2282 assert(tl>=0);
2283 if(tl>=0) {
2284 s1l=get_reg(i_regs->regmap,rs1[i]);
2285 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2286 s2l=get_reg(i_regs->regmap,rs2[i]);
2287 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2288 if(rs1[i]&&rs2[i]) {
2289 assert(s1l>=0);assert(s1h>=0);
2290 assert(s2l>=0);assert(s2h>=0);
2291 if(opcode2[i]==0x24) { // AND
2292 emit_and(s1l,s2l,tl);
2293 emit_and(s1h,s2h,th);
2294 } else
2295 if(opcode2[i]==0x25) { // OR
2296 emit_or(s1l,s2l,tl);
2297 emit_or(s1h,s2h,th);
2298 } else
2299 if(opcode2[i]==0x26) { // XOR
2300 emit_xor(s1l,s2l,tl);
2301 emit_xor(s1h,s2h,th);
2302 } else
2303 if(opcode2[i]==0x27) { // NOR
2304 emit_or(s1l,s2l,tl);
2305 emit_or(s1h,s2h,th);
2306 emit_not(tl,tl);
2307 emit_not(th,th);
2308 }
2309 }
2310 else
2311 {
2312 if(opcode2[i]==0x24) { // AND
2313 emit_zeroreg(tl);
2314 emit_zeroreg(th);
2315 } else
2316 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2317 if(rs1[i]){
2318 if(s1l>=0) emit_mov(s1l,tl);
2319 else emit_loadreg(rs1[i],tl);
2320 if(s1h>=0) emit_mov(s1h,th);
2321 else emit_loadreg(rs1[i]|64,th);
2322 }
2323 else
2324 if(rs2[i]){
2325 if(s2l>=0) emit_mov(s2l,tl);
2326 else emit_loadreg(rs2[i],tl);
2327 if(s2h>=0) emit_mov(s2h,th);
2328 else emit_loadreg(rs2[i]|64,th);
2329 }
2330 else{
2331 emit_zeroreg(tl);
2332 emit_zeroreg(th);
2333 }
2334 } else
2335 if(opcode2[i]==0x27) { // NOR
2336 if(rs1[i]){
2337 if(s1l>=0) emit_not(s1l,tl);
2338 else{
2339 emit_loadreg(rs1[i],tl);
2340 emit_not(tl,tl);
2341 }
2342 if(s1h>=0) emit_not(s1h,th);
2343 else{
2344 emit_loadreg(rs1[i]|64,th);
2345 emit_not(th,th);
2346 }
2347 }
2348 else
2349 if(rs2[i]){
2350 if(s2l>=0) emit_not(s2l,tl);
2351 else{
2352 emit_loadreg(rs2[i],tl);
2353 emit_not(tl,tl);
2354 }
2355 if(s2h>=0) emit_not(s2h,th);
2356 else{
2357 emit_loadreg(rs2[i]|64,th);
2358 emit_not(th,th);
2359 }
2360 }
2361 else {
2362 emit_movimm(-1,tl);
2363 emit_movimm(-1,th);
2364 }
2365 }
2366 }
2367 }
2368 }
2369 else
2370 {
2371 // 32 bit
2372 if(tl>=0) {
2373 s1l=get_reg(i_regs->regmap,rs1[i]);
2374 s2l=get_reg(i_regs->regmap,rs2[i]);
2375 if(rs1[i]&&rs2[i]) {
2376 assert(s1l>=0);
2377 assert(s2l>=0);
2378 if(opcode2[i]==0x24) { // AND
2379 emit_and(s1l,s2l,tl);
2380 } else
2381 if(opcode2[i]==0x25) { // OR
2382 emit_or(s1l,s2l,tl);
2383 } else
2384 if(opcode2[i]==0x26) { // XOR
2385 emit_xor(s1l,s2l,tl);
2386 } else
2387 if(opcode2[i]==0x27) { // NOR
2388 emit_or(s1l,s2l,tl);
2389 emit_not(tl,tl);
2390 }
2391 }
2392 else
2393 {
2394 if(opcode2[i]==0x24) { // AND
2395 emit_zeroreg(tl);
2396 } else
2397 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2398 if(rs1[i]){
2399 if(s1l>=0) emit_mov(s1l,tl);
2400 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2401 }
2402 else
2403 if(rs2[i]){
2404 if(s2l>=0) emit_mov(s2l,tl);
2405 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2406 }
2407 else emit_zeroreg(tl);
2408 } else
2409 if(opcode2[i]==0x27) { // NOR
2410 if(rs1[i]){
2411 if(s1l>=0) emit_not(s1l,tl);
2412 else {
2413 emit_loadreg(rs1[i],tl);
2414 emit_not(tl,tl);
2415 }
2416 }
2417 else
2418 if(rs2[i]){
2419 if(s2l>=0) emit_not(s2l,tl);
2420 else {
2421 emit_loadreg(rs2[i],tl);
2422 emit_not(tl,tl);
2423 }
2424 }
2425 else emit_movimm(-1,tl);
2426 }
2427 }
2428 }
2429 }
2430 }
2431 }
2432}
2433
2434void imm16_assemble(int i,struct regstat *i_regs)
2435{
2436 if (opcode[i]==0x0f) { // LUI
2437 if(rt1[i]) {
2438 signed char t;
2439 t=get_reg(i_regs->regmap,rt1[i]);
2440 //assert(t>=0);
2441 if(t>=0) {
2442 if(!((i_regs->isconst>>t)&1))
2443 emit_movimm(imm[i]<<16,t);
2444 }
2445 }
2446 }
2447 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2448 if(rt1[i]) {
2449 signed char s,t;
2450 t=get_reg(i_regs->regmap,rt1[i]);
2451 s=get_reg(i_regs->regmap,rs1[i]);
2452 if(rs1[i]) {
2453 //assert(t>=0);
2454 //assert(s>=0);
2455 if(t>=0) {
2456 if(!((i_regs->isconst>>t)&1)) {
2457 if(s<0) {
2458 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2459 emit_addimm(t,imm[i],t);
2460 }else{
2461 if(!((i_regs->wasconst>>s)&1))
2462 emit_addimm(s,imm[i],t);
2463 else
2464 emit_movimm(constmap[i][s]+imm[i],t);
2465 }
2466 }
2467 }
2468 } else {
2469 if(t>=0) {
2470 if(!((i_regs->isconst>>t)&1))
2471 emit_movimm(imm[i],t);
2472 }
2473 }
2474 }
2475 }
2476 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2477 if(rt1[i]) {
2478 signed char sh,sl,th,tl;
2479 th=get_reg(i_regs->regmap,rt1[i]|64);
2480 tl=get_reg(i_regs->regmap,rt1[i]);
2481 sh=get_reg(i_regs->regmap,rs1[i]|64);
2482 sl=get_reg(i_regs->regmap,rs1[i]);
2483 if(tl>=0) {
2484 if(rs1[i]) {
2485 assert(sh>=0);
2486 assert(sl>=0);
2487 if(th>=0) {
2488 emit_addimm64_32(sh,sl,imm[i],th,tl);
2489 }
2490 else {
2491 emit_addimm(sl,imm[i],tl);
2492 }
2493 } else {
2494 emit_movimm(imm[i],tl);
2495 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2496 }
2497 }
2498 }
2499 }
2500 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2501 if(rt1[i]) {
2502 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2503 signed char sh,sl,t;
2504 t=get_reg(i_regs->regmap,rt1[i]);
2505 sh=get_reg(i_regs->regmap,rs1[i]|64);
2506 sl=get_reg(i_regs->regmap,rs1[i]);
2507 //assert(t>=0);
2508 if(t>=0) {
2509 if(rs1[i]>0) {
2510 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2511 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2512 if(opcode[i]==0x0a) { // SLTI
2513 if(sl<0) {
2514 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2515 emit_slti32(t,imm[i],t);
2516 }else{
2517 emit_slti32(sl,imm[i],t);
2518 }
2519 }
2520 else { // SLTIU
2521 if(sl<0) {
2522 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2523 emit_sltiu32(t,imm[i],t);
2524 }else{
2525 emit_sltiu32(sl,imm[i],t);
2526 }
2527 }
2528 }else{ // 64-bit
2529 assert(sl>=0);
2530 if(opcode[i]==0x0a) // SLTI
2531 emit_slti64_32(sh,sl,imm[i],t);
2532 else // SLTIU
2533 emit_sltiu64_32(sh,sl,imm[i],t);
2534 }
2535 }else{
2536 // SLTI(U) with r0 is just stupid,
2537 // nonetheless examples can be found
2538 if(opcode[i]==0x0a) // SLTI
2539 if(0<imm[i]) emit_movimm(1,t);
2540 else emit_zeroreg(t);
2541 else // SLTIU
2542 {
2543 if(imm[i]) emit_movimm(1,t);
2544 else emit_zeroreg(t);
2545 }
2546 }
2547 }
2548 }
2549 }
2550 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2551 if(rt1[i]) {
2552 signed char sh,sl,th,tl;
2553 th=get_reg(i_regs->regmap,rt1[i]|64);
2554 tl=get_reg(i_regs->regmap,rt1[i]);
2555 sh=get_reg(i_regs->regmap,rs1[i]|64);
2556 sl=get_reg(i_regs->regmap,rs1[i]);
2557 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2558 if(opcode[i]==0x0c) //ANDI
2559 {
2560 if(rs1[i]) {
2561 if(sl<0) {
2562 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2563 emit_andimm(tl,imm[i],tl);
2564 }else{
2565 if(!((i_regs->wasconst>>sl)&1))
2566 emit_andimm(sl,imm[i],tl);
2567 else
2568 emit_movimm(constmap[i][sl]&imm[i],tl);
2569 }
2570 }
2571 else
2572 emit_zeroreg(tl);
2573 if(th>=0) emit_zeroreg(th);
2574 }
2575 else
2576 {
2577 if(rs1[i]) {
2578 if(sl<0) {
2579 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2580 }
2581 if(th>=0) {
2582 if(sh<0) {
2583 emit_loadreg(rs1[i]|64,th);
2584 }else{
2585 emit_mov(sh,th);
2586 }
2587 }
2588 if(opcode[i]==0x0d) //ORI
2589 if(sl<0) {
2590 emit_orimm(tl,imm[i],tl);
2591 }else{
2592 if(!((i_regs->wasconst>>sl)&1))
2593 emit_orimm(sl,imm[i],tl);
2594 else
2595 emit_movimm(constmap[i][sl]|imm[i],tl);
2596 }
2597 if(opcode[i]==0x0e) //XORI
2598 if(sl<0) {
2599 emit_xorimm(tl,imm[i],tl);
2600 }else{
2601 if(!((i_regs->wasconst>>sl)&1))
2602 emit_xorimm(sl,imm[i],tl);
2603 else
2604 emit_movimm(constmap[i][sl]^imm[i],tl);
2605 }
2606 }
2607 else {
2608 emit_movimm(imm[i],tl);
2609 if(th>=0) emit_zeroreg(th);
2610 }
2611 }
2612 }
2613 }
2614 }
2615}
2616
2617void shiftimm_assemble(int i,struct regstat *i_regs)
2618{
2619 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2620 {
2621 if(rt1[i]) {
2622 signed char s,t;
2623 t=get_reg(i_regs->regmap,rt1[i]);
2624 s=get_reg(i_regs->regmap,rs1[i]);
2625 //assert(t>=0);
2626 if(t>=0){
2627 if(rs1[i]==0)
2628 {
2629 emit_zeroreg(t);
2630 }
2631 else
2632 {
2633 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2634 if(imm[i]) {
2635 if(opcode2[i]==0) // SLL
2636 {
2637 emit_shlimm(s<0?t:s,imm[i],t);
2638 }
2639 if(opcode2[i]==2) // SRL
2640 {
2641 emit_shrimm(s<0?t:s,imm[i],t);
2642 }
2643 if(opcode2[i]==3) // SRA
2644 {
2645 emit_sarimm(s<0?t:s,imm[i],t);
2646 }
2647 }else{
2648 // Shift by zero
2649 if(s>=0 && s!=t) emit_mov(s,t);
2650 }
2651 }
2652 }
2653 //emit_storereg(rt1[i],t); //DEBUG
2654 }
2655 }
2656 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2657 {
2658 if(rt1[i]) {
2659 signed char sh,sl,th,tl;
2660 th=get_reg(i_regs->regmap,rt1[i]|64);
2661 tl=get_reg(i_regs->regmap,rt1[i]);
2662 sh=get_reg(i_regs->regmap,rs1[i]|64);
2663 sl=get_reg(i_regs->regmap,rs1[i]);
2664 if(tl>=0) {
2665 if(rs1[i]==0)
2666 {
2667 emit_zeroreg(tl);
2668 if(th>=0) emit_zeroreg(th);
2669 }
2670 else
2671 {
2672 assert(sl>=0);
2673 assert(sh>=0);
2674 if(imm[i]) {
2675 if(opcode2[i]==0x38) // DSLL
2676 {
2677 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2678 emit_shlimm(sl,imm[i],tl);
2679 }
2680 if(opcode2[i]==0x3a) // DSRL
2681 {
2682 emit_shrdimm(sl,sh,imm[i],tl);
2683 if(th>=0) emit_shrimm(sh,imm[i],th);
2684 }
2685 if(opcode2[i]==0x3b) // DSRA
2686 {
2687 emit_shrdimm(sl,sh,imm[i],tl);
2688 if(th>=0) emit_sarimm(sh,imm[i],th);
2689 }
2690 }else{
2691 // Shift by zero
2692 if(sl!=tl) emit_mov(sl,tl);
2693 if(th>=0&&sh!=th) emit_mov(sh,th);
2694 }
2695 }
2696 }
2697 }
2698 }
2699 if(opcode2[i]==0x3c) // DSLL32
2700 {
2701 if(rt1[i]) {
2702 signed char sl,tl,th;
2703 tl=get_reg(i_regs->regmap,rt1[i]);
2704 th=get_reg(i_regs->regmap,rt1[i]|64);
2705 sl=get_reg(i_regs->regmap,rs1[i]);
2706 if(th>=0||tl>=0){
2707 assert(tl>=0);
2708 assert(th>=0);
2709 assert(sl>=0);
2710 emit_mov(sl,th);
2711 emit_zeroreg(tl);
2712 if(imm[i]>32)
2713 {
2714 emit_shlimm(th,imm[i]&31,th);
2715 }
2716 }
2717 }
2718 }
2719 if(opcode2[i]==0x3e) // DSRL32
2720 {
2721 if(rt1[i]) {
2722 signed char sh,tl,th;
2723 tl=get_reg(i_regs->regmap,rt1[i]);
2724 th=get_reg(i_regs->regmap,rt1[i]|64);
2725 sh=get_reg(i_regs->regmap,rs1[i]|64);
2726 if(tl>=0){
2727 assert(sh>=0);
2728 emit_mov(sh,tl);
2729 if(th>=0) emit_zeroreg(th);
2730 if(imm[i]>32)
2731 {
2732 emit_shrimm(tl,imm[i]&31,tl);
2733 }
2734 }
2735 }
2736 }
2737 if(opcode2[i]==0x3f) // DSRA32
2738 {
2739 if(rt1[i]) {
2740 signed char sh,tl;
2741 tl=get_reg(i_regs->regmap,rt1[i]);
2742 sh=get_reg(i_regs->regmap,rs1[i]|64);
2743 if(tl>=0){
2744 assert(sh>=0);
2745 emit_mov(sh,tl);
2746 if(imm[i]>32)
2747 {
2748 emit_sarimm(tl,imm[i]&31,tl);
2749 }
2750 }
2751 }
2752 }
2753}
2754
2755#ifndef shift_assemble
2756void shift_assemble(int i,struct regstat *i_regs)
2757{
2758 printf("Need shift_assemble for this architecture.\n");
2759 exit(1);
2760}
2761#endif
2762
2763void load_assemble(int i,struct regstat *i_regs)
2764{
2765 int s,th,tl,addr,map=-1;
2766 int offset;
2767 int jaddr=0;
5bf843dc 2768 int memtarget=0,c=0;
57871462 2769 u_int hr,reglist=0;
2770 th=get_reg(i_regs->regmap,rt1[i]|64);
2771 tl=get_reg(i_regs->regmap,rt1[i]);
2772 s=get_reg(i_regs->regmap,rs1[i]);
2773 offset=imm[i];
2774 for(hr=0;hr<HOST_REGS;hr++) {
2775 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2776 }
2777 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2778 if(s>=0) {
2779 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2780 if (c) {
2781 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2782 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2783 }
57871462 2784 }
57871462 2785 //printf("load_assemble: c=%d\n",c);
2786 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2787 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2788#ifdef PCSX
f18c0f46 2789 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2790 ||rt1[i]==0) {
5bf843dc 2791 // could be FIFO, must perform the read
f18c0f46 2792 // ||dummy read
5bf843dc 2793 assem_debug("(forced read)\n");
2794 tl=get_reg(i_regs->regmap,-1);
2795 assert(tl>=0);
5bf843dc 2796 }
f18c0f46 2797#endif
5bf843dc 2798 if(offset||s<0||c) addr=tl;
2799 else addr=s;
535d208a 2800 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2801 if(tl>=0) {
2802 //printf("load_assemble: c=%d\n",c);
2803 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2804 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2805 reglist&=~(1<<tl);
2806 if(th>=0) reglist&=~(1<<th);
2807 if(!using_tlb) {
2808 if(!c) {
2809 #ifdef RAM_OFFSET
2810 map=get_reg(i_regs->regmap,ROREG);
2811 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2812 #endif
57871462 2813//#define R29_HACK 1
535d208a 2814 #ifdef R29_HACK
2815 // Strmnnrmn's speed hack
2816 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2817 #endif
2818 {
dadf55f2 2819 #ifdef PCSX
2820 if(sp_in_mirror&&rs1[i]==29) {
2821 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2822 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
2823 }
2824 else
2825 #endif
535d208a 2826 emit_cmpimm(addr,RAM_SIZE);
2827 jaddr=(int)out;
2828 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2829 // Hint to branch predictor that the branch is unlikely to be taken
2830 if(rs1[i]>=28)
2831 emit_jno_unlikely(0);
2832 else
57871462 2833 #endif
535d208a 2834 emit_jno(0);
57871462 2835 }
535d208a 2836 }
2837 }else{ // using tlb
2838 int x=0;
2839 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2840 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2841 map=get_reg(i_regs->regmap,TLREG);
2842 assert(map>=0);
2843 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2844 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2845 }
2846 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2847 if (opcode[i]==0x20) { // LB
2848 if(!c||memtarget) {
2849 if(!dummy) {
57871462 2850 #ifdef HOST_IMM_ADDR32
2851 if(c)
2852 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2853 else
2854 #endif
2855 {
2856 //emit_xorimm(addr,3,tl);
2857 //gen_tlb_addr_r(tl,map);
2858 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2859 int x=0,a=tl;
2002a1db 2860#ifdef BIG_ENDIAN_MIPS
57871462 2861 if(!c) emit_xorimm(addr,3,tl);
2862 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2863#else
535d208a 2864 if(!c) a=addr;
dadf55f2 2865#endif
2866#ifdef PCSX
2867 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2002a1db 2868#endif
535d208a 2869 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2870 }
57871462 2871 }
535d208a 2872 if(jaddr)
2873 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2874 }
535d208a 2875 else
2876 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2877 }
2878 if (opcode[i]==0x21) { // LH
2879 if(!c||memtarget) {
2880 if(!dummy) {
57871462 2881 #ifdef HOST_IMM_ADDR32
2882 if(c)
2883 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2884 else
2885 #endif
2886 {
535d208a 2887 int x=0,a=tl;
2002a1db 2888#ifdef BIG_ENDIAN_MIPS
57871462 2889 if(!c) emit_xorimm(addr,2,tl);
2890 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2891#else
535d208a 2892 if(!c) a=addr;
dadf55f2 2893#endif
2894#ifdef PCSX
2895 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2002a1db 2896#endif
57871462 2897 //#ifdef
2898 //emit_movswl_indexed_tlb(x,tl,map,tl);
2899 //else
2900 if(map>=0) {
535d208a 2901 gen_tlb_addr_r(a,map);
2902 emit_movswl_indexed(x,a,tl);
2903 }else{
2904 #ifdef RAM_OFFSET
2905 emit_movswl_indexed(x,a,tl);
2906 #else
2907 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2908 #endif
2909 }
57871462 2910 }
57871462 2911 }
535d208a 2912 if(jaddr)
2913 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2914 }
535d208a 2915 else
2916 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2917 }
2918 if (opcode[i]==0x23) { // LW
2919 if(!c||memtarget) {
2920 if(!dummy) {
dadf55f2 2921 int a=addr;
2922#ifdef PCSX
2923 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2924#endif
57871462 2925 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2926 #ifdef HOST_IMM_ADDR32
2927 if(c)
2928 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2929 else
2930 #endif
dadf55f2 2931 emit_readword_indexed_tlb(0,a,map,tl);
57871462 2932 }
535d208a 2933 if(jaddr)
2934 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2935 }
535d208a 2936 else
2937 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2938 }
2939 if (opcode[i]==0x24) { // LBU
2940 if(!c||memtarget) {
2941 if(!dummy) {
57871462 2942 #ifdef HOST_IMM_ADDR32
2943 if(c)
2944 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2945 else
2946 #endif
2947 {
2948 //emit_xorimm(addr,3,tl);
2949 //gen_tlb_addr_r(tl,map);
2950 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2951 int x=0,a=tl;
2002a1db 2952#ifdef BIG_ENDIAN_MIPS
57871462 2953 if(!c) emit_xorimm(addr,3,tl);
2954 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2955#else
535d208a 2956 if(!c) a=addr;
dadf55f2 2957#endif
2958#ifdef PCSX
2959 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2002a1db 2960#endif
535d208a 2961 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 2962 }
57871462 2963 }
535d208a 2964 if(jaddr)
2965 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2966 }
535d208a 2967 else
2968 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2969 }
2970 if (opcode[i]==0x25) { // LHU
2971 if(!c||memtarget) {
2972 if(!dummy) {
57871462 2973 #ifdef HOST_IMM_ADDR32
2974 if(c)
2975 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2976 else
2977 #endif
2978 {
535d208a 2979 int x=0,a=tl;
2002a1db 2980#ifdef BIG_ENDIAN_MIPS
57871462 2981 if(!c) emit_xorimm(addr,2,tl);
2982 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2983#else
535d208a 2984 if(!c) a=addr;
dadf55f2 2985#endif
2986#ifdef PCSX
2987 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2002a1db 2988#endif
57871462 2989 //#ifdef
2990 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2991 //#else
2992 if(map>=0) {
535d208a 2993 gen_tlb_addr_r(a,map);
2994 emit_movzwl_indexed(x,a,tl);
2995 }else{
2996 #ifdef RAM_OFFSET
2997 emit_movzwl_indexed(x,a,tl);
2998 #else
2999 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3000 #endif
3001 }
57871462 3002 }
3003 }
535d208a 3004 if(jaddr)
3005 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3006 }
535d208a 3007 else
3008 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3009 }
3010 if (opcode[i]==0x27) { // LWU
3011 assert(th>=0);
3012 if(!c||memtarget) {
3013 if(!dummy) {
dadf55f2 3014 int a=addr;
3015#ifdef PCSX
3016 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
3017#endif
57871462 3018 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3019 #ifdef HOST_IMM_ADDR32
3020 if(c)
3021 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3022 else
3023 #endif
dadf55f2 3024 emit_readword_indexed_tlb(0,a,map,tl);
57871462 3025 }
535d208a 3026 if(jaddr)
3027 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3028 }
3029 else {
3030 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3031 }
535d208a 3032 emit_zeroreg(th);
3033 }
3034 if (opcode[i]==0x37) { // LD
3035 if(!c||memtarget) {
3036 if(!dummy) {
dadf55f2 3037 int a=addr;
3038#ifdef PCSX
3039 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
3040#endif
57871462 3041 //gen_tlb_addr_r(tl,map);
3042 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3043 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3044 #ifdef HOST_IMM_ADDR32
3045 if(c)
3046 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3047 else
3048 #endif
dadf55f2 3049 emit_readdword_indexed_tlb(0,a,map,th,tl);
57871462 3050 }
535d208a 3051 if(jaddr)
3052 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3053 }
535d208a 3054 else
3055 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3056 }
535d208a 3057 }
3058 //emit_storereg(rt1[i],tl); // DEBUG
57871462 3059 //if(opcode[i]==0x23)
3060 //if(opcode[i]==0x24)
3061 //if(opcode[i]==0x23||opcode[i]==0x24)
3062 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3063 {
3064 //emit_pusha();
3065 save_regs(0x100f);
3066 emit_readword((int)&last_count,ECX);
3067 #ifdef __i386__
3068 if(get_reg(i_regs->regmap,CCREG)<0)
3069 emit_loadreg(CCREG,HOST_CCREG);
3070 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3071 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3072 emit_writeword(HOST_CCREG,(int)&Count);
3073 #endif
3074 #ifdef __arm__
3075 if(get_reg(i_regs->regmap,CCREG)<0)
3076 emit_loadreg(CCREG,0);
3077 else
3078 emit_mov(HOST_CCREG,0);
3079 emit_add(0,ECX,0);
3080 emit_addimm(0,2*ccadj[i],0);
3081 emit_writeword(0,(int)&Count);
3082 #endif
3083 emit_call((int)memdebug);
3084 //emit_popa();
3085 restore_regs(0x100f);
3086 }/**/
3087}
3088
3089#ifndef loadlr_assemble
3090void loadlr_assemble(int i,struct regstat *i_regs)
3091{
3092 printf("Need loadlr_assemble for this architecture.\n");
3093 exit(1);
3094}
3095#endif
3096
3097void store_assemble(int i,struct regstat *i_regs)
3098{
3099 int s,th,tl,map=-1;
3100 int addr,temp;
3101 int offset;
3102 int jaddr=0,jaddr2,type;
666a299d 3103 int memtarget=0,c=0;
57871462 3104 int agr=AGEN1+(i&1);
3105 u_int hr,reglist=0;
3106 th=get_reg(i_regs->regmap,rs2[i]|64);
3107 tl=get_reg(i_regs->regmap,rs2[i]);
3108 s=get_reg(i_regs->regmap,rs1[i]);
3109 temp=get_reg(i_regs->regmap,agr);
3110 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3111 offset=imm[i];
3112 if(s>=0) {
3113 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3114 if(c) {
3115 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3116 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3117 }
57871462 3118 }
3119 assert(tl>=0);
3120 assert(temp>=0);
3121 for(hr=0;hr<HOST_REGS;hr++) {
3122 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3123 }
3124 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3125 if(offset||s<0||c) addr=temp;
3126 else addr=s;
3127 if(!using_tlb) {
3128 if(!c) {
dadf55f2 3129 #ifdef PCSX
3130 if(sp_in_mirror&&rs1[i]==29) {
3131 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3132 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
3133 }
3134 else
3135 #endif
57871462 3136 #ifdef R29_HACK
3137 // Strmnnrmn's speed hack
4cb76aa4 3138 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3139 #endif
4cb76aa4 3140 emit_cmpimm(addr,RAM_SIZE);
57871462 3141 #ifdef DESTRUCTIVE_SHIFT
3142 if(s==addr) emit_mov(s,temp);
3143 #endif
3144 #ifdef R29_HACK
dadf55f2 3145 memtarget=1;
4cb76aa4 3146 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3147 #endif
3148 {
3149 jaddr=(int)out;
3150 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3151 // Hint to branch predictor that the branch is unlikely to be taken
3152 if(rs1[i]>=28)
3153 emit_jno_unlikely(0);
3154 else
3155 #endif
3156 emit_jno(0);
3157 }
3158 }
3159 }else{ // using tlb
3160 int x=0;
3161 if (opcode[i]==0x28) x=3; // SB
3162 if (opcode[i]==0x29) x=2; // SH
3163 map=get_reg(i_regs->regmap,TLREG);
3164 assert(map>=0);
3165 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3166 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3167 }
3168
3169 if (opcode[i]==0x28) { // SB
3170 if(!c||memtarget) {
97a238a6 3171 int x=0,a=temp;
2002a1db 3172#ifdef BIG_ENDIAN_MIPS
57871462 3173 if(!c) emit_xorimm(addr,3,temp);
3174 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3175#else
97a238a6 3176 if(!c) a=addr;
dadf55f2 3177#endif
3178#ifdef PCSX
3179 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2002a1db 3180#endif
57871462 3181 //gen_tlb_addr_w(temp,map);
3182 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 3183 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 3184 }
3185 type=STOREB_STUB;
3186 }
3187 if (opcode[i]==0x29) { // SH
3188 if(!c||memtarget) {
97a238a6 3189 int x=0,a=temp;
2002a1db 3190#ifdef BIG_ENDIAN_MIPS
57871462 3191 if(!c) emit_xorimm(addr,2,temp);
3192 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3193#else
97a238a6 3194 if(!c) a=addr;
dadf55f2 3195#endif
3196#ifdef PCSX
3197 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2002a1db 3198#endif
57871462 3199 //#ifdef
3200 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3201 //#else
3202 if(map>=0) {
97a238a6 3203 gen_tlb_addr_w(a,map);
3204 emit_writehword_indexed(tl,x,a);
57871462 3205 }else
97a238a6 3206 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
57871462 3207 }
3208 type=STOREH_STUB;
3209 }
3210 if (opcode[i]==0x2B) { // SW
dadf55f2 3211 if(!c||memtarget) {
3212 int a=addr;
3213#ifdef PCSX
3214 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
3215#endif
57871462 3216 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
dadf55f2 3217 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3218 }
57871462 3219 type=STOREW_STUB;
3220 }
3221 if (opcode[i]==0x3F) { // SD
3222 if(!c||memtarget) {
dadf55f2 3223 int a=addr;
3224#ifdef PCSX
3225 if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
3226#endif
57871462 3227 if(rs2[i]) {
3228 assert(th>=0);
3229 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3230 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
dadf55f2 3231 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
57871462 3232 }else{
3233 // Store zero
3234 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3235 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
dadf55f2 3236 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
57871462 3237 }
3238 }
3239 type=STORED_STUB;
3240 }
57871462 3241 if(!using_tlb) {
3242 if(!c||memtarget) {
3243 #ifdef DESTRUCTIVE_SHIFT
3244 // The x86 shift operation is 'destructive'; it overwrites the
3245 // source register, so we need to make a copy first and use that.
3246 addr=temp;
3247 #endif
3248 #if defined(HOST_IMM8)
3249 int ir=get_reg(i_regs->regmap,INVCP);
3250 assert(ir>=0);
3251 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3252 #else
3253 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3254 #endif
0bbd1454 3255 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3256 emit_callne(invalidate_addr_reg[addr]);
3257 #else
57871462 3258 jaddr2=(int)out;
3259 emit_jne(0);
3260 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3261 #endif
57871462 3262 }
3263 }
3eaa7048 3264 if(jaddr) {
3265 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3266 } else if(c&&!memtarget) {
3267 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3268 }
57871462 3269 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3270 //if(opcode[i]==0x2B || opcode[i]==0x28)
3271 //if(opcode[i]==0x2B || opcode[i]==0x29)
3272 //if(opcode[i]==0x2B)
3273 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3274 {
3275 //emit_pusha();
3276 save_regs(0x100f);
3277 emit_readword((int)&last_count,ECX);
3278 #ifdef __i386__
3279 if(get_reg(i_regs->regmap,CCREG)<0)
3280 emit_loadreg(CCREG,HOST_CCREG);
3281 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3282 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3283 emit_writeword(HOST_CCREG,(int)&Count);
3284 #endif
3285 #ifdef __arm__
3286 if(get_reg(i_regs->regmap,CCREG)<0)
3287 emit_loadreg(CCREG,0);
3288 else
3289 emit_mov(HOST_CCREG,0);
3290 emit_add(0,ECX,0);
3291 emit_addimm(0,2*ccadj[i],0);
3292 emit_writeword(0,(int)&Count);
3293 #endif
3294 emit_call((int)memdebug);
3295 //emit_popa();
3296 restore_regs(0x100f);
3297 }/**/
3298}
3299
3300void storelr_assemble(int i,struct regstat *i_regs)
3301{
3302 int s,th,tl;
3303 int temp;
3304 int temp2;
3305 int offset;
3306 int jaddr=0,jaddr2;
3307 int case1,case2,case3;
3308 int done0,done1,done2;
af4ee1fe 3309 int memtarget=0,c=0;
fab5d06d 3310 int agr=AGEN1+(i&1);
57871462 3311 u_int hr,reglist=0;
3312 th=get_reg(i_regs->regmap,rs2[i]|64);
3313 tl=get_reg(i_regs->regmap,rs2[i]);
3314 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3315 temp=get_reg(i_regs->regmap,agr);
3316 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3317 offset=imm[i];
3318 if(s>=0) {
3319 c=(i_regs->isconst>>s)&1;
af4ee1fe 3320 if(c) {
3321 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3322 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3323 }
57871462 3324 }
3325 assert(tl>=0);
3326 for(hr=0;hr<HOST_REGS;hr++) {
3327 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3328 }
535d208a 3329 assert(temp>=0);
3330 if(!using_tlb) {
3331 if(!c) {
3332 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3333 if(!offset&&s!=temp) emit_mov(s,temp);
3334 jaddr=(int)out;
3335 emit_jno(0);
3336 }
3337 else
3338 {
3339 if(!memtarget||!rs1[i]) {
57871462 3340 jaddr=(int)out;
3341 emit_jmp(0);
3342 }
57871462 3343 }
535d208a 3344 #ifdef RAM_OFFSET
3345 int map=get_reg(i_regs->regmap,ROREG);
3346 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3347 gen_tlb_addr_w(temp,map);
3348 #else
3349 if((u_int)rdram!=0x80000000)
3350 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3351 #endif
3352 }else{ // using tlb
3353 int map=get_reg(i_regs->regmap,TLREG);
3354 assert(map>=0);
3355 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3356 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3357 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3358 if(!jaddr&&!memtarget) {
3359 jaddr=(int)out;
3360 emit_jmp(0);
57871462 3361 }
535d208a 3362 gen_tlb_addr_w(temp,map);
3363 }
3364
3365 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3366 temp2=get_reg(i_regs->regmap,FTEMP);
3367 if(!rs2[i]) temp2=th=tl;
3368 }
57871462 3369
2002a1db 3370#ifndef BIG_ENDIAN_MIPS
3371 emit_xorimm(temp,3,temp);
3372#endif
535d208a 3373 emit_testimm(temp,2);
3374 case2=(int)out;
3375 emit_jne(0);
3376 emit_testimm(temp,1);
3377 case1=(int)out;
3378 emit_jne(0);
3379 // 0
3380 if (opcode[i]==0x2A) { // SWL
3381 emit_writeword_indexed(tl,0,temp);
3382 }
3383 if (opcode[i]==0x2E) { // SWR
3384 emit_writebyte_indexed(tl,3,temp);
3385 }
3386 if (opcode[i]==0x2C) { // SDL
3387 emit_writeword_indexed(th,0,temp);
3388 if(rs2[i]) emit_mov(tl,temp2);
3389 }
3390 if (opcode[i]==0x2D) { // SDR
3391 emit_writebyte_indexed(tl,3,temp);
3392 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3393 }
3394 done0=(int)out;
3395 emit_jmp(0);
3396 // 1
3397 set_jump_target(case1,(int)out);
3398 if (opcode[i]==0x2A) { // SWL
3399 // Write 3 msb into three least significant bytes
3400 if(rs2[i]) emit_rorimm(tl,8,tl);
3401 emit_writehword_indexed(tl,-1,temp);
3402 if(rs2[i]) emit_rorimm(tl,16,tl);
3403 emit_writebyte_indexed(tl,1,temp);
3404 if(rs2[i]) emit_rorimm(tl,8,tl);
3405 }
3406 if (opcode[i]==0x2E) { // SWR
3407 // Write two lsb into two most significant bytes
3408 emit_writehword_indexed(tl,1,temp);
3409 }
3410 if (opcode[i]==0x2C) { // SDL
3411 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3412 // Write 3 msb into three least significant bytes
3413 if(rs2[i]) emit_rorimm(th,8,th);
3414 emit_writehword_indexed(th,-1,temp);
3415 if(rs2[i]) emit_rorimm(th,16,th);
3416 emit_writebyte_indexed(th,1,temp);
3417 if(rs2[i]) emit_rorimm(th,8,th);
3418 }
3419 if (opcode[i]==0x2D) { // SDR
3420 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3421 // Write two lsb into two most significant bytes
3422 emit_writehword_indexed(tl,1,temp);
3423 }
3424 done1=(int)out;
3425 emit_jmp(0);
3426 // 2
3427 set_jump_target(case2,(int)out);
3428 emit_testimm(temp,1);
3429 case3=(int)out;
3430 emit_jne(0);
3431 if (opcode[i]==0x2A) { // SWL
3432 // Write two msb into two least significant bytes
3433 if(rs2[i]) emit_rorimm(tl,16,tl);
3434 emit_writehword_indexed(tl,-2,temp);
3435 if(rs2[i]) emit_rorimm(tl,16,tl);
3436 }
3437 if (opcode[i]==0x2E) { // SWR
3438 // Write 3 lsb into three most significant bytes
3439 emit_writebyte_indexed(tl,-1,temp);
3440 if(rs2[i]) emit_rorimm(tl,8,tl);
3441 emit_writehword_indexed(tl,0,temp);
3442 if(rs2[i]) emit_rorimm(tl,24,tl);
3443 }
3444 if (opcode[i]==0x2C) { // SDL
3445 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3446 // Write two msb into two least significant bytes
3447 if(rs2[i]) emit_rorimm(th,16,th);
3448 emit_writehword_indexed(th,-2,temp);
3449 if(rs2[i]) emit_rorimm(th,16,th);
3450 }
3451 if (opcode[i]==0x2D) { // SDR
3452 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3453 // Write 3 lsb into three most significant bytes
3454 emit_writebyte_indexed(tl,-1,temp);
3455 if(rs2[i]) emit_rorimm(tl,8,tl);
3456 emit_writehword_indexed(tl,0,temp);
3457 if(rs2[i]) emit_rorimm(tl,24,tl);
3458 }
3459 done2=(int)out;
3460 emit_jmp(0);
3461 // 3
3462 set_jump_target(case3,(int)out);
3463 if (opcode[i]==0x2A) { // SWL
3464 // Write msb into least significant byte
3465 if(rs2[i]) emit_rorimm(tl,24,tl);
3466 emit_writebyte_indexed(tl,-3,temp);
3467 if(rs2[i]) emit_rorimm(tl,8,tl);
3468 }
3469 if (opcode[i]==0x2E) { // SWR
3470 // Write entire word
3471 emit_writeword_indexed(tl,-3,temp);
3472 }
3473 if (opcode[i]==0x2C) { // SDL
3474 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3475 // Write msb into least significant byte
3476 if(rs2[i]) emit_rorimm(th,24,th);
3477 emit_writebyte_indexed(th,-3,temp);
3478 if(rs2[i]) emit_rorimm(th,8,th);
3479 }
3480 if (opcode[i]==0x2D) { // SDR
3481 if(rs2[i]) emit_mov(th,temp2);
3482 // Write entire word
3483 emit_writeword_indexed(tl,-3,temp);
3484 }
3485 set_jump_target(done0,(int)out);
3486 set_jump_target(done1,(int)out);
3487 set_jump_target(done2,(int)out);
3488 if (opcode[i]==0x2C) { // SDL
3489 emit_testimm(temp,4);
57871462 3490 done0=(int)out;
57871462 3491 emit_jne(0);
535d208a 3492 emit_andimm(temp,~3,temp);
3493 emit_writeword_indexed(temp2,4,temp);
3494 set_jump_target(done0,(int)out);
3495 }
3496 if (opcode[i]==0x2D) { // SDR
3497 emit_testimm(temp,4);
3498 done0=(int)out;
3499 emit_jeq(0);
3500 emit_andimm(temp,~3,temp);
3501 emit_writeword_indexed(temp2,-4,temp);
57871462 3502 set_jump_target(done0,(int)out);
57871462 3503 }
535d208a 3504 if(!c||!memtarget)
3505 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
57871462 3506 if(!using_tlb) {
535d208a 3507 #ifdef RAM_OFFSET
3508 int map=get_reg(i_regs->regmap,ROREG);
3509 if(map<0) map=HOST_TEMPREG;
3510 gen_orig_addr_w(temp,map);
3511 #else
57871462 3512 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
535d208a 3513 #endif
57871462 3514 #if defined(HOST_IMM8)
3515 int ir=get_reg(i_regs->regmap,INVCP);
3516 assert(ir>=0);
3517 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3518 #else
3519 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3520 #endif
535d208a 3521 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3522 emit_callne(invalidate_addr_reg[temp]);
3523 #else
57871462 3524 jaddr2=(int)out;
3525 emit_jne(0);
3526 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3527 #endif
57871462 3528 }
3529 /*
3530 emit_pusha();
3531 //save_regs(0x100f);
3532 emit_readword((int)&last_count,ECX);
3533 if(get_reg(i_regs->regmap,CCREG)<0)
3534 emit_loadreg(CCREG,HOST_CCREG);
3535 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3536 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3537 emit_writeword(HOST_CCREG,(int)&Count);
3538 emit_call((int)memdebug);
3539 emit_popa();
3540 //restore_regs(0x100f);
3541 /**/
3542}
3543
3544void c1ls_assemble(int i,struct regstat *i_regs)
3545{
3d624f89 3546#ifndef DISABLE_COP1
57871462 3547 int s,th,tl;
3548 int temp,ar;
3549 int map=-1;
3550 int offset;
3551 int c=0;
3552 int jaddr,jaddr2=0,jaddr3,type;
3553 int agr=AGEN1+(i&1);
3554 u_int hr,reglist=0;
3555 th=get_reg(i_regs->regmap,FTEMP|64);
3556 tl=get_reg(i_regs->regmap,FTEMP);
3557 s=get_reg(i_regs->regmap,rs1[i]);
3558 temp=get_reg(i_regs->regmap,agr);
3559 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3560 offset=imm[i];
3561 assert(tl>=0);
3562 assert(rs1[i]>0);
3563 assert(temp>=0);
3564 for(hr=0;hr<HOST_REGS;hr++) {
3565 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3566 }
3567 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3568 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3569 {
3570 // Loads use a temporary register which we need to save
3571 reglist|=1<<temp;
3572 }
3573 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3574 ar=temp;
3575 else // LWC1/LDC1
3576 ar=tl;
3577 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3578 //else c=(i_regs->wasconst>>s)&1;
3579 if(s>=0) c=(i_regs->wasconst>>s)&1;
3580 // Check cop1 unusable
3581 if(!cop1_usable) {
3582 signed char rs=get_reg(i_regs->regmap,CSREG);
3583 assert(rs>=0);
3584 emit_testimm(rs,0x20000000);
3585 jaddr=(int)out;
3586 emit_jeq(0);
3587 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3588 cop1_usable=1;
3589 }
3590 if (opcode[i]==0x39) { // SWC1 (get float address)
3591 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3592 }
3593 if (opcode[i]==0x3D) { // SDC1 (get double address)
3594 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3595 }
3596 // Generate address + offset
3597 if(!using_tlb) {
3598 if(!c)
4cb76aa4 3599 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
57871462 3600 }
3601 else
3602 {
3603 map=get_reg(i_regs->regmap,TLREG);
3604 assert(map>=0);
3605 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3606 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3607 }
3608 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3609 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3610 }
3611 }
3612 if (opcode[i]==0x39) { // SWC1 (read float)
3613 emit_readword_indexed(0,tl,tl);
3614 }
3615 if (opcode[i]==0x3D) { // SDC1 (read double)
3616 emit_readword_indexed(4,tl,th);
3617 emit_readword_indexed(0,tl,tl);
3618 }
3619 if (opcode[i]==0x31) { // LWC1 (get target address)
3620 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3621 }
3622 if (opcode[i]==0x35) { // LDC1 (get target address)
3623 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3624 }
3625 if(!using_tlb) {
3626 if(!c) {
3627 jaddr2=(int)out;
3628 emit_jno(0);
3629 }
4cb76aa4 3630 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
57871462 3631 jaddr2=(int)out;
3632 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3633 }
3634 #ifdef DESTRUCTIVE_SHIFT
3635 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3636 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3637 }
3638 #endif
3639 }else{
3640 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3641 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3642 }
3643 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3644 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3645 }
3646 }
3647 if (opcode[i]==0x31) { // LWC1
3648 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3649 //gen_tlb_addr_r(ar,map);
3650 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3651 #ifdef HOST_IMM_ADDR32
3652 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3653 else
3654 #endif
3655 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3656 type=LOADW_STUB;
3657 }
3658 if (opcode[i]==0x35) { // LDC1
3659 assert(th>=0);
3660 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3661 //gen_tlb_addr_r(ar,map);
3662 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3663 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3664 #ifdef HOST_IMM_ADDR32
3665 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3666 else
3667 #endif
3668 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3669 type=LOADD_STUB;
3670 }
3671 if (opcode[i]==0x39) { // SWC1
3672 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3673 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3674 type=STOREW_STUB;
3675 }
3676 if (opcode[i]==0x3D) { // SDC1
3677 assert(th>=0);
3678 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3679 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3680 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3681 type=STORED_STUB;
3682 }
3683 if(!using_tlb) {
3684 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3685 #ifndef DESTRUCTIVE_SHIFT
3686 temp=offset||c||s<0?ar:s;
3687 #endif
3688 #if defined(HOST_IMM8)
3689 int ir=get_reg(i_regs->regmap,INVCP);
3690 assert(ir>=0);
3691 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3692 #else
3693 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3694 #endif
0bbd1454 3695 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3696 emit_callne(invalidate_addr_reg[temp]);
3697 #else
57871462 3698 jaddr3=(int)out;
3699 emit_jne(0);
3700 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
0bbd1454 3701 #endif
57871462 3702 }
3703 }
3704 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3705 if (opcode[i]==0x31) { // LWC1 (write float)
3706 emit_writeword_indexed(tl,0,temp);
3707 }
3708 if (opcode[i]==0x35) { // LDC1 (write double)
3709 emit_writeword_indexed(th,4,temp);
3710 emit_writeword_indexed(tl,0,temp);
3711 }
3712 //if(opcode[i]==0x39)
3713 /*if(opcode[i]==0x39||opcode[i]==0x31)
3714 {
3715 emit_pusha();
3716 emit_readword((int)&last_count,ECX);
3717 if(get_reg(i_regs->regmap,CCREG)<0)
3718 emit_loadreg(CCREG,HOST_CCREG);
3719 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3720 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3721 emit_writeword(HOST_CCREG,(int)&Count);
3722 emit_call((int)memdebug);
3723 emit_popa();
3724 }/**/
3d624f89 3725#else
3726 cop1_unusable(i, i_regs);
3727#endif
57871462 3728}
3729
b9b61529 3730void c2ls_assemble(int i,struct regstat *i_regs)
3731{
3732 int s,tl;
3733 int ar;
3734 int offset;
1fd1aceb 3735 int memtarget=0,c=0;
c2e3bd42 3736 int jaddr2=0,jaddr3,type;
b9b61529 3737 int agr=AGEN1+(i&1);
3738 u_int hr,reglist=0;
3739 u_int copr=(source[i]>>16)&0x1f;
3740 s=get_reg(i_regs->regmap,rs1[i]);
3741 tl=get_reg(i_regs->regmap,FTEMP);
3742 offset=imm[i];
3743 assert(rs1[i]>0);
3744 assert(tl>=0);
3745 assert(!using_tlb);
3746
3747 for(hr=0;hr<HOST_REGS;hr++) {
3748 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3749 }
3750 if(i_regs->regmap[HOST_CCREG]==CCREG)
3751 reglist&=~(1<<HOST_CCREG);
3752
3753 // get the address
3754 if (opcode[i]==0x3a) { // SWC2
3755 ar=get_reg(i_regs->regmap,agr);
3756 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3757 reglist|=1<<ar;
3758 } else { // LWC2
3759 ar=tl;
3760 }
1fd1aceb 3761 if(s>=0) c=(i_regs->wasconst>>s)&1;
3762 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3763 if (!offset&&!c&&s>=0) ar=s;
3764 assert(ar>=0);
3765
3766 if (opcode[i]==0x3a) { // SWC2
3767 cop2_get_dreg(copr,tl,HOST_TEMPREG);
1fd1aceb 3768 type=STOREW_STUB;
b9b61529 3769 }
1fd1aceb 3770 else
b9b61529 3771 type=LOADW_STUB;
1fd1aceb 3772
3773 if(c&&!memtarget) {
3774 jaddr2=(int)out;
3775 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3776 }
1fd1aceb 3777 else {
3778 if(!c) {
3779 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3780 jaddr2=(int)out;
3781 emit_jno(0);
3782 }
3783 if (opcode[i]==0x32) { // LWC2
3784 #ifdef HOST_IMM_ADDR32
3785 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3786 else
3787 #endif
3788 emit_readword_indexed(0,ar,tl);
3789 }
3790 if (opcode[i]==0x3a) { // SWC2
3791 #ifdef DESTRUCTIVE_SHIFT
3792 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3793 #endif
3794 emit_writeword_indexed(tl,0,ar);
3795 }
b9b61529 3796 }
3797 if(jaddr2)
3798 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3799 if (opcode[i]==0x3a) { // SWC2
3800#if defined(HOST_IMM8)
3801 int ir=get_reg(i_regs->regmap,INVCP);
3802 assert(ir>=0);
3803 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3804#else
3805 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3806#endif
0bbd1454 3807 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3808 emit_callne(invalidate_addr_reg[ar]);
3809 #else
b9b61529 3810 jaddr3=(int)out;
3811 emit_jne(0);
3812 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3813 #endif
b9b61529 3814 }
3815 if (opcode[i]==0x32) { // LWC2
3816 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3817 }
3818}
3819
57871462 3820#ifndef multdiv_assemble
3821void multdiv_assemble(int i,struct regstat *i_regs)
3822{
3823 printf("Need multdiv_assemble for this architecture.\n");
3824 exit(1);
3825}
3826#endif
3827
3828void mov_assemble(int i,struct regstat *i_regs)
3829{
3830 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3831 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
57871462 3832 if(rt1[i]) {
3833 signed char sh,sl,th,tl;
3834 th=get_reg(i_regs->regmap,rt1[i]|64);
3835 tl=get_reg(i_regs->regmap,rt1[i]);
3836 //assert(tl>=0);
3837 if(tl>=0) {
3838 sh=get_reg(i_regs->regmap,rs1[i]|64);
3839 sl=get_reg(i_regs->regmap,rs1[i]);
3840 if(sl>=0) emit_mov(sl,tl);
3841 else emit_loadreg(rs1[i],tl);
3842 if(th>=0) {
3843 if(sh>=0) emit_mov(sh,th);
3844 else emit_loadreg(rs1[i]|64,th);
3845 }
3846 }
3847 }
3848}
3849
3850#ifndef fconv_assemble
3851void fconv_assemble(int i,struct regstat *i_regs)
3852{
3853 printf("Need fconv_assemble for this architecture.\n");
3854 exit(1);
3855}
3856#endif
3857
3858#if 0
3859void float_assemble(int i,struct regstat *i_regs)
3860{
3861 printf("Need float_assemble for this architecture.\n");
3862 exit(1);
3863}
3864#endif
3865
3866void syscall_assemble(int i,struct regstat *i_regs)
3867{
3868 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3869 assert(ccreg==HOST_CCREG);
3870 assert(!is_delayslot);
3871 emit_movimm(start+i*4,EAX); // Get PC
3872 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
7139f3c8 3873 emit_jmp((int)jump_syscall_hle); // XXX
3874}
3875
3876void hlecall_assemble(int i,struct regstat *i_regs)
3877{
3878 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3879 assert(ccreg==HOST_CCREG);
3880 assert(!is_delayslot);
3881 emit_movimm(start+i*4+4,0); // Get PC
67ba0fb4 3882 emit_movimm((int)psxHLEt[source[i]&7],1);
7139f3c8 3883 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
67ba0fb4 3884 emit_jmp((int)jump_hlecall);
57871462 3885}
3886
1e973cb0 3887void intcall_assemble(int i,struct regstat *i_regs)
3888{
3889 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3890 assert(ccreg==HOST_CCREG);
3891 assert(!is_delayslot);
3892 emit_movimm(start+i*4,0); // Get PC
3893 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3894 emit_jmp((int)jump_intcall);
3895}
3896
57871462 3897void ds_assemble(int i,struct regstat *i_regs)
3898{
3899 is_delayslot=1;
3900 switch(itype[i]) {
3901 case ALU:
3902 alu_assemble(i,i_regs);break;
3903 case IMM16:
3904 imm16_assemble(i,i_regs);break;
3905 case SHIFT:
3906 shift_assemble(i,i_regs);break;
3907 case SHIFTIMM:
3908 shiftimm_assemble(i,i_regs);break;
3909 case LOAD:
3910 load_assemble(i,i_regs);break;
3911 case LOADLR:
3912 loadlr_assemble(i,i_regs);break;
3913 case STORE:
3914 store_assemble(i,i_regs);break;
3915 case STORELR:
3916 storelr_assemble(i,i_regs);break;
3917 case COP0:
3918 cop0_assemble(i,i_regs);break;
3919 case COP1:
3920 cop1_assemble(i,i_regs);break;
3921 case C1LS:
3922 c1ls_assemble(i,i_regs);break;
b9b61529 3923 case COP2:
3924 cop2_assemble(i,i_regs);break;
3925 case C2LS:
3926 c2ls_assemble(i,i_regs);break;
3927 case C2OP:
3928 c2op_assemble(i,i_regs);break;
57871462 3929 case FCONV:
3930 fconv_assemble(i,i_regs);break;
3931 case FLOAT:
3932 float_assemble(i,i_regs);break;
3933 case FCOMP:
3934 fcomp_assemble(i,i_regs);break;
3935 case MULTDIV:
3936 multdiv_assemble(i,i_regs);break;
3937 case MOV:
3938 mov_assemble(i,i_regs);break;
3939 case SYSCALL:
7139f3c8 3940 case HLECALL:
1e973cb0 3941 case INTCALL:
57871462 3942 case SPAN:
3943 case UJUMP:
3944 case RJUMP:
3945 case CJUMP:
3946 case SJUMP:
3947 case FJUMP:
3948 printf("Jump in the delay slot. This is probably a bug.\n");
3949 }
3950 is_delayslot=0;
3951}
3952
3953// Is the branch target a valid internal jump?
3954int internal_branch(uint64_t i_is32,int addr)
3955{
3956 if(addr&1) return 0; // Indirect (register) jump
3957 if(addr>=start && addr<start+slen*4-4)
3958 {
3959 int t=(addr-start)>>2;
3960 // Delay slots are not valid branch targets
3961 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3962 // 64 -> 32 bit transition requires a recompile
3963 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3964 {
3965 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3966 else printf("optimizable: yes\n");
3967 }*/
3968 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
a28c6ce8 3969#ifndef FORCE32
57871462 3970 if(requires_32bit[t]&~i_is32) return 0;
a28c6ce8 3971 else
3972#endif
3973 return 1;
57871462 3974 }
3975 return 0;
3976}
3977
3978#ifndef wb_invalidate
3979void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3980 uint64_t u,uint64_t uu)
3981{
3982 int hr;
3983 for(hr=0;hr<HOST_REGS;hr++) {
3984 if(hr!=EXCLUDE_REG) {
3985 if(pre[hr]!=entry[hr]) {
3986 if(pre[hr]>=0) {
3987 if((dirty>>hr)&1) {
3988 if(get_reg(entry,pre[hr])<0) {
3989 if(pre[hr]<64) {
3990 if(!((u>>pre[hr])&1)) {
3991 emit_storereg(pre[hr],hr);
3992 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3993 emit_sarimm(hr,31,hr);
3994 emit_storereg(pre[hr]|64,hr);
3995 }
3996 }
3997 }else{
3998 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3999 emit_storereg(pre[hr],hr);
4000 }
4001 }
4002 }
4003 }
4004 }
4005 }
4006 }
4007 }
4008 // Move from one register to another (no writeback)
4009 for(hr=0;hr<HOST_REGS;hr++) {
4010 if(hr!=EXCLUDE_REG) {
4011 if(pre[hr]!=entry[hr]) {
4012 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4013 int nr;
4014 if((nr=get_reg(entry,pre[hr]))>=0) {
4015 emit_mov(hr,nr);
4016 }
4017 }
4018 }
4019 }
4020 }
4021}
4022#endif
4023
4024// Load the specified registers
4025// This only loads the registers given as arguments because
4026// we don't want to load things that will be overwritten
4027void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4028{
4029 int hr;
4030 // Load 32-bit regs
4031 for(hr=0;hr<HOST_REGS;hr++) {
4032 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4033 if(entry[hr]!=regmap[hr]) {
4034 if(regmap[hr]==rs1||regmap[hr]==rs2)
4035 {
4036 if(regmap[hr]==0) {
4037 emit_zeroreg(hr);
4038 }
4039 else
4040 {
4041 emit_loadreg(regmap[hr],hr);
4042 }
4043 }
4044 }
4045 }
4046 }
4047 //Load 64-bit regs
4048 for(hr=0;hr<HOST_REGS;hr++) {
4049 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4050 if(entry[hr]!=regmap[hr]) {
4051 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4052 {
4053 assert(regmap[hr]!=64);
4054 if((is32>>(regmap[hr]&63))&1) {
4055 int lr=get_reg(regmap,regmap[hr]-64);
4056 if(lr>=0)
4057 emit_sarimm(lr,31,hr);
4058 else
4059 emit_loadreg(regmap[hr],hr);
4060 }
4061 else
4062 {
4063 emit_loadreg(regmap[hr],hr);
4064 }
4065 }
4066 }
4067 }
4068 }
4069}
4070
4071// Load registers prior to the start of a loop
4072// so that they are not loaded within the loop
4073static void loop_preload(signed char pre[],signed char entry[])
4074{
4075 int hr;
4076 for(hr=0;hr<HOST_REGS;hr++) {
4077 if(hr!=EXCLUDE_REG) {
4078 if(pre[hr]!=entry[hr]) {
4079 if(entry[hr]>=0) {
4080 if(get_reg(pre,entry[hr])<0) {
4081 assem_debug("loop preload:\n");
4082 //printf("loop preload: %d\n",hr);
4083 if(entry[hr]==0) {
4084 emit_zeroreg(hr);
4085 }
4086 else if(entry[hr]<TEMPREG)
4087 {
4088 emit_loadreg(entry[hr],hr);
4089 }
4090 else if(entry[hr]-64<TEMPREG)
4091 {
4092 emit_loadreg(entry[hr],hr);
4093 }
4094 }
4095 }
4096 }
4097 }
4098 }
4099}
4100
4101// Generate address for load/store instruction
b9b61529 4102// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
57871462 4103void address_generation(int i,struct regstat *i_regs,signed char entry[])
4104{
b9b61529 4105 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
5194fb95 4106 int ra=-1;
57871462 4107 int agr=AGEN1+(i&1);
4108 int mgr=MGEN1+(i&1);
4109 if(itype[i]==LOAD) {
4110 ra=get_reg(i_regs->regmap,rt1[i]);
535d208a 4111 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4112 assert(ra>=0);
57871462 4113 }
4114 if(itype[i]==LOADLR) {
4115 ra=get_reg(i_regs->regmap,FTEMP);
4116 }
4117 if(itype[i]==STORE||itype[i]==STORELR) {
4118 ra=get_reg(i_regs->regmap,agr);
4119 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4120 }
b9b61529 4121 if(itype[i]==C1LS||itype[i]==C2LS) {
4122 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 4123 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 4124 else { // SWC1/SDC1/SWC2/SDC2
57871462 4125 ra=get_reg(i_regs->regmap,agr);
4126 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4127 }
4128 }
4129 int rs=get_reg(i_regs->regmap,rs1[i]);
4130 int rm=get_reg(i_regs->regmap,TLREG);
4131 if(ra>=0) {
4132 int offset=imm[i];
4133 int c=(i_regs->wasconst>>rs)&1;
4134 if(rs1[i]==0) {
4135 // Using r0 as a base address
4136 /*if(rm>=0) {
4137 if(!entry||entry[rm]!=mgr) {
4138 generate_map_const(offset,rm);
4139 } // else did it in the previous cycle
4140 }*/
4141 if(!entry||entry[ra]!=agr) {
4142 if (opcode[i]==0x22||opcode[i]==0x26) {
4143 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4144 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4145 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4146 }else{
4147 emit_movimm(offset,ra);
4148 }
4149 } // else did it in the previous cycle
4150 }
4151 else if(rs<0) {
4152 if(!entry||entry[ra]!=rs1[i])
4153 emit_loadreg(rs1[i],ra);
4154 //if(!entry||entry[ra]!=rs1[i])
4155 // printf("poor load scheduling!\n");
4156 }
4157 else if(c) {
4158 if(rm>=0) {
4159 if(!entry||entry[rm]!=mgr) {
b9b61529 4160 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
57871462 4161 // Stores to memory go thru the mapper to detect self-modifying
4162 // code, loads don't.
4163 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4cb76aa4 4164 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4165 generate_map_const(constmap[i][rs]+offset,rm);
4166 }else{
4167 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4168 generate_map_const(constmap[i][rs]+offset,rm);
4169 }
4170 }
4171 }
4172 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4173 if(!entry||entry[ra]!=agr) {
4174 if (opcode[i]==0x22||opcode[i]==0x26) {
4175 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4176 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4177 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4178 }else{
4179 #ifdef HOST_IMM_ADDR32
b9b61529 4180 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4181 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4182 #endif
4183 emit_movimm(constmap[i][rs]+offset,ra);
4184 }
4185 } // else did it in the previous cycle
4186 } // else load_consts already did it
4187 }
4188 if(offset&&!c&&rs1[i]) {
4189 if(rs>=0) {
4190 emit_addimm(rs,offset,ra);
4191 }else{
4192 emit_addimm(ra,offset,ra);
4193 }
4194 }
4195 }
4196 }
4197 // Preload constants for next instruction
b9b61529 4198 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 4199 int agr,ra;
4200 #ifndef HOST_IMM_ADDR32
4201 // Mapper entry
4202 agr=MGEN1+((i+1)&1);
4203 ra=get_reg(i_regs->regmap,agr);
4204 if(ra>=0) {
4205 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4206 int offset=imm[i+1];
4207 int c=(regs[i+1].wasconst>>rs)&1;
4208 if(c) {
b9b61529 4209 if(itype[i+1]==STORE||itype[i+1]==STORELR
4210 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
57871462 4211 // Stores to memory go thru the mapper to detect self-modifying
4212 // code, loads don't.
4213 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4cb76aa4 4214 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4215 generate_map_const(constmap[i+1][rs]+offset,ra);
4216 }else{
4217 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4218 generate_map_const(constmap[i+1][rs]+offset,ra);
4219 }
4220 }
4221 /*else if(rs1[i]==0) {
4222 generate_map_const(offset,ra);
4223 }*/
4224 }
4225 #endif
4226 // Actual address
4227 agr=AGEN1+((i+1)&1);
4228 ra=get_reg(i_regs->regmap,agr);
4229 if(ra>=0) {
4230 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4231 int offset=imm[i+1];
4232 int c=(regs[i+1].wasconst>>rs)&1;
4233 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4234 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4235 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4236 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4237 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4238 }else{
4239 #ifdef HOST_IMM_ADDR32
b9b61529 4240 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4241 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4242 #endif
4243 emit_movimm(constmap[i+1][rs]+offset,ra);
4244 }
4245 }
4246 else if(rs1[i+1]==0) {
4247 // Using r0 as a base address
4248 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4249 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4250 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4251 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4252 }else{
4253 emit_movimm(offset,ra);
4254 }
4255 }
4256 }
4257 }
4258}
4259
4260int get_final_value(int hr, int i, int *value)
4261{
4262 int reg=regs[i].regmap[hr];
4263 while(i<slen-1) {
4264 if(regs[i+1].regmap[hr]!=reg) break;
4265 if(!((regs[i+1].isconst>>hr)&1)) break;
4266 if(bt[i+1]) break;
4267 i++;
4268 }
4269 if(i<slen-1) {
4270 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4271 *value=constmap[i][hr];
4272 return 1;
4273 }
4274 if(!bt[i+1]) {
4275 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4276 // Load in delay slot, out-of-order execution
4277 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4278 {
4279 #ifdef HOST_IMM_ADDR32
4280 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4281 #endif
4282 // Precompute load address
4283 *value=constmap[i][hr]+imm[i+2];
4284 return 1;
4285 }
4286 }
4287 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4288 {
4289 #ifdef HOST_IMM_ADDR32
4290 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4291 #endif
4292 // Precompute load address
4293 *value=constmap[i][hr]+imm[i+1];
4294 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4295 return 1;
4296 }
4297 }
4298 }
4299 *value=constmap[i][hr];
4300 //printf("c=%x\n",(int)constmap[i][hr]);
4301 if(i==slen-1) return 1;
4302 if(reg<64) {
4303 return !((unneeded_reg[i+1]>>reg)&1);
4304 }else{
4305 return !((unneeded_reg_upper[i+1]>>reg)&1);
4306 }
4307}
4308
4309// Load registers with known constants
4310void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4311{
4312 int hr;
4313 // Load 32-bit regs
4314 for(hr=0;hr<HOST_REGS;hr++) {
4315 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4316 //if(entry[hr]!=regmap[hr]) {
4317 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4318 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4319 int value;
4320 if(get_final_value(hr,i,&value)) {
4321 if(value==0) {
4322 emit_zeroreg(hr);
4323 }
4324 else {
4325 emit_movimm(value,hr);
4326 }
4327 }
4328 }
4329 }
4330 }
4331 }
4332 // Load 64-bit regs
4333 for(hr=0;hr<HOST_REGS;hr++) {
4334 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4335 //if(entry[hr]!=regmap[hr]) {
4336 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4337 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4338 if((is32>>(regmap[hr]&63))&1) {
4339 int lr=get_reg(regmap,regmap[hr]-64);
4340 assert(lr>=0);
4341 emit_sarimm(lr,31,hr);
4342 }
4343 else
4344 {
4345 int value;
4346 if(get_final_value(hr,i,&value)) {
4347 if(value==0) {
4348 emit_zeroreg(hr);
4349 }
4350 else {
4351 emit_movimm(value,hr);
4352 }
4353 }
4354 }
4355 }
4356 }
4357 }
4358 }
4359}
4360void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4361{
4362 int hr;
4363 // Load 32-bit regs
4364 for(hr=0;hr<HOST_REGS;hr++) {
4365 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4366 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4367 int value=constmap[i][hr];
4368 if(value==0) {
4369 emit_zeroreg(hr);
4370 }
4371 else {
4372 emit_movimm(value,hr);
4373 }
4374 }
4375 }
4376 }
4377 // Load 64-bit regs
4378 for(hr=0;hr<HOST_REGS;hr++) {
4379 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4380 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4381 if((is32>>(regmap[hr]&63))&1) {
4382 int lr=get_reg(regmap,regmap[hr]-64);
4383 assert(lr>=0);
4384 emit_sarimm(lr,31,hr);
4385 }
4386 else
4387 {
4388 int value=constmap[i][hr];
4389 if(value==0) {
4390 emit_zeroreg(hr);
4391 }
4392 else {
4393 emit_movimm(value,hr);
4394 }
4395 }
4396 }
4397 }
4398 }
4399}
4400
4401// Write out all dirty registers (except cycle count)
4402void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4403{
4404 int hr;
4405 for(hr=0;hr<HOST_REGS;hr++) {
4406 if(hr!=EXCLUDE_REG) {
4407 if(i_regmap[hr]>0) {
4408 if(i_regmap[hr]!=CCREG) {
4409 if((i_dirty>>hr)&1) {
4410 if(i_regmap[hr]<64) {
4411 emit_storereg(i_regmap[hr],hr);
24385cae 4412#ifndef FORCE32
57871462 4413 if( ((i_is32>>i_regmap[hr])&1) ) {
4414 #ifdef DESTRUCTIVE_WRITEBACK
4415 emit_sarimm(hr,31,hr);
4416 emit_storereg(i_regmap[hr]|64,hr);
4417 #else
4418 emit_sarimm(hr,31,HOST_TEMPREG);
4419 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4420 #endif
4421 }
24385cae 4422#endif
57871462 4423 }else{
4424 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4425 emit_storereg(i_regmap[hr],hr);
4426 }
4427 }
4428 }
4429 }
4430 }
4431 }
4432 }
4433}
4434// Write out dirty registers that we need to reload (pair with load_needed_regs)
4435// This writes the registers not written by store_regs_bt
4436void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4437{
4438 int hr;
4439 int t=(addr-start)>>2;
4440 for(hr=0;hr<HOST_REGS;hr++) {
4441 if(hr!=EXCLUDE_REG) {
4442 if(i_regmap[hr]>0) {
4443 if(i_regmap[hr]!=CCREG) {
4444 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4445 if((i_dirty>>hr)&1) {
4446 if(i_regmap[hr]<64) {
4447 emit_storereg(i_regmap[hr],hr);
24385cae 4448#ifndef FORCE32
57871462 4449 if( ((i_is32>>i_regmap[hr])&1) ) {
4450 #ifdef DESTRUCTIVE_WRITEBACK
4451 emit_sarimm(hr,31,hr);
4452 emit_storereg(i_regmap[hr]|64,hr);
4453 #else
4454 emit_sarimm(hr,31,HOST_TEMPREG);
4455 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4456 #endif
4457 }
24385cae 4458#endif
57871462 4459 }else{
4460 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4461 emit_storereg(i_regmap[hr],hr);
4462 }
4463 }
4464 }
4465 }
4466 }
4467 }
4468 }
4469 }
4470}
4471
4472// Load all registers (except cycle count)
4473void load_all_regs(signed char i_regmap[])
4474{
4475 int hr;
4476 for(hr=0;hr<HOST_REGS;hr++) {
4477 if(hr!=EXCLUDE_REG) {
4478 if(i_regmap[hr]==0) {
4479 emit_zeroreg(hr);
4480 }
4481 else
4482 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4483 {
4484 emit_loadreg(i_regmap[hr],hr);
4485 }
4486 }
4487 }
4488}
4489
4490// Load all current registers also needed by next instruction
4491void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4492{
4493 int hr;
4494 for(hr=0;hr<HOST_REGS;hr++) {
4495 if(hr!=EXCLUDE_REG) {
4496 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4497 if(i_regmap[hr]==0) {
4498 emit_zeroreg(hr);
4499 }
4500 else
4501 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4502 {
4503 emit_loadreg(i_regmap[hr],hr);
4504 }
4505 }
4506 }
4507 }
4508}
4509
4510// Load all regs, storing cycle count if necessary
4511void load_regs_entry(int t)
4512{
4513 int hr;
4514 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4515 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4516 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4517 emit_storereg(CCREG,HOST_CCREG);
4518 }
4519 // Load 32-bit regs
4520 for(hr=0;hr<HOST_REGS;hr++) {
4521 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4522 if(regs[t].regmap_entry[hr]==0) {
4523 emit_zeroreg(hr);
4524 }
4525 else if(regs[t].regmap_entry[hr]!=CCREG)
4526 {
4527 emit_loadreg(regs[t].regmap_entry[hr],hr);
4528 }
4529 }
4530 }
4531 // Load 64-bit regs
4532 for(hr=0;hr<HOST_REGS;hr++) {
4533 if(regs[t].regmap_entry[hr]>=64) {
4534 assert(regs[t].regmap_entry[hr]!=64);
4535 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4536 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4537 if(lr<0) {
4538 emit_loadreg(regs[t].regmap_entry[hr],hr);
4539 }
4540 else
4541 {
4542 emit_sarimm(lr,31,hr);
4543 }
4544 }
4545 else
4546 {
4547 emit_loadreg(regs[t].regmap_entry[hr],hr);
4548 }
4549 }
4550 }
4551}
4552
4553// Store dirty registers prior to branch
4554void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4555{
4556 if(internal_branch(i_is32,addr))
4557 {
4558 int t=(addr-start)>>2;
4559 int hr;
4560 for(hr=0;hr<HOST_REGS;hr++) {
4561 if(hr!=EXCLUDE_REG) {
4562 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4563 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4564 if((i_dirty>>hr)&1) {
4565 if(i_regmap[hr]<64) {
4566 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4567 emit_storereg(i_regmap[hr],hr);
4568 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4569 #ifdef DESTRUCTIVE_WRITEBACK
4570 emit_sarimm(hr,31,hr);
4571 emit_storereg(i_regmap[hr]|64,hr);
4572 #else
4573 emit_sarimm(hr,31,HOST_TEMPREG);
4574 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4575 #endif
4576 }
4577 }
4578 }else{
4579 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4580 emit_storereg(i_regmap[hr],hr);
4581 }
4582 }
4583 }
4584 }
4585 }
4586 }
4587 }
4588 }
4589 else
4590 {
4591 // Branch out of this block, write out all dirty regs
4592 wb_dirtys(i_regmap,i_is32,i_dirty);
4593 }
4594}
4595
4596// Load all needed registers for branch target
4597void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4598{
4599 //if(addr>=start && addr<(start+slen*4))
4600 if(internal_branch(i_is32,addr))
4601 {
4602 int t=(addr-start)>>2;
4603 int hr;
4604 // Store the cycle count before loading something else
4605 if(i_regmap[HOST_CCREG]!=CCREG) {
4606 assert(i_regmap[HOST_CCREG]==-1);
4607 }
4608 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4609 emit_storereg(CCREG,HOST_CCREG);
4610 }
4611 // Load 32-bit regs
4612 for(hr=0;hr<HOST_REGS;hr++) {
4613 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4614 #ifdef DESTRUCTIVE_WRITEBACK
4615 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4616 #else
4617 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4618 #endif
4619 if(regs[t].regmap_entry[hr]==0) {
4620 emit_zeroreg(hr);
4621 }
4622 else if(regs[t].regmap_entry[hr]!=CCREG)
4623 {
4624 emit_loadreg(regs[t].regmap_entry[hr],hr);
4625 }
4626 }
4627 }
4628 }
4629 //Load 64-bit regs
4630 for(hr=0;hr<HOST_REGS;hr++) {
4631 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64) {
4632 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4633 assert(regs[t].regmap_entry[hr]!=64);
4634 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4635 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4636 if(lr<0) {
4637 emit_loadreg(regs[t].regmap_entry[hr],hr);
4638 }
4639 else
4640 {
4641 emit_sarimm(lr,31,hr);
4642 }
4643 }
4644 else
4645 {
4646 emit_loadreg(regs[t].regmap_entry[hr],hr);
4647 }
4648 }
4649 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4650 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4651 assert(lr>=0);
4652 emit_sarimm(lr,31,hr);
4653 }
4654 }
4655 }
4656 }
4657}
4658
4659int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4660{
4661 if(addr>=start && addr<start+slen*4-4)
4662 {
4663 int t=(addr-start)>>2;
4664 int hr;
4665 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4666 for(hr=0;hr<HOST_REGS;hr++)
4667 {
4668 if(hr!=EXCLUDE_REG)
4669 {
4670 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4671 {
4672 if(regs[t].regmap_entry[hr]!=-1)
4673 {
4674 return 0;
4675 }
4676 else
4677 if((i_dirty>>hr)&1)
4678 {
4679 if(i_regmap[hr]<64)
4680 {
4681 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4682 return 0;
4683 }
4684 else
4685 {
4686 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4687 return 0;
4688 }
4689 }
4690 }
4691 else // Same register but is it 32-bit or dirty?
4692 if(i_regmap[hr]>=0)
4693 {
4694 if(!((regs[t].dirty>>hr)&1))
4695 {
4696 if((i_dirty>>hr)&1)
4697 {
4698 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4699 {
4700 //printf("%x: dirty no match\n",addr);
4701 return 0;
4702 }
4703 }
4704 }
4705 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4706 {
4707 //printf("%x: is32 no match\n",addr);
4708 return 0;
4709 }
4710 }
4711 }
4712 }
4713 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
a28c6ce8 4714#ifndef FORCE32
57871462 4715 if(requires_32bit[t]&~i_is32) return 0;
a28c6ce8 4716#endif
57871462 4717 // Delay slots are not valid branch targets
4718 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4719 // Delay slots require additional processing, so do not match
4720 if(is_ds[t]) return 0;
4721 }
4722 else
4723 {
4724 int hr;
4725 for(hr=0;hr<HOST_REGS;hr++)
4726 {
4727 if(hr!=EXCLUDE_REG)
4728 {
4729 if(i_regmap[hr]>=0)
4730 {
4731 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4732 {
4733 if((i_dirty>>hr)&1)
4734 {
4735 return 0;
4736 }
4737 }
4738 }
4739 }
4740 }
4741 }
4742 return 1;
4743}
4744
4745// Used when a branch jumps into the delay slot of another branch
4746void ds_assemble_entry(int i)
4747{
4748 int t=(ba[i]-start)>>2;
4749 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4750 assem_debug("Assemble delay slot at %x\n",ba[i]);
4751 assem_debug("<->\n");
4752 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4753 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4754 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4755 address_generation(t,&regs[t],regs[t].regmap_entry);
b9b61529 4756 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
57871462 4757 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4758 cop1_usable=0;
4759 is_delayslot=0;
4760 switch(itype[t]) {
4761 case ALU:
4762 alu_assemble(t,&regs[t]);break;
4763 case IMM16:
4764 imm16_assemble(t,&regs[t]);break;
4765 case SHIFT:
4766 shift_assemble(t,&regs[t]);break;
4767 case SHIFTIMM:
4768 shiftimm_assemble(t,&regs[t]);break;
4769 case LOAD:
4770 load_assemble(t,&regs[t]);break;
4771 case LOADLR:
4772 loadlr_assemble(t,&regs[t]);break;
4773 case STORE:
4774 store_assemble(t,&regs[t]);break;
4775 case STORELR:
4776 storelr_assemble(t,&regs[t]);break;
4777 case COP0:
4778 cop0_assemble(t,&regs[t]);break;
4779 case COP1:
4780 cop1_assemble(t,&regs[t]);break;
4781 case C1LS:
4782 c1ls_assemble(t,&regs[t]);break;
b9b61529 4783 case COP2:
4784 cop2_assemble(t,&regs[t]);break;
4785 case C2LS:
4786 c2ls_assemble(t,&regs[t]);break;
4787 case C2OP:
4788 c2op_assemble(t,&regs[t]);break;
57871462 4789 case FCONV:
4790 fconv_assemble(t,&regs[t]);break;
4791 case FLOAT:
4792 float_assemble(t,&regs[t]);break;
4793 case FCOMP:
4794 fcomp_assemble(t,&regs[t]);break;
4795 case MULTDIV:
4796 multdiv_assemble(t,&regs[t]);break;
4797 case MOV:
4798 mov_assemble(t,&regs[t]);break;
4799 case SYSCALL:
7139f3c8 4800 case HLECALL:
1e973cb0 4801 case INTCALL:
57871462 4802 case SPAN:
4803 case UJUMP:
4804 case RJUMP:
4805 case CJUMP:
4806 case SJUMP:
4807 case FJUMP:
4808 printf("Jump in the delay slot. This is probably a bug.\n");
4809 }
4810 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4811 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4812 if(internal_branch(regs[t].is32,ba[i]+4))
4813 assem_debug("branch: internal\n");
4814 else
4815 assem_debug("branch: external\n");
4816 assert(internal_branch(regs[t].is32,ba[i]+4));
4817 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4818 emit_jmp(0);
4819}
4820
4821void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4822{
4823 int count;
4824 int jaddr;
4825 int idle=0;
4826 if(itype[i]==RJUMP)
4827 {
4828 *adj=0;
4829 }
4830 //if(ba[i]>=start && ba[i]<(start+slen*4))
4831 if(internal_branch(branch_regs[i].is32,ba[i]))
4832 {
4833 int t=(ba[i]-start)>>2;
4834 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4835 else *adj=ccadj[t];
4836 }
4837 else
4838 {
4839 *adj=0;
4840 }
4841 count=ccadj[i];
4842 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4843 // Idle loop
4844 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4845 idle=(int)out;
4846 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4847 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4848 jaddr=(int)out;
4849 emit_jmp(0);
4850 }
4851 else if(*adj==0||invert) {
4852 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4853 jaddr=(int)out;
4854 emit_jns(0);
4855 }
4856 else
4857 {
eeb1feeb 4858 emit_cmpimm(HOST_CCREG,-CLOCK_DIVIDER*(count+2));
57871462 4859 jaddr=(int)out;
4860 emit_jns(0);
4861 }
4862 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4863}
4864
4865void do_ccstub(int n)
4866{
4867 literal_pool(256);
4868 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4869 set_jump_target(stubs[n][1],(int)out);
4870 int i=stubs[n][4];
4871 if(stubs[n][6]==NULLDS) {
4872 // Delay slot instruction is nullified ("likely" branch)
4873 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4874 }
4875 else if(stubs[n][6]!=TAKEN) {
4876 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4877 }
4878 else {
4879 if(internal_branch(branch_regs[i].is32,ba[i]))
4880 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4881 }
4882 if(stubs[n][5]!=-1)
4883 {
4884 // Save PC as return address
4885 emit_movimm(stubs[n][5],EAX);
4886 emit_writeword(EAX,(int)&pcaddr);
4887 }
4888 else
4889 {
4890 // Return address depends on which way the branch goes
4891 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4892 {
4893 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4894 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4895 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4896 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4897 if(rs1[i]==0)
4898 {
4899 s1l=s2l;s1h=s2h;
4900 s2l=s2h=-1;
4901 }
4902 else if(rs2[i]==0)
4903 {
4904 s2l=s2h=-1;
4905 }
4906 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4907 s1h=s2h=-1;
4908 }
4909 assert(s1l>=0);
4910 #ifdef DESTRUCTIVE_WRITEBACK
4911 if(rs1[i]) {
4912 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4913 emit_loadreg(rs1[i],s1l);
4914 }
4915 else {
4916 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4917 emit_loadreg(rs2[i],s1l);
4918 }
4919 if(s2l>=0)
4920 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4921 emit_loadreg(rs2[i],s2l);
4922 #endif
4923 int hr=0;
5194fb95 4924 int addr=-1,alt=-1,ntaddr=-1;
57871462 4925 while(hr<HOST_REGS)
4926 {
4927 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4928 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4929 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4930 {
4931 addr=hr++;break;
4932 }
4933 hr++;
4934 }
4935 while(hr<HOST_REGS)
4936 {
4937 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4938 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4939 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4940 {
4941 alt=hr++;break;
4942 }
4943 hr++;
4944 }
4945 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4946 {
4947 while(hr<HOST_REGS)
4948 {
4949 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4950 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4951 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4952 {
4953 ntaddr=hr;break;
4954 }
4955 hr++;
4956 }
4957 assert(hr<HOST_REGS);
4958 }
4959 if((opcode[i]&0x2f)==4) // BEQ
4960 {
4961 #ifdef HAVE_CMOV_IMM
4962 if(s1h<0) {
4963 if(s2l>=0) emit_cmp(s1l,s2l);
4964 else emit_test(s1l,s1l);
4965 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4966 }
4967 else
4968 #endif
4969 {
4970 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4971 if(s1h>=0) {
4972 if(s2h>=0) emit_cmp(s1h,s2h);
4973 else emit_test(s1h,s1h);
4974 emit_cmovne_reg(alt,addr);
4975 }
4976 if(s2l>=0) emit_cmp(s1l,s2l);
4977 else emit_test(s1l,s1l);
4978 emit_cmovne_reg(alt,addr);
4979 }
4980 }
4981 if((opcode[i]&0x2f)==5) // BNE
4982 {
4983 #ifdef HAVE_CMOV_IMM
4984 if(s1h<0) {
4985 if(s2l>=0) emit_cmp(s1l,s2l);
4986 else emit_test(s1l,s1l);
4987 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4988 }
4989 else
4990 #endif
4991 {
4992 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4993 if(s1h>=0) {
4994 if(s2h>=0) emit_cmp(s1h,s2h);
4995 else emit_test(s1h,s1h);
4996 emit_cmovne_reg(alt,addr);
4997 }
4998 if(s2l>=0) emit_cmp(s1l,s2l);
4999 else emit_test(s1l,s1l);
5000 emit_cmovne_reg(alt,addr);
5001 }
5002 }
5003 if((opcode[i]&0x2f)==6) // BLEZ
5004 {
5005 //emit_movimm(ba[i],alt);
5006 //emit_movimm(start+i*4+8,addr);
5007 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5008 emit_cmpimm(s1l,1);
5009 if(s1h>=0) emit_mov(addr,ntaddr);
5010 emit_cmovl_reg(alt,addr);
5011 if(s1h>=0) {
5012 emit_test(s1h,s1h);
5013 emit_cmovne_reg(ntaddr,addr);
5014 emit_cmovs_reg(alt,addr);
5015 }
5016 }
5017 if((opcode[i]&0x2f)==7) // BGTZ
5018 {
5019 //emit_movimm(ba[i],addr);
5020 //emit_movimm(start+i*4+8,ntaddr);
5021 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5022 emit_cmpimm(s1l,1);
5023 if(s1h>=0) emit_mov(addr,alt);
5024 emit_cmovl_reg(ntaddr,addr);
5025 if(s1h>=0) {
5026 emit_test(s1h,s1h);
5027 emit_cmovne_reg(alt,addr);
5028 emit_cmovs_reg(ntaddr,addr);
5029 }
5030 }
5031 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5032 {
5033 //emit_movimm(ba[i],alt);
5034 //emit_movimm(start+i*4+8,addr);
5035 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5036 if(s1h>=0) emit_test(s1h,s1h);
5037 else emit_test(s1l,s1l);
5038 emit_cmovs_reg(alt,addr);
5039 }
5040 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5041 {
5042 //emit_movimm(ba[i],addr);
5043 //emit_movimm(start+i*4+8,alt);
5044 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5045 if(s1h>=0) emit_test(s1h,s1h);
5046 else emit_test(s1l,s1l);
5047 emit_cmovs_reg(alt,addr);
5048 }
5049 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5050 if(source[i]&0x10000) // BC1T
5051 {
5052 //emit_movimm(ba[i],alt);
5053 //emit_movimm(start+i*4+8,addr);
5054 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5055 emit_testimm(s1l,0x800000);
5056 emit_cmovne_reg(alt,addr);
5057 }
5058 else // BC1F
5059 {
5060 //emit_movimm(ba[i],addr);
5061 //emit_movimm(start+i*4+8,alt);
5062 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5063 emit_testimm(s1l,0x800000);
5064 emit_cmovne_reg(alt,addr);
5065 }
5066 }
5067 emit_writeword(addr,(int)&pcaddr);
5068 }
5069 else
5070 if(itype[i]==RJUMP)
5071 {
5072 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5073 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5074 r=get_reg(branch_regs[i].regmap,RTEMP);
5075 }
5076 emit_writeword(r,(int)&pcaddr);
5077 }
5078 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5079 }
5080 // Update cycle count
5081 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5082 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5083 emit_call((int)cc_interrupt);
5084 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5085 if(stubs[n][6]==TAKEN) {
5086 if(internal_branch(branch_regs[i].is32,ba[i]))
5087 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5088 else if(itype[i]==RJUMP) {
5089 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5090 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5091 else
5092 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5093 }
5094 }else if(stubs[n][6]==NOTTAKEN) {
5095 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5096 else load_all_regs(branch_regs[i].regmap);
5097 }else if(stubs[n][6]==NULLDS) {
5098 // Delay slot instruction is nullified ("likely" branch)
5099 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5100 else load_all_regs(regs[i].regmap);
5101 }else{
5102 load_all_regs(branch_regs[i].regmap);
5103 }
5104 emit_jmp(stubs[n][2]); // return address
5105
5106 /* This works but uses a lot of memory...
5107 emit_readword((int)&last_count,ECX);
5108 emit_add(HOST_CCREG,ECX,EAX);
5109 emit_writeword(EAX,(int)&Count);
5110 emit_call((int)gen_interupt);
5111 emit_readword((int)&Count,HOST_CCREG);
5112 emit_readword((int)&next_interupt,EAX);
5113 emit_readword((int)&pending_exception,EBX);
5114 emit_writeword(EAX,(int)&last_count);
5115 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5116 emit_test(EBX,EBX);
5117 int jne_instr=(int)out;
5118 emit_jne(0);
5119 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5120 load_all_regs(branch_regs[i].regmap);
5121 emit_jmp(stubs[n][2]); // return address
5122 set_jump_target(jne_instr,(int)out);
5123 emit_readword((int)&pcaddr,EAX);
5124 // Call get_addr_ht instead of doing the hash table here.
5125 // This code is executed infrequently and takes up a lot of space
5126 // so smaller is better.
5127 emit_storereg(CCREG,HOST_CCREG);
5128 emit_pushreg(EAX);
5129 emit_call((int)get_addr_ht);
5130 emit_loadreg(CCREG,HOST_CCREG);
5131 emit_addimm(ESP,4,ESP);
5132 emit_jmpreg(EAX);*/
5133}
5134
5135add_to_linker(int addr,int target,int ext)
5136{
5137 link_addr[linkcount][0]=addr;
5138 link_addr[linkcount][1]=target;
5139 link_addr[linkcount][2]=ext;
5140 linkcount++;
5141}
5142
5143void ujump_assemble(int i,struct regstat *i_regs)
5144{
5145 signed char *i_regmap=i_regs->regmap;
5146 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5147 address_generation(i+1,i_regs,regs[i].regmap_entry);
5148 #ifdef REG_PREFETCH
5149 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5150 if(rt1[i]==31&&temp>=0)
5151 {
5152 int return_address=start+i*4+8;
5153 if(get_reg(branch_regs[i].regmap,31)>0)
5154 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5155 }
5156 #endif
57871462 5157 if(rt1[i]==31) {
5158 int rt;
5159 unsigned int return_address;
57871462 5160 rt=get_reg(branch_regs[i].regmap,31);
5161 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5162 //assert(rt>=0);
5163 return_address=start+i*4+8;
5164 if(rt>=0) {
5165 #ifdef USE_MINI_HT
4ef8f67d 5166 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5167 int temp=-1; // note: must be ds-safe
57871462 5168 #ifdef HOST_TEMPREG
4ef8f67d 5169 temp=HOST_TEMPREG;
57871462 5170 #endif
5171 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5172 else emit_movimm(return_address,rt);
5173 }
5174 else
5175 #endif
5176 {
5177 #ifdef REG_PREFETCH
5178 if(temp>=0)
5179 {
5180 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5181 }
5182 #endif
5183 emit_movimm(return_address,rt); // PC into link register
5184 #ifdef IMM_PREFETCH
5185 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5186 #endif
5187 }
5188 }
5189 }
4ef8f67d 5190 ds_assemble(i+1,i_regs);
5191 uint64_t bc_unneeded=branch_regs[i].u;
5192 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5193 bc_unneeded|=1|(1LL<<rt1[i]);
5194 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5195 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5196 bc_unneeded,bc_unneeded_upper);
5197 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
57871462 5198 int cc,adj;
5199 cc=get_reg(branch_regs[i].regmap,CCREG);
5200 assert(cc==HOST_CCREG);
5201 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5202 #ifdef REG_PREFETCH
5203 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5204 #endif
5205 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5206 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5207 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5208 if(internal_branch(branch_regs[i].is32,ba[i]))
5209 assem_debug("branch: internal\n");
5210 else
5211 assem_debug("branch: external\n");
5212 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5213 ds_assemble_entry(i);
5214 }
5215 else {
5216 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5217 emit_jmp(0);
5218 }
5219}
5220
5221void rjump_assemble(int i,struct regstat *i_regs)
5222{
5223 signed char *i_regmap=i_regs->regmap;
5224 int temp;
5225 int rs,cc,adj;
5226 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5227 assert(rs>=0);
5228 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5229 // Delay slot abuse, make a copy of the branch address register
5230 temp=get_reg(branch_regs[i].regmap,RTEMP);
5231 assert(temp>=0);
5232 assert(regs[i].regmap[temp]==RTEMP);
5233 emit_mov(rs,temp);
5234 rs=temp;
5235 }
5236 address_generation(i+1,i_regs,regs[i].regmap_entry);
5237 #ifdef REG_PREFETCH
5238 if(rt1[i]==31)
5239 {
5240 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5241 int return_address=start+i*4+8;
5242 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5243 }
5244 }
5245 #endif
5246 #ifdef USE_MINI_HT
5247 if(rs1[i]==31) {
5248 int rh=get_reg(regs[i].regmap,RHASH);
5249 if(rh>=0) do_preload_rhash(rh);
5250 }
5251 #endif
5252 ds_assemble(i+1,i_regs);
5253 uint64_t bc_unneeded=branch_regs[i].u;
5254 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5255 bc_unneeded|=1|(1LL<<rt1[i]);
5256 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5257 bc_unneeded&=~(1LL<<rs1[i]);
5258 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5259 bc_unneeded,bc_unneeded_upper);
5260 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5067f341 5261 if(rt1[i]!=0) {
57871462 5262 int rt,return_address;
5067f341 5263 assert(rt1[i+1]!=rt1[i]);
5264 assert(rt2[i+1]!=rt1[i]);
5265 rt=get_reg(branch_regs[i].regmap,rt1[i]);
57871462 5266 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5267 assert(rt>=0);
5268 return_address=start+i*4+8;
5269 #ifdef REG_PREFETCH
5270 if(temp>=0)
5271 {
5272 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5273 }
5274 #endif
5275 emit_movimm(return_address,rt); // PC into link register
5276 #ifdef IMM_PREFETCH
5277 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5278 #endif
5279 }
5280 cc=get_reg(branch_regs[i].regmap,CCREG);
5281 assert(cc==HOST_CCREG);
5282 #ifdef USE_MINI_HT
5283 int rh=get_reg(branch_regs[i].regmap,RHASH);
5284 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5285 if(rs1[i]==31) {
5286 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5287 do_preload_rhtbl(ht);
5288 do_rhash(rs,rh);
5289 }
5290 #endif
5291 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5292 #ifdef DESTRUCTIVE_WRITEBACK
5293 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5294 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5295 emit_loadreg(rs1[i],rs);
5296 }
5297 }
5298 #endif
5299 #ifdef REG_PREFETCH
5300 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5301 #endif
5302 #ifdef USE_MINI_HT
5303 if(rs1[i]==31) {
5304 do_miniht_load(ht,rh);
5305 }
5306 #endif
5307 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5308 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5309 //assert(adj==0);
5310 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5311 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5312 emit_jns(0);
5313 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5314 #ifdef USE_MINI_HT
5315 if(rs1[i]==31) {
5316 do_miniht_jump(rs,rh,ht);
5317 }
5318 else
5319 #endif
5320 {
5321 //if(rs!=EAX) emit_mov(rs,EAX);
5322 //emit_jmp((int)jump_vaddr_eax);
5323 emit_jmp(jump_vaddr_reg[rs]);
5324 }
5325 /* Check hash table
5326 temp=!rs;
5327 emit_mov(rs,temp);
5328 emit_shrimm(rs,16,rs);
5329 emit_xor(temp,rs,rs);
5330 emit_movzwl_reg(rs,rs);
5331 emit_shlimm(rs,4,rs);
5332 emit_cmpmem_indexed((int)hash_table,rs,temp);
5333 emit_jne((int)out+14);
5334 emit_readword_indexed((int)hash_table+4,rs,rs);
5335 emit_jmpreg(rs);
5336 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5337 emit_addimm_no_flags(8,rs);
5338 emit_jeq((int)out-17);
5339 // No hit on hash table, call compiler
5340 emit_pushreg(temp);
5341//DEBUG >
5342#ifdef DEBUG_CYCLE_COUNT
5343 emit_readword((int)&last_count,ECX);
5344 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5345 emit_readword((int)&next_interupt,ECX);
5346 emit_writeword(HOST_CCREG,(int)&Count);
5347 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5348 emit_writeword(ECX,(int)&last_count);
5349#endif
5350//DEBUG <
5351 emit_storereg(CCREG,HOST_CCREG);
5352 emit_call((int)get_addr);
5353 emit_loadreg(CCREG,HOST_CCREG);
5354 emit_addimm(ESP,4,ESP);
5355 emit_jmpreg(EAX);*/
5356 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5357 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5358 #endif
5359}
5360
5361void cjump_assemble(int i,struct regstat *i_regs)
5362{
5363 signed char *i_regmap=i_regs->regmap;
5364 int cc;
5365 int match;
5366 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5367 assem_debug("match=%d\n",match);
5368 int s1h,s1l,s2h,s2l;
5369 int prev_cop1_usable=cop1_usable;
5370 int unconditional=0,nop=0;
5371 int only32=0;
57871462 5372 int invert=0;
5373 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5374 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5375 if(!match) invert=1;
5376 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5377 if(i>(ba[i]-start)>>2) invert=1;
5378 #endif
e1190b87 5379
5380 if(ooo[i]) {
57871462 5381 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5382 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5383 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5384 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5385 }
5386 else {
5387 s1l=get_reg(i_regmap,rs1[i]);
5388 s1h=get_reg(i_regmap,rs1[i]|64);
5389 s2l=get_reg(i_regmap,rs2[i]);
5390 s2h=get_reg(i_regmap,rs2[i]|64);
5391 }
5392 if(rs1[i]==0&&rs2[i]==0)
5393 {
5394 if(opcode[i]&1) nop=1;
5395 else unconditional=1;
5396 //assert(opcode[i]!=5);
5397 //assert(opcode[i]!=7);
5398 //assert(opcode[i]!=0x15);
5399 //assert(opcode[i]!=0x17);
5400 }
5401 else if(rs1[i]==0)
5402 {
5403 s1l=s2l;s1h=s2h;
5404 s2l=s2h=-1;
5405 only32=(regs[i].was32>>rs2[i])&1;
5406 }
5407 else if(rs2[i]==0)
5408 {
5409 s2l=s2h=-1;
5410 only32=(regs[i].was32>>rs1[i])&1;
5411 }
5412 else {
5413 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5414 }
5415
e1190b87 5416 if(ooo[i]) {
57871462 5417 // Out of order execution (delay slot first)
5418 //printf("OOOE\n");
5419 address_generation(i+1,i_regs,regs[i].regmap_entry);
5420 ds_assemble(i+1,i_regs);
5421 int adj;
5422 uint64_t bc_unneeded=branch_regs[i].u;
5423 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5424 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5425 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5426 bc_unneeded|=1;
5427 bc_unneeded_upper|=1;
5428 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5429 bc_unneeded,bc_unneeded_upper);
5430 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5431 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5432 cc=get_reg(branch_regs[i].regmap,CCREG);
5433 assert(cc==HOST_CCREG);
5434 if(unconditional)
5435 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5436 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5437 //assem_debug("cycle count (adj)\n");
5438 if(unconditional) {
5439 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5440 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5441 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5442 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5443 if(internal)
5444 assem_debug("branch: internal\n");
5445 else
5446 assem_debug("branch: external\n");
5447 if(internal&&is_ds[(ba[i]-start)>>2]) {
5448 ds_assemble_entry(i);
5449 }
5450 else {
5451 add_to_linker((int)out,ba[i],internal);
5452 emit_jmp(0);
5453 }
5454 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5455 if(((u_int)out)&7) emit_addnop(0);
5456 #endif
5457 }
5458 }
5459 else if(nop) {
5460 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5461 int jaddr=(int)out;
5462 emit_jns(0);
5463 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5464 }
5465 else {
5466 int taken=0,nottaken=0,nottaken1=0;
5467 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5468 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5469 if(!only32)
5470 {
5471 assert(s1h>=0);
5472 if(opcode[i]==4) // BEQ
5473 {
5474 if(s2h>=0) emit_cmp(s1h,s2h);
5475 else emit_test(s1h,s1h);
5476 nottaken1=(int)out;
5477 emit_jne(1);
5478 }
5479 if(opcode[i]==5) // BNE
5480 {
5481 if(s2h>=0) emit_cmp(s1h,s2h);
5482 else emit_test(s1h,s1h);
5483 if(invert) taken=(int)out;
5484 else add_to_linker((int)out,ba[i],internal);
5485 emit_jne(0);
5486 }
5487 if(opcode[i]==6) // BLEZ
5488 {
5489 emit_test(s1h,s1h);
5490 if(invert) taken=(int)out;
5491 else add_to_linker((int)out,ba[i],internal);
5492 emit_js(0);
5493 nottaken1=(int)out;
5494 emit_jne(1);
5495 }
5496 if(opcode[i]==7) // BGTZ
5497 {
5498 emit_test(s1h,s1h);
5499 nottaken1=(int)out;
5500 emit_js(1);
5501 if(invert) taken=(int)out;
5502 else add_to_linker((int)out,ba[i],internal);
5503 emit_jne(0);
5504 }
5505 } // if(!only32)
5506
5507 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5508 assert(s1l>=0);
5509 if(opcode[i]==4) // BEQ
5510 {
5511 if(s2l>=0) emit_cmp(s1l,s2l);
5512 else emit_test(s1l,s1l);
5513 if(invert){
5514 nottaken=(int)out;
5515 emit_jne(1);
5516 }else{
5517 add_to_linker((int)out,ba[i],internal);
5518 emit_jeq(0);
5519 }
5520 }
5521 if(opcode[i]==5) // BNE
5522 {
5523 if(s2l>=0) emit_cmp(s1l,s2l);
5524 else emit_test(s1l,s1l);
5525 if(invert){
5526 nottaken=(int)out;
5527 emit_jeq(1);
5528 }else{
5529 add_to_linker((int)out,ba[i],internal);
5530 emit_jne(0);
5531 }
5532 }
5533 if(opcode[i]==6) // BLEZ
5534 {
5535 emit_cmpimm(s1l,1);
5536 if(invert){
5537 nottaken=(int)out;
5538 emit_jge(1);
5539 }else{
5540 add_to_linker((int)out,ba[i],internal);
5541 emit_jl(0);
5542 }
5543 }
5544 if(opcode[i]==7) // BGTZ
5545 {
5546 emit_cmpimm(s1l,1);
5547 if(invert){
5548 nottaken=(int)out;
5549 emit_jl(1);
5550 }else{
5551 add_to_linker((int)out,ba[i],internal);
5552 emit_jge(0);
5553 }
5554 }
5555 if(invert) {
5556 if(taken) set_jump_target(taken,(int)out);
5557 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5558 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5559 if(adj) {
5560 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5561 add_to_linker((int)out,ba[i],internal);
5562 }else{
5563 emit_addnop(13);
5564 add_to_linker((int)out,ba[i],internal*2);
5565 }
5566 emit_jmp(0);
5567 }else
5568 #endif
5569 {
5570 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5571 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5572 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5573 if(internal)
5574 assem_debug("branch: internal\n");
5575 else
5576 assem_debug("branch: external\n");
5577 if(internal&&is_ds[(ba[i]-start)>>2]) {
5578 ds_assemble_entry(i);
5579 }
5580 else {
5581 add_to_linker((int)out,ba[i],internal);
5582 emit_jmp(0);
5583 }
5584 }
5585 set_jump_target(nottaken,(int)out);
5586 }
5587
5588 if(nottaken1) set_jump_target(nottaken1,(int)out);
5589 if(adj) {
5590 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5591 }
5592 } // (!unconditional)
5593 } // if(ooo)
5594 else
5595 {
5596 // In-order execution (branch first)
5597 //if(likely[i]) printf("IOL\n");
5598 //else
5599 //printf("IOE\n");
5600 int taken=0,nottaken=0,nottaken1=0;
5601 if(!unconditional&&!nop) {
5602 if(!only32)
5603 {
5604 assert(s1h>=0);
5605 if((opcode[i]&0x2f)==4) // BEQ
5606 {
5607 if(s2h>=0) emit_cmp(s1h,s2h);
5608 else emit_test(s1h,s1h);
5609 nottaken1=(int)out;
5610 emit_jne(2);
5611 }
5612 if((opcode[i]&0x2f)==5) // BNE
5613 {
5614 if(s2h>=0) emit_cmp(s1h,s2h);
5615 else emit_test(s1h,s1h);
5616 taken=(int)out;
5617 emit_jne(1);
5618 }
5619 if((opcode[i]&0x2f)==6) // BLEZ
5620 {
5621 emit_test(s1h,s1h);
5622 taken=(int)out;
5623 emit_js(1);
5624 nottaken1=(int)out;
5625 emit_jne(2);
5626 }
5627 if((opcode[i]&0x2f)==7) // BGTZ
5628 {
5629 emit_test(s1h,s1h);
5630 nottaken1=(int)out;
5631 emit_js(2);
5632 taken=(int)out;
5633 emit_jne(1);
5634 }
5635 } // if(!only32)
5636
5637 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5638 assert(s1l>=0);
5639 if((opcode[i]&0x2f)==4) // BEQ
5640 {
5641 if(s2l>=0) emit_cmp(s1l,s2l);
5642 else emit_test(s1l,s1l);
5643 nottaken=(int)out;
5644 emit_jne(2);
5645 }
5646 if((opcode[i]&0x2f)==5) // BNE
5647 {
5648 if(s2l>=0) emit_cmp(s1l,s2l);
5649 else emit_test(s1l,s1l);
5650 nottaken=(int)out;
5651 emit_jeq(2);
5652 }
5653 if((opcode[i]&0x2f)==6) // BLEZ
5654 {
5655 emit_cmpimm(s1l,1);
5656 nottaken=(int)out;
5657 emit_jge(2);
5658 }
5659 if((opcode[i]&0x2f)==7) // BGTZ
5660 {
5661 emit_cmpimm(s1l,1);
5662 nottaken=(int)out;
5663 emit_jl(2);
5664 }
5665 } // if(!unconditional)
5666 int adj;
5667 uint64_t ds_unneeded=branch_regs[i].u;
5668 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5669 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5670 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5671 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5672 ds_unneeded|=1;
5673 ds_unneeded_upper|=1;
5674 // branch taken
5675 if(!nop) {
5676 if(taken) set_jump_target(taken,(int)out);
5677 assem_debug("1:\n");
5678 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5679 ds_unneeded,ds_unneeded_upper);
5680 // load regs
5681 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5682 address_generation(i+1,&branch_regs[i],0);
5683 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5684 ds_assemble(i+1,&branch_regs[i]);
5685 cc=get_reg(branch_regs[i].regmap,CCREG);
5686 if(cc==-1) {
5687 emit_loadreg(CCREG,cc=HOST_CCREG);
5688 // CHECK: Is the following instruction (fall thru) allocated ok?
5689 }
5690 assert(cc==HOST_CCREG);
5691 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5692 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5693 assem_debug("cycle count (adj)\n");
5694 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5695 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5696 if(internal)
5697 assem_debug("branch: internal\n");
5698 else
5699 assem_debug("branch: external\n");
5700 if(internal&&is_ds[(ba[i]-start)>>2]) {
5701 ds_assemble_entry(i);
5702 }
5703 else {
5704 add_to_linker((int)out,ba[i],internal);
5705 emit_jmp(0);
5706 }
5707 }
5708 // branch not taken
5709 cop1_usable=prev_cop1_usable;
5710 if(!unconditional) {
5711 if(nottaken1) set_jump_target(nottaken1,(int)out);
5712 set_jump_target(nottaken,(int)out);
5713 assem_debug("2:\n");
5714 if(!likely[i]) {
5715 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5716 ds_unneeded,ds_unneeded_upper);
5717 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5718 address_generation(i+1,&branch_regs[i],0);
5719 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5720 ds_assemble(i+1,&branch_regs[i]);
5721 }
5722 cc=get_reg(branch_regs[i].regmap,CCREG);
5723 if(cc==-1&&!likely[i]) {
5724 // Cycle count isn't in a register, temporarily load it then write it out
5725 emit_loadreg(CCREG,HOST_CCREG);
5726 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5727 int jaddr=(int)out;
5728 emit_jns(0);
5729 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5730 emit_storereg(CCREG,HOST_CCREG);
5731 }
5732 else{
5733 cc=get_reg(i_regmap,CCREG);
5734 assert(cc==HOST_CCREG);
5735 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5736 int jaddr=(int)out;
5737 emit_jns(0);
5738 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5739 }
5740 }
5741 }
5742}
5743
5744void sjump_assemble(int i,struct regstat *i_regs)
5745{
5746 signed char *i_regmap=i_regs->regmap;
5747 int cc;
5748 int match;
5749 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5750 assem_debug("smatch=%d\n",match);
5751 int s1h,s1l;
5752 int prev_cop1_usable=cop1_usable;
5753 int unconditional=0,nevertaken=0;
5754 int only32=0;
57871462 5755 int invert=0;
5756 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5757 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5758 if(!match) invert=1;
5759 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5760 if(i>(ba[i]-start)>>2) invert=1;
5761 #endif
5762
5763 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
df894a3a 5764 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
57871462 5765
e1190b87 5766 if(ooo[i]) {
57871462 5767 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5768 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5769 }
5770 else {
5771 s1l=get_reg(i_regmap,rs1[i]);
5772 s1h=get_reg(i_regmap,rs1[i]|64);
5773 }
5774 if(rs1[i]==0)
5775 {
5776 if(opcode2[i]&1) unconditional=1;
5777 else nevertaken=1;
5778 // These are never taken (r0 is never less than zero)
5779 //assert(opcode2[i]!=0);
5780 //assert(opcode2[i]!=2);
5781 //assert(opcode2[i]!=0x10);
5782 //assert(opcode2[i]!=0x12);
5783 }
5784 else {
5785 only32=(regs[i].was32>>rs1[i])&1;
5786 }
5787
e1190b87 5788 if(ooo[i]) {
57871462 5789 // Out of order execution (delay slot first)
5790 //printf("OOOE\n");
5791 address_generation(i+1,i_regs,regs[i].regmap_entry);
5792 ds_assemble(i+1,i_regs);
5793 int adj;
5794 uint64_t bc_unneeded=branch_regs[i].u;
5795 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5796 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5797 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5798 bc_unneeded|=1;
5799 bc_unneeded_upper|=1;
5800 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5801 bc_unneeded,bc_unneeded_upper);
5802 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5803 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5804 if(rt1[i]==31) {
5805 int rt,return_address;
57871462 5806 rt=get_reg(branch_regs[i].regmap,31);
5807 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5808 if(rt>=0) {
5809 // Save the PC even if the branch is not taken
5810 return_address=start+i*4+8;
5811 emit_movimm(return_address,rt); // PC into link register
5812 #ifdef IMM_PREFETCH
5813 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5814 #endif
5815 }
5816 }
5817 cc=get_reg(branch_regs[i].regmap,CCREG);
5818 assert(cc==HOST_CCREG);
5819 if(unconditional)
5820 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5821 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5822 assem_debug("cycle count (adj)\n");
5823 if(unconditional) {
5824 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5825 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5826 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5827 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5828 if(internal)
5829 assem_debug("branch: internal\n");
5830 else
5831 assem_debug("branch: external\n");
5832 if(internal&&is_ds[(ba[i]-start)>>2]) {
5833 ds_assemble_entry(i);
5834 }
5835 else {
5836 add_to_linker((int)out,ba[i],internal);
5837 emit_jmp(0);
5838 }
5839 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5840 if(((u_int)out)&7) emit_addnop(0);
5841 #endif
5842 }
5843 }
5844 else if(nevertaken) {
5845 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5846 int jaddr=(int)out;
5847 emit_jns(0);
5848 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5849 }
5850 else {
5851 int nottaken=0;
5852 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5853 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5854 if(!only32)
5855 {
5856 assert(s1h>=0);
df894a3a 5857 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5858 {
5859 emit_test(s1h,s1h);
5860 if(invert){
5861 nottaken=(int)out;
5862 emit_jns(1);
5863 }else{
5864 add_to_linker((int)out,ba[i],internal);
5865 emit_js(0);
5866 }
5867 }
df894a3a 5868 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5869 {
5870 emit_test(s1h,s1h);
5871 if(invert){
5872 nottaken=(int)out;
5873 emit_js(1);
5874 }else{
5875 add_to_linker((int)out,ba[i],internal);
5876 emit_jns(0);
5877 }
5878 }
5879 } // if(!only32)
5880 else
5881 {
5882 assert(s1l>=0);
df894a3a 5883 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5884 {
5885 emit_test(s1l,s1l);
5886 if(invert){
5887 nottaken=(int)out;
5888 emit_jns(1);
5889 }else{
5890 add_to_linker((int)out,ba[i],internal);
5891 emit_js(0);
5892 }
5893 }
df894a3a 5894 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5895 {
5896 emit_test(s1l,s1l);
5897 if(invert){
5898 nottaken=(int)out;
5899 emit_js(1);
5900 }else{
5901 add_to_linker((int)out,ba[i],internal);
5902 emit_jns(0);
5903 }
5904 }
5905 } // if(!only32)
5906
5907 if(invert) {
5908 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5909 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5910 if(adj) {
5911 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5912 add_to_linker((int)out,ba[i],internal);
5913 }else{
5914 emit_addnop(13);
5915 add_to_linker((int)out,ba[i],internal*2);
5916 }
5917 emit_jmp(0);
5918 }else
5919 #endif
5920 {
5921 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5922 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5923 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5924 if(internal)
5925 assem_debug("branch: internal\n");
5926 else
5927 assem_debug("branch: external\n");
5928 if(internal&&is_ds[(ba[i]-start)>>2]) {
5929 ds_assemble_entry(i);
5930 }
5931 else {
5932 add_to_linker((int)out,ba[i],internal);
5933 emit_jmp(0);
5934 }
5935 }
5936 set_jump_target(nottaken,(int)out);
5937 }
5938
5939 if(adj) {
5940 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5941 }
5942 } // (!unconditional)
5943 } // if(ooo)
5944 else
5945 {
5946 // In-order execution (branch first)
5947 //printf("IOE\n");
5948 int nottaken=0;
a6491170 5949 if(rt1[i]==31) {
5950 int rt,return_address;
a6491170 5951 rt=get_reg(branch_regs[i].regmap,31);
5952 if(rt>=0) {
5953 // Save the PC even if the branch is not taken
5954 return_address=start+i*4+8;
5955 emit_movimm(return_address,rt); // PC into link register
5956 #ifdef IMM_PREFETCH
5957 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5958 #endif
5959 }
5960 }
57871462 5961 if(!unconditional) {
5962 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5963 if(!only32)
5964 {
5965 assert(s1h>=0);
a6491170 5966 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5967 {
5968 emit_test(s1h,s1h);
5969 nottaken=(int)out;
5970 emit_jns(1);
5971 }
a6491170 5972 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5973 {
5974 emit_test(s1h,s1h);
5975 nottaken=(int)out;
5976 emit_js(1);
5977 }
5978 } // if(!only32)
5979 else
5980 {
5981 assert(s1l>=0);
a6491170 5982 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5983 {
5984 emit_test(s1l,s1l);
5985 nottaken=(int)out;
5986 emit_jns(1);
5987 }
a6491170 5988 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5989 {
5990 emit_test(s1l,s1l);
5991 nottaken=(int)out;
5992 emit_js(1);
5993 }
5994 }
5995 } // if(!unconditional)
5996 int adj;
5997 uint64_t ds_unneeded=branch_regs[i].u;
5998 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5999 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6000 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6001 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6002 ds_unneeded|=1;
6003 ds_unneeded_upper|=1;
6004 // branch taken
6005 if(!nevertaken) {
6006 //assem_debug("1:\n");
6007 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6008 ds_unneeded,ds_unneeded_upper);
6009 // load regs
6010 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6011 address_generation(i+1,&branch_regs[i],0);
6012 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6013 ds_assemble(i+1,&branch_regs[i]);
6014 cc=get_reg(branch_regs[i].regmap,CCREG);
6015 if(cc==-1) {
6016 emit_loadreg(CCREG,cc=HOST_CCREG);
6017 // CHECK: Is the following instruction (fall thru) allocated ok?
6018 }
6019 assert(cc==HOST_CCREG);
6020 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6021 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6022 assem_debug("cycle count (adj)\n");
6023 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6024 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6025 if(internal)
6026 assem_debug("branch: internal\n");
6027 else
6028 assem_debug("branch: external\n");
6029 if(internal&&is_ds[(ba[i]-start)>>2]) {
6030 ds_assemble_entry(i);
6031 }
6032 else {
6033 add_to_linker((int)out,ba[i],internal);
6034 emit_jmp(0);
6035 }
6036 }
6037 // branch not taken
6038 cop1_usable=prev_cop1_usable;
6039 if(!unconditional) {
6040 set_jump_target(nottaken,(int)out);
6041 assem_debug("1:\n");
6042 if(!likely[i]) {
6043 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6044 ds_unneeded,ds_unneeded_upper);
6045 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6046 address_generation(i+1,&branch_regs[i],0);
6047 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6048 ds_assemble(i+1,&branch_regs[i]);
6049 }
6050 cc=get_reg(branch_regs[i].regmap,CCREG);
6051 if(cc==-1&&!likely[i]) {
6052 // Cycle count isn't in a register, temporarily load it then write it out
6053 emit_loadreg(CCREG,HOST_CCREG);
6054 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6055 int jaddr=(int)out;
6056 emit_jns(0);
6057 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6058 emit_storereg(CCREG,HOST_CCREG);
6059 }
6060 else{
6061 cc=get_reg(i_regmap,CCREG);
6062 assert(cc==HOST_CCREG);
6063 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6064 int jaddr=(int)out;
6065 emit_jns(0);
6066 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6067 }
6068 }
6069 }
6070}
6071
6072void fjump_assemble(int i,struct regstat *i_regs)
6073{
6074 signed char *i_regmap=i_regs->regmap;
6075 int cc;
6076 int match;
6077 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6078 assem_debug("fmatch=%d\n",match);
6079 int fs,cs;
6080 int eaddr;
57871462 6081 int invert=0;
6082 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6083 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 6084 if(!match) invert=1;
6085 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6086 if(i>(ba[i]-start)>>2) invert=1;
6087 #endif
6088
e1190b87 6089 if(ooo[i]) {
57871462 6090 fs=get_reg(branch_regs[i].regmap,FSREG);
6091 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6092 }
6093 else {
6094 fs=get_reg(i_regmap,FSREG);
6095 }
6096
6097 // Check cop1 unusable
6098 if(!cop1_usable) {
6099 cs=get_reg(i_regmap,CSREG);
6100 assert(cs>=0);
6101 emit_testimm(cs,0x20000000);
6102 eaddr=(int)out;
6103 emit_jeq(0);
6104 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6105 cop1_usable=1;
6106 }
6107
e1190b87 6108 if(ooo[i]) {
57871462 6109 // Out of order execution (delay slot first)
6110 //printf("OOOE\n");
6111 ds_assemble(i+1,i_regs);
6112 int adj;
6113 uint64_t bc_unneeded=branch_regs[i].u;
6114 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6115 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6116 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6117 bc_unneeded|=1;
6118 bc_unneeded_upper|=1;
6119 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6120 bc_unneeded,bc_unneeded_upper);
6121 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6122 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6123 cc=get_reg(branch_regs[i].regmap,CCREG);
6124 assert(cc==HOST_CCREG);
6125 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6126 assem_debug("cycle count (adj)\n");
6127 if(1) {
6128 int nottaken=0;
6129 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6130 if(1) {
6131 assert(fs>=0);
6132 emit_testimm(fs,0x800000);
6133 if(source[i]&0x10000) // BC1T
6134 {
6135 if(invert){
6136 nottaken=(int)out;
6137 emit_jeq(1);
6138 }else{
6139 add_to_linker((int)out,ba[i],internal);
6140 emit_jne(0);
6141 }
6142 }
6143 else // BC1F
6144 if(invert){
6145 nottaken=(int)out;
6146 emit_jne(1);
6147 }else{
6148 add_to_linker((int)out,ba[i],internal);
6149 emit_jeq(0);
6150 }
6151 {
6152 }
6153 } // if(!only32)
6154
6155 if(invert) {
6156 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6157 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6158 else if(match) emit_addnop(13);
6159 #endif
6160 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6161 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6162 if(internal)
6163 assem_debug("branch: internal\n");
6164 else
6165 assem_debug("branch: external\n");
6166 if(internal&&is_ds[(ba[i]-start)>>2]) {
6167 ds_assemble_entry(i);
6168 }
6169 else {
6170 add_to_linker((int)out,ba[i],internal);
6171 emit_jmp(0);
6172 }
6173 set_jump_target(nottaken,(int)out);
6174 }
6175
6176 if(adj) {
6177 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6178 }
6179 } // (!unconditional)
6180 } // if(ooo)
6181 else
6182 {
6183 // In-order execution (branch first)
6184 //printf("IOE\n");
6185 int nottaken=0;
6186 if(1) {
6187 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6188 if(1) {
6189 assert(fs>=0);
6190 emit_testimm(fs,0x800000);
6191 if(source[i]&0x10000) // BC1T
6192 {
6193 nottaken=(int)out;
6194 emit_jeq(1);
6195 }
6196 else // BC1F
6197 {
6198 nottaken=(int)out;
6199 emit_jne(1);
6200 }
6201 }
6202 } // if(!unconditional)
6203 int adj;
6204 uint64_t ds_unneeded=branch_regs[i].u;
6205 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6206 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6207 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6208 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6209 ds_unneeded|=1;
6210 ds_unneeded_upper|=1;
6211 // branch taken
6212 //assem_debug("1:\n");
6213 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6214 ds_unneeded,ds_unneeded_upper);
6215 // load regs
6216 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6217 address_generation(i+1,&branch_regs[i],0);
6218 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6219 ds_assemble(i+1,&branch_regs[i]);
6220 cc=get_reg(branch_regs[i].regmap,CCREG);
6221 if(cc==-1) {
6222 emit_loadreg(CCREG,cc=HOST_CCREG);
6223 // CHECK: Is the following instruction (fall thru) allocated ok?
6224 }
6225 assert(cc==HOST_CCREG);
6226 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6227 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6228 assem_debug("cycle count (adj)\n");
6229 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6230 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6231 if(internal)
6232 assem_debug("branch: internal\n");
6233 else
6234 assem_debug("branch: external\n");
6235 if(internal&&is_ds[(ba[i]-start)>>2]) {
6236 ds_assemble_entry(i);
6237 }
6238 else {
6239 add_to_linker((int)out,ba[i],internal);
6240 emit_jmp(0);
6241 }
6242
6243 // branch not taken
6244 if(1) { // <- FIXME (don't need this)
6245 set_jump_target(nottaken,(int)out);
6246 assem_debug("1:\n");
6247 if(!likely[i]) {
6248 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6249 ds_unneeded,ds_unneeded_upper);
6250 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6251 address_generation(i+1,&branch_regs[i],0);
6252 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6253 ds_assemble(i+1,&branch_regs[i]);
6254 }
6255 cc=get_reg(branch_regs[i].regmap,CCREG);
6256 if(cc==-1&&!likely[i]) {
6257 // Cycle count isn't in a register, temporarily load it then write it out
6258 emit_loadreg(CCREG,HOST_CCREG);
6259 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6260 int jaddr=(int)out;
6261 emit_jns(0);
6262 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6263 emit_storereg(CCREG,HOST_CCREG);
6264 }
6265 else{
6266 cc=get_reg(i_regmap,CCREG);
6267 assert(cc==HOST_CCREG);
6268 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6269 int jaddr=(int)out;
6270 emit_jns(0);
6271 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6272 }
6273 }
6274 }
6275}
6276
6277static void pagespan_assemble(int i,struct regstat *i_regs)
6278{
6279 int s1l=get_reg(i_regs->regmap,rs1[i]);
6280 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6281 int s2l=get_reg(i_regs->regmap,rs2[i]);
6282 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6283 void *nt_branch=NULL;
6284 int taken=0;
6285 int nottaken=0;
6286 int unconditional=0;
6287 if(rs1[i]==0)
6288 {
6289 s1l=s2l;s1h=s2h;
6290 s2l=s2h=-1;
6291 }
6292 else if(rs2[i]==0)
6293 {
6294 s2l=s2h=-1;
6295 }
6296 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6297 s1h=s2h=-1;
6298 }
6299 int hr=0;
6300 int addr,alt,ntaddr;
6301 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6302 else {
6303 while(hr<HOST_REGS)
6304 {
6305 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6306 (i_regs->regmap[hr]&63)!=rs1[i] &&
6307 (i_regs->regmap[hr]&63)!=rs2[i] )
6308 {
6309 addr=hr++;break;
6310 }
6311 hr++;
6312 }
6313 }
6314 while(hr<HOST_REGS)
6315 {
6316 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6317 (i_regs->regmap[hr]&63)!=rs1[i] &&
6318 (i_regs->regmap[hr]&63)!=rs2[i] )
6319 {
6320 alt=hr++;break;
6321 }
6322 hr++;
6323 }
6324 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6325 {
6326 while(hr<HOST_REGS)
6327 {
6328 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6329 (i_regs->regmap[hr]&63)!=rs1[i] &&
6330 (i_regs->regmap[hr]&63)!=rs2[i] )
6331 {
6332 ntaddr=hr;break;
6333 }
6334 hr++;
6335 }
6336 }
6337 assert(hr<HOST_REGS);
6338 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6339 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6340 }
6341 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6342 if(opcode[i]==2) // J
6343 {
6344 unconditional=1;
6345 }
6346 if(opcode[i]==3) // JAL
6347 {
6348 // TODO: mini_ht
6349 int rt=get_reg(i_regs->regmap,31);
6350 emit_movimm(start+i*4+8,rt);
6351 unconditional=1;
6352 }
6353 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6354 {
6355 emit_mov(s1l,addr);
6356 if(opcode2[i]==9) // JALR
6357 {
5067f341 6358 int rt=get_reg(i_regs->regmap,rt1[i]);
57871462 6359 emit_movimm(start+i*4+8,rt);
6360 }
6361 }
6362 if((opcode[i]&0x3f)==4) // BEQ
6363 {
6364 if(rs1[i]==rs2[i])
6365 {
6366 unconditional=1;
6367 }
6368 else
6369 #ifdef HAVE_CMOV_IMM
6370 if(s1h<0) {
6371 if(s2l>=0) emit_cmp(s1l,s2l);
6372 else emit_test(s1l,s1l);
6373 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6374 }
6375 else
6376 #endif
6377 {
6378 assert(s1l>=0);
6379 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6380 if(s1h>=0) {
6381 if(s2h>=0) emit_cmp(s1h,s2h);
6382 else emit_test(s1h,s1h);
6383 emit_cmovne_reg(alt,addr);
6384 }
6385 if(s2l>=0) emit_cmp(s1l,s2l);
6386 else emit_test(s1l,s1l);
6387 emit_cmovne_reg(alt,addr);
6388 }
6389 }
6390 if((opcode[i]&0x3f)==5) // BNE
6391 {
6392 #ifdef HAVE_CMOV_IMM
6393 if(s1h<0) {
6394 if(s2l>=0) emit_cmp(s1l,s2l);
6395 else emit_test(s1l,s1l);
6396 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6397 }
6398 else
6399 #endif
6400 {
6401 assert(s1l>=0);
6402 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6403 if(s1h>=0) {
6404 if(s2h>=0) emit_cmp(s1h,s2h);
6405 else emit_test(s1h,s1h);
6406 emit_cmovne_reg(alt,addr);
6407 }
6408 if(s2l>=0) emit_cmp(s1l,s2l);
6409 else emit_test(s1l,s1l);
6410 emit_cmovne_reg(alt,addr);
6411 }
6412 }
6413 if((opcode[i]&0x3f)==0x14) // BEQL
6414 {
6415 if(s1h>=0) {
6416 if(s2h>=0) emit_cmp(s1h,s2h);
6417 else emit_test(s1h,s1h);
6418 nottaken=(int)out;
6419 emit_jne(0);
6420 }
6421 if(s2l>=0) emit_cmp(s1l,s2l);
6422 else emit_test(s1l,s1l);
6423 if(nottaken) set_jump_target(nottaken,(int)out);
6424 nottaken=(int)out;
6425 emit_jne(0);
6426 }
6427 if((opcode[i]&0x3f)==0x15) // BNEL
6428 {
6429 if(s1h>=0) {
6430 if(s2h>=0) emit_cmp(s1h,s2h);
6431 else emit_test(s1h,s1h);
6432 taken=(int)out;
6433 emit_jne(0);
6434 }
6435 if(s2l>=0) emit_cmp(s1l,s2l);
6436 else emit_test(s1l,s1l);
6437 nottaken=(int)out;
6438 emit_jeq(0);
6439 if(taken) set_jump_target(taken,(int)out);
6440 }
6441 if((opcode[i]&0x3f)==6) // BLEZ
6442 {
6443 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6444 emit_cmpimm(s1l,1);
6445 if(s1h>=0) emit_mov(addr,ntaddr);
6446 emit_cmovl_reg(alt,addr);
6447 if(s1h>=0) {
6448 emit_test(s1h,s1h);
6449 emit_cmovne_reg(ntaddr,addr);
6450 emit_cmovs_reg(alt,addr);
6451 }
6452 }
6453 if((opcode[i]&0x3f)==7) // BGTZ
6454 {
6455 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6456 emit_cmpimm(s1l,1);
6457 if(s1h>=0) emit_mov(addr,alt);
6458 emit_cmovl_reg(ntaddr,addr);
6459 if(s1h>=0) {
6460 emit_test(s1h,s1h);
6461 emit_cmovne_reg(alt,addr);
6462 emit_cmovs_reg(ntaddr,addr);
6463 }
6464 }
6465 if((opcode[i]&0x3f)==0x16) // BLEZL
6466 {
6467 assert((opcode[i]&0x3f)!=0x16);
6468 }
6469 if((opcode[i]&0x3f)==0x17) // BGTZL
6470 {
6471 assert((opcode[i]&0x3f)!=0x17);
6472 }
6473 assert(opcode[i]!=1); // BLTZ/BGEZ
6474
6475 //FIXME: Check CSREG
6476 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6477 if((source[i]&0x30000)==0) // BC1F
6478 {
6479 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6480 emit_testimm(s1l,0x800000);
6481 emit_cmovne_reg(alt,addr);
6482 }
6483 if((source[i]&0x30000)==0x10000) // BC1T
6484 {
6485 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6486 emit_testimm(s1l,0x800000);
6487 emit_cmovne_reg(alt,addr);
6488 }
6489 if((source[i]&0x30000)==0x20000) // BC1FL
6490 {
6491 emit_testimm(s1l,0x800000);
6492 nottaken=(int)out;
6493 emit_jne(0);
6494 }
6495 if((source[i]&0x30000)==0x30000) // BC1TL
6496 {
6497 emit_testimm(s1l,0x800000);
6498 nottaken=(int)out;
6499 emit_jeq(0);
6500 }
6501 }
6502
6503 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6504 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6505 if(likely[i]||unconditional)
6506 {
6507 emit_movimm(ba[i],HOST_BTREG);
6508 }
6509 else if(addr!=HOST_BTREG)
6510 {
6511 emit_mov(addr,HOST_BTREG);
6512 }
6513 void *branch_addr=out;
6514 emit_jmp(0);
6515 int target_addr=start+i*4+5;
6516 void *stub=out;
6517 void *compiled_target_addr=check_addr(target_addr);
6518 emit_extjump_ds((int)branch_addr,target_addr);
6519 if(compiled_target_addr) {
6520 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6521 add_link(target_addr,stub);
6522 }
6523 else set_jump_target((int)branch_addr,(int)stub);
6524 if(likely[i]) {
6525 // Not-taken path
6526 set_jump_target((int)nottaken,(int)out);
6527 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6528 void *branch_addr=out;
6529 emit_jmp(0);
6530 int target_addr=start+i*4+8;
6531 void *stub=out;
6532 void *compiled_target_addr=check_addr(target_addr);
6533 emit_extjump_ds((int)branch_addr,target_addr);
6534 if(compiled_target_addr) {
6535 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6536 add_link(target_addr,stub);
6537 }
6538 else set_jump_target((int)branch_addr,(int)stub);
6539 }
6540}
6541
6542// Assemble the delay slot for the above
6543static void pagespan_ds()
6544{
6545 assem_debug("initial delay slot:\n");
6546 u_int vaddr=start+1;
94d23bb9 6547 u_int page=get_page(vaddr);
6548 u_int vpage=get_vpage(vaddr);
57871462 6549 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6550 do_dirty_stub_ds();
6551 ll_add(jump_in+page,vaddr,(void *)out);
6552 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6553 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6554 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6555 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6556 emit_writeword(HOST_BTREG,(int)&branch_target);
6557 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6558 address_generation(0,&regs[0],regs[0].regmap_entry);
b9b61529 6559 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
57871462 6560 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6561 cop1_usable=0;
6562 is_delayslot=0;
6563 switch(itype[0]) {
6564 case ALU:
6565 alu_assemble(0,&regs[0]);break;
6566 case IMM16:
6567 imm16_assemble(0,&regs[0]);break;
6568 case SHIFT:
6569 shift_assemble(0,&regs[0]);break;
6570 case SHIFTIMM:
6571 shiftimm_assemble(0,&regs[0]);break;
6572 case LOAD:
6573 load_assemble(0,&regs[0]);break;
6574 case LOADLR:
6575 loadlr_assemble(0,&regs[0]);break;
6576 case STORE:
6577 store_assemble(0,&regs[0]);break;
6578 case STORELR:
6579 storelr_assemble(0,&regs[0]);break;
6580 case COP0:
6581 cop0_assemble(0,&regs[0]);break;
6582 case COP1:
6583 cop1_assemble(0,&regs[0]);break;
6584 case C1LS:
6585 c1ls_assemble(0,&regs[0]);break;
b9b61529 6586 case COP2:
6587 cop2_assemble(0,&regs[0]);break;
6588 case C2LS:
6589 c2ls_assemble(0,&regs[0]);break;
6590 case C2OP:
6591 c2op_assemble(0,&regs[0]);break;
57871462 6592 case FCONV:
6593 fconv_assemble(0,&regs[0]);break;
6594 case FLOAT:
6595 float_assemble(0,&regs[0]);break;
6596 case FCOMP:
6597 fcomp_assemble(0,&regs[0]);break;
6598 case MULTDIV:
6599 multdiv_assemble(0,&regs[0]);break;
6600 case MOV:
6601 mov_assemble(0,&regs[0]);break;
6602 case SYSCALL:
7139f3c8 6603 case HLECALL:
1e973cb0 6604 case INTCALL:
57871462 6605 case SPAN:
6606 case UJUMP:
6607 case RJUMP:
6608 case CJUMP:
6609 case SJUMP:
6610 case FJUMP:
6611 printf("Jump in the delay slot. This is probably a bug.\n");
6612 }
6613 int btaddr=get_reg(regs[0].regmap,BTREG);
6614 if(btaddr<0) {
6615 btaddr=get_reg(regs[0].regmap,-1);
6616 emit_readword((int)&branch_target,btaddr);
6617 }
6618 assert(btaddr!=HOST_CCREG);
6619 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6620#ifdef HOST_IMM8
6621 emit_movimm(start+4,HOST_TEMPREG);
6622 emit_cmp(btaddr,HOST_TEMPREG);
6623#else
6624 emit_cmpimm(btaddr,start+4);
6625#endif
6626 int branch=(int)out;
6627 emit_jeq(0);
6628 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6629 emit_jmp(jump_vaddr_reg[btaddr]);
6630 set_jump_target(branch,(int)out);
6631 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6632 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6633}
6634
6635// Basic liveness analysis for MIPS registers
6636void unneeded_registers(int istart,int iend,int r)
6637{
6638 int i;
6639 uint64_t u,uu,b,bu;
6640 uint64_t temp_u,temp_uu;
6641 uint64_t tdep;
6642 if(iend==slen-1) {
6643 u=1;uu=1;
6644 }else{
6645 u=unneeded_reg[iend+1];
6646 uu=unneeded_reg_upper[iend+1];
6647 u=1;uu=1;
6648 }
6649 for (i=iend;i>=istart;i--)
6650 {
6651 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6652 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6653 {
6654 // If subroutine call, flag return address as a possible branch target
6655 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6656
6657 if(ba[i]<start || ba[i]>=(start+slen*4))
6658 {
6659 // Branch out of this block, flush all regs
6660 u=1;
6661 uu=1;
6662 /* Hexagon hack
6663 if(itype[i]==UJUMP&&rt1[i]==31)
6664 {
6665 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6666 }
6667 if(itype[i]==RJUMP&&rs1[i]==31)
6668 {
6669 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6670 }
4cb76aa4 6671 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
57871462 6672 if(itype[i]==UJUMP&&rt1[i]==31)
6673 {
6674 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6675 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6676 }
6677 if(itype[i]==RJUMP&&rs1[i]==31)
6678 {
6679 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6680 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6681 }
6682 }*/
6683 branch_unneeded_reg[i]=u;
6684 branch_unneeded_reg_upper[i]=uu;
6685 // Merge in delay slot
6686 tdep=(~uu>>rt1[i+1])&1;
6687 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6688 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6689 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6690 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6691 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6692 u|=1;uu|=1;
6693 // If branch is "likely" (and conditional)
6694 // then we skip the delay slot on the fall-thru path
6695 if(likely[i]) {
6696 if(i<slen-1) {
6697 u&=unneeded_reg[i+2];
6698 uu&=unneeded_reg_upper[i+2];
6699 }
6700 else
6701 {
6702 u=1;
6703 uu=1;
6704 }
6705 }
6706 }
6707 else
6708 {
6709 // Internal branch, flag target
6710 bt[(ba[i]-start)>>2]=1;
6711 if(ba[i]<=start+i*4) {
6712 // Backward branch
6713 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6714 {
6715 // Unconditional branch
6716 temp_u=1;temp_uu=1;
6717 } else {
6718 // Conditional branch (not taken case)
6719 temp_u=unneeded_reg[i+2];
6720 temp_uu=unneeded_reg_upper[i+2];
6721 }
6722 // Merge in delay slot
6723 tdep=(~temp_uu>>rt1[i+1])&1;
6724 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6725 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6726 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6727 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6728 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6729 temp_u|=1;temp_uu|=1;
6730 // If branch is "likely" (and conditional)
6731 // then we skip the delay slot on the fall-thru path
6732 if(likely[i]) {
6733 if(i<slen-1) {
6734 temp_u&=unneeded_reg[i+2];
6735 temp_uu&=unneeded_reg_upper[i+2];
6736 }
6737 else
6738 {
6739 temp_u=1;
6740 temp_uu=1;
6741 }
6742 }
6743 tdep=(~temp_uu>>rt1[i])&1;
6744 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6745 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6746 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6747 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6748 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6749 temp_u|=1;temp_uu|=1;
6750 unneeded_reg[i]=temp_u;
6751 unneeded_reg_upper[i]=temp_uu;
6752 // Only go three levels deep. This recursion can take an
6753 // excessive amount of time if there are a lot of nested loops.
6754 if(r<2) {
6755 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6756 }else{
6757 unneeded_reg[(ba[i]-start)>>2]=1;
6758 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6759 }
6760 } /*else*/ if(1) {
6761 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6762 {
6763 // Unconditional branch
6764 u=unneeded_reg[(ba[i]-start)>>2];
6765 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6766 branch_unneeded_reg[i]=u;
6767 branch_unneeded_reg_upper[i]=uu;
6768 //u=1;
6769 //uu=1;
6770 //branch_unneeded_reg[i]=u;
6771 //branch_unneeded_reg_upper[i]=uu;
6772 // Merge in delay slot
6773 tdep=(~uu>>rt1[i+1])&1;
6774 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6775 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6776 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6777 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6778 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6779 u|=1;uu|=1;
6780 } else {
6781 // Conditional branch
6782 b=unneeded_reg[(ba[i]-start)>>2];
6783 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6784 branch_unneeded_reg[i]=b;
6785 branch_unneeded_reg_upper[i]=bu;
6786 //b=1;
6787 //bu=1;
6788 //branch_unneeded_reg[i]=b;
6789 //branch_unneeded_reg_upper[i]=bu;
6790 // Branch delay slot
6791 tdep=(~uu>>rt1[i+1])&1;
6792 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6793 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6794 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6795 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6796 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6797 b|=1;bu|=1;
6798 // If branch is "likely" then we skip the
6799 // delay slot on the fall-thru path
6800 if(likely[i]) {
6801 u=b;
6802 uu=bu;
6803 if(i<slen-1) {
6804 u&=unneeded_reg[i+2];
6805 uu&=unneeded_reg_upper[i+2];
6806 //u=1;
6807 //uu=1;
6808 }
6809 } else {
6810 u&=b;
6811 uu&=bu;
6812 //u=1;
6813 //uu=1;
6814 }
6815 if(i<slen-1) {
6816 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6817 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6818 //branch_unneeded_reg[i]=1;
6819 //branch_unneeded_reg_upper[i]=1;
6820 } else {
6821 branch_unneeded_reg[i]=1;
6822 branch_unneeded_reg_upper[i]=1;
6823 }
6824 }
6825 }
6826 }
6827 }
1e973cb0 6828 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 6829 {
6830 // SYSCALL instruction (software interrupt)
6831 u=1;
6832 uu=1;
6833 }
6834 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6835 {
6836 // ERET instruction (return from interrupt)
6837 u=1;
6838 uu=1;
6839 }
6840 //u=uu=1; // DEBUG
6841 tdep=(~uu>>rt1[i])&1;
6842 // Written registers are unneeded
6843 u|=1LL<<rt1[i];
6844 u|=1LL<<rt2[i];
6845 uu|=1LL<<rt1[i];
6846 uu|=1LL<<rt2[i];
6847 // Accessed registers are needed
6848 u&=~(1LL<<rs1[i]);
6849 u&=~(1LL<<rs2[i]);
6850 uu&=~(1LL<<us1[i]);
6851 uu&=~(1LL<<us2[i]);
6852 // Source-target dependencies
6853 uu&=~(tdep<<dep1[i]);
6854 uu&=~(tdep<<dep2[i]);
6855 // R0 is always unneeded
6856 u|=1;uu|=1;
6857 // Save it
6858 unneeded_reg[i]=u;
6859 unneeded_reg_upper[i]=uu;
6860 /*
6861 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6862 printf("U:");
6863 int r;
6864 for(r=1;r<=CCREG;r++) {
6865 if((unneeded_reg[i]>>r)&1) {
6866 if(r==HIREG) printf(" HI");
6867 else if(r==LOREG) printf(" LO");
6868 else printf(" r%d",r);
6869 }
6870 }
6871 printf(" UU:");
6872 for(r=1;r<=CCREG;r++) {
6873 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6874 if(r==HIREG) printf(" HI");
6875 else if(r==LOREG) printf(" LO");
6876 else printf(" r%d",r);
6877 }
6878 }
6879 printf("\n");*/
6880 }
252c20fc 6881#ifdef FORCE32
6882 for (i=iend;i>=istart;i--)
6883 {
6884 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6885 }
6886#endif
57871462 6887}
6888
6889// Identify registers which are likely to contain 32-bit values
6890// This is used to predict whether any branches will jump to a
6891// location with 64-bit values in registers.
6892static void provisional_32bit()
6893{
6894 int i,j;
6895 uint64_t is32=1;
6896 uint64_t lastbranch=1;
6897
6898 for(i=0;i<slen;i++)
6899 {
6900 if(i>0) {
6901 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6902 if(i>1) is32=lastbranch;
6903 else is32=1;
6904 }
6905 }
6906 if(i>1)
6907 {
6908 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6909 if(likely[i-2]) {
6910 if(i>2) is32=lastbranch;
6911 else is32=1;
6912 }
6913 }
6914 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6915 {
6916 if(rs1[i-2]==0||rs2[i-2]==0)
6917 {
6918 if(rs1[i-2]) {
6919 is32|=1LL<<rs1[i-2];
6920 }
6921 if(rs2[i-2]) {
6922 is32|=1LL<<rs2[i-2];
6923 }
6924 }
6925 }
6926 }
6927 // If something jumps here with 64-bit values
6928 // then promote those registers to 64 bits
6929 if(bt[i])
6930 {
6931 uint64_t temp_is32=is32;
6932 for(j=i-1;j>=0;j--)
6933 {
6934 if(ba[j]==start+i*4)
6935 //temp_is32&=branch_regs[j].is32;
6936 temp_is32&=p32[j];
6937 }
6938 for(j=i;j<slen;j++)
6939 {
6940 if(ba[j]==start+i*4)
6941 temp_is32=1;
6942 }
6943 is32=temp_is32;
6944 }
6945 int type=itype[i];
6946 int op=opcode[i];
6947 int op2=opcode2[i];
6948 int rt=rt1[i];
6949 int s1=rs1[i];
6950 int s2=rs2[i];
6951 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6952 // Branches don't write registers, consider the delay slot instead.
6953 type=itype[i+1];
6954 op=opcode[i+1];
6955 op2=opcode2[i+1];
6956 rt=rt1[i+1];
6957 s1=rs1[i+1];
6958 s2=rs2[i+1];
6959 lastbranch=is32;
6960 }
6961 switch(type) {
6962 case LOAD:
6963 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6964 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6965 is32&=~(1LL<<rt);
6966 else
6967 is32|=1LL<<rt;
6968 break;
6969 case STORE:
6970 case STORELR:
6971 break;
6972 case LOADLR:
6973 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6974 if(op==0x22) is32|=1LL<<rt; // LWL
6975 break;
6976 case IMM16:
6977 if (op==0x08||op==0x09|| // ADDI/ADDIU
6978 op==0x0a||op==0x0b|| // SLTI/SLTIU
6979 op==0x0c|| // ANDI
6980 op==0x0f) // LUI
6981 {
6982 is32|=1LL<<rt;
6983 }
6984 if(op==0x18||op==0x19) { // DADDI/DADDIU
6985 is32&=~(1LL<<rt);
6986 //if(imm[i]==0)
6987 // is32|=((is32>>s1)&1LL)<<rt;
6988 }
6989 if(op==0x0d||op==0x0e) { // ORI/XORI
6990 uint64_t sr=((is32>>s1)&1LL);
6991 is32&=~(1LL<<rt);
6992 is32|=sr<<rt;
6993 }
6994 break;
6995 case UJUMP:
6996 break;
6997 case RJUMP:
6998 break;
6999 case CJUMP:
7000 break;
7001 case SJUMP:
7002 break;
7003 case FJUMP:
7004 break;
7005 case ALU:
7006 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7007 is32|=1LL<<rt;
7008 }
7009 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7010 is32|=1LL<<rt;
7011 }
7012 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7013 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7014 is32&=~(1LL<<rt);
7015 is32|=sr<<rt;
7016 }
7017 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7018 if(s1==0&&s2==0) {
7019 is32|=1LL<<rt;
7020 }
7021 else if(s2==0) {
7022 uint64_t sr=((is32>>s1)&1LL);
7023 is32&=~(1LL<<rt);
7024 is32|=sr<<rt;
7025 }
7026 else if(s1==0) {
7027 uint64_t sr=((is32>>s2)&1LL);
7028 is32&=~(1LL<<rt);
7029 is32|=sr<<rt;
7030 }
7031 else {
7032 is32&=~(1LL<<rt);
7033 }
7034 }
7035 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7036 if(s1==0&&s2==0) {
7037 is32|=1LL<<rt;
7038 }
7039 else if(s2==0) {
7040 uint64_t sr=((is32>>s1)&1LL);
7041 is32&=~(1LL<<rt);
7042 is32|=sr<<rt;
7043 }
7044 else {
7045 is32&=~(1LL<<rt);
7046 }
7047 }
7048 break;
7049 case MULTDIV:
7050 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7051 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7052 }
7053 else {
7054 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7055 }
7056 break;
7057 case MOV:
7058 {
7059 uint64_t sr=((is32>>s1)&1LL);
7060 is32&=~(1LL<<rt);
7061 is32|=sr<<rt;
7062 }
7063 break;
7064 case SHIFT:
7065 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7066 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7067 break;
7068 case SHIFTIMM:
7069 is32|=1LL<<rt;
7070 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7071 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7072 break;
7073 case COP0:
7074 if(op2==0) is32|=1LL<<rt; // MFC0
7075 break;
7076 case COP1:
b9b61529 7077 case COP2:
57871462 7078 if(op2==0) is32|=1LL<<rt; // MFC1
7079 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7080 if(op2==2) is32|=1LL<<rt; // CFC1
7081 break;
7082 case C1LS:
b9b61529 7083 case C2LS:
57871462 7084 break;
7085 case FLOAT:
7086 case FCONV:
7087 break;
7088 case FCOMP:
7089 break;
b9b61529 7090 case C2OP:
57871462 7091 case SYSCALL:
7139f3c8 7092 case HLECALL:
57871462 7093 break;
7094 default:
7095 break;
7096 }
7097 is32|=1;
7098 p32[i]=is32;
7099
7100 if(i>0)
7101 {
7102 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7103 {
7104 if(rt1[i-1]==31) // JAL/JALR
7105 {
7106 // Subroutine call will return here, don't alloc any registers
7107 is32=1;
7108 }
7109 else if(i+1<slen)
7110 {
7111 // Internal branch will jump here, match registers to caller
7112 is32=0x3FFFFFFFFLL;
7113 }
7114 }
7115 }
7116 }
7117}
7118
7119// Identify registers which may be assumed to contain 32-bit values
7120// and where optimizations will rely on this.
7121// This is used to determine whether backward branches can safely
7122// jump to a location with 64-bit values in registers.
7123static void provisional_r32()
7124{
7125 u_int r32=0;
7126 int i;
7127
7128 for (i=slen-1;i>=0;i--)
7129 {
7130 int hr;
7131 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7132 {
7133 if(ba[i]<start || ba[i]>=(start+slen*4))
7134 {
7135 // Branch out of this block, don't need anything
7136 r32=0;
7137 }
7138 else
7139 {
7140 // Internal branch
7141 // Need whatever matches the target
7142 // (and doesn't get overwritten by the delay slot instruction)
7143 r32=0;
7144 int t=(ba[i]-start)>>2;
7145 if(ba[i]>start+i*4) {
7146 // Forward branch
7147 //if(!(requires_32bit[t]&~regs[i].was32))
7148 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7149 if(!(pr32[t]&~regs[i].was32))
7150 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7151 }else{
7152 // Backward branch
7153 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7154 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7155 }
7156 }
7157 // Conditional branch may need registers for following instructions
7158 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7159 {
7160 if(i<slen-2) {
7161 //r32|=requires_32bit[i+2];
7162 r32|=pr32[i+2];
7163 r32&=regs[i].was32;
7164 // Mark this address as a branch target since it may be called
7165 // upon return from interrupt
7166 //bt[i+2]=1;
7167 }
7168 }
7169 // Merge in delay slot
7170 if(!likely[i]) {
7171 // These are overwritten unless the branch is "likely"
7172 // and the delay slot is nullified if not taken
7173 r32&=~(1LL<<rt1[i+1]);
7174 r32&=~(1LL<<rt2[i+1]);
7175 }
7176 // Assume these are needed (delay slot)
7177 if(us1[i+1]>0)
7178 {
7179 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7180 }
7181 if(us2[i+1]>0)
7182 {
7183 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7184 }
7185 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7186 {
7187 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7188 }
7189 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7190 {
7191 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7192 }
7193 }
1e973cb0 7194 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7195 {
7196 // SYSCALL instruction (software interrupt)
7197 r32=0;
7198 }
7199 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7200 {
7201 // ERET instruction (return from interrupt)
7202 r32=0;
7203 }
7204 // Check 32 bits
7205 r32&=~(1LL<<rt1[i]);
7206 r32&=~(1LL<<rt2[i]);
7207 if(us1[i]>0)
7208 {
7209 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7210 }
7211 if(us2[i]>0)
7212 {
7213 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7214 }
7215 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7216 {
7217 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7218 }
7219 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7220 {
7221 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7222 }
7223 //requires_32bit[i]=r32;
7224 pr32[i]=r32;
7225
7226 // Dirty registers which are 32-bit, require 32-bit input
7227 // as they will be written as 32-bit values
7228 for(hr=0;hr<HOST_REGS;hr++)
7229 {
7230 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7231 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7232 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7233 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7234 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7235 }
7236 }
7237 }
7238 }
7239}
7240
7241// Write back dirty registers as soon as we will no longer modify them,
7242// so that we don't end up with lots of writes at the branches.
7243void clean_registers(int istart,int iend,int wr)
7244{
7245 int i;
7246 int r;
7247 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7248 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7249 if(iend==slen-1) {
7250 will_dirty_i=will_dirty_next=0;
7251 wont_dirty_i=wont_dirty_next=0;
7252 }else{
7253 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7254 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7255 }
7256 for (i=iend;i>=istart;i--)
7257 {
7258 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7259 {
7260 if(ba[i]<start || ba[i]>=(start+slen*4))
7261 {
7262 // Branch out of this block, flush all regs
7263 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7264 {
7265 // Unconditional branch
7266 will_dirty_i=0;
7267 wont_dirty_i=0;
7268 // Merge in delay slot (will dirty)
7269 for(r=0;r<HOST_REGS;r++) {
7270 if(r!=EXCLUDE_REG) {
7271 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7272 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7273 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7274 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7275 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7276 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7277 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7278 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7279 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7280 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7281 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7282 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7283 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7284 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7285 }
7286 }
7287 }
7288 else
7289 {
7290 // Conditional branch
7291 will_dirty_i=0;
7292 wont_dirty_i=wont_dirty_next;
7293 // Merge in delay slot (will dirty)
7294 for(r=0;r<HOST_REGS;r++) {
7295 if(r!=EXCLUDE_REG) {
7296 if(!likely[i]) {
7297 // Might not dirty if likely branch is not taken
7298 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7299 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7300 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7301 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7302 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7303 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7304 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7305 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7306 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7307 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7308 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7309 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7310 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7311 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7312 }
7313 }
7314 }
7315 }
7316 // Merge in delay slot (wont dirty)
7317 for(r=0;r<HOST_REGS;r++) {
7318 if(r!=EXCLUDE_REG) {
7319 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7320 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7321 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7322 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7323 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7324 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7325 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7326 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7327 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7328 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7329 }
7330 }
7331 if(wr) {
7332 #ifndef DESTRUCTIVE_WRITEBACK
7333 branch_regs[i].dirty&=wont_dirty_i;
7334 #endif
7335 branch_regs[i].dirty|=will_dirty_i;
7336 }
7337 }
7338 else
7339 {
7340 // Internal branch
7341 if(ba[i]<=start+i*4) {
7342 // Backward branch
7343 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7344 {
7345 // Unconditional branch
7346 temp_will_dirty=0;
7347 temp_wont_dirty=0;
7348 // Merge in delay slot (will dirty)
7349 for(r=0;r<HOST_REGS;r++) {
7350 if(r!=EXCLUDE_REG) {
7351 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7352 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7353 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7354 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7355 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7356 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7357 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7358 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7359 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7360 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7361 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7362 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7363 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7364 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7365 }
7366 }
7367 } else {
7368 // Conditional branch (not taken case)
7369 temp_will_dirty=will_dirty_next;
7370 temp_wont_dirty=wont_dirty_next;
7371 // Merge in delay slot (will dirty)
7372 for(r=0;r<HOST_REGS;r++) {
7373 if(r!=EXCLUDE_REG) {
7374 if(!likely[i]) {
7375 // Will not dirty if likely branch is not taken
7376 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7377 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7378 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7379 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7380 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7381 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7382 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7383 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7384 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7385 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7386 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7387 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7388 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7389 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7390 }
7391 }
7392 }
7393 }
7394 // Merge in delay slot (wont dirty)
7395 for(r=0;r<HOST_REGS;r++) {
7396 if(r!=EXCLUDE_REG) {
7397 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7398 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7399 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7400 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7401 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7402 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7403 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7404 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7405 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7406 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7407 }
7408 }
7409 // Deal with changed mappings
7410 if(i<iend) {
7411 for(r=0;r<HOST_REGS;r++) {
7412 if(r!=EXCLUDE_REG) {
7413 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7414 temp_will_dirty&=~(1<<r);
7415 temp_wont_dirty&=~(1<<r);
7416 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7417 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7418 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7419 } else {
7420 temp_will_dirty|=1<<r;
7421 temp_wont_dirty|=1<<r;
7422 }
7423 }
7424 }
7425 }
7426 }
7427 if(wr) {
7428 will_dirty[i]=temp_will_dirty;
7429 wont_dirty[i]=temp_wont_dirty;
7430 clean_registers((ba[i]-start)>>2,i-1,0);
7431 }else{
7432 // Limit recursion. It can take an excessive amount
7433 // of time if there are a lot of nested loops.
7434 will_dirty[(ba[i]-start)>>2]=0;
7435 wont_dirty[(ba[i]-start)>>2]=-1;
7436 }
7437 }
7438 /*else*/ if(1)
7439 {
7440 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7441 {
7442 // Unconditional branch
7443 will_dirty_i=0;
7444 wont_dirty_i=0;
7445 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7446 for(r=0;r<HOST_REGS;r++) {
7447 if(r!=EXCLUDE_REG) {
7448 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7449 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7450 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7451 }
7452 }
7453 }
7454 //}
7455 // Merge in delay slot
7456 for(r=0;r<HOST_REGS;r++) {
7457 if(r!=EXCLUDE_REG) {
7458 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7459 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7460 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7461 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7462 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7463 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7464 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7465 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7466 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7467 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7468 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7469 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7470 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7471 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7472 }
7473 }
7474 } else {
7475 // Conditional branch
7476 will_dirty_i=will_dirty_next;
7477 wont_dirty_i=wont_dirty_next;
7478 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7479 for(r=0;r<HOST_REGS;r++) {
7480 if(r!=EXCLUDE_REG) {
7481 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7482 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7483 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7484 }
7485 else
7486 {
7487 will_dirty_i&=~(1<<r);
7488 }
7489 // Treat delay slot as part of branch too
7490 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7491 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7492 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7493 }
7494 else
7495 {
7496 will_dirty[i+1]&=~(1<<r);
7497 }*/
7498 }
7499 }
7500 //}
7501 // Merge in delay slot
7502 for(r=0;r<HOST_REGS;r++) {
7503 if(r!=EXCLUDE_REG) {
7504 if(!likely[i]) {
7505 // Might not dirty if likely branch is not taken
7506 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7507 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7508 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7509 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7510 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7511 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7512 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7513 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7514 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7515 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7516 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7517 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7518 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7519 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7520 }
7521 }
7522 }
7523 }
7524 // Merge in delay slot
7525 for(r=0;r<HOST_REGS;r++) {
7526 if(r!=EXCLUDE_REG) {
7527 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7528 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7529 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7530 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7531 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7532 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7533 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7534 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7535 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7536 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7537 }
7538 }
7539 if(wr) {
7540 #ifndef DESTRUCTIVE_WRITEBACK
7541 branch_regs[i].dirty&=wont_dirty_i;
7542 #endif
7543 branch_regs[i].dirty|=will_dirty_i;
7544 }
7545 }
7546 }
7547 }
1e973cb0 7548 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7549 {
7550 // SYSCALL instruction (software interrupt)
7551 will_dirty_i=0;
7552 wont_dirty_i=0;
7553 }
7554 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7555 {
7556 // ERET instruction (return from interrupt)
7557 will_dirty_i=0;
7558 wont_dirty_i=0;
7559 }
7560 will_dirty_next=will_dirty_i;
7561 wont_dirty_next=wont_dirty_i;
7562 for(r=0;r<HOST_REGS;r++) {
7563 if(r!=EXCLUDE_REG) {
7564 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7565 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7566 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7567 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7568 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7569 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7570 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7571 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7572 if(i>istart) {
7573 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7574 {
7575 // Don't store a register immediately after writing it,
7576 // may prevent dual-issue.
7577 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7578 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7579 }
7580 }
7581 }
7582 }
7583 // Save it
7584 will_dirty[i]=will_dirty_i;
7585 wont_dirty[i]=wont_dirty_i;
7586 // Mark registers that won't be dirtied as not dirty
7587 if(wr) {
7588 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7589 for(r=0;r<HOST_REGS;r++) {
7590 if((will_dirty_i>>r)&1) {
7591 printf(" r%d",r);
7592 }
7593 }
7594 printf("\n");*/
7595
7596 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7597 regs[i].dirty|=will_dirty_i;
7598 #ifndef DESTRUCTIVE_WRITEBACK
7599 regs[i].dirty&=wont_dirty_i;
7600 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7601 {
7602 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7603 for(r=0;r<HOST_REGS;r++) {
7604 if(r!=EXCLUDE_REG) {
7605 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7606 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7607 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7608 }
7609 }
7610 }
7611 }
7612 else
7613 {
7614 if(i<iend) {
7615 for(r=0;r<HOST_REGS;r++) {
7616 if(r!=EXCLUDE_REG) {
7617 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7618 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7619 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7620 }
7621 }
7622 }
7623 }
7624 #endif
7625 //}
7626 }
7627 // Deal with changed mappings
7628 temp_will_dirty=will_dirty_i;
7629 temp_wont_dirty=wont_dirty_i;
7630 for(r=0;r<HOST_REGS;r++) {
7631 if(r!=EXCLUDE_REG) {
7632 int nr;
7633 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7634 if(wr) {
7635 #ifndef DESTRUCTIVE_WRITEBACK
7636 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7637 #endif
7638 regs[i].wasdirty|=will_dirty_i&(1<<r);
7639 }
7640 }
7641 else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7642 // Register moved to a different register
7643 will_dirty_i&=~(1<<r);
7644 wont_dirty_i&=~(1<<r);
7645 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7646 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7647 if(wr) {
7648 #ifndef DESTRUCTIVE_WRITEBACK
7649 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7650 #endif
7651 regs[i].wasdirty|=will_dirty_i&(1<<r);
7652 }
7653 }
7654 else {
7655 will_dirty_i&=~(1<<r);
7656 wont_dirty_i&=~(1<<r);
7657 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7658 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7659 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7660 } else {
7661 wont_dirty_i|=1<<r;
7662 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7663 }
7664 }
7665 }
7666 }
7667 }
7668}
7669
7670 /* disassembly */
7671void disassemble_inst(int i)
7672{
7673 if (bt[i]) printf("*"); else printf(" ");
7674 switch(itype[i]) {
7675 case UJUMP:
7676 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7677 case CJUMP:
7678 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7679 case SJUMP:
7680 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7681 case FJUMP:
7682 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7683 case RJUMP:
74426039 7684 if (opcode[i]==0x9&&rt1[i]!=31)
5067f341 7685 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7686 else
7687 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7688 break;
57871462 7689 case SPAN:
7690 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7691 case IMM16:
7692 if(opcode[i]==0xf) //LUI
7693 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7694 else
7695 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7696 break;
7697 case LOAD:
7698 case LOADLR:
7699 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7700 break;
7701 case STORE:
7702 case STORELR:
7703 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7704 break;
7705 case ALU:
7706 case SHIFT:
7707 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7708 break;
7709 case MULTDIV:
7710 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7711 break;
7712 case SHIFTIMM:
7713 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7714 break;
7715 case MOV:
7716 if((opcode2[i]&0x1d)==0x10)
7717 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7718 else if((opcode2[i]&0x1d)==0x11)
7719 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7720 else
7721 printf (" %x: %s\n",start+i*4,insn[i]);
7722 break;
7723 case COP0:
7724 if(opcode2[i]==0)
7725 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7726 else if(opcode2[i]==4)
7727 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7728 else printf (" %x: %s\n",start+i*4,insn[i]);
7729 break;
7730 case COP1:
7731 if(opcode2[i]<3)
7732 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7733 else if(opcode2[i]>3)
7734 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7735 else printf (" %x: %s\n",start+i*4,insn[i]);
7736 break;
b9b61529 7737 case COP2:
7738 if(opcode2[i]<3)
7739 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7740 else if(opcode2[i]>3)
7741 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7742 else printf (" %x: %s\n",start+i*4,insn[i]);
7743 break;
57871462 7744 case C1LS:
7745 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7746 break;
b9b61529 7747 case C2LS:
7748 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7749 break;
1e973cb0 7750 case INTCALL:
7751 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7752 break;
57871462 7753 default:
7754 //printf (" %s %8x\n",insn[i],source[i]);
7755 printf (" %x: %s\n",start+i*4,insn[i]);
7756 }
7757}
7758
dc990066 7759// clear the state completely, instead of just marking
7760// things invalid like invalidate_all_pages() does
7761void new_dynarec_clear_full()
57871462 7762{
57871462 7763 int n;
35775df7 7764 out=(u_char *)BASE_ADDR;
7765 memset(invalid_code,1,sizeof(invalid_code));
7766 memset(hash_table,0xff,sizeof(hash_table));
57871462 7767 memset(mini_ht,-1,sizeof(mini_ht));
7768 memset(restore_candidate,0,sizeof(restore_candidate));
dc990066 7769 memset(shadow,0,sizeof(shadow));
57871462 7770 copy=shadow;
7771 expirep=16384; // Expiry pointer, +2 blocks
7772 pending_exception=0;
7773 literalcount=0;
57871462 7774 stop_after_jal=0;
7775 // TLB
af4ee1fe 7776#ifndef DISABLE_TLB
57871462 7777 using_tlb=0;
af4ee1fe 7778#endif
dadf55f2 7779 sp_in_mirror=0;
57871462 7780 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7781 memory_map[n]=-1;
7782 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7783 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7784 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7785 memory_map[n]=-1;
dc990066 7786 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7787 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7788 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7789}
7790
7791void new_dynarec_init()
7792{
7793 printf("Init new dynarec\n");
7794 out=(u_char *)BASE_ADDR;
7795 if (mmap (out, 1<<TARGET_SIZE_2,
7796 PROT_READ | PROT_WRITE | PROT_EXEC,
7797 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7798 -1, 0) <= 0) {printf("mmap() failed\n");}
7799#ifdef MUPEN64
7800 rdword=&readmem_dword;
7801 fake_pc.f.r.rs=&readmem_dword;
7802 fake_pc.f.r.rt=&readmem_dword;
7803 fake_pc.f.r.rd=&readmem_dword;
7804#endif
7805 int n;
7806 new_dynarec_clear_full();
7807#ifdef HOST_IMM8
7808 // Copy this into local area so we don't have to put it in every literal pool
7809 invc_ptr=invalid_code;
7810#endif
24385cae 7811#ifdef MUPEN64
57871462 7812 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7813 writemem[n] = write_nomem_new;
7814 writememb[n] = write_nomemb_new;
7815 writememh[n] = write_nomemh_new;
24385cae 7816#ifndef FORCE32
57871462 7817 writememd[n] = write_nomemd_new;
24385cae 7818#endif
57871462 7819 readmem[n] = read_nomem_new;
7820 readmemb[n] = read_nomemb_new;
7821 readmemh[n] = read_nomemh_new;
24385cae 7822#ifndef FORCE32
57871462 7823 readmemd[n] = read_nomemd_new;
24385cae 7824#endif
57871462 7825 }
7826 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7827 writemem[n] = write_rdram_new;
7828 writememb[n] = write_rdramb_new;
7829 writememh[n] = write_rdramh_new;
24385cae 7830#ifndef FORCE32
57871462 7831 writememd[n] = write_rdramd_new;
24385cae 7832#endif
57871462 7833 }
7834 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7835 writemem[n] = write_nomem_new;
7836 writememb[n] = write_nomemb_new;
7837 writememh[n] = write_nomemh_new;
24385cae 7838#ifndef FORCE32
57871462 7839 writememd[n] = write_nomemd_new;
24385cae 7840#endif
57871462 7841 readmem[n] = read_nomem_new;
7842 readmemb[n] = read_nomemb_new;
7843 readmemh[n] = read_nomemh_new;
24385cae 7844#ifndef FORCE32
57871462 7845 readmemd[n] = read_nomemd_new;
24385cae 7846#endif
57871462 7847 }
24385cae 7848#endif
57871462 7849 tlb_hacks();
7850 arch_init();
7851}
7852
7853void new_dynarec_cleanup()
7854{
7855 int n;
7856 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7857 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7858 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7859 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7860 #ifdef ROM_COPY
7861 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7862 #endif
7863}
7864
7865int new_recompile_block(int addr)
7866{
7867/*
7868 if(addr==0x800cd050) {
7869 int block;
7870 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7871 int n;
7872 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7873 }
7874*/
7875 //if(Count==365117028) tracedebug=1;
7876 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7877 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7878 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7879 //if(debug)
7880 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7881 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7882 /*if(Count>=312978186) {
7883 rlist();
7884 }*/
7885 //rlist();
7886 start = (u_int)addr&~3;
7887 //assert(((u_int)addr&1)==0);
7139f3c8 7888#ifdef PCSX
dadf55f2 7889 if(!sp_in_mirror&&(signed int)(psxRegs.GPR.n.sp&0xffe00000)>0x80200000&&
7890 0x10000<=psxRegs.GPR.n.sp&&(psxRegs.GPR.n.sp&~0xe0e00000)<RAM_SIZE) {
c2e3bd42 7891 printf("SP hack enabled (%08x), @%08x\n", psxRegs.GPR.n.sp, psxRegs.pc);
dadf55f2 7892 sp_in_mirror=1;
7893 }
9ad4d757 7894 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 7895 {
7139f3c8 7896 // XXX: is this enough? Maybe check hleSoftCall?
bb5285ef 7897 u_int beginning=(u_int)out;
7139f3c8 7898 u_int page=get_page(start);
7139f3c8 7899 invalid_code[start>>12]=0;
7900 emit_movimm(start,0);
7901 emit_writeword(0,(int)&pcaddr);
bb5285ef 7902 emit_jmp((int)new_dyna_leave);
7903#ifdef __arm__
7904 __clear_cache((void *)beginning,out);
7905#endif
9ad4d757 7906 ll_add(jump_in+page,start,(void *)beginning);
7139f3c8 7907 return 0;
7908 }
560e4a12 7909 else if ((u_int)addr < 0x00200000 ||
7910 (0xa0000000 <= addr && addr < 0xa0200000)) {
7139f3c8 7911 // used for BIOS calls mostly?
560e4a12 7912 source = (u_int *)((u_int)rdram+(start&0x1fffff));
7913 pagelimit = (addr&0xa0000000)|0x00200000;
7914 }
7915 else if (!Config.HLE && (
7916/* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7917 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7918 // BIOS
7919 source = (u_int *)((u_int)psxR+(start&0x7ffff));
7920 pagelimit = (addr&0xfff00000)|0x80000;
7139f3c8 7921 }
7922 else
7923#endif
3d624f89 7924#ifdef MUPEN64
57871462 7925 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7926 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7927 pagelimit = 0xa4001000;
7928 }
3d624f89 7929 else
7930#endif
4cb76aa4 7931 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
57871462 7932 source = (u_int *)((u_int)rdram+start-0x80000000);
4cb76aa4 7933 pagelimit = 0x80000000+RAM_SIZE;
57871462 7934 }
90ae6d4e 7935#ifndef DISABLE_TLB
57871462 7936 else if ((signed int)addr >= (signed int)0xC0000000) {
7937 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7938 //if(tlb_LUT_r[start>>12])
7939 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7940 if((signed int)memory_map[start>>12]>=0) {
7941 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7942 pagelimit=(start+4096)&0xFFFFF000;
7943 int map=memory_map[start>>12];
7944 int i;
7945 for(i=0;i<5;i++) {
7946 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7947 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7948 }
7949 assem_debug("pagelimit=%x\n",pagelimit);
7950 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7951 }
7952 else {
7953 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7954 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
560e4a12 7955 return -1; // Caller will invoke exception handler
57871462 7956 }
7957 //printf("source= %x\n",(int)source);
7958 }
90ae6d4e 7959#endif
57871462 7960 else {
7961 printf("Compile at bogus memory address: %x \n", (int)addr);
7962 exit(1);
7963 }
7964
7965 /* Pass 1: disassemble */
7966 /* Pass 2: register dependencies, branch targets */
7967 /* Pass 3: register allocation */
7968 /* Pass 4: branch dependencies */
7969 /* Pass 5: pre-alloc */
7970 /* Pass 6: optimize clean/dirty state */
7971 /* Pass 7: flag 32-bit registers */
7972 /* Pass 8: assembly */
7973 /* Pass 9: linker */
7974 /* Pass 10: garbage collection / free memory */
7975
7976 int i,j;
7977 int done=0;
7978 unsigned int type,op,op2;
7979
7980 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7981
7982 /* Pass 1 disassembly */
7983
7984 for(i=0;!done;i++) {
e1190b87 7985 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7986 minimum_free_regs[i]=0;
57871462 7987 opcode[i]=op=source[i]>>26;
7988 switch(op)
7989 {
7990 case 0x00: strcpy(insn[i],"special"); type=NI;
7991 op2=source[i]&0x3f;
7992 switch(op2)
7993 {
7994 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7995 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7996 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7997 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7998 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7999 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8000 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8001 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8002 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8003 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8004 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8005 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8006 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8007 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8008 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
57871462 8009 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8010 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8011 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8012 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
57871462 8013 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8014 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8015 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8016 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8017 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8018 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8019 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8020 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8021 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8022 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
57871462 8023 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8024 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8025 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8026 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8027 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8028 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7f2607ea 8029#ifndef FORCE32
8030 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8031 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8032 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8033 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8034 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8035 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8036 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8037 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8038 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8039 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8040 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
57871462 8041 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8042 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8043 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8044 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8045 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8046 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7f2607ea 8047#endif
57871462 8048 }
8049 break;
8050 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8051 op2=(source[i]>>16)&0x1f;
8052 switch(op2)
8053 {
8054 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8055 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8056 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8057 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8058 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8059 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8060 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8061 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8062 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8063 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8064 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8065 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8066 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8067 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8068 }
8069 break;
8070 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8071 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8072 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8073 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8074 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8075 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8076 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8077 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8078 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8079 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8080 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8081 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8082 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8083 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8084 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8085 op2=(source[i]>>21)&0x1f;
8086 switch(op2)
8087 {
8088 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8089 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8090 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8091 switch(source[i]&0x3f)
8092 {
8093 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8094 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8095 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8096 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
576bbd8f 8097#ifdef PCSX
8098 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8099#else
57871462 8100 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
576bbd8f 8101#endif
57871462 8102 }
8103 }
8104 break;
8105 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8106 op2=(source[i]>>21)&0x1f;
8107 switch(op2)
8108 {
8109 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8110 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8111 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8112 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8113 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8114 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8115 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8116 switch((source[i]>>16)&0x3)
8117 {
8118 case 0x00: strcpy(insn[i],"BC1F"); break;
8119 case 0x01: strcpy(insn[i],"BC1T"); break;
8120 case 0x02: strcpy(insn[i],"BC1FL"); break;
8121 case 0x03: strcpy(insn[i],"BC1TL"); break;
8122 }
8123 break;
8124 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8125 switch(source[i]&0x3f)
8126 {
8127 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8128 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8129 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8130 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8131 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8132 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8133 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8134 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8135 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8136 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8137 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8138 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8139 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8140 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8141 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8142 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8143 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8144 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8145 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8146 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8147 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8148 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8149 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8150 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8151 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8152 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8153 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8154 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8155 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8156 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8157 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8158 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8159 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8160 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8161 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8162 }
8163 break;
8164 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8165 switch(source[i]&0x3f)
8166 {
8167 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8168 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8169 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8170 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8171 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8172 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8173 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8174 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8175 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8176 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8177 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8178 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8179 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8180 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8181 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8182 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8183 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8184 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8185 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8186 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8187 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8188 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8189 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8190 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8191 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8192 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8193 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8194 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8195 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8196 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8197 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8198 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8199 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8200 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8201 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8202 }
8203 break;
8204 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8205 switch(source[i]&0x3f)
8206 {
8207 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8208 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8209 }
8210 break;
8211 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8212 switch(source[i]&0x3f)
8213 {
8214 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8215 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8216 }
8217 break;
8218 }
8219 break;
909168d6 8220#ifndef FORCE32
57871462 8221 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8222 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8223 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8224 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8225 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8226 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8227 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8228 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 8229#endif
57871462 8230 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8231 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8232 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8233 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8234 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8235 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8236 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8237 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8238 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8239 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8240 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8241 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
996cc15d 8242#ifndef FORCE32
57871462 8243 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8244 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 8245#endif
57871462 8246 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8247 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8248 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8249 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
996cc15d 8250#ifndef FORCE32
57871462 8251 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8252 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8253 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 8254#endif
57871462 8255 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8256 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
996cc15d 8257#ifndef FORCE32
57871462 8258 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8259 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8260 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 8261#endif
b9b61529 8262#ifdef PCSX
8263 case 0x12: strcpy(insn[i],"COP2"); type=NI;
c7abc864 8264 // note: COP MIPS-1 encoding differs from MIPS32
b9b61529 8265 op2=(source[i]>>21)&0x1f;
c7abc864 8266 if (source[i]&0x3f) {
8267 if (gte_handlers[source[i]&0x3f]!=NULL) {
8268 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8269 type=C2OP;
8270 }
8271 }
8272 else switch(op2)
b9b61529 8273 {
8274 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8275 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8276 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8277 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 8278 }
8279 break;
8280 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8281 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8282 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8283#endif
90ae6d4e 8284 default: strcpy(insn[i],"???"); type=NI;
75dec299 8285 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 8286 break;
57871462 8287 }
8288 itype[i]=type;
8289 opcode2[i]=op2;
8290 /* Get registers/immediates */
8291 lt1[i]=0;
8292 us1[i]=0;
8293 us2[i]=0;
8294 dep1[i]=0;
8295 dep2[i]=0;
8296 switch(type) {
8297 case LOAD:
8298 rs1[i]=(source[i]>>21)&0x1f;
8299 rs2[i]=0;
8300 rt1[i]=(source[i]>>16)&0x1f;
8301 rt2[i]=0;
8302 imm[i]=(short)source[i];
8303 break;
8304 case STORE:
8305 case STORELR:
8306 rs1[i]=(source[i]>>21)&0x1f;
8307 rs2[i]=(source[i]>>16)&0x1f;
8308 rt1[i]=0;
8309 rt2[i]=0;
8310 imm[i]=(short)source[i];
8311 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8312 break;
8313 case LOADLR:
8314 // LWL/LWR only load part of the register,
8315 // therefore the target register must be treated as a source too
8316 rs1[i]=(source[i]>>21)&0x1f;
8317 rs2[i]=(source[i]>>16)&0x1f;
8318 rt1[i]=(source[i]>>16)&0x1f;
8319 rt2[i]=0;
8320 imm[i]=(short)source[i];
8321 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8322 if(op==0x26) dep1[i]=rt1[i]; // LWR
8323 break;
8324 case IMM16:
8325 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8326 else rs1[i]=(source[i]>>21)&0x1f;
8327 rs2[i]=0;
8328 rt1[i]=(source[i]>>16)&0x1f;
8329 rt2[i]=0;
8330 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8331 imm[i]=(unsigned short)source[i];
8332 }else{
8333 imm[i]=(short)source[i];
8334 }
8335 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8336 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8337 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8338 break;
8339 case UJUMP:
8340 rs1[i]=0;
8341 rs2[i]=0;
8342 rt1[i]=0;
8343 rt2[i]=0;
8344 // The JAL instruction writes to r31.
8345 if (op&1) {
8346 rt1[i]=31;
8347 }
8348 rs2[i]=CCREG;
8349 break;
8350 case RJUMP:
8351 rs1[i]=(source[i]>>21)&0x1f;
8352 rs2[i]=0;
8353 rt1[i]=0;
8354 rt2[i]=0;
5067f341 8355 // The JALR instruction writes to rd.
57871462 8356 if (op2&1) {
5067f341 8357 rt1[i]=(source[i]>>11)&0x1f;
57871462 8358 }
8359 rs2[i]=CCREG;
8360 break;
8361 case CJUMP:
8362 rs1[i]=(source[i]>>21)&0x1f;
8363 rs2[i]=(source[i]>>16)&0x1f;
8364 rt1[i]=0;
8365 rt2[i]=0;
8366 if(op&2) { // BGTZ/BLEZ
8367 rs2[i]=0;
8368 }
8369 us1[i]=rs1[i];
8370 us2[i]=rs2[i];
8371 likely[i]=op>>4;
8372 break;
8373 case SJUMP:
8374 rs1[i]=(source[i]>>21)&0x1f;
8375 rs2[i]=CCREG;
8376 rt1[i]=0;
8377 rt2[i]=0;
8378 us1[i]=rs1[i];
8379 if(op2&0x10) { // BxxAL
8380 rt1[i]=31;
8381 // NOTE: If the branch is not taken, r31 is still overwritten
8382 }
8383 likely[i]=(op2&2)>>1;
8384 break;
8385 case FJUMP:
8386 rs1[i]=FSREG;
8387 rs2[i]=CSREG;
8388 rt1[i]=0;
8389 rt2[i]=0;
8390 likely[i]=((source[i])>>17)&1;
8391 break;
8392 case ALU:
8393 rs1[i]=(source[i]>>21)&0x1f; // source
8394 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8395 rt1[i]=(source[i]>>11)&0x1f; // destination
8396 rt2[i]=0;
8397 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8398 us1[i]=rs1[i];us2[i]=rs2[i];
8399 }
8400 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8401 dep1[i]=rs1[i];dep2[i]=rs2[i];
8402 }
8403 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8404 dep1[i]=rs1[i];dep2[i]=rs2[i];
8405 }
8406 break;
8407 case MULTDIV:
8408 rs1[i]=(source[i]>>21)&0x1f; // source
8409 rs2[i]=(source[i]>>16)&0x1f; // divisor
8410 rt1[i]=HIREG;
8411 rt2[i]=LOREG;
8412 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8413 us1[i]=rs1[i];us2[i]=rs2[i];
8414 }
8415 break;
8416 case MOV:
8417 rs1[i]=0;
8418 rs2[i]=0;
8419 rt1[i]=0;
8420 rt2[i]=0;
8421 if(op2==0x10) rs1[i]=HIREG; // MFHI
8422 if(op2==0x11) rt1[i]=HIREG; // MTHI
8423 if(op2==0x12) rs1[i]=LOREG; // MFLO
8424 if(op2==0x13) rt1[i]=LOREG; // MTLO
8425 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8426 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8427 dep1[i]=rs1[i];
8428 break;
8429 case SHIFT:
8430 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8431 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8432 rt1[i]=(source[i]>>11)&0x1f; // destination
8433 rt2[i]=0;
8434 // DSLLV/DSRLV/DSRAV are 64-bit
8435 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8436 break;
8437 case SHIFTIMM:
8438 rs1[i]=(source[i]>>16)&0x1f;
8439 rs2[i]=0;
8440 rt1[i]=(source[i]>>11)&0x1f;
8441 rt2[i]=0;
8442 imm[i]=(source[i]>>6)&0x1f;
8443 // DSxx32 instructions
8444 if(op2>=0x3c) imm[i]|=0x20;
8445 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8446 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8447 break;
8448 case COP0:
8449 rs1[i]=0;
8450 rs2[i]=0;
8451 rt1[i]=0;
8452 rt2[i]=0;
8453 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8454 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8455 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8456 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8457 break;
8458 case COP1:
b9b61529 8459 case COP2:
57871462 8460 rs1[i]=0;
8461 rs2[i]=0;
8462 rt1[i]=0;
8463 rt2[i]=0;
8464 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8465 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8466 if(op2==5) us1[i]=rs1[i]; // DMTC1
8467 rs2[i]=CSREG;
8468 break;
8469 case C1LS:
8470 rs1[i]=(source[i]>>21)&0x1F;
8471 rs2[i]=CSREG;
8472 rt1[i]=0;
8473 rt2[i]=0;
8474 imm[i]=(short)source[i];
8475 break;
b9b61529 8476 case C2LS:
8477 rs1[i]=(source[i]>>21)&0x1F;
8478 rs2[i]=0;
8479 rt1[i]=0;
8480 rt2[i]=0;
8481 imm[i]=(short)source[i];
8482 break;
57871462 8483 case FLOAT:
8484 case FCONV:
8485 rs1[i]=0;
8486 rs2[i]=CSREG;
8487 rt1[i]=0;
8488 rt2[i]=0;
8489 break;
8490 case FCOMP:
8491 rs1[i]=FSREG;
8492 rs2[i]=CSREG;
8493 rt1[i]=FSREG;
8494 rt2[i]=0;
8495 break;
8496 case SYSCALL:
7139f3c8 8497 case HLECALL:
1e973cb0 8498 case INTCALL:
57871462 8499 rs1[i]=CCREG;
8500 rs2[i]=0;
8501 rt1[i]=0;
8502 rt2[i]=0;
8503 break;
8504 default:
8505 rs1[i]=0;
8506 rs2[i]=0;
8507 rt1[i]=0;
8508 rt2[i]=0;
8509 }
8510 /* Calculate branch target addresses */
8511 if(type==UJUMP)
8512 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8513 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8514 ba[i]=start+i*4+8; // Ignore never taken branch
8515 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8516 ba[i]=start+i*4+8; // Ignore never taken branch
8517 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8518 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8519 else ba[i]=-1;
26869094 8520#ifdef PCSX
3e535354 8521 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8522 int do_in_intrp=0;
8523 // branch in delay slot?
8524 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8525 // don't handle first branch and call interpreter if it's hit
8526 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8527 do_in_intrp=1;
8528 }
8529 // basic load delay detection
8530 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8531 int t=(ba[i-1]-start)/4;
8532 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8533 // jump target wants DS result - potential load delay effect
8534 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8535 do_in_intrp=1;
8536 bt[t+1]=1; // expected return from interpreter
8537 }
8538 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8539 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8540 // v0 overwrite like this is a sign of trouble, bail out
8541 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8542 do_in_intrp=1;
8543 }
8544 }
3e535354 8545 if(do_in_intrp) {
8546 rs1[i-1]=CCREG;
8547 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
26869094 8548 ba[i-1]=-1;
8549 itype[i-1]=INTCALL;
8550 done=2;
3e535354 8551 i--; // don't compile the DS
26869094 8552 }
3e535354 8553 }
26869094 8554#endif
3e535354 8555 /* Is this the end of the block? */
8556 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
5067f341 8557 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
1e973cb0 8558 done=2;
57871462 8559 }
8560 else {
8561 if(stop_after_jal) done=1;
8562 // Stop on BREAK
8563 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8564 }
8565 // Don't recompile stuff that's already compiled
8566 if(check_addr(start+i*4+4)) done=1;
8567 // Don't get too close to the limit
8568 if(i>MAXBLOCK/2) done=1;
8569 }
75dec299 8570 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
1e973cb0 8571 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8572 if(done==2) {
8573 // Does the block continue due to a branch?
8574 for(j=i-1;j>=0;j--)
8575 {
8576 if(ba[j]==start+i*4+4) done=j=0;
8577 if(ba[j]==start+i*4+8) done=j=0;
8578 }
8579 }
75dec299 8580 //assert(i<MAXBLOCK-1);
57871462 8581 if(start+i*4==pagelimit-4) done=1;
8582 assert(start+i*4<pagelimit);
8583 if (i==MAXBLOCK-1) done=1;
8584 // Stop if we're compiling junk
8585 if(itype[i]==NI&&opcode[i]==0x11) {
8586 done=stop_after_jal=1;
8587 printf("Disabled speculative precompilation\n");
8588 }
8589 }
8590 slen=i;
8591 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8592 if(start+i*4==pagelimit) {
8593 itype[i-1]=SPAN;
8594 }
8595 }
8596 assert(slen>0);
8597
8598 /* Pass 2 - Register dependencies and branch targets */
8599
8600 unneeded_registers(0,slen-1,0);
8601
8602 /* Pass 3 - Register allocation */
8603
8604 struct regstat current; // Current register allocations/status
8605 current.is32=1;
8606 current.dirty=0;
8607 current.u=unneeded_reg[0];
8608 current.uu=unneeded_reg_upper[0];
8609 clear_all_regs(current.regmap);
8610 alloc_reg(&current,0,CCREG);
8611 dirty_reg(&current,CCREG);
8612 current.isconst=0;
8613 current.wasconst=0;
8614 int ds=0;
8615 int cc=0;
5194fb95 8616 int hr=-1;
6ebf4adf 8617
8618#ifndef FORCE32
57871462 8619 provisional_32bit();
6ebf4adf 8620#endif
57871462 8621 if((u_int)addr&1) {
8622 // First instruction is delay slot
8623 cc=-1;
8624 bt[1]=1;
8625 ds=1;
8626 unneeded_reg[0]=1;
8627 unneeded_reg_upper[0]=1;
8628 current.regmap[HOST_BTREG]=BTREG;
8629 }
8630
8631 for(i=0;i<slen;i++)
8632 {
8633 if(bt[i])
8634 {
8635 int hr;
8636 for(hr=0;hr<HOST_REGS;hr++)
8637 {
8638 // Is this really necessary?
8639 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8640 }
8641 current.isconst=0;
8642 }
8643 if(i>1)
8644 {
8645 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8646 {
8647 if(rs1[i-2]==0||rs2[i-2]==0)
8648 {
8649 if(rs1[i-2]) {
8650 current.is32|=1LL<<rs1[i-2];
8651 int hr=get_reg(current.regmap,rs1[i-2]|64);
8652 if(hr>=0) current.regmap[hr]=-1;
8653 }
8654 if(rs2[i-2]) {
8655 current.is32|=1LL<<rs2[i-2];
8656 int hr=get_reg(current.regmap,rs2[i-2]|64);
8657 if(hr>=0) current.regmap[hr]=-1;
8658 }
8659 }
8660 }
8661 }
6ebf4adf 8662#ifndef FORCE32
57871462 8663 // If something jumps here with 64-bit values
8664 // then promote those registers to 64 bits
8665 if(bt[i])
8666 {
8667 uint64_t temp_is32=current.is32;
8668 for(j=i-1;j>=0;j--)
8669 {
8670 if(ba[j]==start+i*4)
8671 temp_is32&=branch_regs[j].is32;
8672 }
8673 for(j=i;j<slen;j++)
8674 {
8675 if(ba[j]==start+i*4)
8676 //temp_is32=1;
8677 temp_is32&=p32[j];
8678 }
8679 if(temp_is32!=current.is32) {
8680 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8681 #ifdef DESTRUCTIVE_WRITEBACK
8682 for(hr=0;hr<HOST_REGS;hr++)
8683 {
8684 int r=current.regmap[hr];
8685 if(r>0&&r<64)
8686 {
8687 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8688 temp_is32|=1LL<<r;
8689 //printf("restore %d\n",r);
8690 }
8691 }
8692 }
8693 #endif
8694 current.is32=temp_is32;
8695 }
8696 }
6ebf4adf 8697#else
24385cae 8698 current.is32=-1LL;
8699#endif
8700
57871462 8701 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8702 regs[i].wasconst=current.isconst;
8703 regs[i].was32=current.is32;
8704 regs[i].wasdirty=current.dirty;
6ebf4adf 8705 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
57871462 8706 // To change a dirty register from 32 to 64 bits, we must write
8707 // it out during the previous cycle (for branches, 2 cycles)
8708 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8709 {
8710 uint64_t temp_is32=current.is32;
8711 for(j=i-1;j>=0;j--)
8712 {
8713 if(ba[j]==start+i*4+4)
8714 temp_is32&=branch_regs[j].is32;
8715 }
8716 for(j=i;j<slen;j++)
8717 {
8718 if(ba[j]==start+i*4+4)
8719 //temp_is32=1;
8720 temp_is32&=p32[j];
8721 }
8722 if(temp_is32!=current.is32) {
8723 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8724 for(hr=0;hr<HOST_REGS;hr++)
8725 {
8726 int r=current.regmap[hr];
8727 if(r>0)
8728 {
8729 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8730 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8731 {
8732 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8733 {
8734 //printf("dump %d/r%d\n",hr,r);
8735 current.regmap[hr]=-1;
8736 if(get_reg(current.regmap,r|64)>=0)
8737 current.regmap[get_reg(current.regmap,r|64)]=-1;
8738 }
8739 }
8740 }
8741 }
8742 }
8743 }
8744 }
8745 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8746 {
8747 uint64_t temp_is32=current.is32;
8748 for(j=i-1;j>=0;j--)
8749 {
8750 if(ba[j]==start+i*4+8)
8751 temp_is32&=branch_regs[j].is32;
8752 }
8753 for(j=i;j<slen;j++)
8754 {
8755 if(ba[j]==start+i*4+8)
8756 //temp_is32=1;
8757 temp_is32&=p32[j];
8758 }
8759 if(temp_is32!=current.is32) {
8760 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8761 for(hr=0;hr<HOST_REGS;hr++)
8762 {
8763 int r=current.regmap[hr];
8764 if(r>0)
8765 {
8766 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8767 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8768 {
8769 //printf("dump %d/r%d\n",hr,r);
8770 current.regmap[hr]=-1;
8771 if(get_reg(current.regmap,r|64)>=0)
8772 current.regmap[get_reg(current.regmap,r|64)]=-1;
8773 }
8774 }
8775 }
8776 }
8777 }
8778 }
8779 #endif
8780 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8781 if(i+1<slen) {
8782 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8783 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8784 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8785 current.u|=1;
8786 current.uu|=1;
8787 } else {
8788 current.u=1;
8789 current.uu=1;
8790 }
8791 } else {
8792 if(i+1<slen) {
8793 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8794 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8795 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8796 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8797 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8798 current.u|=1;
8799 current.uu|=1;
8800 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8801 }
8802 is_ds[i]=ds;
8803 if(ds) {
8804 ds=0; // Skip delay slot, already allocated as part of branch
8805 // ...but we need to alloc it in case something jumps here
8806 if(i+1<slen) {
8807 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8808 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8809 }else{
8810 current.u=branch_unneeded_reg[i-1];
8811 current.uu=branch_unneeded_reg_upper[i-1];
8812 }
8813 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8814 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8815 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8816 current.u|=1;
8817 current.uu|=1;
8818 struct regstat temp;
8819 memcpy(&temp,&current,sizeof(current));
8820 temp.wasdirty=temp.dirty;
8821 temp.was32=temp.is32;
8822 // TODO: Take into account unconditional branches, as below
8823 delayslot_alloc(&temp,i);
8824 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8825 regs[i].wasdirty=temp.wasdirty;
8826 regs[i].was32=temp.was32;
8827 regs[i].dirty=temp.dirty;
8828 regs[i].is32=temp.is32;
8829 regs[i].isconst=0;
8830 regs[i].wasconst=0;
8831 current.isconst=0;
8832 // Create entry (branch target) regmap
8833 for(hr=0;hr<HOST_REGS;hr++)
8834 {
8835 int r=temp.regmap[hr];
8836 if(r>=0) {
8837 if(r!=regmap_pre[i][hr]) {
8838 regs[i].regmap_entry[hr]=-1;
8839 }
8840 else
8841 {
8842 if(r<64){
8843 if((current.u>>r)&1) {
8844 regs[i].regmap_entry[hr]=-1;
8845 regs[i].regmap[hr]=-1;
8846 //Don't clear regs in the delay slot as the branch might need them
8847 //current.regmap[hr]=-1;
8848 }else
8849 regs[i].regmap_entry[hr]=r;
8850 }
8851 else {
8852 if((current.uu>>(r&63))&1) {
8853 regs[i].regmap_entry[hr]=-1;
8854 regs[i].regmap[hr]=-1;
8855 //Don't clear regs in the delay slot as the branch might need them
8856 //current.regmap[hr]=-1;
8857 }else
8858 regs[i].regmap_entry[hr]=r;
8859 }
8860 }
8861 } else {
8862 // First instruction expects CCREG to be allocated
8863 if(i==0&&hr==HOST_CCREG)
8864 regs[i].regmap_entry[hr]=CCREG;
8865 else
8866 regs[i].regmap_entry[hr]=-1;
8867 }
8868 }
8869 }
8870 else { // Not delay slot
8871 switch(itype[i]) {
8872 case UJUMP:
8873 //current.isconst=0; // DEBUG
8874 //current.wasconst=0; // DEBUG
8875 //regs[i].wasconst=0; // DEBUG
8876 clear_const(&current,rt1[i]);
8877 alloc_cc(&current,i);
8878 dirty_reg(&current,CCREG);
2adcd6fa 8879 ooo[i]=1;
8880 delayslot_alloc(&current,i+1);
57871462 8881 if (rt1[i]==31) {
8882 alloc_reg(&current,i,31);
8883 dirty_reg(&current,31);
4ef8f67d 8884 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8885 //assert(rt1[i+1]!=rt1[i]);
57871462 8886 #ifdef REG_PREFETCH
8887 alloc_reg(&current,i,PTEMP);
8888 #endif
8889 //current.is32|=1LL<<rt1[i];
8890 }
57871462 8891 //current.isconst=0; // DEBUG
8892 ds=1;
8893 //printf("i=%d, isconst=%x\n",i,current.isconst);
8894 break;
8895 case RJUMP:
8896 //current.isconst=0;
8897 //current.wasconst=0;
8898 //regs[i].wasconst=0;
8899 clear_const(&current,rs1[i]);
8900 clear_const(&current,rt1[i]);
8901 alloc_cc(&current,i);
8902 dirty_reg(&current,CCREG);
8903 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8904 alloc_reg(&current,i,rs1[i]);
5067f341 8905 if (rt1[i]!=0) {
8906 alloc_reg(&current,i,rt1[i]);
8907 dirty_reg(&current,rt1[i]);
68b3faee 8908 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
076655d1 8909 assert(rt1[i+1]!=rt1[i]);
57871462 8910 #ifdef REG_PREFETCH
8911 alloc_reg(&current,i,PTEMP);
8912 #endif
8913 }
8914 #ifdef USE_MINI_HT
8915 if(rs1[i]==31) { // JALR
8916 alloc_reg(&current,i,RHASH);
8917 #ifndef HOST_IMM_ADDR32
8918 alloc_reg(&current,i,RHTBL);
8919 #endif
8920 }
8921 #endif
8922 delayslot_alloc(&current,i+1);
8923 } else {
8924 // The delay slot overwrites our source register,
8925 // allocate a temporary register to hold the old value.
8926 current.isconst=0;
8927 current.wasconst=0;
8928 regs[i].wasconst=0;
8929 delayslot_alloc(&current,i+1);
8930 current.isconst=0;
8931 alloc_reg(&current,i,RTEMP);
8932 }
8933 //current.isconst=0; // DEBUG
e1190b87 8934 ooo[i]=1;
57871462 8935 ds=1;
8936 break;
8937 case CJUMP:
8938 //current.isconst=0;
8939 //current.wasconst=0;
8940 //regs[i].wasconst=0;
8941 clear_const(&current,rs1[i]);
8942 clear_const(&current,rs2[i]);
8943 if((opcode[i]&0x3E)==4) // BEQ/BNE
8944 {
8945 alloc_cc(&current,i);
8946 dirty_reg(&current,CCREG);
8947 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8948 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8949 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8950 {
8951 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8952 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8953 }
8954 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8955 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8956 // The delay slot overwrites one of our conditions.
8957 // Allocate the branch condition registers instead.
57871462 8958 current.isconst=0;
8959 current.wasconst=0;
8960 regs[i].wasconst=0;
8961 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8962 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8963 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8964 {
8965 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8966 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8967 }
8968 }
e1190b87 8969 else
8970 {
8971 ooo[i]=1;
8972 delayslot_alloc(&current,i+1);
8973 }
57871462 8974 }
8975 else
8976 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8977 {
8978 alloc_cc(&current,i);
8979 dirty_reg(&current,CCREG);
8980 alloc_reg(&current,i,rs1[i]);
8981 if(!(current.is32>>rs1[i]&1))
8982 {
8983 alloc_reg64(&current,i,rs1[i]);
8984 }
8985 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8986 // The delay slot overwrites one of our conditions.
8987 // Allocate the branch condition registers instead.
57871462 8988 current.isconst=0;
8989 current.wasconst=0;
8990 regs[i].wasconst=0;
8991 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8992 if(!((current.is32>>rs1[i])&1))
8993 {
8994 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8995 }
8996 }
e1190b87 8997 else
8998 {
8999 ooo[i]=1;
9000 delayslot_alloc(&current,i+1);
9001 }
57871462 9002 }
9003 else
9004 // Don't alloc the delay slot yet because we might not execute it
9005 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9006 {
9007 current.isconst=0;
9008 current.wasconst=0;
9009 regs[i].wasconst=0;
9010 alloc_cc(&current,i);
9011 dirty_reg(&current,CCREG);
9012 alloc_reg(&current,i,rs1[i]);
9013 alloc_reg(&current,i,rs2[i]);
9014 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9015 {
9016 alloc_reg64(&current,i,rs1[i]);
9017 alloc_reg64(&current,i,rs2[i]);
9018 }
9019 }
9020 else
9021 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9022 {
9023 current.isconst=0;
9024 current.wasconst=0;
9025 regs[i].wasconst=0;
9026 alloc_cc(&current,i);
9027 dirty_reg(&current,CCREG);
9028 alloc_reg(&current,i,rs1[i]);
9029 if(!(current.is32>>rs1[i]&1))
9030 {
9031 alloc_reg64(&current,i,rs1[i]);
9032 }
9033 }
9034 ds=1;
9035 //current.isconst=0;
9036 break;
9037 case SJUMP:
9038 //current.isconst=0;
9039 //current.wasconst=0;
9040 //regs[i].wasconst=0;
9041 clear_const(&current,rs1[i]);
9042 clear_const(&current,rt1[i]);
9043 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9044 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9045 {
9046 alloc_cc(&current,i);
9047 dirty_reg(&current,CCREG);
9048 alloc_reg(&current,i,rs1[i]);
9049 if(!(current.is32>>rs1[i]&1))
9050 {
9051 alloc_reg64(&current,i,rs1[i]);
9052 }
9053 if (rt1[i]==31) { // BLTZAL/BGEZAL
9054 alloc_reg(&current,i,31);
9055 dirty_reg(&current,31);
57871462 9056 //#ifdef REG_PREFETCH
9057 //alloc_reg(&current,i,PTEMP);
9058 //#endif
9059 //current.is32|=1LL<<rt1[i];
9060 }
e1190b87 9061 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9062 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
57871462 9063 // Allocate the branch condition registers instead.
57871462 9064 current.isconst=0;
9065 current.wasconst=0;
9066 regs[i].wasconst=0;
9067 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9068 if(!((current.is32>>rs1[i])&1))
9069 {
9070 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9071 }
9072 }
e1190b87 9073 else
9074 {
9075 ooo[i]=1;
9076 delayslot_alloc(&current,i+1);
9077 }
57871462 9078 }
9079 else
9080 // Don't alloc the delay slot yet because we might not execute it
9081 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9082 {
9083 current.isconst=0;
9084 current.wasconst=0;
9085 regs[i].wasconst=0;
9086 alloc_cc(&current,i);
9087 dirty_reg(&current,CCREG);
9088 alloc_reg(&current,i,rs1[i]);
9089 if(!(current.is32>>rs1[i]&1))
9090 {
9091 alloc_reg64(&current,i,rs1[i]);
9092 }
9093 }
9094 ds=1;
9095 //current.isconst=0;
9096 break;
9097 case FJUMP:
9098 current.isconst=0;
9099 current.wasconst=0;
9100 regs[i].wasconst=0;
9101 if(likely[i]==0) // BC1F/BC1T
9102 {
9103 // TODO: Theoretically we can run out of registers here on x86.
9104 // The delay slot can allocate up to six, and we need to check
9105 // CSREG before executing the delay slot. Possibly we can drop
9106 // the cycle count and then reload it after checking that the
9107 // FPU is in a usable state, or don't do out-of-order execution.
9108 alloc_cc(&current,i);
9109 dirty_reg(&current,CCREG);
9110 alloc_reg(&current,i,FSREG);
9111 alloc_reg(&current,i,CSREG);
9112 if(itype[i+1]==FCOMP) {
9113 // The delay slot overwrites the branch condition.
9114 // Allocate the branch condition registers instead.
57871462 9115 alloc_cc(&current,i);
9116 dirty_reg(&current,CCREG);
9117 alloc_reg(&current,i,CSREG);
9118 alloc_reg(&current,i,FSREG);
9119 }
9120 else {
e1190b87 9121 ooo[i]=1;
57871462 9122 delayslot_alloc(&current,i+1);
9123 alloc_reg(&current,i+1,CSREG);
9124 }
9125 }
9126 else
9127 // Don't alloc the delay slot yet because we might not execute it
9128 if(likely[i]) // BC1FL/BC1TL
9129 {
9130 alloc_cc(&current,i);
9131 dirty_reg(&current,CCREG);
9132 alloc_reg(&current,i,CSREG);
9133 alloc_reg(&current,i,FSREG);
9134 }
9135 ds=1;
9136 current.isconst=0;
9137 break;
9138 case IMM16:
9139 imm16_alloc(&current,i);
9140 break;
9141 case LOAD:
9142 case LOADLR:
9143 load_alloc(&current,i);
9144 break;
9145 case STORE:
9146 case STORELR:
9147 store_alloc(&current,i);
9148 break;
9149 case ALU:
9150 alu_alloc(&current,i);
9151 break;
9152 case SHIFT:
9153 shift_alloc(&current,i);
9154 break;
9155 case MULTDIV:
9156 multdiv_alloc(&current,i);
9157 break;
9158 case SHIFTIMM:
9159 shiftimm_alloc(&current,i);
9160 break;
9161 case MOV:
9162 mov_alloc(&current,i);
9163 break;
9164 case COP0:
9165 cop0_alloc(&current,i);
9166 break;
9167 case COP1:
b9b61529 9168 case COP2:
57871462 9169 cop1_alloc(&current,i);
9170 break;
9171 case C1LS:
9172 c1ls_alloc(&current,i);
9173 break;
b9b61529 9174 case C2LS:
9175 c2ls_alloc(&current,i);
9176 break;
9177 case C2OP:
9178 c2op_alloc(&current,i);
9179 break;
57871462 9180 case FCONV:
9181 fconv_alloc(&current,i);
9182 break;
9183 case FLOAT:
9184 float_alloc(&current,i);
9185 break;
9186 case FCOMP:
9187 fcomp_alloc(&current,i);
9188 break;
9189 case SYSCALL:
7139f3c8 9190 case HLECALL:
1e973cb0 9191 case INTCALL:
57871462 9192 syscall_alloc(&current,i);
9193 break;
9194 case SPAN:
9195 pagespan_alloc(&current,i);
9196 break;
9197 }
9198
9199 // Drop the upper half of registers that have become 32-bit
9200 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9201 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9202 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9203 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9204 current.uu|=1;
9205 } else {
9206 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9207 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9208 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9209 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9210 current.uu|=1;
9211 }
9212
9213 // Create entry (branch target) regmap
9214 for(hr=0;hr<HOST_REGS;hr++)
9215 {
9216 int r,or,er;
9217 r=current.regmap[hr];
9218 if(r>=0) {
9219 if(r!=regmap_pre[i][hr]) {
9220 // TODO: delay slot (?)
9221 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9222 if(or<0||(r&63)>=TEMPREG){
9223 regs[i].regmap_entry[hr]=-1;
9224 }
9225 else
9226 {
9227 // Just move it to a different register
9228 regs[i].regmap_entry[hr]=r;
9229 // If it was dirty before, it's still dirty
9230 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9231 }
9232 }
9233 else
9234 {
9235 // Unneeded
9236 if(r==0){
9237 regs[i].regmap_entry[hr]=0;
9238 }
9239 else
9240 if(r<64){
9241 if((current.u>>r)&1) {
9242 regs[i].regmap_entry[hr]=-1;
9243 //regs[i].regmap[hr]=-1;
9244 current.regmap[hr]=-1;
9245 }else
9246 regs[i].regmap_entry[hr]=r;
9247 }
9248 else {
9249 if((current.uu>>(r&63))&1) {
9250 regs[i].regmap_entry[hr]=-1;
9251 //regs[i].regmap[hr]=-1;
9252 current.regmap[hr]=-1;
9253 }else
9254 regs[i].regmap_entry[hr]=r;
9255 }
9256 }
9257 } else {
9258 // Branches expect CCREG to be allocated at the target
9259 if(regmap_pre[i][hr]==CCREG)
9260 regs[i].regmap_entry[hr]=CCREG;
9261 else
9262 regs[i].regmap_entry[hr]=-1;
9263 }
9264 }
9265 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9266 }
9267 /* Branch post-alloc */
9268 if(i>0)
9269 {
9270 current.was32=current.is32;
9271 current.wasdirty=current.dirty;
9272 switch(itype[i-1]) {
9273 case UJUMP:
9274 memcpy(&branch_regs[i-1],&current,sizeof(current));
9275 branch_regs[i-1].isconst=0;
9276 branch_regs[i-1].wasconst=0;
9277 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9278 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9279 alloc_cc(&branch_regs[i-1],i-1);
9280 dirty_reg(&branch_regs[i-1],CCREG);
9281 if(rt1[i-1]==31) { // JAL
9282 alloc_reg(&branch_regs[i-1],i-1,31);
9283 dirty_reg(&branch_regs[i-1],31);
9284 branch_regs[i-1].is32|=1LL<<31;
9285 }
9286 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9287 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9288 break;
9289 case RJUMP:
9290 memcpy(&branch_regs[i-1],&current,sizeof(current));
9291 branch_regs[i-1].isconst=0;
9292 branch_regs[i-1].wasconst=0;
9293 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9294 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9295 alloc_cc(&branch_regs[i-1],i-1);
9296 dirty_reg(&branch_regs[i-1],CCREG);
9297 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
5067f341 9298 if(rt1[i-1]!=0) { // JALR
9299 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9300 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9301 branch_regs[i-1].is32|=1LL<<rt1[i-1];
57871462 9302 }
9303 #ifdef USE_MINI_HT
9304 if(rs1[i-1]==31) { // JALR
9305 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9306 #ifndef HOST_IMM_ADDR32
9307 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9308 #endif
9309 }
9310 #endif
9311 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9312 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9313 break;
9314 case CJUMP:
9315 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9316 {
9317 alloc_cc(&current,i-1);
9318 dirty_reg(&current,CCREG);
9319 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9320 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9321 // The delay slot overwrote one of our conditions
9322 // Delay slot goes after the test (in order)
9323 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9324 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9325 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9326 current.u|=1;
9327 current.uu|=1;
9328 delayslot_alloc(&current,i);
9329 current.isconst=0;
9330 }
9331 else
9332 {
9333 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9334 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9335 // Alloc the branch condition registers
9336 if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9337 if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9338 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9339 {
9340 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9341 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9342 }
9343 }
9344 memcpy(&branch_regs[i-1],&current,sizeof(current));
9345 branch_regs[i-1].isconst=0;
9346 branch_regs[i-1].wasconst=0;
9347 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9348 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9349 }
9350 else
9351 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9352 {
9353 alloc_cc(&current,i-1);
9354 dirty_reg(&current,CCREG);
9355 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9356 // The delay slot overwrote the branch condition
9357 // Delay slot goes after the test (in order)
9358 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9359 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9360 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9361 current.u|=1;
9362 current.uu|=1;
9363 delayslot_alloc(&current,i);
9364 current.isconst=0;
9365 }
9366 else
9367 {
9368 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9369 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9370 // Alloc the branch condition register
9371 alloc_reg(&current,i-1,rs1[i-1]);
9372 if(!(current.is32>>rs1[i-1]&1))
9373 {
9374 alloc_reg64(&current,i-1,rs1[i-1]);
9375 }
9376 }
9377 memcpy(&branch_regs[i-1],&current,sizeof(current));
9378 branch_regs[i-1].isconst=0;
9379 branch_regs[i-1].wasconst=0;
9380 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9381 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9382 }
9383 else
9384 // Alloc the delay slot in case the branch is taken
9385 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9386 {
9387 memcpy(&branch_regs[i-1],&current,sizeof(current));
9388 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9389 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9390 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9391 alloc_cc(&branch_regs[i-1],i);
9392 dirty_reg(&branch_regs[i-1],CCREG);
9393 delayslot_alloc(&branch_regs[i-1],i);
9394 branch_regs[i-1].isconst=0;
9395 alloc_reg(&current,i,CCREG); // Not taken path
9396 dirty_reg(&current,CCREG);
9397 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9398 }
9399 else
9400 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9401 {
9402 memcpy(&branch_regs[i-1],&current,sizeof(current));
9403 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9404 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9405 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9406 alloc_cc(&branch_regs[i-1],i);
9407 dirty_reg(&branch_regs[i-1],CCREG);
9408 delayslot_alloc(&branch_regs[i-1],i);
9409 branch_regs[i-1].isconst=0;
9410 alloc_reg(&current,i,CCREG); // Not taken path
9411 dirty_reg(&current,CCREG);
9412 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9413 }
9414 break;
9415 case SJUMP:
9416 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9417 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9418 {
9419 alloc_cc(&current,i-1);
9420 dirty_reg(&current,CCREG);
9421 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9422 // The delay slot overwrote the branch condition
9423 // Delay slot goes after the test (in order)
9424 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9425 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9426 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9427 current.u|=1;
9428 current.uu|=1;
9429 delayslot_alloc(&current,i);
9430 current.isconst=0;
9431 }
9432 else
9433 {
9434 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9435 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9436 // Alloc the branch condition register
9437 alloc_reg(&current,i-1,rs1[i-1]);
9438 if(!(current.is32>>rs1[i-1]&1))
9439 {
9440 alloc_reg64(&current,i-1,rs1[i-1]);
9441 }
9442 }
9443 memcpy(&branch_regs[i-1],&current,sizeof(current));
9444 branch_regs[i-1].isconst=0;
9445 branch_regs[i-1].wasconst=0;
9446 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9447 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9448 }
9449 else
9450 // Alloc the delay slot in case the branch is taken
9451 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9452 {
9453 memcpy(&branch_regs[i-1],&current,sizeof(current));
9454 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9455 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9456 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9457 alloc_cc(&branch_regs[i-1],i);
9458 dirty_reg(&branch_regs[i-1],CCREG);
9459 delayslot_alloc(&branch_regs[i-1],i);
9460 branch_regs[i-1].isconst=0;
9461 alloc_reg(&current,i,CCREG); // Not taken path
9462 dirty_reg(&current,CCREG);
9463 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9464 }
9465 // FIXME: BLTZAL/BGEZAL
9466 if(opcode2[i-1]&0x10) { // BxxZAL
9467 alloc_reg(&branch_regs[i-1],i-1,31);
9468 dirty_reg(&branch_regs[i-1],31);
9469 branch_regs[i-1].is32|=1LL<<31;
9470 }
9471 break;
9472 case FJUMP:
9473 if(likely[i-1]==0) // BC1F/BC1T
9474 {
9475 alloc_cc(&current,i-1);
9476 dirty_reg(&current,CCREG);
9477 if(itype[i]==FCOMP) {
9478 // The delay slot overwrote the branch condition
9479 // Delay slot goes after the test (in order)
9480 delayslot_alloc(&current,i);
9481 current.isconst=0;
9482 }
9483 else
9484 {
9485 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9486 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9487 // Alloc the branch condition register
9488 alloc_reg(&current,i-1,FSREG);
9489 }
9490 memcpy(&branch_regs[i-1],&current,sizeof(current));
9491 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9492 }
9493 else // BC1FL/BC1TL
9494 {
9495 // Alloc the delay slot in case the branch is taken
9496 memcpy(&branch_regs[i-1],&current,sizeof(current));
9497 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9498 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9499 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9500 alloc_cc(&branch_regs[i-1],i);
9501 dirty_reg(&branch_regs[i-1],CCREG);
9502 delayslot_alloc(&branch_regs[i-1],i);
9503 branch_regs[i-1].isconst=0;
9504 alloc_reg(&current,i,CCREG); // Not taken path
9505 dirty_reg(&current,CCREG);
9506 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9507 }
9508 break;
9509 }
9510
9511 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9512 {
9513 if(rt1[i-1]==31) // JAL/JALR
9514 {
9515 // Subroutine call will return here, don't alloc any registers
9516 current.is32=1;
9517 current.dirty=0;
9518 clear_all_regs(current.regmap);
9519 alloc_reg(&current,i,CCREG);
9520 dirty_reg(&current,CCREG);
9521 }
9522 else if(i+1<slen)
9523 {
9524 // Internal branch will jump here, match registers to caller
9525 current.is32=0x3FFFFFFFFLL;
9526 current.dirty=0;
9527 clear_all_regs(current.regmap);
9528 alloc_reg(&current,i,CCREG);
9529 dirty_reg(&current,CCREG);
9530 for(j=i-1;j>=0;j--)
9531 {
9532 if(ba[j]==start+i*4+4) {
9533 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9534 current.is32=branch_regs[j].is32;
9535 current.dirty=branch_regs[j].dirty;
9536 break;
9537 }
9538 }
9539 while(j>=0) {
9540 if(ba[j]==start+i*4+4) {
9541 for(hr=0;hr<HOST_REGS;hr++) {
9542 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9543 current.regmap[hr]=-1;
9544 }
9545 current.is32&=branch_regs[j].is32;
9546 current.dirty&=branch_regs[j].dirty;
9547 }
9548 }
9549 j--;
9550 }
9551 }
9552 }
9553 }
9554
9555 // Count cycles in between branches
9556 ccadj[i]=cc;
7139f3c8 9557 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
57871462 9558 {
9559 cc=0;
9560 }
fb407447 9561#ifdef PCSX
9562 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9563 {
9564 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9565 }
9566 else if(itype[i]==C2LS)
9567 {
9568 cc+=4;
9569 }
9570#endif
57871462 9571 else
9572 {
9573 cc++;
9574 }
9575
9576 flush_dirty_uppers(&current);
9577 if(!is_ds[i]) {
9578 regs[i].is32=current.is32;
9579 regs[i].dirty=current.dirty;
9580 regs[i].isconst=current.isconst;
9581 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9582 }
9583 for(hr=0;hr<HOST_REGS;hr++) {
9584 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9585 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9586 regs[i].wasconst&=~(1<<hr);
9587 }
9588 }
9589 }
9590 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9591 }
9592
9593 /* Pass 4 - Cull unused host registers */
9594
9595 uint64_t nr=0;
9596
9597 for (i=slen-1;i>=0;i--)
9598 {
9599 int hr;
9600 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9601 {
9602 if(ba[i]<start || ba[i]>=(start+slen*4))
9603 {
9604 // Branch out of this block, don't need anything
9605 nr=0;
9606 }
9607 else
9608 {
9609 // Internal branch
9610 // Need whatever matches the target
9611 nr=0;
9612 int t=(ba[i]-start)>>2;
9613 for(hr=0;hr<HOST_REGS;hr++)
9614 {
9615 if(regs[i].regmap_entry[hr]>=0) {
9616 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9617 }
9618 }
9619 }
9620 // Conditional branch may need registers for following instructions
9621 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9622 {
9623 if(i<slen-2) {
9624 nr|=needed_reg[i+2];
9625 for(hr=0;hr<HOST_REGS;hr++)
9626 {
9627 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9628 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9629 }
9630 }
9631 }
9632 // Don't need stuff which is overwritten
f5955059 9633 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9634 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 9635 // Merge in delay slot
9636 for(hr=0;hr<HOST_REGS;hr++)
9637 {
9638 if(!likely[i]) {
9639 // These are overwritten unless the branch is "likely"
9640 // and the delay slot is nullified if not taken
9641 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9642 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9643 }
9644 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9645 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9646 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9647 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9648 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9649 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9650 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9651 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9652 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9653 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9654 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9655 }
9656 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9657 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9658 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9659 }
b9b61529 9660 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
57871462 9661 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9662 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9663 }
9664 }
9665 }
1e973cb0 9666 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 9667 {
9668 // SYSCALL instruction (software interrupt)
9669 nr=0;
9670 }
9671 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9672 {
9673 // ERET instruction (return from interrupt)
9674 nr=0;
9675 }
9676 else // Non-branch
9677 {
9678 if(i<slen-1) {
9679 for(hr=0;hr<HOST_REGS;hr++) {
9680 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9681 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9682 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9683 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9684 }
9685 }
9686 }
9687 for(hr=0;hr<HOST_REGS;hr++)
9688 {
9689 // Overwritten registers are not needed
9690 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9691 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9692 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9693 // Source registers are needed
9694 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9695 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9696 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9697 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9698 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9699 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9700 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9701 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9702 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9703 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9704 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9705 }
9706 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9707 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9708 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9709 }
b9b61529 9710 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
57871462 9711 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9712 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9713 }
9714 // Don't store a register immediately after writing it,
9715 // may prevent dual-issue.
9716 // But do so if this is a branch target, otherwise we
9717 // might have to load the register before the branch.
9718 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9719 if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9720 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9721 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9722 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9723 }
9724 if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9725 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9726 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9727 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9728 }
9729 }
9730 }
9731 // Cycle count is needed at branches. Assume it is needed at the target too.
9732 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9733 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9734 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9735 }
9736 // Save it
9737 needed_reg[i]=nr;
9738
9739 // Deallocate unneeded registers
9740 for(hr=0;hr<HOST_REGS;hr++)
9741 {
9742 if(!((nr>>hr)&1)) {
9743 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9744 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9745 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9746 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9747 {
9748 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9749 {
9750 if(likely[i]) {
9751 regs[i].regmap[hr]=-1;
9752 regs[i].isconst&=~(1<<hr);
79c75f1b 9753 if(i<slen-2) {
9754 regmap_pre[i+2][hr]=-1;
9755 regs[i+2].wasconst&=~(1<<hr);
9756 }
57871462 9757 }
9758 }
9759 }
9760 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9761 {
9762 int d1=0,d2=0,map=0,temp=0;
9763 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9764 {
9765 d1=dep1[i+1];
9766 d2=dep2[i+1];
9767 }
9768 if(using_tlb) {
9769 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9770 itype[i+1]==STORE || itype[i+1]==STORELR ||
b9b61529 9771 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9772 map=TLREG;
9773 } else
b9b61529 9774 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9775 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9776 map=INVCP;
9777 }
9778 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
b9b61529 9779 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9780 temp=FTEMP;
9781 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9782 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9783 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9784 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9785 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9786 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9787 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9788 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9789 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9790 regs[i].regmap[hr]!=map )
9791 {
9792 regs[i].regmap[hr]=-1;
9793 regs[i].isconst&=~(1<<hr);
9794 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9795 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9796 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9797 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9798 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9799 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9800 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9801 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9802 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9803 branch_regs[i].regmap[hr]!=map)
9804 {
9805 branch_regs[i].regmap[hr]=-1;
9806 branch_regs[i].regmap_entry[hr]=-1;
9807 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9808 {
9809 if(!likely[i]&&i<slen-2) {
9810 regmap_pre[i+2][hr]=-1;
79c75f1b 9811 regs[i+2].wasconst&=~(1<<hr);
57871462 9812 }
9813 }
9814 }
9815 }
9816 }
9817 else
9818 {
9819 // Non-branch
9820 if(i>0)
9821 {
9822 int d1=0,d2=0,map=-1,temp=-1;
9823 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9824 {
9825 d1=dep1[i];
9826 d2=dep2[i];
9827 }
9828 if(using_tlb) {
9829 if(itype[i]==LOAD || itype[i]==LOADLR ||
9830 itype[i]==STORE || itype[i]==STORELR ||
b9b61529 9831 itype[i]==C1LS || itype[i]==C2LS)
57871462 9832 map=TLREG;
b9b61529 9833 } else if(itype[i]==STORE || itype[i]==STORELR ||
9834 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9835 map=INVCP;
9836 }
9837 if(itype[i]==LOADLR || itype[i]==STORELR ||
b9b61529 9838 itype[i]==C1LS || itype[i]==C2LS)
57871462 9839 temp=FTEMP;
9840 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9841 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9842 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9843 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9844 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9845 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9846 {
9847 if(i<slen-1&&!is_ds[i]) {
9848 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9849 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9850 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9851 {
9852 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9853 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9854 }
9855 regmap_pre[i+1][hr]=-1;
9856 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 9857 regs[i+1].wasconst&=~(1<<hr);
57871462 9858 }
9859 regs[i].regmap[hr]=-1;
9860 regs[i].isconst&=~(1<<hr);
9861 }
9862 }
9863 }
9864 }
9865 }
9866 }
9867
9868 /* Pass 5 - Pre-allocate registers */
9869
9870 // If a register is allocated during a loop, try to allocate it for the
9871 // entire loop, if possible. This avoids loading/storing registers
9872 // inside of the loop.
9873
9874 signed char f_regmap[HOST_REGS];
9875 clear_all_regs(f_regmap);
9876 for(i=0;i<slen-1;i++)
9877 {
9878 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9879 {
9880 if(ba[i]>=start && ba[i]<(start+i*4))
9881 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9882 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9883 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9884 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
b9b61529 9885 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9886 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
57871462 9887 {
9888 int t=(ba[i]-start)>>2;
9889 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9890 if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9891 for(hr=0;hr<HOST_REGS;hr++)
9892 {
9893 if(regs[i].regmap[hr]>64) {
9894 if(!((regs[i].dirty>>hr)&1))
9895 f_regmap[hr]=regs[i].regmap[hr];
9896 else f_regmap[hr]=-1;
9897 }
b372a952 9898 else if(regs[i].regmap[hr]>=0) {
9899 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9900 // dealloc old register
9901 int n;
9902 for(n=0;n<HOST_REGS;n++)
9903 {
9904 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9905 }
9906 // and alloc new one
9907 f_regmap[hr]=regs[i].regmap[hr];
9908 }
9909 }
57871462 9910 if(branch_regs[i].regmap[hr]>64) {
9911 if(!((branch_regs[i].dirty>>hr)&1))
9912 f_regmap[hr]=branch_regs[i].regmap[hr];
9913 else f_regmap[hr]=-1;
9914 }
b372a952 9915 else if(branch_regs[i].regmap[hr]>=0) {
9916 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9917 // dealloc old register
9918 int n;
9919 for(n=0;n<HOST_REGS;n++)
9920 {
9921 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9922 }
9923 // and alloc new one
9924 f_regmap[hr]=branch_regs[i].regmap[hr];
9925 }
9926 }
e1190b87 9927 if(ooo[i]) {
9928 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9929 f_regmap[hr]=branch_regs[i].regmap[hr];
9930 }else{
9931 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 9932 f_regmap[hr]=branch_regs[i].regmap[hr];
9933 }
9934 // Avoid dirty->clean transition
e1190b87 9935 #ifdef DESTRUCTIVE_WRITEBACK
57871462 9936 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 9937 #endif
9938 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9939 // case above, however it's always a good idea. We can't hoist the
9940 // load if the register was already allocated, so there's no point
9941 // wasting time analyzing most of these cases. It only "succeeds"
9942 // when the mapping was different and the load can be replaced with
9943 // a mov, which is of negligible benefit. So such cases are
9944 // skipped below.
57871462 9945 if(f_regmap[hr]>0) {
e1190b87 9946 if(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0) {
57871462 9947 int r=f_regmap[hr];
9948 for(j=t;j<=i;j++)
9949 {
9950 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9951 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9952 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9953 if(r>63) {
9954 // NB This can exclude the case where the upper-half
9955 // register is lower numbered than the lower-half
9956 // register. Not sure if it's worth fixing...
9957 if(get_reg(regs[j].regmap,r&63)<0) break;
e1190b87 9958 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
57871462 9959 if(regs[j].is32&(1LL<<(r&63))) break;
9960 }
9961 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9962 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9963 int k;
9964 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9965 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9966 if(r>63) {
9967 if(get_reg(regs[i].regmap,r&63)<0) break;
9968 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9969 }
9970 k=i;
9971 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 9972 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9973 //printf("no free regs for store %x\n",start+(k-1)*4);
9974 break;
57871462 9975 }
57871462 9976 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9977 //printf("no-match due to different register\n");
9978 break;
9979 }
9980 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9981 //printf("no-match due to branch\n");
9982 break;
9983 }
9984 // call/ret fast path assumes no registers allocated
9985 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9986 break;
9987 }
9988 if(r>63) {
9989 // NB This can exclude the case where the upper-half
9990 // register is lower numbered than the lower-half
9991 // register. Not sure if it's worth fixing...
9992 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9993 if(regs[k-1].is32&(1LL<<(r&63))) break;
9994 }
9995 k--;
9996 }
9997 if(i<slen-1) {
9998 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9999 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10000 //printf("bad match after branch\n");
10001 break;
10002 }
10003 }
10004 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
10005 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10006 while(k<i) {
10007 regs[k].regmap_entry[hr]=f_regmap[hr];
10008 regs[k].regmap[hr]=f_regmap[hr];
10009 regmap_pre[k+1][hr]=f_regmap[hr];
10010 regs[k].wasdirty&=~(1<<hr);
10011 regs[k].dirty&=~(1<<hr);
10012 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
10013 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
10014 regs[k].wasconst&=~(1<<hr);
10015 regs[k].isconst&=~(1<<hr);
10016 k++;
10017 }
10018 }
10019 else {
10020 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10021 break;
10022 }
10023 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10024 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
10025 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10026 regs[i].regmap_entry[hr]=f_regmap[hr];
10027 regs[i].regmap[hr]=f_regmap[hr];
10028 regs[i].wasdirty&=~(1<<hr);
10029 regs[i].dirty&=~(1<<hr);
10030 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
10031 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
10032 regs[i].wasconst&=~(1<<hr);
10033 regs[i].isconst&=~(1<<hr);
10034 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10035 branch_regs[i].wasdirty&=~(1<<hr);
10036 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
10037 branch_regs[i].regmap[hr]=f_regmap[hr];
10038 branch_regs[i].dirty&=~(1<<hr);
10039 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
10040 branch_regs[i].wasconst&=~(1<<hr);
10041 branch_regs[i].isconst&=~(1<<hr);
10042 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10043 regmap_pre[i+2][hr]=f_regmap[hr];
10044 regs[i+2].wasdirty&=~(1<<hr);
10045 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10046 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10047 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10048 }
10049 }
10050 }
10051 for(k=t;k<j;k++) {
e1190b87 10052 // Alloc register clean at beginning of loop,
10053 // but may dirty it in pass 6
57871462 10054 regs[k].regmap_entry[hr]=f_regmap[hr];
10055 regs[k].regmap[hr]=f_regmap[hr];
57871462 10056 regs[k].dirty&=~(1<<hr);
10057 regs[k].wasconst&=~(1<<hr);
10058 regs[k].isconst&=~(1<<hr);
e1190b87 10059 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10060 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10061 branch_regs[k].regmap[hr]=f_regmap[hr];
10062 branch_regs[k].dirty&=~(1<<hr);
10063 branch_regs[k].wasconst&=~(1<<hr);
10064 branch_regs[k].isconst&=~(1<<hr);
10065 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10066 regmap_pre[k+2][hr]=f_regmap[hr];
10067 regs[k+2].wasdirty&=~(1<<hr);
10068 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10069 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10070 }
10071 }
10072 else
10073 {
10074 regmap_pre[k+1][hr]=f_regmap[hr];
10075 regs[k+1].wasdirty&=~(1<<hr);
10076 }
57871462 10077 }
10078 if(regs[j].regmap[hr]==f_regmap[hr])
10079 regs[j].regmap_entry[hr]=f_regmap[hr];
10080 break;
10081 }
10082 if(j==i) break;
10083 if(regs[j].regmap[hr]>=0)
10084 break;
10085 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10086 //printf("no-match due to different register\n");
10087 break;
10088 }
10089 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10090 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10091 break;
10092 }
e1190b87 10093 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10094 {
10095 // Stop on unconditional branch
10096 break;
10097 }
10098 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10099 {
10100 if(ooo[j]) {
10101 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10102 break;
10103 }else{
10104 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10105 break;
10106 }
10107 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10108 //printf("no-match due to different register (branch)\n");
57871462 10109 break;
10110 }
10111 }
e1190b87 10112 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10113 //printf("No free regs for store %x\n",start+j*4);
10114 break;
10115 }
57871462 10116 if(f_regmap[hr]>=64) {
10117 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10118 break;
10119 }
10120 else
10121 {
10122 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10123 break;
10124 }
10125 }
10126 }
10127 }
10128 }
10129 }
10130 }
10131 }
10132 }else{
10133 int count=0;
10134 for(hr=0;hr<HOST_REGS;hr++)
10135 {
10136 if(hr!=EXCLUDE_REG) {
10137 if(regs[i].regmap[hr]>64) {
10138 if(!((regs[i].dirty>>hr)&1))
10139 f_regmap[hr]=regs[i].regmap[hr];
10140 }
b372a952 10141 else if(regs[i].regmap[hr]>=0) {
10142 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10143 // dealloc old register
10144 int n;
10145 for(n=0;n<HOST_REGS;n++)
10146 {
10147 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10148 }
10149 // and alloc new one
10150 f_regmap[hr]=regs[i].regmap[hr];
10151 }
10152 }
57871462 10153 else if(regs[i].regmap[hr]<0) count++;
10154 }
10155 }
10156 // Try to restore cycle count at branch targets
10157 if(bt[i]) {
10158 for(j=i;j<slen-1;j++) {
10159 if(regs[j].regmap[HOST_CCREG]!=-1) break;
e1190b87 10160 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10161 //printf("no free regs for store %x\n",start+j*4);
10162 break;
57871462 10163 }
57871462 10164 }
10165 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10166 int k=i;
10167 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10168 while(k<j) {
10169 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10170 regs[k].regmap[HOST_CCREG]=CCREG;
10171 regmap_pre[k+1][HOST_CCREG]=CCREG;
10172 regs[k+1].wasdirty|=1<<HOST_CCREG;
10173 regs[k].dirty|=1<<HOST_CCREG;
10174 regs[k].wasconst&=~(1<<HOST_CCREG);
10175 regs[k].isconst&=~(1<<HOST_CCREG);
10176 k++;
10177 }
10178 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10179 }
10180 // Work backwards from the branch target
10181 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10182 {
10183 //printf("Extend backwards\n");
10184 int k;
10185 k=i;
10186 while(regs[k-1].regmap[HOST_CCREG]==-1) {
e1190b87 10187 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10188 //printf("no free regs for store %x\n",start+(k-1)*4);
10189 break;
57871462 10190 }
57871462 10191 k--;
10192 }
10193 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10194 //printf("Extend CC, %x ->\n",start+k*4);
10195 while(k<=i) {
10196 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10197 regs[k].regmap[HOST_CCREG]=CCREG;
10198 regmap_pre[k+1][HOST_CCREG]=CCREG;
10199 regs[k+1].wasdirty|=1<<HOST_CCREG;
10200 regs[k].dirty|=1<<HOST_CCREG;
10201 regs[k].wasconst&=~(1<<HOST_CCREG);
10202 regs[k].isconst&=~(1<<HOST_CCREG);
10203 k++;
10204 }
10205 }
10206 else {
10207 //printf("Fail Extend CC, %x ->\n",start+k*4);
10208 }
10209 }
10210 }
10211 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10212 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10213 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
e1190b87 10214 itype[i]!=FCONV&&itype[i]!=FCOMP)
57871462 10215 {
10216 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10217 }
10218 }
10219 }
10220
10221 // This allocates registers (if possible) one instruction prior
10222 // to use, which can avoid a load-use penalty on certain CPUs.
10223 for(i=0;i<slen-1;i++)
10224 {
10225 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10226 {
10227 if(!bt[i+1])
10228 {
b9b61529 10229 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10230 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
57871462 10231 {
10232 if(rs1[i+1]) {
10233 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10234 {
10235 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10236 {
10237 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10238 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10239 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10240 regs[i].isconst&=~(1<<hr);
10241 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10242 constmap[i][hr]=constmap[i+1][hr];
10243 regs[i+1].wasdirty&=~(1<<hr);
10244 regs[i].dirty&=~(1<<hr);
10245 }
10246 }
10247 }
10248 if(rs2[i+1]) {
10249 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10250 {
10251 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10252 {
10253 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10254 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10255 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10256 regs[i].isconst&=~(1<<hr);
10257 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10258 constmap[i][hr]=constmap[i+1][hr];
10259 regs[i+1].wasdirty&=~(1<<hr);
10260 regs[i].dirty&=~(1<<hr);
10261 }
10262 }
10263 }
10264 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10265 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10266 {
10267 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10268 {
10269 regs[i].regmap[hr]=rs1[i+1];
10270 regmap_pre[i+1][hr]=rs1[i+1];
10271 regs[i+1].regmap_entry[hr]=rs1[i+1];
10272 regs[i].isconst&=~(1<<hr);
10273 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10274 constmap[i][hr]=constmap[i+1][hr];
10275 regs[i+1].wasdirty&=~(1<<hr);
10276 regs[i].dirty&=~(1<<hr);
10277 }
10278 }
10279 }
10280 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10281 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10282 {
10283 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10284 {
10285 regs[i].regmap[hr]=rs1[i+1];
10286 regmap_pre[i+1][hr]=rs1[i+1];
10287 regs[i+1].regmap_entry[hr]=rs1[i+1];
10288 regs[i].isconst&=~(1<<hr);
10289 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10290 constmap[i][hr]=constmap[i+1][hr];
10291 regs[i+1].wasdirty&=~(1<<hr);
10292 regs[i].dirty&=~(1<<hr);
10293 }
10294 }
10295 }
10296 #ifndef HOST_IMM_ADDR32
b9b61529 10297 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 10298 hr=get_reg(regs[i+1].regmap,TLREG);
10299 if(hr>=0) {
10300 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10301 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10302 int nr;
10303 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10304 {
10305 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10306 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10307 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10308 regs[i].isconst&=~(1<<hr);
10309 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10310 constmap[i][hr]=constmap[i+1][hr];
10311 regs[i+1].wasdirty&=~(1<<hr);
10312 regs[i].dirty&=~(1<<hr);
10313 }
10314 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10315 {
10316 // move it to another register
10317 regs[i+1].regmap[hr]=-1;
10318 regmap_pre[i+2][hr]=-1;
10319 regs[i+1].regmap[nr]=TLREG;
10320 regmap_pre[i+2][nr]=TLREG;
10321 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10322 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10323 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10324 regs[i].isconst&=~(1<<nr);
10325 regs[i+1].isconst&=~(1<<nr);
10326 regs[i].dirty&=~(1<<nr);
10327 regs[i+1].wasdirty&=~(1<<nr);
10328 regs[i+1].dirty&=~(1<<nr);
10329 regs[i+2].wasdirty&=~(1<<nr);
10330 }
10331 }
10332 }
10333 }
10334 #endif
b9b61529 10335 if(itype[i+1]==STORE||itype[i+1]==STORELR
10336 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
57871462 10337 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10338 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10339 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10340 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10341 assert(hr>=0);
10342 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10343 {
10344 regs[i].regmap[hr]=rs1[i+1];
10345 regmap_pre[i+1][hr]=rs1[i+1];
10346 regs[i+1].regmap_entry[hr]=rs1[i+1];
10347 regs[i].isconst&=~(1<<hr);
10348 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10349 constmap[i][hr]=constmap[i+1][hr];
10350 regs[i+1].wasdirty&=~(1<<hr);
10351 regs[i].dirty&=~(1<<hr);
10352 }
10353 }
10354 }
b9b61529 10355 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
57871462 10356 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10357 int nr;
10358 hr=get_reg(regs[i+1].regmap,FTEMP);
10359 assert(hr>=0);
10360 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10361 {
10362 regs[i].regmap[hr]=rs1[i+1];
10363 regmap_pre[i+1][hr]=rs1[i+1];
10364 regs[i+1].regmap_entry[hr]=rs1[i+1];
10365 regs[i].isconst&=~(1<<hr);
10366 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10367 constmap[i][hr]=constmap[i+1][hr];
10368 regs[i+1].wasdirty&=~(1<<hr);
10369 regs[i].dirty&=~(1<<hr);
10370 }
10371 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10372 {
10373 // move it to another register
10374 regs[i+1].regmap[hr]=-1;
10375 regmap_pre[i+2][hr]=-1;
10376 regs[i+1].regmap[nr]=FTEMP;
10377 regmap_pre[i+2][nr]=FTEMP;
10378 regs[i].regmap[nr]=rs1[i+1];
10379 regmap_pre[i+1][nr]=rs1[i+1];
10380 regs[i+1].regmap_entry[nr]=rs1[i+1];
10381 regs[i].isconst&=~(1<<nr);
10382 regs[i+1].isconst&=~(1<<nr);
10383 regs[i].dirty&=~(1<<nr);
10384 regs[i+1].wasdirty&=~(1<<nr);
10385 regs[i+1].dirty&=~(1<<nr);
10386 regs[i+2].wasdirty&=~(1<<nr);
10387 }
10388 }
10389 }
b9b61529 10390 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
57871462 10391 if(itype[i+1]==LOAD)
10392 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
b9b61529 10393 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 10394 hr=get_reg(regs[i+1].regmap,FTEMP);
b9b61529 10395 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 10396 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10397 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10398 }
10399 if(hr>=0&&regs[i].regmap[hr]<0) {
10400 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10401 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10402 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10403 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10404 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10405 regs[i].isconst&=~(1<<hr);
10406 regs[i+1].wasdirty&=~(1<<hr);
10407 regs[i].dirty&=~(1<<hr);
10408 }
10409 }
10410 }
10411 }
10412 }
10413 }
10414 }
10415
10416 /* Pass 6 - Optimize clean/dirty state */
10417 clean_registers(0,slen-1,1);
10418
10419 /* Pass 7 - Identify 32-bit registers */
a28c6ce8 10420#ifndef FORCE32
57871462 10421 provisional_r32();
10422
10423 u_int r32=0;
10424
10425 for (i=slen-1;i>=0;i--)
10426 {
10427 int hr;
10428 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10429 {
10430 if(ba[i]<start || ba[i]>=(start+slen*4))
10431 {
10432 // Branch out of this block, don't need anything
10433 r32=0;
10434 }
10435 else
10436 {
10437 // Internal branch
10438 // Need whatever matches the target
10439 // (and doesn't get overwritten by the delay slot instruction)
10440 r32=0;
10441 int t=(ba[i]-start)>>2;
10442 if(ba[i]>start+i*4) {
10443 // Forward branch
10444 if(!(requires_32bit[t]&~regs[i].was32))
10445 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10446 }else{
10447 // Backward branch
10448 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10449 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10450 if(!(pr32[t]&~regs[i].was32))
10451 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10452 }
10453 }
10454 // Conditional branch may need registers for following instructions
10455 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10456 {
10457 if(i<slen-2) {
10458 r32|=requires_32bit[i+2];
10459 r32&=regs[i].was32;
10460 // Mark this address as a branch target since it may be called
10461 // upon return from interrupt
10462 bt[i+2]=1;
10463 }
10464 }
10465 // Merge in delay slot
10466 if(!likely[i]) {
10467 // These are overwritten unless the branch is "likely"
10468 // and the delay slot is nullified if not taken
10469 r32&=~(1LL<<rt1[i+1]);
10470 r32&=~(1LL<<rt2[i+1]);
10471 }
10472 // Assume these are needed (delay slot)
10473 if(us1[i+1]>0)
10474 {
10475 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10476 }
10477 if(us2[i+1]>0)
10478 {
10479 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10480 }
10481 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10482 {
10483 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10484 }
10485 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10486 {
10487 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10488 }
10489 }
1e973cb0 10490 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 10491 {
10492 // SYSCALL instruction (software interrupt)
10493 r32=0;
10494 }
10495 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10496 {
10497 // ERET instruction (return from interrupt)
10498 r32=0;
10499 }
10500 // Check 32 bits
10501 r32&=~(1LL<<rt1[i]);
10502 r32&=~(1LL<<rt2[i]);
10503 if(us1[i]>0)
10504 {
10505 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10506 }
10507 if(us2[i]>0)
10508 {
10509 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10510 }
10511 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10512 {
10513 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10514 }
10515 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10516 {
10517 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10518 }
10519 requires_32bit[i]=r32;
10520
10521 // Dirty registers which are 32-bit, require 32-bit input
10522 // as they will be written as 32-bit values
10523 for(hr=0;hr<HOST_REGS;hr++)
10524 {
10525 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10526 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10527 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10528 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10529 }
10530 }
10531 }
10532 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10533 }
04fd948a 10534#else
10535 for (i=slen-1;i>=0;i--)
10536 {
10537 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10538 {
10539 // Conditional branch
10540 if((source[i]>>16)!=0x1000&&i<slen-2) {
10541 // Mark this address as a branch target since it may be called
10542 // upon return from interrupt
10543 bt[i+2]=1;
10544 }
10545 }
10546 }
a28c6ce8 10547#endif
57871462 10548
10549 if(itype[slen-1]==SPAN) {
10550 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10551 }
10552
10553 /* Debug/disassembly */
10554 if((void*)assem_debug==(void*)printf)
10555 for(i=0;i<slen;i++)
10556 {
10557 printf("U:");
10558 int r;
10559 for(r=1;r<=CCREG;r++) {
10560 if((unneeded_reg[i]>>r)&1) {
10561 if(r==HIREG) printf(" HI");
10562 else if(r==LOREG) printf(" LO");
10563 else printf(" r%d",r);
10564 }
10565 }
90ae6d4e 10566#ifndef FORCE32
57871462 10567 printf(" UU:");
10568 for(r=1;r<=CCREG;r++) {
10569 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10570 if(r==HIREG) printf(" HI");
10571 else if(r==LOREG) printf(" LO");
10572 else printf(" r%d",r);
10573 }
10574 }
10575 printf(" 32:");
10576 for(r=0;r<=CCREG;r++) {
10577 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10578 if((regs[i].was32>>r)&1) {
10579 if(r==CCREG) printf(" CC");
10580 else if(r==HIREG) printf(" HI");
10581 else if(r==LOREG) printf(" LO");
10582 else printf(" r%d",r);
10583 }
10584 }
90ae6d4e 10585#endif
57871462 10586 printf("\n");
10587 #if defined(__i386__) || defined(__x86_64__)
10588 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10589 #endif
10590 #ifdef __arm__
10591 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10592 #endif
10593 printf("needs: ");
10594 if(needed_reg[i]&1) printf("eax ");
10595 if((needed_reg[i]>>1)&1) printf("ecx ");
10596 if((needed_reg[i]>>2)&1) printf("edx ");
10597 if((needed_reg[i]>>3)&1) printf("ebx ");
10598 if((needed_reg[i]>>5)&1) printf("ebp ");
10599 if((needed_reg[i]>>6)&1) printf("esi ");
10600 if((needed_reg[i]>>7)&1) printf("edi ");
10601 printf("r:");
10602 for(r=0;r<=CCREG;r++) {
10603 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10604 if((requires_32bit[i]>>r)&1) {
10605 if(r==CCREG) printf(" CC");
10606 else if(r==HIREG) printf(" HI");
10607 else if(r==LOREG) printf(" LO");
10608 else printf(" r%d",r);
10609 }
10610 }
10611 printf("\n");
10612 /*printf("pr:");
10613 for(r=0;r<=CCREG;r++) {
10614 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10615 if((pr32[i]>>r)&1) {
10616 if(r==CCREG) printf(" CC");
10617 else if(r==HIREG) printf(" HI");
10618 else if(r==LOREG) printf(" LO");
10619 else printf(" r%d",r);
10620 }
10621 }
10622 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10623 printf("\n");*/
10624 #if defined(__i386__) || defined(__x86_64__)
10625 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10626 printf("dirty: ");
10627 if(regs[i].wasdirty&1) printf("eax ");
10628 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10629 if((regs[i].wasdirty>>2)&1) printf("edx ");
10630 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10631 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10632 if((regs[i].wasdirty>>6)&1) printf("esi ");
10633 if((regs[i].wasdirty>>7)&1) printf("edi ");
10634 #endif
10635 #ifdef __arm__
10636 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10637 printf("dirty: ");
10638 if(regs[i].wasdirty&1) printf("r0 ");
10639 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10640 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10641 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10642 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10643 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10644 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10645 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10646 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10647 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10648 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10649 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10650 #endif
10651 printf("\n");
10652 disassemble_inst(i);
10653 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10654 #if defined(__i386__) || defined(__x86_64__)
10655 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10656 if(regs[i].dirty&1) printf("eax ");
10657 if((regs[i].dirty>>1)&1) printf("ecx ");
10658 if((regs[i].dirty>>2)&1) printf("edx ");
10659 if((regs[i].dirty>>3)&1) printf("ebx ");
10660 if((regs[i].dirty>>5)&1) printf("ebp ");
10661 if((regs[i].dirty>>6)&1) printf("esi ");
10662 if((regs[i].dirty>>7)&1) printf("edi ");
10663 #endif
10664 #ifdef __arm__
10665 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10666 if(regs[i].dirty&1) printf("r0 ");
10667 if((regs[i].dirty>>1)&1) printf("r1 ");
10668 if((regs[i].dirty>>2)&1) printf("r2 ");
10669 if((regs[i].dirty>>3)&1) printf("r3 ");
10670 if((regs[i].dirty>>4)&1) printf("r4 ");
10671 if((regs[i].dirty>>5)&1) printf("r5 ");
10672 if((regs[i].dirty>>6)&1) printf("r6 ");
10673 if((regs[i].dirty>>7)&1) printf("r7 ");
10674 if((regs[i].dirty>>8)&1) printf("r8 ");
10675 if((regs[i].dirty>>9)&1) printf("r9 ");
10676 if((regs[i].dirty>>10)&1) printf("r10 ");
10677 if((regs[i].dirty>>12)&1) printf("r12 ");
10678 #endif
10679 printf("\n");
10680 if(regs[i].isconst) {
10681 printf("constants: ");
10682 #if defined(__i386__) || defined(__x86_64__)
10683 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10684 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10685 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10686 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10687 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10688 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10689 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10690 #endif
10691 #ifdef __arm__
10692 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10693 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10694 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10695 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10696 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10697 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10698 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10699 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10700 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10701 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10702 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10703 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10704 #endif
10705 printf("\n");
10706 }
90ae6d4e 10707#ifndef FORCE32
57871462 10708 printf(" 32:");
10709 for(r=0;r<=CCREG;r++) {
10710 if((regs[i].is32>>r)&1) {
10711 if(r==CCREG) printf(" CC");
10712 else if(r==HIREG) printf(" HI");
10713 else if(r==LOREG) printf(" LO");
10714 else printf(" r%d",r);
10715 }
10716 }
10717 printf("\n");
90ae6d4e 10718#endif
57871462 10719 /*printf(" p32:");
10720 for(r=0;r<=CCREG;r++) {
10721 if((p32[i]>>r)&1) {
10722 if(r==CCREG) printf(" CC");
10723 else if(r==HIREG) printf(" HI");
10724 else if(r==LOREG) printf(" LO");
10725 else printf(" r%d",r);
10726 }
10727 }
10728 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10729 else printf("\n");*/
10730 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10731 #if defined(__i386__) || defined(__x86_64__)
10732 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10733 if(branch_regs[i].dirty&1) printf("eax ");
10734 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10735 if((branch_regs[i].dirty>>2)&1) printf("edx ");
10736 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10737 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10738 if((branch_regs[i].dirty>>6)&1) printf("esi ");
10739 if((branch_regs[i].dirty>>7)&1) printf("edi ");
10740 #endif
10741 #ifdef __arm__
10742 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10743 if(branch_regs[i].dirty&1) printf("r0 ");
10744 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10745 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10746 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10747 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10748 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10749 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10750 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10751 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10752 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10753 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10754 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10755 #endif
90ae6d4e 10756#ifndef FORCE32
57871462 10757 printf(" 32:");
10758 for(r=0;r<=CCREG;r++) {
10759 if((branch_regs[i].is32>>r)&1) {
10760 if(r==CCREG) printf(" CC");
10761 else if(r==HIREG) printf(" HI");
10762 else if(r==LOREG) printf(" LO");
10763 else printf(" r%d",r);
10764 }
10765 }
10766 printf("\n");
90ae6d4e 10767#endif
57871462 10768 }
10769 }
10770
10771 /* Pass 8 - Assembly */
10772 linkcount=0;stubcount=0;
10773 ds=0;is_delayslot=0;
10774 cop1_usable=0;
10775 uint64_t is32_pre=0;
10776 u_int dirty_pre=0;
10777 u_int beginning=(u_int)out;
10778 if((u_int)addr&1) {
10779 ds=1;
10780 pagespan_ds();
10781 }
9ad4d757 10782 u_int instr_addr0_override=0;
10783
10784#ifdef PCSX
10785 if (start == 0x80030000) {
10786 // nasty hack for fastbios thing
10787 instr_addr0_override=(u_int)out;
10788 emit_movimm(start,0);
10789 emit_readword((int)&pcaddr,1);
10790 emit_writeword(0,(int)&pcaddr);
10791 emit_cmp(0,1);
10792 emit_jne((int)new_dyna_leave);
10793 }
10794#endif
57871462 10795 for(i=0;i<slen;i++)
10796 {
10797 //if(ds) printf("ds: ");
10798 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10799 if(ds) {
10800 ds=0; // Skip delay slot
10801 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10802 instr_addr[i]=0;
10803 } else {
10804 #ifndef DESTRUCTIVE_WRITEBACK
10805 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10806 {
10807 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10808 unneeded_reg[i],unneeded_reg_upper[i]);
10809 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10810 unneeded_reg[i],unneeded_reg_upper[i]);
10811 }
10812 is32_pre=regs[i].is32;
10813 dirty_pre=regs[i].dirty;
10814 #endif
10815 // write back
10816 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10817 {
10818 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10819 unneeded_reg[i],unneeded_reg_upper[i]);
10820 loop_preload(regmap_pre[i],regs[i].regmap_entry);
10821 }
10822 // branch target entry point
10823 instr_addr[i]=(u_int)out;
10824 assem_debug("<->\n");
10825 // load regs
10826 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10827 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10828 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10829 address_generation(i,&regs[i],regs[i].regmap_entry);
10830 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10831 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10832 {
10833 // Load the delay slot registers if necessary
4ef8f67d 10834 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
57871462 10835 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
4ef8f67d 10836 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
57871462 10837 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
b9b61529 10838 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
57871462 10839 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10840 }
10841 else if(i+1<slen)
10842 {
10843 // Preload registers for following instruction
10844 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10845 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10846 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10847 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10848 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10849 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10850 }
10851 // TODO: if(is_ooo(i)) address_generation(i+1);
10852 if(itype[i]==CJUMP||itype[i]==FJUMP)
10853 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
b9b61529 10854 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
57871462 10855 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10856 if(bt[i]) cop1_usable=0;
10857 // assemble
10858 switch(itype[i]) {
10859 case ALU:
10860 alu_assemble(i,&regs[i]);break;
10861 case IMM16:
10862 imm16_assemble(i,&regs[i]);break;
10863 case SHIFT:
10864 shift_assemble(i,&regs[i]);break;
10865 case SHIFTIMM:
10866 shiftimm_assemble(i,&regs[i]);break;
10867 case LOAD:
10868 load_assemble(i,&regs[i]);break;
10869 case LOADLR:
10870 loadlr_assemble(i,&regs[i]);break;
10871 case STORE:
10872 store_assemble(i,&regs[i]);break;
10873 case STORELR:
10874 storelr_assemble(i,&regs[i]);break;
10875 case COP0:
10876 cop0_assemble(i,&regs[i]);break;
10877 case COP1:
10878 cop1_assemble(i,&regs[i]);break;
10879 case C1LS:
10880 c1ls_assemble(i,&regs[i]);break;
b9b61529 10881 case COP2:
10882 cop2_assemble(i,&regs[i]);break;
10883 case C2LS:
10884 c2ls_assemble(i,&regs[i]);break;
10885 case C2OP:
10886 c2op_assemble(i,&regs[i]);break;
57871462 10887 case FCONV:
10888 fconv_assemble(i,&regs[i]);break;
10889 case FLOAT:
10890 float_assemble(i,&regs[i]);break;
10891 case FCOMP:
10892 fcomp_assemble(i,&regs[i]);break;
10893 case MULTDIV:
10894 multdiv_assemble(i,&regs[i]);break;
10895 case MOV:
10896 mov_assemble(i,&regs[i]);break;
10897 case SYSCALL:
10898 syscall_assemble(i,&regs[i]);break;
7139f3c8 10899 case HLECALL:
10900 hlecall_assemble(i,&regs[i]);break;
1e973cb0 10901 case INTCALL:
10902 intcall_assemble(i,&regs[i]);break;
57871462 10903 case UJUMP:
10904 ujump_assemble(i,&regs[i]);ds=1;break;
10905 case RJUMP:
10906 rjump_assemble(i,&regs[i]);ds=1;break;
10907 case CJUMP:
10908 cjump_assemble(i,&regs[i]);ds=1;break;
10909 case SJUMP:
10910 sjump_assemble(i,&regs[i]);ds=1;break;
10911 case FJUMP:
10912 fjump_assemble(i,&regs[i]);ds=1;break;
10913 case SPAN:
10914 pagespan_assemble(i,&regs[i]);break;
10915 }
10916 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10917 literal_pool(1024);
10918 else
10919 literal_pool_jumpover(256);
10920 }
10921 }
10922 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10923 // If the block did not end with an unconditional branch,
10924 // add a jump to the next instruction.
10925 if(i>1) {
10926 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10927 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10928 assert(i==slen);
10929 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10930 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10931 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10932 emit_loadreg(CCREG,HOST_CCREG);
10933 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10934 }
10935 else if(!likely[i-2])
10936 {
10937 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10938 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10939 }
10940 else
10941 {
10942 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10943 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10944 }
10945 add_to_linker((int)out,start+i*4,0);
10946 emit_jmp(0);
10947 }
10948 }
10949 else
10950 {
10951 assert(i>0);
10952 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10953 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10954 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10955 emit_loadreg(CCREG,HOST_CCREG);
10956 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10957 add_to_linker((int)out,start+i*4,0);
10958 emit_jmp(0);
10959 }
10960
10961 // TODO: delay slot stubs?
10962 // Stubs
10963 for(i=0;i<stubcount;i++)
10964 {
10965 switch(stubs[i][0])
10966 {
10967 case LOADB_STUB:
10968 case LOADH_STUB:
10969 case LOADW_STUB:
10970 case LOADD_STUB:
10971 case LOADBU_STUB:
10972 case LOADHU_STUB:
10973 do_readstub(i);break;
10974 case STOREB_STUB:
10975 case STOREH_STUB:
10976 case STOREW_STUB:
10977 case STORED_STUB:
10978 do_writestub(i);break;
10979 case CC_STUB:
10980 do_ccstub(i);break;
10981 case INVCODE_STUB:
10982 do_invstub(i);break;
10983 case FP_STUB:
10984 do_cop1stub(i);break;
10985 case STORELR_STUB:
10986 do_unalignedwritestub(i);break;
10987 }
10988 }
10989
9ad4d757 10990 if (instr_addr0_override)
10991 instr_addr[0] = instr_addr0_override;
10992
57871462 10993 /* Pass 9 - Linker */
10994 for(i=0;i<linkcount;i++)
10995 {
10996 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10997 literal_pool(64);
10998 if(!link_addr[i][2])
10999 {
11000 void *stub=out;
11001 void *addr=check_addr(link_addr[i][1]);
11002 emit_extjump(link_addr[i][0],link_addr[i][1]);
11003 if(addr) {
11004 set_jump_target(link_addr[i][0],(int)addr);
11005 add_link(link_addr[i][1],stub);
11006 }
11007 else set_jump_target(link_addr[i][0],(int)stub);
11008 }
11009 else
11010 {
11011 // Internal branch
11012 int target=(link_addr[i][1]-start)>>2;
11013 assert(target>=0&&target<slen);
11014 assert(instr_addr[target]);
11015 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11016 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11017 //#else
11018 set_jump_target(link_addr[i][0],instr_addr[target]);
11019 //#endif
11020 }
11021 }
11022 // External Branch Targets (jump_in)
11023 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11024 for(i=0;i<slen;i++)
11025 {
11026 if(bt[i]||i==0)
11027 {
11028 if(instr_addr[i]) // TODO - delay slots (=null)
11029 {
11030 u_int vaddr=start+i*4;
94d23bb9 11031 u_int page=get_page(vaddr);
11032 u_int vpage=get_vpage(vaddr);
57871462 11033 literal_pool(256);
11034 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
a28c6ce8 11035#ifndef FORCE32
57871462 11036 if(!requires_32bit[i])
a28c6ce8 11037#else
11038 if(1)
11039#endif
57871462 11040 {
11041 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11042 assem_debug("jump_in: %x\n",start+i*4);
11043 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11044 int entry_point=do_dirty_stub(i);
11045 ll_add(jump_in+page,vaddr,(void *)entry_point);
11046 // If there was an existing entry in the hash table,
11047 // replace it with the new address.
11048 // Don't add new entries. We'll insert the
11049 // ones that actually get used in check_addr().
11050 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11051 if(ht_bin[0]==vaddr) {
11052 ht_bin[1]=entry_point;
11053 }
11054 if(ht_bin[2]==vaddr) {
11055 ht_bin[3]=entry_point;
11056 }
11057 }
11058 else
11059 {
11060 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11061 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11062 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11063 //int entry_point=(int)out;
11064 ////assem_debug("entry_point: %x\n",entry_point);
11065 //load_regs_entry(i);
11066 //if(entry_point==(int)out)
11067 // entry_point=instr_addr[i];
11068 //else
11069 // emit_jmp(instr_addr[i]);
11070 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11071 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11072 int entry_point=do_dirty_stub(i);
11073 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11074 }
11075 }
11076 }
11077 }
11078 // Write out the literal pool if necessary
11079 literal_pool(0);
11080 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11081 // Align code
11082 if(((u_int)out)&7) emit_addnop(13);
11083 #endif
11084 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11085 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11086 memcpy(copy,source,slen*4);
11087 copy+=slen*4;
11088
11089 #ifdef __arm__
11090 __clear_cache((void *)beginning,out);
11091 #endif
11092
11093 // If we're within 256K of the end of the buffer,
11094 // start over from the beginning. (Is 256K enough?)
11095 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11096
11097 // Trap writes to any of the pages we compiled
11098 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11099 invalid_code[i]=0;
90ae6d4e 11100#ifndef DISABLE_TLB
57871462 11101 memory_map[i]|=0x40000000;
11102 if((signed int)start>=(signed int)0xC0000000) {
11103 assert(using_tlb);
11104 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11105 invalid_code[j]=0;
11106 memory_map[j]|=0x40000000;
11107 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11108 }
90ae6d4e 11109#endif
57871462 11110 }
b12c9fb8 11111#ifdef PCSX
11112 // PCSX maps all RAM mirror invalid_code tests to 0x80000000..0x80000000+RAM_SIZE
11113 if(get_page(start)<(RAM_SIZE>>12))
11114 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11115 invalid_code[((u_int)0x80000000>>12)|i]=0;
11116#endif
57871462 11117
11118 /* Pass 10 - Free memory by expiring oldest blocks */
11119
11120 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11121 while(expirep!=end)
11122 {
11123 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11124 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11125 inv_debug("EXP: Phase %d\n",expirep);
11126 switch((expirep>>11)&3)
11127 {
11128 case 0:
11129 // Clear jump_in and jump_dirty
11130 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11131 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11132 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11133 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11134 break;
11135 case 1:
11136 // Clear pointers
11137 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11138 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11139 break;
11140 case 2:
11141 // Clear hash table
11142 for(i=0;i<32;i++) {
11143 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11144 if((ht_bin[3]>>shift)==(base>>shift) ||
11145 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11146 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11147 ht_bin[2]=ht_bin[3]=-1;
11148 }
11149 if((ht_bin[1]>>shift)==(base>>shift) ||
11150 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11151 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11152 ht_bin[0]=ht_bin[2];
11153 ht_bin[1]=ht_bin[3];
11154 ht_bin[2]=ht_bin[3]=-1;
11155 }
11156 }
11157 break;
11158 case 3:
11159 // Clear jump_out
dd3a91a1 11160 #ifdef __arm__
11161 if((expirep&2047)==0)
11162 do_clear_cache();
11163 #endif
57871462 11164 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11165 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11166 break;
11167 }
11168 expirep=(expirep+1)&65535;
11169 }
11170 return 0;
11171}
b9b61529 11172
11173// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork