7e605697 |
1 | /* |
274c4243 |
2 | * (C) GraÅžvydas "notaz" Ignotas, 2010-2011 |
7e605697 |
3 | * |
4 | * This work is licensed under the terms of GNU GPL version 2 or later. |
5 | * See the COPYING file in the top-level directory. |
6 | */ |
7 | |
8 | #include <stdio.h> |
c6c3b1b3 |
9 | #include <sys/mman.h> |
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10 | #include "../psxhw.h" |
11 | #include "../cdrom.h" |
12 | #include "../mdec.h" |
13 | #include "emu_if.h" |
14 | #include "pcsxmem.h" |
15 | |
16 | //#define memprintf printf |
17 | #define memprintf(...) |
18 | |
b1be1eee |
19 | static u32 *mem_readtab; |
20 | static u32 *mem_writetab; |
21 | static u32 mem_iortab[(1+2+4) * 0x1000 / 4]; |
22 | static u32 mem_iowtab[(1+2+4) * 0x1000 / 4]; |
23 | static u32 mem_ffwtab[(1+2+4) * 0x1000 / 4]; |
24 | //static u32 mem_unmrtab[(1+2+4) * 0x1000 / 4]; |
25 | static u32 mem_unmwtab[(1+2+4) * 0x1000 / 4]; |
26 | |
27 | static void map_item(u32 *out, const void *h, u32 flag) |
28 | { |
29 | u32 hv = (u32)h; |
30 | if (hv & 1) |
31 | fprintf(stderr, "%p has LSB set\n", h); |
32 | *out = (hv >> 1) | (flag << 31); |
33 | } |
34 | |
35 | // size must be power of 2, at least 4k |
36 | #define map_l1_mem(tab, i, addr, size, base) \ |
37 | map_item(&tab[((addr)>>12) + i], (u8 *)(base) - (u32)(addr) - ((i << 12) & ~(size - 1)), 0) |
38 | |
39 | #define IOMEM32(a) (((a) & 0xfff) / 4) |
40 | #define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2)) |
41 | #define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff)) |
42 | |
054175e9 |
43 | u8 zero_mem[0x1000]; |
7a481d40 |
44 | |
63cb0298 |
45 | u32 read_mem_dummy() |
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46 | { |
63cb0298 |
47 | return 0; |
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48 | } |
49 | |
b96d3df7 |
50 | static void write_mem_dummy(u32 data) |
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51 | { |
b96d3df7 |
52 | memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle); |
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53 | } |
54 | |
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55 | /* IO handlers */ |
56 | static u32 io_read_sio16() |
57 | { |
58 | return sioRead8() | (sioRead8() << 8); |
59 | } |
60 | |
61 | static u32 io_read_sio32() |
62 | { |
63 | return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24); |
64 | } |
65 | |
66 | static void io_write_sio16(u32 value) |
67 | { |
68 | sioWrite8((unsigned char)value); |
69 | sioWrite8((unsigned char)(value>>8)); |
70 | } |
71 | |
72 | static void io_write_sio32(u32 value) |
73 | { |
74 | sioWrite8((unsigned char)value); |
b96d3df7 |
75 | sioWrite8((unsigned char)(value >> 8)); |
76 | sioWrite8((unsigned char)(value >> 16)); |
77 | sioWrite8((unsigned char)(value >> 24)); |
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78 | } |
79 | |
b1be1eee |
80 | static void map_rcnt_rcount0(u32 mode) |
81 | { |
59fb0bb4 |
82 | if (mode & 0x100) { // pixel clock |
b1be1eee |
83 | map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1); |
84 | map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1); |
85 | } |
86 | else { |
87 | map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1); |
88 | map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1); |
89 | } |
90 | } |
91 | |
92 | static void map_rcnt_rcount1(u32 mode) |
93 | { |
59fb0bb4 |
94 | if (mode & 0x100) { // hcnt |
b1be1eee |
95 | map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1); |
96 | map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1); |
97 | } |
98 | else { |
99 | map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1); |
100 | map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1); |
101 | } |
102 | } |
103 | |
104 | static void map_rcnt_rcount2(u32 mode) |
105 | { |
106 | if (mode & 0x01) { // gate |
107 | map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0); |
108 | map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0); |
109 | } |
110 | else if (mode & 0x200) { // clk/8 |
111 | map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1); |
112 | map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1); |
113 | } |
114 | else { |
115 | map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1); |
116 | map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1); |
117 | } |
118 | } |
119 | |
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120 | #define make_rcnt_funcs(i) \ |
121 | static u32 io_rcnt_read_count##i() { return psxRcntRcount(i); } \ |
122 | static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \ |
123 | static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \ |
124 | static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \ |
b1be1eee |
125 | static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \ |
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126 | static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); } |
127 | |
128 | make_rcnt_funcs(0) |
129 | make_rcnt_funcs(1) |
130 | make_rcnt_funcs(2) |
131 | |
132 | static void io_write_ireg16(u32 value) |
133 | { |
134 | if (Config.Sio) psxHu16ref(0x1070) |= 0x80; |
135 | if (Config.SpuIrq) psxHu16ref(0x1070) |= 0x200; |
136 | psxHu16ref(0x1070) &= psxHu16(0x1074) & value; |
137 | } |
138 | |
139 | static void io_write_imask16(u32 value) |
140 | { |
141 | psxHu16ref(0x1074) = value; |
142 | if (psxHu16ref(0x1070) & value) |
d28b54b1 |
143 | new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1); |
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144 | } |
145 | |
146 | static void io_write_ireg32(u32 value) |
147 | { |
148 | if (Config.Sio) psxHu32ref(0x1070) |= 0x80; |
149 | if (Config.SpuIrq) psxHu32ref(0x1070) |= 0x200; |
150 | psxHu32ref(0x1070) &= psxHu32(0x1074) & value; |
151 | } |
152 | |
153 | static void io_write_imask32(u32 value) |
154 | { |
155 | psxHu32ref(0x1074) = value; |
156 | if (psxHu32ref(0x1070) & value) |
d28b54b1 |
157 | new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1); |
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158 | } |
159 | |
160 | static void io_write_dma_icr32(u32 value) |
161 | { |
1f77c863 |
162 | u32 tmp = value & 0x00ff803f; |
163 | tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000; |
164 | if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000) |
165 | || tmp & HW_DMA_ICR_BUS_ERROR) { |
166 | if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT)) |
167 | psxHu32ref(0x1070) |= SWAP32(8); |
168 | tmp |= HW_DMA_ICR_IRQ_SENT; |
169 | } |
170 | HW_DMA_ICR = SWAPu32(tmp); |
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171 | } |
172 | |
173 | #define make_dma_func(n) \ |
174 | static void io_write_chcr##n(u32 value) \ |
175 | { \ |
176 | HW_DMA##n##_CHCR = value; \ |
177 | if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \ |
178 | psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \ |
179 | } \ |
180 | } |
181 | |
182 | make_dma_func(0) |
183 | make_dma_func(1) |
184 | make_dma_func(2) |
185 | make_dma_func(3) |
186 | make_dma_func(4) |
187 | make_dma_func(6) |
188 | |
b96d3df7 |
189 | static void io_spu_write16(u32 value) |
190 | { |
191 | // meh |
192 | SPU_writeRegister(address, value); |
193 | } |
194 | |
195 | static void io_spu_write32(u32 value) |
196 | { |
197 | SPUwriteRegister wfunc = SPU_writeRegister; |
198 | u32 a = address; |
199 | |
200 | wfunc(a, value & 0xffff); |
201 | wfunc(a + 2, value >> 16); |
202 | } |
203 | |
b96d3df7 |
204 | static void map_ram_write(void) |
205 | { |
206 | int i; |
207 | |
208 | for (i = 0; i < (0x800000 >> 12); i++) { |
209 | map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM); |
210 | map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM); |
211 | map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM); |
212 | } |
213 | } |
214 | |
215 | static void unmap_ram_write(void) |
216 | { |
217 | int i; |
218 | |
219 | for (i = 0; i < (0x800000 >> 12); i++) { |
220 | map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1); |
221 | map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1); |
222 | map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1); |
223 | } |
224 | } |
225 | |
226 | static void write_biu(u32 value) |
227 | { |
228 | memprintf("write_biu %08x, %08x @%08x %u\n", address, value, psxRegs.pc, psxRegs.cycle); |
229 | |
230 | if (address != 0xfffe0130) |
231 | return; |
232 | |
233 | switch (value) { |
234 | case 0x800: case 0x804: |
235 | unmap_ram_write(); |
236 | break; |
237 | case 0: case 0x1e988: |
238 | map_ram_write(); |
239 | break; |
240 | default: |
241 | printf("write_biu: unexpected val: %08x\n", value); |
242 | break; |
243 | } |
244 | } |
245 | |
b1be1eee |
246 | void new_dyna_pcsx_mem_load_state(void) |
247 | { |
248 | map_rcnt_rcount0(rcnts[0].mode); |
249 | map_rcnt_rcount1(rcnts[1].mode); |
250 | map_rcnt_rcount2(rcnts[2].mode); |
251 | } |
252 | |
253 | int pcsxmem_is_handler_dynamic(u_int addr) |
254 | { |
255 | if ((addr & 0xfffff000) != 0x1f801000) |
256 | return 0; |
257 | |
258 | addr &= 0xffff; |
259 | return addr == 0x1100 || addr == 0x1110 || addr == 0x1120; |
260 | } |
261 | |
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262 | void new_dyna_pcsx_mem_init(void) |
263 | { |
264 | int i; |
63cb0298 |
265 | |
c6c3b1b3 |
266 | // have to map these further to keep tcache close to .text |
267 | mem_readtab = mmap((void *)0x08000000, 0x200000 * 4, PROT_READ | PROT_WRITE, |
268 | MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); |
269 | if (mem_readtab == MAP_FAILED) { |
270 | fprintf(stderr, "failed to map mem tables\n"); |
271 | exit(1); |
272 | } |
273 | mem_writetab = mem_readtab + 0x100000; |
274 | |
275 | // 1st level lookup: |
276 | // 0: direct mem |
277 | // 1: use 2nd lookup |
278 | // 2nd level lookup: |
279 | // 0: direct mem variable |
280 | // 1: memhandler |
281 | |
282 | // default/unmapped memhandlers |
283 | for (i = 0; i < 0x100000; i++) { |
284 | //map_item(&mem_readtab[i], mem_unmrtab, 1); |
054175e9 |
285 | map_l1_mem(mem_readtab, i, 0, 0x1000, zero_mem); |
c6c3b1b3 |
286 | map_item(&mem_writetab[i], mem_unmwtab, 1); |
287 | } |
288 | |
289 | // RAM and it's mirrors |
290 | for (i = 0; i < (0x800000 >> 12); i++) { |
291 | map_l1_mem(mem_readtab, i, 0x80000000, 0x200000, psxM); |
c6c3b1b3 |
292 | map_l1_mem(mem_readtab, i, 0x00000000, 0x200000, psxM); |
c6c3b1b3 |
293 | map_l1_mem(mem_readtab, i, 0xa0000000, 0x200000, psxM); |
c6c3b1b3 |
294 | } |
b96d3df7 |
295 | map_ram_write(); |
c6c3b1b3 |
296 | |
297 | // BIOS and it's mirrors |
298 | for (i = 0; i < (0x80000 >> 12); i++) { |
299 | map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR); |
300 | map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR); |
301 | } |
302 | |
303 | // scratchpad |
304 | map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH); |
305 | map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH); |
306 | |
307 | // I/O |
308 | map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1); |
309 | map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1); |
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310 | |
c6c3b1b3 |
311 | // L2 |
312 | // unmapped tables |
b96d3df7 |
313 | for (i = 0; i < (1+2+4) * 0x1000 / 4; i++) |
c6c3b1b3 |
314 | map_item(&mem_unmwtab[i], write_mem_dummy, 1); |
315 | |
316 | // fill IO tables |
317 | for (i = 0; i < 0x1000/4; i++) { |
318 | map_item(&mem_iortab[i], &psxH[0x1000], 0); |
319 | map_item(&mem_iowtab[i], &psxH[0x1000], 0); |
320 | } |
321 | for (; i < 0x1000/4 + 0x1000/2; i++) { |
322 | map_item(&mem_iortab[i], &psxH[0x1000], 0); |
323 | map_item(&mem_iowtab[i], &psxH[0x1000], 0); |
324 | } |
325 | for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) { |
326 | map_item(&mem_iortab[i], &psxH[0x1000], 0); |
327 | map_item(&mem_iowtab[i], &psxH[0x1000], 0); |
328 | } |
329 | |
330 | map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1); |
331 | map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1); |
332 | map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1); |
333 | map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1); |
334 | map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1); |
335 | map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1); |
336 | map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1); |
337 | map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1); |
338 | map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1); |
339 | map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1); |
340 | // map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1); |
341 | // map_item(&mem_iortab[IOMEM32(0x1814)], GPU_readStatus, 1); |
342 | map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1); |
343 | map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1); |
344 | |
345 | map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1); |
346 | map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1); |
347 | map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1); |
348 | map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1); |
349 | map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1); |
350 | map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1); |
351 | map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1); |
352 | map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1); |
353 | map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1); |
354 | map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1); |
355 | map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1); |
356 | map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1); |
357 | map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1); |
358 | map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1); |
359 | |
360 | map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1); |
361 | map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1); |
362 | map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1); |
363 | map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1); |
364 | map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1); |
365 | |
b96d3df7 |
366 | // write(u32 data) |
367 | map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1); |
368 | map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1); |
369 | map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1); |
370 | map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1); |
371 | map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1); |
372 | map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1); |
373 | map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1); |
374 | map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1); |
375 | map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1); |
376 | map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1); |
377 | map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1); |
378 | map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1); |
379 | map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1); |
380 | map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1); |
381 | map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1); |
382 | map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1); |
383 | map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1); |
384 | map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1); |
385 | map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1); |
386 | // map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1); |
387 | // map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1); |
388 | map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1); |
389 | map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1); |
390 | |
391 | map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1); |
392 | map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1); |
393 | map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1); |
394 | map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1); |
395 | map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1); |
396 | map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1); |
397 | map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1); |
398 | map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1); |
399 | map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1); |
400 | map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1); |
401 | map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1); |
402 | map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1); |
403 | map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1); |
404 | map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1); |
405 | map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1); |
406 | map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1); |
407 | |
408 | map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1); |
409 | map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1); |
410 | map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1); |
411 | map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1); |
412 | map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1); |
413 | |
414 | for (i = 0x1c00; i < 0x1e00; i += 2) { |
415 | map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1); |
416 | map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1); |
417 | } |
418 | |
419 | // misc |
420 | map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1); |
421 | for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) |
422 | map_item(&mem_ffwtab[i], write_biu, 1); |
423 | |
c6c3b1b3 |
424 | mem_rtab = mem_readtab; |
425 | mem_wtab = mem_writetab; |
b1be1eee |
426 | |
427 | new_dyna_pcsx_mem_load_state(); |
7e605697 |
428 | } |
429 | |
430 | void new_dyna_pcsx_mem_reset(void) |
431 | { |
c6c3b1b3 |
432 | int i; |
433 | |
7e605697 |
434 | // plugins might change so update the pointers |
c6c3b1b3 |
435 | map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1); |
436 | map_item(&mem_iortab[IOMEM32(0x1814)], GPU_readStatus, 1); |
437 | |
438 | for (i = 0x1c00; i < 0x1e00; i += 2) |
439 | map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1); |
440 | |
b96d3df7 |
441 | map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1); |
442 | map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1); |
7e605697 |
443 | } |