libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2011 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24 #include <errno.h>
  25 #include <sys/mman.h>
  26
  27 #include "emu_if.h" //emulator interface
  28
  29 //#define DISASM
  30 //#define assem_debug printf
  31 //#define inv_debug printf
  32 #define assem_debug(...)
  33 #define inv_debug(...)
  34
  35 #ifdef __i386__
  36 #include "assem_x86.h"
  37 #endif
  38 #ifdef __x86_64__
  39 #include "assem_x64.h"
  40 #endif
  41 #ifdef __arm__
  42 #include "assem_arm.h"
  43 #endif
  44
  45 #ifdef __BLACKBERRY_QNX__
  46 #undef __clear_cache
  47 #define __clear_cache(start,end) msync(start, (size_t)((void*)end - (void*)start), MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
  48 #elif defined(__MACH__)
  49 #include <libkern/OSCacheControl.h>
  50 #define __clear_cache mach_clear_cache
  51 static void __clear_cache(void *start, void *end) {
  52   size_t len = (char *)end - (char *)start;
  53   sys_dcache_flush(start, len);
  54   sys_icache_invalidate(start, len);
  55 }
  56 #endif
  57
  58 #define MAXBLOCK 4096
  59 #define MAX_OUTPUT_BLOCK_SIZE 262144
  60
  61 struct regstat
  62 {
  63   signed char regmap_entry[HOST_REGS];
  64   signed char regmap[HOST_REGS];
  65   uint64_t was32;
  66   uint64_t is32;
  67   uint64_t wasdirty;
  68   uint64_t dirty;
  69   uint64_t u;
  70   uint64_t uu;
  71   u_int wasconst;
  72   u_int isconst;
  73   u_int loadedconst;             // host regs that have constants loaded
  74   u_int waswritten;              // MIPS regs that were used as store base before
  75 };
  76
  77 // note: asm depends on this layout
  78 struct ll_entry
  79 {
  80   u_int vaddr;
  81   u_int reg_sv_flags;
  82   void *addr;
  83   struct ll_entry *next;
  84 };
  85
  86   // used by asm:
  87   u_char *out;
  88   u_int hash_table[65536][4]  __attribute__((aligned(16)));
  89   struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
  90   struct ll_entry *jump_dirty[4096];
  91
  92   static struct ll_entry *jump_out[4096];
  93   static u_int start;
  94   static u_int *source;
  95   static char insn[MAXBLOCK][10];
  96   static u_char itype[MAXBLOCK];
  97   static u_char opcode[MAXBLOCK];
  98   static u_char opcode2[MAXBLOCK];
  99   static u_char bt[MAXBLOCK];
 100   static u_char rs1[MAXBLOCK];
 101   static u_char rs2[MAXBLOCK];
 102   static u_char rt1[MAXBLOCK];
 103   static u_char rt2[MAXBLOCK];
 104   static u_char us1[MAXBLOCK];
 105   static u_char us2[MAXBLOCK];
 106   static u_char dep1[MAXBLOCK];
 107   static u_char dep2[MAXBLOCK];
 108   static u_char lt1[MAXBLOCK];
 109   static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
 110   static uint64_t gte_rt[MAXBLOCK];
 111   static uint64_t gte_unneeded[MAXBLOCK];
 112   static u_int smrv[32]; // speculated MIPS register values
 113   static u_int smrv_strong; // mask or regs that are likely to have correct values
 114   static u_int smrv_weak; // same, but somewhat less likely
 115   static u_int smrv_strong_next; // same, but after current insn executes
 116   static u_int smrv_weak_next;
 117   static int imm[MAXBLOCK];
 118   static u_int ba[MAXBLOCK];
 119   static char likely[MAXBLOCK];
 120   static char is_ds[MAXBLOCK];
 121   static char ooo[MAXBLOCK];
 122   static uint64_t unneeded_reg[MAXBLOCK];
 123   static uint64_t unneeded_reg_upper[MAXBLOCK];
 124   static uint64_t branch_unneeded_reg[MAXBLOCK];
 125   static uint64_t branch_unneeded_reg_upper[MAXBLOCK];
 126   static signed char regmap_pre[MAXBLOCK][HOST_REGS];
 127   static uint64_t current_constmap[HOST_REGS];
 128   static uint64_t constmap[MAXBLOCK][HOST_REGS];
 129   static struct regstat regs[MAXBLOCK];
 130   static struct regstat branch_regs[MAXBLOCK];
 131   static signed char minimum_free_regs[MAXBLOCK];
 132   static u_int needed_reg[MAXBLOCK];
 133   static u_int wont_dirty[MAXBLOCK];
 134   static u_int will_dirty[MAXBLOCK];
 135   static int ccadj[MAXBLOCK];
 136   static int slen;
 137   static u_int instr_addr[MAXBLOCK];
 138   static u_int link_addr[MAXBLOCK][3];
 139   static int linkcount;
 140   static u_int stubs[MAXBLOCK*3][8];
 141   static int stubcount;
 142   static u_int literals[1024][2];
 143   static int literalcount;
 144   static int is_delayslot;
 145   static int cop1_usable;
 146   static char shadow[1048576]  __attribute__((aligned(16)));
 147   static void *copy;
 148   static int expirep;
 149   static u_int stop_after_jal;
 150 #ifndef RAM_FIXED
 151   static u_int ram_offset;
 152 #else
 153   static const u_int ram_offset=0;
 154 #endif
 155
 156   int new_dynarec_hacks;
 157   int new_dynarec_did_compile;
 158   extern u_char restore_candidate[512];
 159   extern int cycle_count;
 160
 161   /* registers that may be allocated */
 162   /* 1-31 gpr */
 163 #define HIREG 32 // hi
 164 #define LOREG 33 // lo
 165 #define FSREG 34 // FPU status (FCSR)
 166 #define CSREG 35 // Coprocessor status
 167 #define CCREG 36 // Cycle count
 168 #define INVCP 37 // Pointer to invalid_code
 169 //#define MMREG 38 // Pointer to memory_map
 170 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 171 #define TEMPREG 40
 172 #define FTEMP 40 // FPU temporary register
 173 #define PTEMP 41 // Prefetch temporary register
 174 //#define TLREG 42 // TLB mapping offset
 175 #define RHASH 43 // Return address hash
 176 #define RHTBL 44 // Return address hash table address
 177 #define RTEMP 45 // JR/JALR address register
 178 #define MAXREG 45
 179 #define AGEN1 46 // Address generation temporary register
 180 //#define AGEN2 47 // Address generation temporary register
 181 //#define MGEN1 48 // Maptable address generation temporary register
 182 //#define MGEN2 49 // Maptable address generation temporary register
 183 #define BTREG 50 // Branch target temporary register
 184
 185   /* instruction types */
 186 #define NOP 0     // No operation
 187 #define LOAD 1    // Load
 188 #define STORE 2   // Store
 189 #define LOADLR 3  // Unaligned load
 190 #define STORELR 4 // Unaligned store
 191 #define MOV 5     // Move
 192 #define ALU 6     // Arithmetic/logic
 193 #define MULTDIV 7 // Multiply/divide
 194 #define SHIFT 8   // Shift by register
 195 #define SHIFTIMM 9// Shift by immediate
 196 #define IMM16 10  // 16-bit immediate
 197 #define RJUMP 11  // Unconditional jump to register
 198 #define UJUMP 12  // Unconditional jump
 199 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 200 #define SJUMP 14  // Conditional branch (regimm format)
 201 #define COP0 15   // Coprocessor 0
 202 #define COP1 16   // Coprocessor 1
 203 #define C1LS 17   // Coprocessor 1 load/store
 204 #define FJUMP 18  // Conditional branch (floating point)
 205 #define FLOAT 19  // Floating point unit
 206 #define FCONV 20  // Convert integer to float
 207 #define FCOMP 21  // Floating point compare (sets FSREG)
 208 #define SYSCALL 22// SYSCALL
 209 #define OTHER 23  // Other
 210 #define SPAN 24   // Branch/delay slot spans 2 pages
 211 #define NI 25     // Not implemented
 212 #define HLECALL 26// PCSX fake opcodes for HLE
 213 #define COP2 27   // Coprocessor 2 move
 214 #define C2LS 28   // Coprocessor 2 load/store
 215 #define C2OP 29   // Coprocessor 2 operation
 216 #define INTCALL 30// Call interpreter to handle rare corner cases
 217
 218   /* stubs */
 219 #define CC_STUB 1
 220 #define FP_STUB 2
 221 #define LOADB_STUB 3
 222 #define LOADH_STUB 4
 223 #define LOADW_STUB 5
 224 #define LOADD_STUB 6
 225 #define LOADBU_STUB 7
 226 #define LOADHU_STUB 8
 227 #define STOREB_STUB 9
 228 #define STOREH_STUB 10
 229 #define STOREW_STUB 11
 230 #define STORED_STUB 12
 231 #define STORELR_STUB 13
 232 #define INVCODE_STUB 14
 233
 234   /* branch codes */
 235 #define TAKEN 1
 236 #define NOTTAKEN 2
 237 #define NULLDS 3
 238
 239 // asm linkage
 240 int new_recompile_block(int addr);
 241 void *get_addr_ht(u_int vaddr);
 242 void invalidate_block(u_int block);
 243 void invalidate_addr(u_int addr);
 244 void remove_hash(int vaddr);
 245 void dyna_linker();
 246 void dyna_linker_ds();
 247 void verify_code();
 248 void verify_code_vm();
 249 void verify_code_ds();
 250 void cc_interrupt();
 251 void fp_exception();
 252 void fp_exception_ds();
 253 void jump_syscall_hle();
 254 void jump_hlecall();
 255 void jump_intcall();
 256 void new_dyna_leave();
 257
 258 // Needed by assembler
 259 static void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 260 static void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 261 static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 262 static void load_all_regs(signed char i_regmap[]);
 263 static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 264 static void load_regs_entry(int t);
 265 static void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 266
 267 static int verify_dirty(u_int *ptr);
 268 static int get_final_value(int hr, int i, int *value);
 269 static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e);
 270 static void add_to_linker(int addr,int target,int ext);
 271
 272 static int tracedebug=0;
 273
 274 //#define DEBUG_CYCLE_COUNT 1
 275
 276 #define NO_CYCLE_PENALTY_THR 12
 277
 278 int cycle_multiplier; // 100 for 1.0
 279
 280 static int CLOCK_ADJUST(int x)
 281 {
 282   int s=(x>>31)|1;
 283   return (x * cycle_multiplier + s * 50) / 100;
 284 }
 285
 286 static u_int get_page(u_int vaddr)
 287 {
 288   u_int page=vaddr&~0xe0000000;
 289   if (page < 0x1000000)
 290     page &= ~0x0e00000; // RAM mirrors
 291   page>>=12;
 292   if(page>2048) page=2048+(page&2047);
 293   return page;
 294 }
 295
 296 // no virtual mem in PCSX
 297 static u_int get_vpage(u_int vaddr)
 298 {
 299   return get_page(vaddr);
 300 }
 301
 302 // Get address from virtual address
 303 // This is called from the recompiled JR/JALR instructions
 304 void *get_addr(u_int vaddr)
 305 {
 306   u_int page=get_page(vaddr);
 307   u_int vpage=get_vpage(vaddr);
 308   struct ll_entry *head;
 309   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 310   head=jump_in[page];
 311   while(head!=NULL) {
 312     if(head->vaddr==vaddr) {
 313   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 314       u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 315       ht_bin[3]=ht_bin[1];
 316       ht_bin[2]=ht_bin[0];
 317       ht_bin[1]=(u_int)head->addr;
 318       ht_bin[0]=vaddr;
 319       return head->addr;
 320     }
 321     head=head->next;
 322   }
 323   head=jump_dirty[vpage];
 324   while(head!=NULL) {
 325     if(head->vaddr==vaddr) {
 326       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 327       // Don't restore blocks which are about to expire from the cache
 328       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 329       if(verify_dirty(head->addr)) {
 330         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 331         invalid_code[vaddr>>12]=0;
 332         inv_code_start=inv_code_end=~0;
 333         if(vpage<2048) {
 334           restore_candidate[vpage>>3]|=1<<(vpage&7);
 335         }
 336         else restore_candidate[page>>3]|=1<<(page&7);
 337         u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 338         if(ht_bin[0]==vaddr) {
 339           ht_bin[1]=(u_int)head->addr; // Replace existing entry
 340         }
 341         else
 342         {
 343           ht_bin[3]=ht_bin[1];
 344           ht_bin[2]=ht_bin[0];
 345           ht_bin[1]=(int)head->addr;
 346           ht_bin[0]=vaddr;
 347         }
 348         return head->addr;
 349       }
 350     }
 351     head=head->next;
 352   }
 353   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 354   int r=new_recompile_block(vaddr);
 355   if(r==0) return get_addr(vaddr);
 356   // Execute in unmapped page, generate pagefault execption
 357   Status|=2;
 358   Cause=(vaddr<<31)|0x8;
 359   EPC=(vaddr&1)?vaddr-5:vaddr;
 360   BadVAddr=(vaddr&~1);
 361   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 362   EntryHi=BadVAddr&0xFFFFE000;
 363   return get_addr_ht(0x80000000);
 364 }
 365 // Look up address in hash table first
 366 void *get_addr_ht(u_int vaddr)
 367 {
 368   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 369   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 370   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 371   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 372   return get_addr(vaddr);
 373 }
 374
 375 void clear_all_regs(signed char regmap[])
 376 {
 377   int hr;
 378   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 379 }
 380
 381 signed char get_reg(signed char regmap[],int r)
 382 {
 383   int hr;
 384   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 385   return -1;
 386 }
 387
 388 // Find a register that is available for two consecutive cycles
 389 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 390 {
 391   int hr;
 392   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 393   return -1;
 394 }
 395
 396 int count_free_regs(signed char regmap[])
 397 {
 398   int count=0;
 399   int hr;
 400   for(hr=0;hr<HOST_REGS;hr++)
 401   {
 402     if(hr!=EXCLUDE_REG) {
 403       if(regmap[hr]<0) count++;
 404     }
 405   }
 406   return count;
 407 }
 408
 409 void dirty_reg(struct regstat *cur,signed char reg)
 410 {
 411   int hr;
 412   if(!reg) return;
 413   for (hr=0;hr<HOST_REGS;hr++) {
 414     if((cur->regmap[hr]&63)==reg) {
 415       cur->dirty|=1<<hr;
 416     }
 417   }
 418 }
 419
 420 // If we dirty the lower half of a 64 bit register which is now being
 421 // sign-extended, we need to dump the upper half.
 422 // Note: Do this only after completion of the instruction, because
 423 // some instructions may need to read the full 64-bit value even if
 424 // overwriting it (eg SLTI, DSRA32).
 425 static void flush_dirty_uppers(struct regstat *cur)
 426 {
 427   int hr,reg;
 428   for (hr=0;hr<HOST_REGS;hr++) {
 429     if((cur->dirty>>hr)&1) {
 430       reg=cur->regmap[hr];
 431       if(reg>=64)
 432         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 433     }
 434   }
 435 }
 436
 437 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 438 {
 439   int hr;
 440   if(!reg) return;
 441   for (hr=0;hr<HOST_REGS;hr++) {
 442     if(cur->regmap[hr]==reg) {
 443       cur->isconst|=1<<hr;
 444       current_constmap[hr]=value;
 445     }
 446     else if((cur->regmap[hr]^64)==reg) {
 447       cur->isconst|=1<<hr;
 448       current_constmap[hr]=value>>32;
 449     }
 450   }
 451 }
 452
 453 void clear_const(struct regstat *cur,signed char reg)
 454 {
 455   int hr;
 456   if(!reg) return;
 457   for (hr=0;hr<HOST_REGS;hr++) {
 458     if((cur->regmap[hr]&63)==reg) {
 459       cur->isconst&=~(1<<hr);
 460     }
 461   }
 462 }
 463
 464 int is_const(struct regstat *cur,signed char reg)
 465 {
 466   int hr;
 467   if(reg<0) return 0;
 468   if(!reg) return 1;
 469   for (hr=0;hr<HOST_REGS;hr++) {
 470     if((cur->regmap[hr]&63)==reg) {
 471       return (cur->isconst>>hr)&1;
 472     }
 473   }
 474   return 0;
 475 }
 476 uint64_t get_const(struct regstat *cur,signed char reg)
 477 {
 478   int hr;
 479   if(!reg) return 0;
 480   for (hr=0;hr<HOST_REGS;hr++) {
 481     if(cur->regmap[hr]==reg) {
 482       return current_constmap[hr];
 483     }
 484   }
 485   SysPrintf("Unknown constant in r%d\n",reg);
 486   exit(1);
 487 }
 488
 489 // Least soon needed registers
 490 // Look at the next ten instructions and see which registers
 491 // will be used.  Try not to reallocate these.
 492 void lsn(u_char hsn[], int i, int *preferred_reg)
 493 {
 494   int j;
 495   int b=-1;
 496   for(j=0;j<9;j++)
 497   {
 498     if(i+j>=slen) {
 499       j=slen-i-1;
 500       break;
 501     }
 502     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 503     {
 504       // Don't go past an unconditonal jump
 505       j++;
 506       break;
 507     }
 508   }
 509   for(;j>=0;j--)
 510   {
 511     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 512     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 513     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 514     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 515     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 516       // Stores can allocate zero
 517       hsn[rs1[i+j]]=j;
 518       hsn[rs2[i+j]]=j;
 519     }
 520     // On some architectures stores need invc_ptr
 521     #if defined(HOST_IMM8)
 522     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 523       hsn[INVCP]=j;
 524     }
 525     #endif
 526     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 527     {
 528       hsn[CCREG]=j;
 529       b=j;
 530     }
 531   }
 532   if(b>=0)
 533   {
 534     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 535     {
 536       // Follow first branch
 537       int t=(ba[i+b]-start)>>2;
 538       j=7-b;if(t+j>=slen) j=slen-t-1;
 539       for(;j>=0;j--)
 540       {
 541         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 542         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 543         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 544         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 545       }
 546     }
 547     // TODO: preferred register based on backward branch
 548   }
 549   // Delay slot should preferably not overwrite branch conditions or cycle count
 550   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 551     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 552     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 553     hsn[CCREG]=1;
 554     // ...or hash tables
 555     hsn[RHASH]=1;
 556     hsn[RHTBL]=1;
 557   }
 558   // Coprocessor load/store needs FTEMP, even if not declared
 559   if(itype[i]==C1LS||itype[i]==C2LS) {
 560     hsn[FTEMP]=0;
 561   }
 562   // Load L/R also uses FTEMP as a temporary register
 563   if(itype[i]==LOADLR) {
 564     hsn[FTEMP]=0;
 565   }
 566   // Also SWL/SWR/SDL/SDR
 567   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 568     hsn[FTEMP]=0;
 569   }
 570   // Don't remove the miniht registers
 571   if(itype[i]==UJUMP||itype[i]==RJUMP)
 572   {
 573     hsn[RHASH]=0;
 574     hsn[RHTBL]=0;
 575   }
 576 }
 577
 578 // We only want to allocate registers if we're going to use them again soon
 579 int needed_again(int r, int i)
 580 {
 581   int j;
 582   int b=-1;
 583   int rn=10;
 584
 585   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 586   {
 587     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 588       return 0; // Don't need any registers if exiting the block
 589   }
 590   for(j=0;j<9;j++)
 591   {
 592     if(i+j>=slen) {
 593       j=slen-i-1;
 594       break;
 595     }
 596     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 597     {
 598       // Don't go past an unconditonal jump
 599       j++;
 600       break;
 601     }
 602     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 603     {
 604       break;
 605     }
 606   }
 607   for(;j>=1;j--)
 608   {
 609     if(rs1[i+j]==r) rn=j;
 610     if(rs2[i+j]==r) rn=j;
 611     if((unneeded_reg[i+j]>>r)&1) rn=10;
 612     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 613     {
 614       b=j;
 615     }
 616   }
 617   /*
 618   if(b>=0)
 619   {
 620     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 621     {
 622       // Follow first branch
 623       int o=rn;
 624       int t=(ba[i+b]-start)>>2;
 625       j=7-b;if(t+j>=slen) j=slen-t-1;
 626       for(;j>=0;j--)
 627       {
 628         if(!((unneeded_reg[t+j]>>r)&1)) {
 629           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 630           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 631         }
 632         else rn=o;
 633       }
 634     }
 635   }*/
 636   if(rn<10) return 1;
 637   (void)b;
 638   return 0;
 639 }
 640
 641 // Try to match register allocations at the end of a loop with those
 642 // at the beginning
 643 int loop_reg(int i, int r, int hr)
 644 {
 645   int j,k;
 646   for(j=0;j<9;j++)
 647   {
 648     if(i+j>=slen) {
 649       j=slen-i-1;
 650       break;
 651     }
 652     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 653     {
 654       // Don't go past an unconditonal jump
 655       j++;
 656       break;
 657     }
 658   }
 659   k=0;
 660   if(i>0){
 661     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 662       k--;
 663   }
 664   for(;k<j;k++)
 665   {
 666     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 667     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 668     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 669     {
 670       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 671       {
 672         int t=(ba[i+k]-start)>>2;
 673         int reg=get_reg(regs[t].regmap_entry,r);
 674         if(reg>=0) return reg;
 675         //reg=get_reg(regs[t+1].regmap_entry,r);
 676         //if(reg>=0) return reg;
 677       }
 678     }
 679   }
 680   return hr;
 681 }
 682
 683
 684 // Allocate every register, preserving source/target regs
 685 void alloc_all(struct regstat *cur,int i)
 686 {
 687   int hr;
 688
 689   for(hr=0;hr<HOST_REGS;hr++) {
 690     if(hr!=EXCLUDE_REG) {
 691       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 692          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 693       {
 694         cur->regmap[hr]=-1;
 695         cur->dirty&=~(1<<hr);
 696       }
 697       // Don't need zeros
 698       if((cur->regmap[hr]&63)==0)
 699       {
 700         cur->regmap[hr]=-1;
 701         cur->dirty&=~(1<<hr);
 702       }
 703     }
 704   }
 705 }
 706
 707 #ifdef __i386__
 708 #include "assem_x86.c"
 709 #endif
 710 #ifdef __x86_64__
 711 #include "assem_x64.c"
 712 #endif
 713 #ifdef __arm__
 714 #include "assem_arm.c"
 715 #endif
 716
 717 // Add virtual address mapping to linked list
 718 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 719 {
 720   struct ll_entry *new_entry;
 721   new_entry=malloc(sizeof(struct ll_entry));
 722   assert(new_entry!=NULL);
 723   new_entry->vaddr=vaddr;
 724   new_entry->reg_sv_flags=0;
 725   new_entry->addr=addr;
 726   new_entry->next=*head;
 727   *head=new_entry;
 728 }
 729
 730 void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
 731 {
 732   ll_add(head,vaddr,addr);
 733   (*head)->reg_sv_flags=reg_sv_flags;
 734 }
 735
 736 // Check if an address is already compiled
 737 // but don't return addresses which are about to expire from the cache
 738 void *check_addr(u_int vaddr)
 739 {
 740   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 741   if(ht_bin[0]==vaddr) {
 742     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 743       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
 744   }
 745   if(ht_bin[2]==vaddr) {
 746     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 747       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
 748   }
 749   u_int page=get_page(vaddr);
 750   struct ll_entry *head;
 751   head=jump_in[page];
 752   while(head!=NULL) {
 753     if(head->vaddr==vaddr) {
 754       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
 755         // Update existing entry with current address
 756         if(ht_bin[0]==vaddr) {
 757           ht_bin[1]=(int)head->addr;
 758           return head->addr;
 759         }
 760         if(ht_bin[2]==vaddr) {
 761           ht_bin[3]=(int)head->addr;
 762           return head->addr;
 763         }
 764         // Insert into hash table with low priority.
 765         // Don't evict existing entries, as they are probably
 766         // addresses that are being accessed frequently.
 767         if(ht_bin[0]==-1) {
 768           ht_bin[1]=(int)head->addr;
 769           ht_bin[0]=vaddr;
 770         }else if(ht_bin[2]==-1) {
 771           ht_bin[3]=(int)head->addr;
 772           ht_bin[2]=vaddr;
 773         }
 774         return head->addr;
 775       }
 776     }
 777     head=head->next;
 778   }
 779   return 0;
 780 }
 781
 782 void remove_hash(int vaddr)
 783 {
 784   //printf("remove hash: %x\n",vaddr);
 785   u_int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
 786   if(ht_bin[2]==vaddr) {
 787     ht_bin[2]=ht_bin[3]=-1;
 788   }
 789   if(ht_bin[0]==vaddr) {
 790     ht_bin[0]=ht_bin[2];
 791     ht_bin[1]=ht_bin[3];
 792     ht_bin[2]=ht_bin[3]=-1;
 793   }
 794 }
 795
 796 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
 797 {
 798   struct ll_entry *next;
 799   while(*head) {
 800     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
 801        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
 802     {
 803       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
 804       remove_hash((*head)->vaddr);
 805       next=(*head)->next;
 806       free(*head);
 807       *head=next;
 808     }
 809     else
 810     {
 811       head=&((*head)->next);
 812     }
 813   }
 814 }
 815
 816 // Remove all entries from linked list
 817 void ll_clear(struct ll_entry **head)
 818 {
 819   struct ll_entry *cur;
 820   struct ll_entry *next;
 821   if((cur=*head)) {
 822     *head=0;
 823     while(cur) {
 824       next=cur->next;
 825       free(cur);
 826       cur=next;
 827     }
 828   }
 829 }
 830
 831 // Dereference the pointers and remove if it matches
 832 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
 833 {
 834   while(head) {
 835     int ptr=get_pointer(head->addr);
 836     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
 837     if(((ptr>>shift)==(addr>>shift)) ||
 838        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
 839     {
 840       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
 841       u_int host_addr=(u_int)kill_pointer(head->addr);
 842       #ifdef __arm__
 843         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
 844       #endif
 845     }
 846     head=head->next;
 847   }
 848 }
 849
 850 // This is called when we write to a compiled block (see do_invstub)
 851 void invalidate_page(u_int page)
 852 {
 853   struct ll_entry *head;
 854   struct ll_entry *next;
 855   head=jump_in[page];
 856   jump_in[page]=0;
 857   while(head!=NULL) {
 858     inv_debug("INVALIDATE: %x\n",head->vaddr);
 859     remove_hash(head->vaddr);
 860     next=head->next;
 861     free(head);
 862     head=next;
 863   }
 864   head=jump_out[page];
 865   jump_out[page]=0;
 866   while(head!=NULL) {
 867     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
 868     u_int host_addr=(u_int)kill_pointer(head->addr);
 869     #ifdef __arm__
 870       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
 871     #endif
 872     next=head->next;
 873     free(head);
 874     head=next;
 875   }
 876 }
 877
 878 static void invalidate_block_range(u_int block, u_int first, u_int last)
 879 {
 880   u_int page=get_page(block<<12);
 881   //printf("first=%d last=%d\n",first,last);
 882   invalidate_page(page);
 883   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
 884   assert(last<page+5);
 885   // Invalidate the adjacent pages if a block crosses a 4K boundary
 886   while(first<page) {
 887     invalidate_page(first);
 888     first++;
 889   }
 890   for(first=page+1;first<last;first++) {
 891     invalidate_page(first);
 892   }
 893   #ifdef __arm__
 894     do_clear_cache();
 895   #endif
 896
 897   // Don't trap writes
 898   invalid_code[block]=1;
 899
 900   #ifdef USE_MINI_HT
 901   memset(mini_ht,-1,sizeof(mini_ht));
 902   #endif
 903 }
 904
 905 void invalidate_block(u_int block)
 906 {
 907   u_int page=get_page(block<<12);
 908   u_int vpage=get_vpage(block<<12);
 909   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
 910   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
 911   u_int first,last;
 912   first=last=page;
 913   struct ll_entry *head;
 914   head=jump_dirty[vpage];
 915   //printf("page=%d vpage=%d\n",page,vpage);
 916   while(head!=NULL) {
 917     u_int start,end;
 918     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
 919       get_bounds((int)head->addr,&start,&end);
 920       //printf("start: %x end: %x\n",start,end);
 921       if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) {
 922         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
 923           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
 924           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
 925         }
 926       }
 927     }
 928     head=head->next;
 929   }
 930   invalidate_block_range(block,first,last);
 931 }
 932
 933 void invalidate_addr(u_int addr)
 934 {
 935   //static int rhits;
 936   // this check is done by the caller
 937   //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
 938   u_int page=get_vpage(addr);
 939   if(page<2048) { // RAM
 940     struct ll_entry *head;
 941     u_int addr_min=~0, addr_max=0;
 942     u_int mask=RAM_SIZE-1;
 943     u_int addr_main=0x80000000|(addr&mask);
 944     int pg1;
 945     inv_code_start=addr_main&~0xfff;
 946     inv_code_end=addr_main|0xfff;
 947     pg1=page;
 948     if (pg1>0) {
 949       // must check previous page too because of spans..
 950       pg1--;
 951       inv_code_start-=0x1000;
 952     }
 953     for(;pg1<=page;pg1++) {
 954       for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
 955         u_int start,end;
 956         get_bounds((int)head->addr,&start,&end);
 957         if(ram_offset) {
 958           start-=ram_offset;
 959           end-=ram_offset;
 960         }
 961         if(start<=addr_main&&addr_main<end) {
 962           if(start<addr_min) addr_min=start;
 963           if(end>addr_max) addr_max=end;
 964         }
 965         else if(addr_main<start) {
 966           if(start<inv_code_end)
 967             inv_code_end=start-1;
 968         }
 969         else {
 970           if(end>inv_code_start)
 971             inv_code_start=end;
 972         }
 973       }
 974     }
 975     if (addr_min!=~0) {
 976       inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
 977       inv_code_start=inv_code_end=~0;
 978       invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
 979       return;
 980     }
 981     else {
 982       inv_code_start=(addr&~mask)|(inv_code_start&mask);
 983       inv_code_end=(addr&~mask)|(inv_code_end&mask);
 984       inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
 985       return;
 986     }
 987   }
 988   invalidate_block(addr>>12);
 989 }
 990
 991 // This is called when loading a save state.
 992 // Anything could have changed, so invalidate everything.
 993 void invalidate_all_pages()
 994 {
 995   u_int page;
 996   for(page=0;page<4096;page++)
 997     invalidate_page(page);
 998   for(page=0;page<1048576;page++)
 999     if(!invalid_code[page]) {
1000       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1001       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1002     }
1003   #ifdef __arm__
1004   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1005   #endif
1006   #ifdef USE_MINI_HT
1007   memset(mini_ht,-1,sizeof(mini_ht));
1008   #endif
1009 }
1010
1011 // Add an entry to jump_out after making a link
1012 void add_link(u_int vaddr,void *src)
1013 {
1014   u_int page=get_page(vaddr);
1015   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1016   int *ptr=(int *)(src+4);
1017   assert((*ptr&0x0fff0000)==0x059f0000);
1018   (void)ptr;
1019   ll_add(jump_out+page,vaddr,src);
1020   //int ptr=get_pointer(src);
1021   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1022 }
1023
1024 // If a code block was found to be unmodified (bit was set in
1025 // restore_candidate) and it remains unmodified (bit is clear
1026 // in invalid_code) then move the entries for that 4K page from
1027 // the dirty list to the clean list.
1028 void clean_blocks(u_int page)
1029 {
1030   struct ll_entry *head;
1031   inv_debug("INV: clean_blocks page=%d\n",page);
1032   head=jump_dirty[page];
1033   while(head!=NULL) {
1034     if(!invalid_code[head->vaddr>>12]) {
1035       // Don't restore blocks which are about to expire from the cache
1036       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1037         u_int start,end;
1038         if(verify_dirty(head->addr)) {
1039           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1040           u_int i;
1041           u_int inv=0;
1042           get_bounds((int)head->addr,&start,&end);
1043           if(start-(u_int)rdram<RAM_SIZE) {
1044             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1045               inv|=invalid_code[i];
1046             }
1047           }
1048           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1049             inv=1;
1050           }
1051           if(!inv) {
1052             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1053             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1054               u_int ppage=page;
1055               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1056               //printf("page=%x, addr=%x\n",page,head->vaddr);
1057               //assert(head->vaddr>>12==(page|0x80000));
1058               ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
1059               u_int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1060               if(ht_bin[0]==head->vaddr) {
1061                 ht_bin[1]=(u_int)clean_addr; // Replace existing entry
1062               }
1063               if(ht_bin[2]==head->vaddr) {
1064                 ht_bin[3]=(u_int)clean_addr; // Replace existing entry
1065               }
1066             }
1067           }
1068         }
1069       }
1070     }
1071     head=head->next;
1072   }
1073 }
1074
1075
1076 void mov_alloc(struct regstat *current,int i)
1077 {
1078   // Note: Don't need to actually alloc the source registers
1079   if((~current->is32>>rs1[i])&1) {
1080     //alloc_reg64(current,i,rs1[i]);
1081     alloc_reg64(current,i,rt1[i]);
1082     current->is32&=~(1LL<<rt1[i]);
1083   } else {
1084     //alloc_reg(current,i,rs1[i]);
1085     alloc_reg(current,i,rt1[i]);
1086     current->is32|=(1LL<<rt1[i]);
1087   }
1088   clear_const(current,rs1[i]);
1089   clear_const(current,rt1[i]);
1090   dirty_reg(current,rt1[i]);
1091 }
1092
1093 void shiftimm_alloc(struct regstat *current,int i)
1094 {
1095   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1096   {
1097     if(rt1[i]) {
1098       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1099       else lt1[i]=rs1[i];
1100       alloc_reg(current,i,rt1[i]);
1101       current->is32|=1LL<<rt1[i];
1102       dirty_reg(current,rt1[i]);
1103       if(is_const(current,rs1[i])) {
1104         int v=get_const(current,rs1[i]);
1105         if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1106         if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1107         if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1108       }
1109       else clear_const(current,rt1[i]);
1110     }
1111   }
1112   else
1113   {
1114     clear_const(current,rs1[i]);
1115     clear_const(current,rt1[i]);
1116   }
1117
1118   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1119   {
1120     if(rt1[i]) {
1121       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1122       alloc_reg64(current,i,rt1[i]);
1123       current->is32&=~(1LL<<rt1[i]);
1124       dirty_reg(current,rt1[i]);
1125     }
1126   }
1127   if(opcode2[i]==0x3c) // DSLL32
1128   {
1129     if(rt1[i]) {
1130       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1131       alloc_reg64(current,i,rt1[i]);
1132       current->is32&=~(1LL<<rt1[i]);
1133       dirty_reg(current,rt1[i]);
1134     }
1135   }
1136   if(opcode2[i]==0x3e) // DSRL32
1137   {
1138     if(rt1[i]) {
1139       alloc_reg64(current,i,rs1[i]);
1140       if(imm[i]==32) {
1141         alloc_reg64(current,i,rt1[i]);
1142         current->is32&=~(1LL<<rt1[i]);
1143       } else {
1144         alloc_reg(current,i,rt1[i]);
1145         current->is32|=1LL<<rt1[i];
1146       }
1147       dirty_reg(current,rt1[i]);
1148     }
1149   }
1150   if(opcode2[i]==0x3f) // DSRA32
1151   {
1152     if(rt1[i]) {
1153       alloc_reg64(current,i,rs1[i]);
1154       alloc_reg(current,i,rt1[i]);
1155       current->is32|=1LL<<rt1[i];
1156       dirty_reg(current,rt1[i]);
1157     }
1158   }
1159 }
1160
1161 void shift_alloc(struct regstat *current,int i)
1162 {
1163   if(rt1[i]) {
1164     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1165     {
1166       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1167       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1168       alloc_reg(current,i,rt1[i]);
1169       if(rt1[i]==rs2[i]) {
1170         alloc_reg_temp(current,i,-1);
1171         minimum_free_regs[i]=1;
1172       }
1173       current->is32|=1LL<<rt1[i];
1174     } else { // DSLLV/DSRLV/DSRAV
1175       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1176       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1177       alloc_reg64(current,i,rt1[i]);
1178       current->is32&=~(1LL<<rt1[i]);
1179       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1180       {
1181         alloc_reg_temp(current,i,-1);
1182         minimum_free_regs[i]=1;
1183       }
1184     }
1185     clear_const(current,rs1[i]);
1186     clear_const(current,rs2[i]);
1187     clear_const(current,rt1[i]);
1188     dirty_reg(current,rt1[i]);
1189   }
1190 }
1191
1192 void alu_alloc(struct regstat *current,int i)
1193 {
1194   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1195     if(rt1[i]) {
1196       if(rs1[i]&&rs2[i]) {
1197         alloc_reg(current,i,rs1[i]);
1198         alloc_reg(current,i,rs2[i]);
1199       }
1200       else {
1201         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1202         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1203       }
1204       alloc_reg(current,i,rt1[i]);
1205     }
1206     current->is32|=1LL<<rt1[i];
1207   }
1208   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1209     if(rt1[i]) {
1210       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1211       {
1212         alloc_reg64(current,i,rs1[i]);
1213         alloc_reg64(current,i,rs2[i]);
1214         alloc_reg(current,i,rt1[i]);
1215       } else {
1216         alloc_reg(current,i,rs1[i]);
1217         alloc_reg(current,i,rs2[i]);
1218         alloc_reg(current,i,rt1[i]);
1219       }
1220     }
1221     current->is32|=1LL<<rt1[i];
1222   }
1223   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1224     if(rt1[i]) {
1225       if(rs1[i]&&rs2[i]) {
1226         alloc_reg(current,i,rs1[i]);
1227         alloc_reg(current,i,rs2[i]);
1228       }
1229       else
1230       {
1231         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1232         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1233       }
1234       alloc_reg(current,i,rt1[i]);
1235       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1236       {
1237         if(!((current->uu>>rt1[i])&1)) {
1238           alloc_reg64(current,i,rt1[i]);
1239         }
1240         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1241           if(rs1[i]&&rs2[i]) {
1242             alloc_reg64(current,i,rs1[i]);
1243             alloc_reg64(current,i,rs2[i]);
1244           }
1245           else
1246           {
1247             // Is is really worth it to keep 64-bit values in registers?
1248             #ifdef NATIVE_64BIT
1249             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1250             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1251             #endif
1252           }
1253         }
1254         current->is32&=~(1LL<<rt1[i]);
1255       } else {
1256         current->is32|=1LL<<rt1[i];
1257       }
1258     }
1259   }
1260   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1261     if(rt1[i]) {
1262       if(rs1[i]&&rs2[i]) {
1263         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1264           alloc_reg64(current,i,rs1[i]);
1265           alloc_reg64(current,i,rs2[i]);
1266           alloc_reg64(current,i,rt1[i]);
1267         } else {
1268           alloc_reg(current,i,rs1[i]);
1269           alloc_reg(current,i,rs2[i]);
1270           alloc_reg(current,i,rt1[i]);
1271         }
1272       }
1273       else {
1274         alloc_reg(current,i,rt1[i]);
1275         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1276           // DADD used as move, or zeroing
1277           // If we have a 64-bit source, then make the target 64 bits too
1278           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1279             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1280             alloc_reg64(current,i,rt1[i]);
1281           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1282             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1283             alloc_reg64(current,i,rt1[i]);
1284           }
1285           if(opcode2[i]>=0x2e&&rs2[i]) {
1286             // DSUB used as negation - 64-bit result
1287             // If we have a 32-bit register, extend it to 64 bits
1288             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1289             alloc_reg64(current,i,rt1[i]);
1290           }
1291         }
1292       }
1293       if(rs1[i]&&rs2[i]) {
1294         current->is32&=~(1LL<<rt1[i]);
1295       } else if(rs1[i]) {
1296         current->is32&=~(1LL<<rt1[i]);
1297         if((current->is32>>rs1[i])&1)
1298           current->is32|=1LL<<rt1[i];
1299       } else if(rs2[i]) {
1300         current->is32&=~(1LL<<rt1[i]);
1301         if((current->is32>>rs2[i])&1)
1302           current->is32|=1LL<<rt1[i];
1303       } else {
1304         current->is32|=1LL<<rt1[i];
1305       }
1306     }
1307   }
1308   clear_const(current,rs1[i]);
1309   clear_const(current,rs2[i]);
1310   clear_const(current,rt1[i]);
1311   dirty_reg(current,rt1[i]);
1312 }
1313
1314 void imm16_alloc(struct regstat *current,int i)
1315 {
1316   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1317   else lt1[i]=rs1[i];
1318   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1319   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1320     current->is32&=~(1LL<<rt1[i]);
1321     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1322       // TODO: Could preserve the 32-bit flag if the immediate is zero
1323       alloc_reg64(current,i,rt1[i]);
1324       alloc_reg64(current,i,rs1[i]);
1325     }
1326     clear_const(current,rs1[i]);
1327     clear_const(current,rt1[i]);
1328   }
1329   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1330     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1331     current->is32|=1LL<<rt1[i];
1332     clear_const(current,rs1[i]);
1333     clear_const(current,rt1[i]);
1334   }
1335   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1336     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1337       if(rs1[i]!=rt1[i]) {
1338         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1339         alloc_reg64(current,i,rt1[i]);
1340         current->is32&=~(1LL<<rt1[i]);
1341       }
1342     }
1343     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1344     if(is_const(current,rs1[i])) {
1345       int v=get_const(current,rs1[i]);
1346       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1347       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1348       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1349     }
1350     else clear_const(current,rt1[i]);
1351   }
1352   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1353     if(is_const(current,rs1[i])) {
1354       int v=get_const(current,rs1[i]);
1355       set_const(current,rt1[i],v+imm[i]);
1356     }
1357     else clear_const(current,rt1[i]);
1358     current->is32|=1LL<<rt1[i];
1359   }
1360   else {
1361     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1362     current->is32|=1LL<<rt1[i];
1363   }
1364   dirty_reg(current,rt1[i]);
1365 }
1366
1367 void load_alloc(struct regstat *current,int i)
1368 {
1369   clear_const(current,rt1[i]);
1370   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1371   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1372   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1373   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1374     alloc_reg(current,i,rt1[i]);
1375     assert(get_reg(current->regmap,rt1[i])>=0);
1376     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1377     {
1378       current->is32&=~(1LL<<rt1[i]);
1379       alloc_reg64(current,i,rt1[i]);
1380     }
1381     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1382     {
1383       current->is32&=~(1LL<<rt1[i]);
1384       alloc_reg64(current,i,rt1[i]);
1385       alloc_all(current,i);
1386       alloc_reg64(current,i,FTEMP);
1387       minimum_free_regs[i]=HOST_REGS;
1388     }
1389     else current->is32|=1LL<<rt1[i];
1390     dirty_reg(current,rt1[i]);
1391     // LWL/LWR need a temporary register for the old value
1392     if(opcode[i]==0x22||opcode[i]==0x26)
1393     {
1394       alloc_reg(current,i,FTEMP);
1395       alloc_reg_temp(current,i,-1);
1396       minimum_free_regs[i]=1;
1397     }
1398   }
1399   else
1400   {
1401     // Load to r0 or unneeded register (dummy load)
1402     // but we still need a register to calculate the address
1403     if(opcode[i]==0x22||opcode[i]==0x26)
1404     {
1405       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1406     }
1407     alloc_reg_temp(current,i,-1);
1408     minimum_free_regs[i]=1;
1409     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1410     {
1411       alloc_all(current,i);
1412       alloc_reg64(current,i,FTEMP);
1413       minimum_free_regs[i]=HOST_REGS;
1414     }
1415   }
1416 }
1417
1418 void store_alloc(struct regstat *current,int i)
1419 {
1420   clear_const(current,rs2[i]);
1421   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1422   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1423   alloc_reg(current,i,rs2[i]);
1424   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1425     alloc_reg64(current,i,rs2[i]);
1426     if(rs2[i]) alloc_reg(current,i,FTEMP);
1427   }
1428   #if defined(HOST_IMM8)
1429   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1430   else alloc_reg(current,i,INVCP);
1431   #endif
1432   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1433     alloc_reg(current,i,FTEMP);
1434   }
1435   // We need a temporary register for address generation
1436   alloc_reg_temp(current,i,-1);
1437   minimum_free_regs[i]=1;
1438 }
1439
1440 void c1ls_alloc(struct regstat *current,int i)
1441 {
1442   //clear_const(current,rs1[i]); // FIXME
1443   clear_const(current,rt1[i]);
1444   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1445   alloc_reg(current,i,CSREG); // Status
1446   alloc_reg(current,i,FTEMP);
1447   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1448     alloc_reg64(current,i,FTEMP);
1449   }
1450   #if defined(HOST_IMM8)
1451   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1452   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1453     alloc_reg(current,i,INVCP);
1454   #endif
1455   // We need a temporary register for address generation
1456   alloc_reg_temp(current,i,-1);
1457 }
1458
1459 void c2ls_alloc(struct regstat *current,int i)
1460 {
1461   clear_const(current,rt1[i]);
1462   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1463   alloc_reg(current,i,FTEMP);
1464   #if defined(HOST_IMM8)
1465   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1466   if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1467     alloc_reg(current,i,INVCP);
1468   #endif
1469   // We need a temporary register for address generation
1470   alloc_reg_temp(current,i,-1);
1471   minimum_free_regs[i]=1;
1472 }
1473
1474 #ifndef multdiv_alloc
1475 void multdiv_alloc(struct regstat *current,int i)
1476 {
1477   //  case 0x18: MULT
1478   //  case 0x19: MULTU
1479   //  case 0x1A: DIV
1480   //  case 0x1B: DIVU
1481   //  case 0x1C: DMULT
1482   //  case 0x1D: DMULTU
1483   //  case 0x1E: DDIV
1484   //  case 0x1F: DDIVU
1485   clear_const(current,rs1[i]);
1486   clear_const(current,rs2[i]);
1487   if(rs1[i]&&rs2[i])
1488   {
1489     if((opcode2[i]&4)==0) // 32-bit
1490     {
1491       current->u&=~(1LL<<HIREG);
1492       current->u&=~(1LL<<LOREG);
1493       alloc_reg(current,i,HIREG);
1494       alloc_reg(current,i,LOREG);
1495       alloc_reg(current,i,rs1[i]);
1496       alloc_reg(current,i,rs2[i]);
1497       current->is32|=1LL<<HIREG;
1498       current->is32|=1LL<<LOREG;
1499       dirty_reg(current,HIREG);
1500       dirty_reg(current,LOREG);
1501     }
1502     else // 64-bit
1503     {
1504       current->u&=~(1LL<<HIREG);
1505       current->u&=~(1LL<<LOREG);
1506       current->uu&=~(1LL<<HIREG);
1507       current->uu&=~(1LL<<LOREG);
1508       alloc_reg64(current,i,HIREG);
1509       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1510       alloc_reg64(current,i,rs1[i]);
1511       alloc_reg64(current,i,rs2[i]);
1512       alloc_all(current,i);
1513       current->is32&=~(1LL<<HIREG);
1514       current->is32&=~(1LL<<LOREG);
1515       dirty_reg(current,HIREG);
1516       dirty_reg(current,LOREG);
1517       minimum_free_regs[i]=HOST_REGS;
1518     }
1519   }
1520   else
1521   {
1522     // Multiply by zero is zero.
1523     // MIPS does not have a divide by zero exception.
1524     // The result is undefined, we return zero.
1525     alloc_reg(current,i,HIREG);
1526     alloc_reg(current,i,LOREG);
1527     current->is32|=1LL<<HIREG;
1528     current->is32|=1LL<<LOREG;
1529     dirty_reg(current,HIREG);
1530     dirty_reg(current,LOREG);
1531   }
1532 }
1533 #endif
1534
1535 void cop0_alloc(struct regstat *current,int i)
1536 {
1537   if(opcode2[i]==0) // MFC0
1538   {
1539     if(rt1[i]) {
1540       clear_const(current,rt1[i]);
1541       alloc_all(current,i);
1542       alloc_reg(current,i,rt1[i]);
1543       current->is32|=1LL<<rt1[i];
1544       dirty_reg(current,rt1[i]);
1545     }
1546   }
1547   else if(opcode2[i]==4) // MTC0
1548   {
1549     if(rs1[i]){
1550       clear_const(current,rs1[i]);
1551       alloc_reg(current,i,rs1[i]);
1552       alloc_all(current,i);
1553     }
1554     else {
1555       alloc_all(current,i); // FIXME: Keep r0
1556       current->u&=~1LL;
1557       alloc_reg(current,i,0);
1558     }
1559   }
1560   else
1561   {
1562     // TLBR/TLBWI/TLBWR/TLBP/ERET
1563     assert(opcode2[i]==0x10);
1564     alloc_all(current,i);
1565   }
1566   minimum_free_regs[i]=HOST_REGS;
1567 }
1568
1569 void cop1_alloc(struct regstat *current,int i)
1570 {
1571   alloc_reg(current,i,CSREG); // Load status
1572   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1573   {
1574     if(rt1[i]){
1575       clear_const(current,rt1[i]);
1576       if(opcode2[i]==1) {
1577         alloc_reg64(current,i,rt1[i]); // DMFC1
1578         current->is32&=~(1LL<<rt1[i]);
1579       }else{
1580         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1581         current->is32|=1LL<<rt1[i];
1582       }
1583       dirty_reg(current,rt1[i]);
1584     }
1585     alloc_reg_temp(current,i,-1);
1586   }
1587   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1588   {
1589     if(rs1[i]){
1590       clear_const(current,rs1[i]);
1591       if(opcode2[i]==5)
1592         alloc_reg64(current,i,rs1[i]); // DMTC1
1593       else
1594         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1595       alloc_reg_temp(current,i,-1);
1596     }
1597     else {
1598       current->u&=~1LL;
1599       alloc_reg(current,i,0);
1600       alloc_reg_temp(current,i,-1);
1601     }
1602   }
1603   minimum_free_regs[i]=1;
1604 }
1605 void fconv_alloc(struct regstat *current,int i)
1606 {
1607   alloc_reg(current,i,CSREG); // Load status
1608   alloc_reg_temp(current,i,-1);
1609   minimum_free_regs[i]=1;
1610 }
1611 void float_alloc(struct regstat *current,int i)
1612 {
1613   alloc_reg(current,i,CSREG); // Load status
1614   alloc_reg_temp(current,i,-1);
1615   minimum_free_regs[i]=1;
1616 }
1617 void c2op_alloc(struct regstat *current,int i)
1618 {
1619   alloc_reg_temp(current,i,-1);
1620 }
1621 void fcomp_alloc(struct regstat *current,int i)
1622 {
1623   alloc_reg(current,i,CSREG); // Load status
1624   alloc_reg(current,i,FSREG); // Load flags
1625   dirty_reg(current,FSREG); // Flag will be modified
1626   alloc_reg_temp(current,i,-1);
1627   minimum_free_regs[i]=1;
1628 }
1629
1630 void syscall_alloc(struct regstat *current,int i)
1631 {
1632   alloc_cc(current,i);
1633   dirty_reg(current,CCREG);
1634   alloc_all(current,i);
1635   minimum_free_regs[i]=HOST_REGS;
1636   current->isconst=0;
1637 }
1638
1639 void delayslot_alloc(struct regstat *current,int i)
1640 {
1641   switch(itype[i]) {
1642     case UJUMP:
1643     case CJUMP:
1644     case SJUMP:
1645     case RJUMP:
1646     case FJUMP:
1647     case SYSCALL:
1648     case HLECALL:
1649     case SPAN:
1650       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1651       SysPrintf("Disabled speculative precompilation\n");
1652       stop_after_jal=1;
1653       break;
1654     case IMM16:
1655       imm16_alloc(current,i);
1656       break;
1657     case LOAD:
1658     case LOADLR:
1659       load_alloc(current,i);
1660       break;
1661     case STORE:
1662     case STORELR:
1663       store_alloc(current,i);
1664       break;
1665     case ALU:
1666       alu_alloc(current,i);
1667       break;
1668     case SHIFT:
1669       shift_alloc(current,i);
1670       break;
1671     case MULTDIV:
1672       multdiv_alloc(current,i);
1673       break;
1674     case SHIFTIMM:
1675       shiftimm_alloc(current,i);
1676       break;
1677     case MOV:
1678       mov_alloc(current,i);
1679       break;
1680     case COP0:
1681       cop0_alloc(current,i);
1682       break;
1683     case COP1:
1684     case COP2:
1685       cop1_alloc(current,i);
1686       break;
1687     case C1LS:
1688       c1ls_alloc(current,i);
1689       break;
1690     case C2LS:
1691       c2ls_alloc(current,i);
1692       break;
1693     case FCONV:
1694       fconv_alloc(current,i);
1695       break;
1696     case FLOAT:
1697       float_alloc(current,i);
1698       break;
1699     case FCOMP:
1700       fcomp_alloc(current,i);
1701       break;
1702     case C2OP:
1703       c2op_alloc(current,i);
1704       break;
1705   }
1706 }
1707
1708 // Special case where a branch and delay slot span two pages in virtual memory
1709 static void pagespan_alloc(struct regstat *current,int i)
1710 {
1711   current->isconst=0;
1712   current->wasconst=0;
1713   regs[i].wasconst=0;
1714   minimum_free_regs[i]=HOST_REGS;
1715   alloc_all(current,i);
1716   alloc_cc(current,i);
1717   dirty_reg(current,CCREG);
1718   if(opcode[i]==3) // JAL
1719   {
1720     alloc_reg(current,i,31);
1721     dirty_reg(current,31);
1722   }
1723   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1724   {
1725     alloc_reg(current,i,rs1[i]);
1726     if (rt1[i]!=0) {
1727       alloc_reg(current,i,rt1[i]);
1728       dirty_reg(current,rt1[i]);
1729     }
1730   }
1731   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1732   {
1733     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1734     if(rs2[i]) alloc_reg(current,i,rs2[i]);
1735     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1736     {
1737       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1738       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1739     }
1740   }
1741   else
1742   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1743   {
1744     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1745     if(!((current->is32>>rs1[i])&1))
1746     {
1747       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1748     }
1749   }
1750   else
1751   if(opcode[i]==0x11) // BC1
1752   {
1753     alloc_reg(current,i,FSREG);
1754     alloc_reg(current,i,CSREG);
1755   }
1756   //else ...
1757 }
1758
1759 static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1760 {
1761   stubs[stubcount][0]=type;
1762   stubs[stubcount][1]=addr;
1763   stubs[stubcount][2]=retaddr;
1764   stubs[stubcount][3]=a;
1765   stubs[stubcount][4]=b;
1766   stubs[stubcount][5]=c;
1767   stubs[stubcount][6]=d;
1768   stubs[stubcount][7]=e;
1769   stubcount++;
1770 }
1771
1772 // Write out a single register
1773 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1774 {
1775   int hr;
1776   for(hr=0;hr<HOST_REGS;hr++) {
1777     if(hr!=EXCLUDE_REG) {
1778       if((regmap[hr]&63)==r) {
1779         if((dirty>>hr)&1) {
1780           if(regmap[hr]<64) {
1781             emit_storereg(r,hr);
1782           }else{
1783             emit_storereg(r|64,hr);
1784           }
1785         }
1786       }
1787     }
1788   }
1789 }
1790
1791 int mchecksum()
1792 {
1793   //if(!tracedebug) return 0;
1794   int i;
1795   int sum=0;
1796   for(i=0;i<2097152;i++) {
1797     unsigned int temp=sum;
1798     sum<<=1;
1799     sum|=(~temp)>>31;
1800     sum^=((u_int *)rdram)[i];
1801   }
1802   return sum;
1803 }
1804 int rchecksum()
1805 {
1806   int i;
1807   int sum=0;
1808   for(i=0;i<64;i++)
1809     sum^=((u_int *)reg)[i];
1810   return sum;
1811 }
1812 void rlist()
1813 {
1814   int i;
1815   printf("TRACE: ");
1816   for(i=0;i<32;i++)
1817     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
1818   printf("\n");
1819 }
1820
1821 void enabletrace()
1822 {
1823   tracedebug=1;
1824 }
1825
1826 void memdebug(int i)
1827 {
1828   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
1829   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
1830   //rlist();
1831   //if(tracedebug) {
1832   //if(Count>=-2084597794) {
1833   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
1834   //if(0) {
1835     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
1836     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
1837     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
1838     rlist();
1839     #ifdef __i386__
1840     printf("TRACE: %x\n",(&i)[-1]);
1841     #endif
1842     #ifdef __arm__
1843     int j;
1844     printf("TRACE: %x \n",(&j)[10]);
1845     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
1846     #endif
1847     //fflush(stdout);
1848   }
1849   //printf("TRACE: %x\n",(&i)[-1]);
1850 }
1851
1852 void alu_assemble(int i,struct regstat *i_regs)
1853 {
1854   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1855     if(rt1[i]) {
1856       signed char s1,s2,t;
1857       t=get_reg(i_regs->regmap,rt1[i]);
1858       if(t>=0) {
1859         s1=get_reg(i_regs->regmap,rs1[i]);
1860         s2=get_reg(i_regs->regmap,rs2[i]);
1861         if(rs1[i]&&rs2[i]) {
1862           assert(s1>=0);
1863           assert(s2>=0);
1864           if(opcode2[i]&2) emit_sub(s1,s2,t);
1865           else emit_add(s1,s2,t);
1866         }
1867         else if(rs1[i]) {
1868           if(s1>=0) emit_mov(s1,t);
1869           else emit_loadreg(rs1[i],t);
1870         }
1871         else if(rs2[i]) {
1872           if(s2>=0) {
1873             if(opcode2[i]&2) emit_neg(s2,t);
1874             else emit_mov(s2,t);
1875           }
1876           else {
1877             emit_loadreg(rs2[i],t);
1878             if(opcode2[i]&2) emit_neg(t,t);
1879           }
1880         }
1881         else emit_zeroreg(t);
1882       }
1883     }
1884   }
1885   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1886     if(rt1[i]) {
1887       signed char s1l,s2l,s1h,s2h,tl,th;
1888       tl=get_reg(i_regs->regmap,rt1[i]);
1889       th=get_reg(i_regs->regmap,rt1[i]|64);
1890       if(tl>=0) {
1891         s1l=get_reg(i_regs->regmap,rs1[i]);
1892         s2l=get_reg(i_regs->regmap,rs2[i]);
1893         s1h=get_reg(i_regs->regmap,rs1[i]|64);
1894         s2h=get_reg(i_regs->regmap,rs2[i]|64);
1895         if(rs1[i]&&rs2[i]) {
1896           assert(s1l>=0);
1897           assert(s2l>=0);
1898           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
1899           else emit_adds(s1l,s2l,tl);
1900           if(th>=0) {
1901             #ifdef INVERTED_CARRY
1902             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
1903             #else
1904             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
1905             #endif
1906             else emit_add(s1h,s2h,th);
1907           }
1908         }
1909         else if(rs1[i]) {
1910           if(s1l>=0) emit_mov(s1l,tl);
1911           else emit_loadreg(rs1[i],tl);
1912           if(th>=0) {
1913             if(s1h>=0) emit_mov(s1h,th);
1914             else emit_loadreg(rs1[i]|64,th);
1915           }
1916         }
1917         else if(rs2[i]) {
1918           if(s2l>=0) {
1919             if(opcode2[i]&2) emit_negs(s2l,tl);
1920             else emit_mov(s2l,tl);
1921           }
1922           else {
1923             emit_loadreg(rs2[i],tl);
1924             if(opcode2[i]&2) emit_negs(tl,tl);
1925           }
1926           if(th>=0) {
1927             #ifdef INVERTED_CARRY
1928             if(s2h>=0) emit_mov(s2h,th);
1929             else emit_loadreg(rs2[i]|64,th);
1930             if(opcode2[i]&2) {
1931               emit_adcimm(-1,th); // x86 has inverted carry flag
1932               emit_not(th,th);
1933             }
1934             #else
1935             if(opcode2[i]&2) {
1936               if(s2h>=0) emit_rscimm(s2h,0,th);
1937               else {
1938                 emit_loadreg(rs2[i]|64,th);
1939                 emit_rscimm(th,0,th);
1940               }
1941             }else{
1942               if(s2h>=0) emit_mov(s2h,th);
1943               else emit_loadreg(rs2[i]|64,th);
1944             }
1945             #endif
1946           }
1947         }
1948         else {
1949           emit_zeroreg(tl);
1950           if(th>=0) emit_zeroreg(th);
1951         }
1952       }
1953     }
1954   }
1955   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1956     if(rt1[i]) {
1957       signed char s1l,s1h,s2l,s2h,t;
1958       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
1959       {
1960         t=get_reg(i_regs->regmap,rt1[i]);
1961         //assert(t>=0);
1962         if(t>=0) {
1963           s1l=get_reg(i_regs->regmap,rs1[i]);
1964           s1h=get_reg(i_regs->regmap,rs1[i]|64);
1965           s2l=get_reg(i_regs->regmap,rs2[i]);
1966           s2h=get_reg(i_regs->regmap,rs2[i]|64);
1967           if(rs2[i]==0) // rx<r0
1968           {
1969             assert(s1h>=0);
1970             if(opcode2[i]==0x2a) // SLT
1971               emit_shrimm(s1h,31,t);
1972             else // SLTU (unsigned can not be less than zero)
1973               emit_zeroreg(t);
1974           }
1975           else if(rs1[i]==0) // r0<rx
1976           {
1977             assert(s2h>=0);
1978             if(opcode2[i]==0x2a) // SLT
1979               emit_set_gz64_32(s2h,s2l,t);
1980             else // SLTU (set if not zero)
1981               emit_set_nz64_32(s2h,s2l,t);
1982           }
1983           else {
1984             assert(s1l>=0);assert(s1h>=0);
1985             assert(s2l>=0);assert(s2h>=0);
1986             if(opcode2[i]==0x2a) // SLT
1987               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
1988             else // SLTU
1989               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
1990           }
1991         }
1992       } else {
1993         t=get_reg(i_regs->regmap,rt1[i]);
1994         //assert(t>=0);
1995         if(t>=0) {
1996           s1l=get_reg(i_regs->regmap,rs1[i]);
1997           s2l=get_reg(i_regs->regmap,rs2[i]);
1998           if(rs2[i]==0) // rx<r0
1999           {
2000             assert(s1l>=0);
2001             if(opcode2[i]==0x2a) // SLT
2002               emit_shrimm(s1l,31,t);
2003             else // SLTU (unsigned can not be less than zero)
2004               emit_zeroreg(t);
2005           }
2006           else if(rs1[i]==0) // r0<rx
2007           {
2008             assert(s2l>=0);
2009             if(opcode2[i]==0x2a) // SLT
2010               emit_set_gz32(s2l,t);
2011             else // SLTU (set if not zero)
2012               emit_set_nz32(s2l,t);
2013           }
2014           else{
2015             assert(s1l>=0);assert(s2l>=0);
2016             if(opcode2[i]==0x2a) // SLT
2017               emit_set_if_less32(s1l,s2l,t);
2018             else // SLTU
2019               emit_set_if_carry32(s1l,s2l,t);
2020           }
2021         }
2022       }
2023     }
2024   }
2025   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2026     if(rt1[i]) {
2027       signed char s1l,s1h,s2l,s2h,th,tl;
2028       tl=get_reg(i_regs->regmap,rt1[i]);
2029       th=get_reg(i_regs->regmap,rt1[i]|64);
2030       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2031       {
2032         assert(tl>=0);
2033         if(tl>=0) {
2034           s1l=get_reg(i_regs->regmap,rs1[i]);
2035           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2036           s2l=get_reg(i_regs->regmap,rs2[i]);
2037           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2038           if(rs1[i]&&rs2[i]) {
2039             assert(s1l>=0);assert(s1h>=0);
2040             assert(s2l>=0);assert(s2h>=0);
2041             if(opcode2[i]==0x24) { // AND
2042               emit_and(s1l,s2l,tl);
2043               emit_and(s1h,s2h,th);
2044             } else
2045             if(opcode2[i]==0x25) { // OR
2046               emit_or(s1l,s2l,tl);
2047               emit_or(s1h,s2h,th);
2048             } else
2049             if(opcode2[i]==0x26) { // XOR
2050               emit_xor(s1l,s2l,tl);
2051               emit_xor(s1h,s2h,th);
2052             } else
2053             if(opcode2[i]==0x27) { // NOR
2054               emit_or(s1l,s2l,tl);
2055               emit_or(s1h,s2h,th);
2056               emit_not(tl,tl);
2057               emit_not(th,th);
2058             }
2059           }
2060           else
2061           {
2062             if(opcode2[i]==0x24) { // AND
2063               emit_zeroreg(tl);
2064               emit_zeroreg(th);
2065             } else
2066             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2067               if(rs1[i]){
2068                 if(s1l>=0) emit_mov(s1l,tl);
2069                 else emit_loadreg(rs1[i],tl);
2070                 if(s1h>=0) emit_mov(s1h,th);
2071                 else emit_loadreg(rs1[i]|64,th);
2072               }
2073               else
2074               if(rs2[i]){
2075                 if(s2l>=0) emit_mov(s2l,tl);
2076                 else emit_loadreg(rs2[i],tl);
2077                 if(s2h>=0) emit_mov(s2h,th);
2078                 else emit_loadreg(rs2[i]|64,th);
2079               }
2080               else{
2081                 emit_zeroreg(tl);
2082                 emit_zeroreg(th);
2083               }
2084             } else
2085             if(opcode2[i]==0x27) { // NOR
2086               if(rs1[i]){
2087                 if(s1l>=0) emit_not(s1l,tl);
2088                 else{
2089                   emit_loadreg(rs1[i],tl);
2090                   emit_not(tl,tl);
2091                 }
2092                 if(s1h>=0) emit_not(s1h,th);
2093                 else{
2094                   emit_loadreg(rs1[i]|64,th);
2095                   emit_not(th,th);
2096                 }
2097               }
2098               else
2099               if(rs2[i]){
2100                 if(s2l>=0) emit_not(s2l,tl);
2101                 else{
2102                   emit_loadreg(rs2[i],tl);
2103                   emit_not(tl,tl);
2104                 }
2105                 if(s2h>=0) emit_not(s2h,th);
2106                 else{
2107                   emit_loadreg(rs2[i]|64,th);
2108                   emit_not(th,th);
2109                 }
2110               }
2111               else {
2112                 emit_movimm(-1,tl);
2113                 emit_movimm(-1,th);
2114               }
2115             }
2116           }
2117         }
2118       }
2119       else
2120       {
2121         // 32 bit
2122         if(tl>=0) {
2123           s1l=get_reg(i_regs->regmap,rs1[i]);
2124           s2l=get_reg(i_regs->regmap,rs2[i]);
2125           if(rs1[i]&&rs2[i]) {
2126             assert(s1l>=0);
2127             assert(s2l>=0);
2128             if(opcode2[i]==0x24) { // AND
2129               emit_and(s1l,s2l,tl);
2130             } else
2131             if(opcode2[i]==0x25) { // OR
2132               emit_or(s1l,s2l,tl);
2133             } else
2134             if(opcode2[i]==0x26) { // XOR
2135               emit_xor(s1l,s2l,tl);
2136             } else
2137             if(opcode2[i]==0x27) { // NOR
2138               emit_or(s1l,s2l,tl);
2139               emit_not(tl,tl);
2140             }
2141           }
2142           else
2143           {
2144             if(opcode2[i]==0x24) { // AND
2145               emit_zeroreg(tl);
2146             } else
2147             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2148               if(rs1[i]){
2149                 if(s1l>=0) emit_mov(s1l,tl);
2150                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2151               }
2152               else
2153               if(rs2[i]){
2154                 if(s2l>=0) emit_mov(s2l,tl);
2155                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2156               }
2157               else emit_zeroreg(tl);
2158             } else
2159             if(opcode2[i]==0x27) { // NOR
2160               if(rs1[i]){
2161                 if(s1l>=0) emit_not(s1l,tl);
2162                 else {
2163                   emit_loadreg(rs1[i],tl);
2164                   emit_not(tl,tl);
2165                 }
2166               }
2167               else
2168               if(rs2[i]){
2169                 if(s2l>=0) emit_not(s2l,tl);
2170                 else {
2171                   emit_loadreg(rs2[i],tl);
2172                   emit_not(tl,tl);
2173                 }
2174               }
2175               else emit_movimm(-1,tl);
2176             }
2177           }
2178         }
2179       }
2180     }
2181   }
2182 }
2183
2184 void imm16_assemble(int i,struct regstat *i_regs)
2185 {
2186   if (opcode[i]==0x0f) { // LUI
2187     if(rt1[i]) {
2188       signed char t;
2189       t=get_reg(i_regs->regmap,rt1[i]);
2190       //assert(t>=0);
2191       if(t>=0) {
2192         if(!((i_regs->isconst>>t)&1))
2193           emit_movimm(imm[i]<<16,t);
2194       }
2195     }
2196   }
2197   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2198     if(rt1[i]) {
2199       signed char s,t;
2200       t=get_reg(i_regs->regmap,rt1[i]);
2201       s=get_reg(i_regs->regmap,rs1[i]);
2202       if(rs1[i]) {
2203         //assert(t>=0);
2204         //assert(s>=0);
2205         if(t>=0) {
2206           if(!((i_regs->isconst>>t)&1)) {
2207             if(s<0) {
2208               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2209               emit_addimm(t,imm[i],t);
2210             }else{
2211               if(!((i_regs->wasconst>>s)&1))
2212                 emit_addimm(s,imm[i],t);
2213               else
2214                 emit_movimm(constmap[i][s]+imm[i],t);
2215             }
2216           }
2217         }
2218       } else {
2219         if(t>=0) {
2220           if(!((i_regs->isconst>>t)&1))
2221             emit_movimm(imm[i],t);
2222         }
2223       }
2224     }
2225   }
2226   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2227     if(rt1[i]) {
2228       signed char sh,sl,th,tl;
2229       th=get_reg(i_regs->regmap,rt1[i]|64);
2230       tl=get_reg(i_regs->regmap,rt1[i]);
2231       sh=get_reg(i_regs->regmap,rs1[i]|64);
2232       sl=get_reg(i_regs->regmap,rs1[i]);
2233       if(tl>=0) {
2234         if(rs1[i]) {
2235           assert(sh>=0);
2236           assert(sl>=0);
2237           if(th>=0) {
2238             emit_addimm64_32(sh,sl,imm[i],th,tl);
2239           }
2240           else {
2241             emit_addimm(sl,imm[i],tl);
2242           }
2243         } else {
2244           emit_movimm(imm[i],tl);
2245           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2246         }
2247       }
2248     }
2249   }
2250   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2251     if(rt1[i]) {
2252       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2253       signed char sh,sl,t;
2254       t=get_reg(i_regs->regmap,rt1[i]);
2255       sh=get_reg(i_regs->regmap,rs1[i]|64);
2256       sl=get_reg(i_regs->regmap,rs1[i]);
2257       //assert(t>=0);
2258       if(t>=0) {
2259         if(rs1[i]>0) {
2260           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2261           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2262             if(opcode[i]==0x0a) { // SLTI
2263               if(sl<0) {
2264                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2265                 emit_slti32(t,imm[i],t);
2266               }else{
2267                 emit_slti32(sl,imm[i],t);
2268               }
2269             }
2270             else { // SLTIU
2271               if(sl<0) {
2272                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2273                 emit_sltiu32(t,imm[i],t);
2274               }else{
2275                 emit_sltiu32(sl,imm[i],t);
2276               }
2277             }
2278           }else{ // 64-bit
2279             assert(sl>=0);
2280             if(opcode[i]==0x0a) // SLTI
2281               emit_slti64_32(sh,sl,imm[i],t);
2282             else // SLTIU
2283               emit_sltiu64_32(sh,sl,imm[i],t);
2284           }
2285         }else{
2286           // SLTI(U) with r0 is just stupid,
2287           // nonetheless examples can be found
2288           if(opcode[i]==0x0a) // SLTI
2289             if(0<imm[i]) emit_movimm(1,t);
2290             else emit_zeroreg(t);
2291           else // SLTIU
2292           {
2293             if(imm[i]) emit_movimm(1,t);
2294             else emit_zeroreg(t);
2295           }
2296         }
2297       }
2298     }
2299   }
2300   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2301     if(rt1[i]) {
2302       signed char sh,sl,th,tl;
2303       th=get_reg(i_regs->regmap,rt1[i]|64);
2304       tl=get_reg(i_regs->regmap,rt1[i]);
2305       sh=get_reg(i_regs->regmap,rs1[i]|64);
2306       sl=get_reg(i_regs->regmap,rs1[i]);
2307       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2308         if(opcode[i]==0x0c) //ANDI
2309         {
2310           if(rs1[i]) {
2311             if(sl<0) {
2312               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2313               emit_andimm(tl,imm[i],tl);
2314             }else{
2315               if(!((i_regs->wasconst>>sl)&1))
2316                 emit_andimm(sl,imm[i],tl);
2317               else
2318                 emit_movimm(constmap[i][sl]&imm[i],tl);
2319             }
2320           }
2321           else
2322             emit_zeroreg(tl);
2323           if(th>=0) emit_zeroreg(th);
2324         }
2325         else
2326         {
2327           if(rs1[i]) {
2328             if(sl<0) {
2329               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2330             }
2331             if(th>=0) {
2332               if(sh<0) {
2333                 emit_loadreg(rs1[i]|64,th);
2334               }else{
2335                 emit_mov(sh,th);
2336               }
2337             }
2338             if(opcode[i]==0x0d) { // ORI
2339               if(sl<0) {
2340                 emit_orimm(tl,imm[i],tl);
2341               }else{
2342                 if(!((i_regs->wasconst>>sl)&1))
2343                   emit_orimm(sl,imm[i],tl);
2344                 else
2345                   emit_movimm(constmap[i][sl]|imm[i],tl);
2346               }
2347             }
2348             if(opcode[i]==0x0e) { // XORI
2349               if(sl<0) {
2350                 emit_xorimm(tl,imm[i],tl);
2351               }else{
2352                 if(!((i_regs->wasconst>>sl)&1))
2353                   emit_xorimm(sl,imm[i],tl);
2354                 else
2355                   emit_movimm(constmap[i][sl]^imm[i],tl);
2356               }
2357             }
2358           }
2359           else {
2360             emit_movimm(imm[i],tl);
2361             if(th>=0) emit_zeroreg(th);
2362           }
2363         }
2364       }
2365     }
2366   }
2367 }
2368
2369 void shiftimm_assemble(int i,struct regstat *i_regs)
2370 {
2371   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2372   {
2373     if(rt1[i]) {
2374       signed char s,t;
2375       t=get_reg(i_regs->regmap,rt1[i]);
2376       s=get_reg(i_regs->regmap,rs1[i]);
2377       //assert(t>=0);
2378       if(t>=0&&!((i_regs->isconst>>t)&1)){
2379         if(rs1[i]==0)
2380         {
2381           emit_zeroreg(t);
2382         }
2383         else
2384         {
2385           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2386           if(imm[i]) {
2387             if(opcode2[i]==0) // SLL
2388             {
2389               emit_shlimm(s<0?t:s,imm[i],t);
2390             }
2391             if(opcode2[i]==2) // SRL
2392             {
2393               emit_shrimm(s<0?t:s,imm[i],t);
2394             }
2395             if(opcode2[i]==3) // SRA
2396             {
2397               emit_sarimm(s<0?t:s,imm[i],t);
2398             }
2399           }else{
2400             // Shift by zero
2401             if(s>=0 && s!=t) emit_mov(s,t);
2402           }
2403         }
2404       }
2405       //emit_storereg(rt1[i],t); //DEBUG
2406     }
2407   }
2408   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2409   {
2410     if(rt1[i]) {
2411       signed char sh,sl,th,tl;
2412       th=get_reg(i_regs->regmap,rt1[i]|64);
2413       tl=get_reg(i_regs->regmap,rt1[i]);
2414       sh=get_reg(i_regs->regmap,rs1[i]|64);
2415       sl=get_reg(i_regs->regmap,rs1[i]);
2416       if(tl>=0) {
2417         if(rs1[i]==0)
2418         {
2419           emit_zeroreg(tl);
2420           if(th>=0) emit_zeroreg(th);
2421         }
2422         else
2423         {
2424           assert(sl>=0);
2425           assert(sh>=0);
2426           if(imm[i]) {
2427             if(opcode2[i]==0x38) // DSLL
2428             {
2429               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2430               emit_shlimm(sl,imm[i],tl);
2431             }
2432             if(opcode2[i]==0x3a) // DSRL
2433             {
2434               emit_shrdimm(sl,sh,imm[i],tl);
2435               if(th>=0) emit_shrimm(sh,imm[i],th);
2436             }
2437             if(opcode2[i]==0x3b) // DSRA
2438             {
2439               emit_shrdimm(sl,sh,imm[i],tl);
2440               if(th>=0) emit_sarimm(sh,imm[i],th);
2441             }
2442           }else{
2443             // Shift by zero
2444             if(sl!=tl) emit_mov(sl,tl);
2445             if(th>=0&&sh!=th) emit_mov(sh,th);
2446           }
2447         }
2448       }
2449     }
2450   }
2451   if(opcode2[i]==0x3c) // DSLL32
2452   {
2453     if(rt1[i]) {
2454       signed char sl,tl,th;
2455       tl=get_reg(i_regs->regmap,rt1[i]);
2456       th=get_reg(i_regs->regmap,rt1[i]|64);
2457       sl=get_reg(i_regs->regmap,rs1[i]);
2458       if(th>=0||tl>=0){
2459         assert(tl>=0);
2460         assert(th>=0);
2461         assert(sl>=0);
2462         emit_mov(sl,th);
2463         emit_zeroreg(tl);
2464         if(imm[i]>32)
2465         {
2466           emit_shlimm(th,imm[i]&31,th);
2467         }
2468       }
2469     }
2470   }
2471   if(opcode2[i]==0x3e) // DSRL32
2472   {
2473     if(rt1[i]) {
2474       signed char sh,tl,th;
2475       tl=get_reg(i_regs->regmap,rt1[i]);
2476       th=get_reg(i_regs->regmap,rt1[i]|64);
2477       sh=get_reg(i_regs->regmap,rs1[i]|64);
2478       if(tl>=0){
2479         assert(sh>=0);
2480         emit_mov(sh,tl);
2481         if(th>=0) emit_zeroreg(th);
2482         if(imm[i]>32)
2483         {
2484           emit_shrimm(tl,imm[i]&31,tl);
2485         }
2486       }
2487     }
2488   }
2489   if(opcode2[i]==0x3f) // DSRA32
2490   {
2491     if(rt1[i]) {
2492       signed char sh,tl;
2493       tl=get_reg(i_regs->regmap,rt1[i]);
2494       sh=get_reg(i_regs->regmap,rs1[i]|64);
2495       if(tl>=0){
2496         assert(sh>=0);
2497         emit_mov(sh,tl);
2498         if(imm[i]>32)
2499         {
2500           emit_sarimm(tl,imm[i]&31,tl);
2501         }
2502       }
2503     }
2504   }
2505 }
2506
2507 #ifndef shift_assemble
2508 void shift_assemble(int i,struct regstat *i_regs)
2509 {
2510   printf("Need shift_assemble for this architecture.\n");
2511   exit(1);
2512 }
2513 #endif
2514
2515 void load_assemble(int i,struct regstat *i_regs)
2516 {
2517   int s,th,tl,addr,map=-1;
2518   int offset;
2519   int jaddr=0;
2520   int memtarget=0,c=0;
2521   int fastload_reg_override=0;
2522   u_int hr,reglist=0;
2523   th=get_reg(i_regs->regmap,rt1[i]|64);
2524   tl=get_reg(i_regs->regmap,rt1[i]);
2525   s=get_reg(i_regs->regmap,rs1[i]);
2526   offset=imm[i];
2527   for(hr=0;hr<HOST_REGS;hr++) {
2528     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2529   }
2530   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2531   if(s>=0) {
2532     c=(i_regs->wasconst>>s)&1;
2533     if (c) {
2534       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2535     }
2536   }
2537   //printf("load_assemble: c=%d\n",c);
2538   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2539   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2540   if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
2541     ||rt1[i]==0) {
2542       // could be FIFO, must perform the read
2543       // ||dummy read
2544       assem_debug("(forced read)\n");
2545       tl=get_reg(i_regs->regmap,-1);
2546       assert(tl>=0);
2547   }
2548   if(offset||s<0||c) addr=tl;
2549   else addr=s;
2550   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2551  if(tl>=0) {
2552   //printf("load_assemble: c=%d\n",c);
2553   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2554   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2555   reglist&=~(1<<tl);
2556   if(th>=0) reglist&=~(1<<th);
2557   if(!c) {
2558     #ifdef RAM_OFFSET
2559     map=get_reg(i_regs->regmap,ROREG);
2560     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2561     #endif
2562     #ifdef R29_HACK
2563     // Strmnnrmn's speed hack
2564     if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2565     #endif
2566     {
2567       jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2568     }
2569   }
2570   else if(ram_offset&&memtarget) {
2571     emit_addimm(addr,ram_offset,HOST_TEMPREG);
2572     fastload_reg_override=HOST_TEMPREG;
2573   }
2574   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2575   if (opcode[i]==0x20) { // LB
2576     if(!c||memtarget) {
2577       if(!dummy) {
2578         #ifdef HOST_IMM_ADDR32
2579         if(c)
2580           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2581         else
2582         #endif
2583         {
2584           //emit_xorimm(addr,3,tl);
2585           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2586           int x=0,a=tl;
2587 #ifdef BIG_ENDIAN_MIPS
2588           if(!c) emit_xorimm(addr,3,tl);
2589           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2590 #else
2591           if(!c) a=addr;
2592 #endif
2593           if(fastload_reg_override) a=fastload_reg_override;
2594
2595           emit_movsbl_indexed_tlb(x,a,map,tl);
2596         }
2597       }
2598       if(jaddr)
2599         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2600     }
2601     else
2602       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2603   }
2604   if (opcode[i]==0x21) { // LH
2605     if(!c||memtarget) {
2606       if(!dummy) {
2607         #ifdef HOST_IMM_ADDR32
2608         if(c)
2609           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2610         else
2611         #endif
2612         {
2613           int x=0,a=tl;
2614 #ifdef BIG_ENDIAN_MIPS
2615           if(!c) emit_xorimm(addr,2,tl);
2616           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2617 #else
2618           if(!c) a=addr;
2619 #endif
2620           if(fastload_reg_override) a=fastload_reg_override;
2621           //#ifdef
2622           //emit_movswl_indexed_tlb(x,tl,map,tl);
2623           //else
2624           if(map>=0) {
2625             emit_movswl_indexed(x,a,tl);
2626           }else{
2627             #if 1 //def RAM_OFFSET
2628             emit_movswl_indexed(x,a,tl);
2629             #else
2630             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2631             #endif
2632           }
2633         }
2634       }
2635       if(jaddr)
2636         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2637     }
2638     else
2639       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2640   }
2641   if (opcode[i]==0x23) { // LW
2642     if(!c||memtarget) {
2643       if(!dummy) {
2644         int a=addr;
2645         if(fastload_reg_override) a=fastload_reg_override;
2646         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2647         #ifdef HOST_IMM_ADDR32
2648         if(c)
2649           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2650         else
2651         #endif
2652         emit_readword_indexed_tlb(0,a,map,tl);
2653       }
2654       if(jaddr)
2655         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2656     }
2657     else
2658       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2659   }
2660   if (opcode[i]==0x24) { // LBU
2661     if(!c||memtarget) {
2662       if(!dummy) {
2663         #ifdef HOST_IMM_ADDR32
2664         if(c)
2665           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2666         else
2667         #endif
2668         {
2669           //emit_xorimm(addr,3,tl);
2670           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2671           int x=0,a=tl;
2672 #ifdef BIG_ENDIAN_MIPS
2673           if(!c) emit_xorimm(addr,3,tl);
2674           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2675 #else
2676           if(!c) a=addr;
2677 #endif
2678           if(fastload_reg_override) a=fastload_reg_override;
2679
2680           emit_movzbl_indexed_tlb(x,a,map,tl);
2681         }
2682       }
2683       if(jaddr)
2684         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2685     }
2686     else
2687       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2688   }
2689   if (opcode[i]==0x25) { // LHU
2690     if(!c||memtarget) {
2691       if(!dummy) {
2692         #ifdef HOST_IMM_ADDR32
2693         if(c)
2694           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2695         else
2696         #endif
2697         {
2698           int x=0,a=tl;
2699 #ifdef BIG_ENDIAN_MIPS
2700           if(!c) emit_xorimm(addr,2,tl);
2701           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2702 #else
2703           if(!c) a=addr;
2704 #endif
2705           if(fastload_reg_override) a=fastload_reg_override;
2706           //#ifdef
2707           //emit_movzwl_indexed_tlb(x,tl,map,tl);
2708           //#else
2709           if(map>=0) {
2710             emit_movzwl_indexed(x,a,tl);
2711           }else{
2712             #if 1 //def RAM_OFFSET
2713             emit_movzwl_indexed(x,a,tl);
2714             #else
2715             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2716             #endif
2717           }
2718         }
2719       }
2720       if(jaddr)
2721         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2722     }
2723     else
2724       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2725   }
2726   if (opcode[i]==0x27) { // LWU
2727     assert(th>=0);
2728     if(!c||memtarget) {
2729       if(!dummy) {
2730         int a=addr;
2731         if(fastload_reg_override) a=fastload_reg_override;
2732         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2733         #ifdef HOST_IMM_ADDR32
2734         if(c)
2735           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2736         else
2737         #endif
2738         emit_readword_indexed_tlb(0,a,map,tl);
2739       }
2740       if(jaddr)
2741         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2742     }
2743     else {
2744       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2745     }
2746     emit_zeroreg(th);
2747   }
2748   if (opcode[i]==0x37) { // LD
2749     if(!c||memtarget) {
2750       if(!dummy) {
2751         int a=addr;
2752         if(fastload_reg_override) a=fastload_reg_override;
2753         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2754         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2755         #ifdef HOST_IMM_ADDR32
2756         if(c)
2757           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2758         else
2759         #endif
2760         emit_readdword_indexed_tlb(0,a,map,th,tl);
2761       }
2762       if(jaddr)
2763         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2764     }
2765     else
2766       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2767   }
2768  }
2769   //emit_storereg(rt1[i],tl); // DEBUG
2770   //if(opcode[i]==0x23)
2771   //if(opcode[i]==0x24)
2772   //if(opcode[i]==0x23||opcode[i]==0x24)
2773   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2774   {
2775     //emit_pusha();
2776     save_regs(0x100f);
2777         emit_readword((int)&last_count,ECX);
2778         #ifdef __i386__
2779         if(get_reg(i_regs->regmap,CCREG)<0)
2780           emit_loadreg(CCREG,HOST_CCREG);
2781         emit_add(HOST_CCREG,ECX,HOST_CCREG);
2782         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2783         emit_writeword(HOST_CCREG,(int)&Count);
2784         #endif
2785         #ifdef __arm__
2786         if(get_reg(i_regs->regmap,CCREG)<0)
2787           emit_loadreg(CCREG,0);
2788         else
2789           emit_mov(HOST_CCREG,0);
2790         emit_add(0,ECX,0);
2791         emit_addimm(0,2*ccadj[i],0);
2792         emit_writeword(0,(int)&Count);
2793         #endif
2794     emit_call((int)memdebug);
2795     //emit_popa();
2796     restore_regs(0x100f);
2797   }*/
2798 }
2799
2800 #ifndef loadlr_assemble
2801 void loadlr_assemble(int i,struct regstat *i_regs)
2802 {
2803   printf("Need loadlr_assemble for this architecture.\n");
2804   exit(1);
2805 }
2806 #endif
2807
2808 void store_assemble(int i,struct regstat *i_regs)
2809 {
2810   int s,th,tl,map=-1;
2811   int addr,temp;
2812   int offset;
2813   int jaddr=0,type;
2814   int memtarget=0,c=0;
2815   int agr=AGEN1+(i&1);
2816   int faststore_reg_override=0;
2817   u_int hr,reglist=0;
2818   th=get_reg(i_regs->regmap,rs2[i]|64);
2819   tl=get_reg(i_regs->regmap,rs2[i]);
2820   s=get_reg(i_regs->regmap,rs1[i]);
2821   temp=get_reg(i_regs->regmap,agr);
2822   if(temp<0) temp=get_reg(i_regs->regmap,-1);
2823   offset=imm[i];
2824   if(s>=0) {
2825     c=(i_regs->wasconst>>s)&1;
2826     if(c) {
2827       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2828     }
2829   }
2830   assert(tl>=0);
2831   assert(temp>=0);
2832   for(hr=0;hr<HOST_REGS;hr++) {
2833     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2834   }
2835   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2836   if(offset||s<0||c) addr=temp;
2837   else addr=s;
2838   if(!c) {
2839     jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
2840   }
2841   else if(ram_offset&&memtarget) {
2842     emit_addimm(addr,ram_offset,HOST_TEMPREG);
2843     faststore_reg_override=HOST_TEMPREG;
2844   }
2845
2846   if (opcode[i]==0x28) { // SB
2847     if(!c||memtarget) {
2848       int x=0,a=temp;
2849 #ifdef BIG_ENDIAN_MIPS
2850       if(!c) emit_xorimm(addr,3,temp);
2851       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2852 #else
2853       if(!c) a=addr;
2854 #endif
2855       if(faststore_reg_override) a=faststore_reg_override;
2856       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
2857       emit_writebyte_indexed_tlb(tl,x,a,map,a);
2858     }
2859     type=STOREB_STUB;
2860   }
2861   if (opcode[i]==0x29) { // SH
2862     if(!c||memtarget) {
2863       int x=0,a=temp;
2864 #ifdef BIG_ENDIAN_MIPS
2865       if(!c) emit_xorimm(addr,2,temp);
2866       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2867 #else
2868       if(!c) a=addr;
2869 #endif
2870       if(faststore_reg_override) a=faststore_reg_override;
2871       //#ifdef
2872       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
2873       //#else
2874       if(map>=0) {
2875         emit_writehword_indexed(tl,x,a);
2876       }else
2877         //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
2878         emit_writehword_indexed(tl,x,a);
2879     }
2880     type=STOREH_STUB;
2881   }
2882   if (opcode[i]==0x2B) { // SW
2883     if(!c||memtarget) {
2884       int a=addr;
2885       if(faststore_reg_override) a=faststore_reg_override;
2886       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
2887       emit_writeword_indexed_tlb(tl,0,a,map,temp);
2888     }
2889     type=STOREW_STUB;
2890   }
2891   if (opcode[i]==0x3F) { // SD
2892     if(!c||memtarget) {
2893       int a=addr;
2894       if(faststore_reg_override) a=faststore_reg_override;
2895       if(rs2[i]) {
2896         assert(th>=0);
2897         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
2898         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
2899         emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
2900       }else{
2901         // Store zero
2902         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
2903         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
2904         emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
2905       }
2906     }
2907     type=STORED_STUB;
2908   }
2909   if(jaddr) {
2910     // PCSX store handlers don't check invcode again
2911     reglist|=1<<addr;
2912     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2913     jaddr=0;
2914   }
2915   if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
2916     if(!c||memtarget) {
2917       #ifdef DESTRUCTIVE_SHIFT
2918       // The x86 shift operation is 'destructive'; it overwrites the
2919       // source register, so we need to make a copy first and use that.
2920       addr=temp;
2921       #endif
2922       #if defined(HOST_IMM8)
2923       int ir=get_reg(i_regs->regmap,INVCP);
2924       assert(ir>=0);
2925       emit_cmpmem_indexedsr12_reg(ir,addr,1);
2926       #else
2927       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
2928       #endif
2929       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
2930       emit_callne(invalidate_addr_reg[addr]);
2931       #else
2932       int jaddr2=(int)out;
2933       emit_jne(0);
2934       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
2935       #endif
2936     }
2937   }
2938   u_int addr_val=constmap[i][s]+offset;
2939   if(jaddr) {
2940     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2941   } else if(c&&!memtarget) {
2942     inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
2943   }
2944   // basic current block modification detection..
2945   // not looking back as that should be in mips cache already
2946   if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
2947     SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
2948     assert(i_regs->regmap==regs[i].regmap); // not delay slot
2949     if(i_regs->regmap==regs[i].regmap) {
2950       load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
2951       wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
2952       emit_movimm(start+i*4+4,0);
2953       emit_writeword(0,(int)&pcaddr);
2954       emit_jmp((int)do_interrupt);
2955     }
2956   }
2957   //if(opcode[i]==0x2B || opcode[i]==0x3F)
2958   //if(opcode[i]==0x2B || opcode[i]==0x28)
2959   //if(opcode[i]==0x2B || opcode[i]==0x29)
2960   //if(opcode[i]==0x2B)
2961   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
2962   {
2963     #ifdef __i386__
2964     emit_pusha();
2965     #endif
2966     #ifdef __arm__
2967     save_regs(0x100f);
2968     #endif
2969         emit_readword((int)&last_count,ECX);
2970         #ifdef __i386__
2971         if(get_reg(i_regs->regmap,CCREG)<0)
2972           emit_loadreg(CCREG,HOST_CCREG);
2973         emit_add(HOST_CCREG,ECX,HOST_CCREG);
2974         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2975         emit_writeword(HOST_CCREG,(int)&Count);
2976         #endif
2977         #ifdef __arm__
2978         if(get_reg(i_regs->regmap,CCREG)<0)
2979           emit_loadreg(CCREG,0);
2980         else
2981           emit_mov(HOST_CCREG,0);
2982         emit_add(0,ECX,0);
2983         emit_addimm(0,2*ccadj[i],0);
2984         emit_writeword(0,(int)&Count);
2985         #endif
2986     emit_call((int)memdebug);
2987     #ifdef __i386__
2988     emit_popa();
2989     #endif
2990     #ifdef __arm__
2991     restore_regs(0x100f);
2992     #endif
2993   }*/
2994 }
2995
2996 void storelr_assemble(int i,struct regstat *i_regs)
2997 {
2998   int s,th,tl;
2999   int temp;
3000   int temp2=-1;
3001   int offset;
3002   int jaddr=0;
3003   int case1,case2,case3;
3004   int done0,done1,done2;
3005   int memtarget=0,c=0;
3006   int agr=AGEN1+(i&1);
3007   u_int hr,reglist=0;
3008   th=get_reg(i_regs->regmap,rs2[i]|64);
3009   tl=get_reg(i_regs->regmap,rs2[i]);
3010   s=get_reg(i_regs->regmap,rs1[i]);
3011   temp=get_reg(i_regs->regmap,agr);
3012   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3013   offset=imm[i];
3014   if(s>=0) {
3015     c=(i_regs->isconst>>s)&1;
3016     if(c) {
3017       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3018     }
3019   }
3020   assert(tl>=0);
3021   for(hr=0;hr<HOST_REGS;hr++) {
3022     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3023   }
3024   assert(temp>=0);
3025   if(!c) {
3026     emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3027     if(!offset&&s!=temp) emit_mov(s,temp);
3028     jaddr=(int)out;
3029     emit_jno(0);
3030   }
3031   else
3032   {
3033     if(!memtarget||!rs1[i]) {
3034       jaddr=(int)out;
3035       emit_jmp(0);
3036     }
3037   }
3038   #ifdef RAM_OFFSET
3039   int map=get_reg(i_regs->regmap,ROREG);
3040   if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3041   #else
3042   if((u_int)rdram!=0x80000000)
3043     emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3044   #endif
3045
3046   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3047     temp2=get_reg(i_regs->regmap,FTEMP);
3048     if(!rs2[i]) temp2=th=tl;
3049   }
3050
3051 #ifndef BIG_ENDIAN_MIPS
3052     emit_xorimm(temp,3,temp);
3053 #endif
3054   emit_testimm(temp,2);
3055   case2=(int)out;
3056   emit_jne(0);
3057   emit_testimm(temp,1);
3058   case1=(int)out;
3059   emit_jne(0);
3060   // 0
3061   if (opcode[i]==0x2A) { // SWL
3062     emit_writeword_indexed(tl,0,temp);
3063   }
3064   if (opcode[i]==0x2E) { // SWR
3065     emit_writebyte_indexed(tl,3,temp);
3066   }
3067   if (opcode[i]==0x2C) { // SDL
3068     emit_writeword_indexed(th,0,temp);
3069     if(rs2[i]) emit_mov(tl,temp2);
3070   }
3071   if (opcode[i]==0x2D) { // SDR
3072     emit_writebyte_indexed(tl,3,temp);
3073     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3074   }
3075   done0=(int)out;
3076   emit_jmp(0);
3077   // 1
3078   set_jump_target(case1,(int)out);
3079   if (opcode[i]==0x2A) { // SWL
3080     // Write 3 msb into three least significant bytes
3081     if(rs2[i]) emit_rorimm(tl,8,tl);
3082     emit_writehword_indexed(tl,-1,temp);
3083     if(rs2[i]) emit_rorimm(tl,16,tl);
3084     emit_writebyte_indexed(tl,1,temp);
3085     if(rs2[i]) emit_rorimm(tl,8,tl);
3086   }
3087   if (opcode[i]==0x2E) { // SWR
3088     // Write two lsb into two most significant bytes
3089     emit_writehword_indexed(tl,1,temp);
3090   }
3091   if (opcode[i]==0x2C) { // SDL
3092     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3093     // Write 3 msb into three least significant bytes
3094     if(rs2[i]) emit_rorimm(th,8,th);
3095     emit_writehword_indexed(th,-1,temp);
3096     if(rs2[i]) emit_rorimm(th,16,th);
3097     emit_writebyte_indexed(th,1,temp);
3098     if(rs2[i]) emit_rorimm(th,8,th);
3099   }
3100   if (opcode[i]==0x2D) { // SDR
3101     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3102     // Write two lsb into two most significant bytes
3103     emit_writehword_indexed(tl,1,temp);
3104   }
3105   done1=(int)out;
3106   emit_jmp(0);
3107   // 2
3108   set_jump_target(case2,(int)out);
3109   emit_testimm(temp,1);
3110   case3=(int)out;
3111   emit_jne(0);
3112   if (opcode[i]==0x2A) { // SWL
3113     // Write two msb into two least significant bytes
3114     if(rs2[i]) emit_rorimm(tl,16,tl);
3115     emit_writehword_indexed(tl,-2,temp);
3116     if(rs2[i]) emit_rorimm(tl,16,tl);
3117   }
3118   if (opcode[i]==0x2E) { // SWR
3119     // Write 3 lsb into three most significant bytes
3120     emit_writebyte_indexed(tl,-1,temp);
3121     if(rs2[i]) emit_rorimm(tl,8,tl);
3122     emit_writehword_indexed(tl,0,temp);
3123     if(rs2[i]) emit_rorimm(tl,24,tl);
3124   }
3125   if (opcode[i]==0x2C) { // SDL
3126     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3127     // Write two msb into two least significant bytes
3128     if(rs2[i]) emit_rorimm(th,16,th);
3129     emit_writehword_indexed(th,-2,temp);
3130     if(rs2[i]) emit_rorimm(th,16,th);
3131   }
3132   if (opcode[i]==0x2D) { // SDR
3133     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3134     // Write 3 lsb into three most significant bytes
3135     emit_writebyte_indexed(tl,-1,temp);
3136     if(rs2[i]) emit_rorimm(tl,8,tl);
3137     emit_writehword_indexed(tl,0,temp);
3138     if(rs2[i]) emit_rorimm(tl,24,tl);
3139   }
3140   done2=(int)out;
3141   emit_jmp(0);
3142   // 3
3143   set_jump_target(case3,(int)out);
3144   if (opcode[i]==0x2A) { // SWL
3145     // Write msb into least significant byte
3146     if(rs2[i]) emit_rorimm(tl,24,tl);
3147     emit_writebyte_indexed(tl,-3,temp);
3148     if(rs2[i]) emit_rorimm(tl,8,tl);
3149   }
3150   if (opcode[i]==0x2E) { // SWR
3151     // Write entire word
3152     emit_writeword_indexed(tl,-3,temp);
3153   }
3154   if (opcode[i]==0x2C) { // SDL
3155     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3156     // Write msb into least significant byte
3157     if(rs2[i]) emit_rorimm(th,24,th);
3158     emit_writebyte_indexed(th,-3,temp);
3159     if(rs2[i]) emit_rorimm(th,8,th);
3160   }
3161   if (opcode[i]==0x2D) { // SDR
3162     if(rs2[i]) emit_mov(th,temp2);
3163     // Write entire word
3164     emit_writeword_indexed(tl,-3,temp);
3165   }
3166   set_jump_target(done0,(int)out);
3167   set_jump_target(done1,(int)out);
3168   set_jump_target(done2,(int)out);
3169   if (opcode[i]==0x2C) { // SDL
3170     emit_testimm(temp,4);
3171     done0=(int)out;
3172     emit_jne(0);
3173     emit_andimm(temp,~3,temp);
3174     emit_writeword_indexed(temp2,4,temp);
3175     set_jump_target(done0,(int)out);
3176   }
3177   if (opcode[i]==0x2D) { // SDR
3178     emit_testimm(temp,4);
3179     done0=(int)out;
3180     emit_jeq(0);
3181     emit_andimm(temp,~3,temp);
3182     emit_writeword_indexed(temp2,-4,temp);
3183     set_jump_target(done0,(int)out);
3184   }
3185   if(!c||!memtarget)
3186     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3187   if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3188     #ifdef RAM_OFFSET
3189     int map=get_reg(i_regs->regmap,ROREG);
3190     if(map<0) map=HOST_TEMPREG;
3191     gen_orig_addr_w(temp,map);
3192     #else
3193     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3194     #endif
3195     #if defined(HOST_IMM8)
3196     int ir=get_reg(i_regs->regmap,INVCP);
3197     assert(ir>=0);
3198     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3199     #else
3200     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3201     #endif
3202     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3203     emit_callne(invalidate_addr_reg[temp]);
3204     #else
3205     int jaddr2=(int)out;
3206     emit_jne(0);
3207     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3208     #endif
3209   }
3210   /*
3211     emit_pusha();
3212     //save_regs(0x100f);
3213         emit_readword((int)&last_count,ECX);
3214         if(get_reg(i_regs->regmap,CCREG)<0)
3215           emit_loadreg(CCREG,HOST_CCREG);
3216         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3217         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3218         emit_writeword(HOST_CCREG,(int)&Count);
3219     emit_call((int)memdebug);
3220     emit_popa();
3221     //restore_regs(0x100f);
3222   */
3223 }
3224
3225 void c1ls_assemble(int i,struct regstat *i_regs)
3226 {
3227   cop1_unusable(i, i_regs);
3228 }
3229
3230 void c2ls_assemble(int i,struct regstat *i_regs)
3231 {
3232   int s,tl;
3233   int ar;
3234   int offset;
3235   int memtarget=0,c=0;
3236   int jaddr2=0,type;
3237   int agr=AGEN1+(i&1);
3238   int fastio_reg_override=0;
3239   u_int hr,reglist=0;
3240   u_int copr=(source[i]>>16)&0x1f;
3241   s=get_reg(i_regs->regmap,rs1[i]);
3242   tl=get_reg(i_regs->regmap,FTEMP);
3243   offset=imm[i];
3244   assert(rs1[i]>0);
3245   assert(tl>=0);
3246
3247   for(hr=0;hr<HOST_REGS;hr++) {
3248     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3249   }
3250   if(i_regs->regmap[HOST_CCREG]==CCREG)
3251     reglist&=~(1<<HOST_CCREG);
3252
3253   // get the address
3254   if (opcode[i]==0x3a) { // SWC2
3255     ar=get_reg(i_regs->regmap,agr);
3256     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3257     reglist|=1<<ar;
3258   } else { // LWC2
3259     ar=tl;
3260   }
3261   if(s>=0) c=(i_regs->wasconst>>s)&1;
3262   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3263   if (!offset&&!c&&s>=0) ar=s;
3264   assert(ar>=0);
3265
3266   if (opcode[i]==0x3a) { // SWC2
3267     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3268     type=STOREW_STUB;
3269   }
3270   else
3271     type=LOADW_STUB;
3272
3273   if(c&&!memtarget) {
3274     jaddr2=(int)out;
3275     emit_jmp(0); // inline_readstub/inline_writestub?
3276   }
3277   else {
3278     if(!c) {
3279       jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3280     }
3281     else if(ram_offset&&memtarget) {
3282       emit_addimm(ar,ram_offset,HOST_TEMPREG);
3283       fastio_reg_override=HOST_TEMPREG;
3284     }
3285     if (opcode[i]==0x32) { // LWC2
3286       #ifdef HOST_IMM_ADDR32
3287       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3288       else
3289       #endif
3290       int a=ar;
3291       if(fastio_reg_override) a=fastio_reg_override;
3292       emit_readword_indexed(0,a,tl);
3293     }
3294     if (opcode[i]==0x3a) { // SWC2
3295       #ifdef DESTRUCTIVE_SHIFT
3296       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3297       #endif
3298       int a=ar;
3299       if(fastio_reg_override) a=fastio_reg_override;
3300       emit_writeword_indexed(tl,0,a);
3301     }
3302   }
3303   if(jaddr2)
3304     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3305   if(opcode[i]==0x3a) // SWC2
3306   if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3307 #if defined(HOST_IMM8)
3308     int ir=get_reg(i_regs->regmap,INVCP);
3309     assert(ir>=0);
3310     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3311 #else
3312     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3313 #endif
3314     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3315     emit_callne(invalidate_addr_reg[ar]);
3316     #else
3317     int jaddr3=(int)out;
3318     emit_jne(0);
3319     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3320     #endif
3321   }
3322   if (opcode[i]==0x32) { // LWC2
3323     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3324   }
3325 }
3326
3327 #ifndef multdiv_assemble
3328 void multdiv_assemble(int i,struct regstat *i_regs)
3329 {
3330   printf("Need multdiv_assemble for this architecture.\n");
3331   exit(1);
3332 }
3333 #endif
3334
3335 void mov_assemble(int i,struct regstat *i_regs)
3336 {
3337   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3338   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3339   if(rt1[i]) {
3340     signed char sh,sl,th,tl;
3341     th=get_reg(i_regs->regmap,rt1[i]|64);
3342     tl=get_reg(i_regs->regmap,rt1[i]);
3343     //assert(tl>=0);
3344     if(tl>=0) {
3345       sh=get_reg(i_regs->regmap,rs1[i]|64);
3346       sl=get_reg(i_regs->regmap,rs1[i]);
3347       if(sl>=0) emit_mov(sl,tl);
3348       else emit_loadreg(rs1[i],tl);
3349       if(th>=0) {
3350         if(sh>=0) emit_mov(sh,th);
3351         else emit_loadreg(rs1[i]|64,th);
3352       }
3353     }
3354   }
3355 }
3356
3357 #ifndef fconv_assemble
3358 void fconv_assemble(int i,struct regstat *i_regs)
3359 {
3360   printf("Need fconv_assemble for this architecture.\n");
3361   exit(1);
3362 }
3363 #endif
3364
3365 #if 0
3366 void float_assemble(int i,struct regstat *i_regs)
3367 {
3368   printf("Need float_assemble for this architecture.\n");
3369   exit(1);
3370 }
3371 #endif
3372
3373 void syscall_assemble(int i,struct regstat *i_regs)
3374 {
3375   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3376   assert(ccreg==HOST_CCREG);
3377   assert(!is_delayslot);
3378   (void)ccreg;
3379   emit_movimm(start+i*4,EAX); // Get PC
3380   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3381   emit_jmp((int)jump_syscall_hle); // XXX
3382 }
3383
3384 void hlecall_assemble(int i,struct regstat *i_regs)
3385 {
3386   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3387   assert(ccreg==HOST_CCREG);
3388   assert(!is_delayslot);
3389   (void)ccreg;
3390   emit_movimm(start+i*4+4,0); // Get PC
3391   emit_movimm((int)psxHLEt[source[i]&7],1);
3392   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
3393   emit_jmp((int)jump_hlecall);
3394 }
3395
3396 void intcall_assemble(int i,struct regstat *i_regs)
3397 {
3398   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3399   assert(ccreg==HOST_CCREG);
3400   assert(!is_delayslot);
3401   (void)ccreg;
3402   emit_movimm(start+i*4,0); // Get PC
3403   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3404   emit_jmp((int)jump_intcall);
3405 }
3406
3407 void ds_assemble(int i,struct regstat *i_regs)
3408 {
3409   speculate_register_values(i);
3410   is_delayslot=1;
3411   switch(itype[i]) {
3412     case ALU:
3413       alu_assemble(i,i_regs);break;
3414     case IMM16:
3415       imm16_assemble(i,i_regs);break;
3416     case SHIFT:
3417       shift_assemble(i,i_regs);break;
3418     case SHIFTIMM:
3419       shiftimm_assemble(i,i_regs);break;
3420     case LOAD:
3421       load_assemble(i,i_regs);break;
3422     case LOADLR:
3423       loadlr_assemble(i,i_regs);break;
3424     case STORE:
3425       store_assemble(i,i_regs);break;
3426     case STORELR:
3427       storelr_assemble(i,i_regs);break;
3428     case COP0:
3429       cop0_assemble(i,i_regs);break;
3430     case COP1:
3431       cop1_assemble(i,i_regs);break;
3432     case C1LS:
3433       c1ls_assemble(i,i_regs);break;
3434     case COP2:
3435       cop2_assemble(i,i_regs);break;
3436     case C2LS:
3437       c2ls_assemble(i,i_regs);break;
3438     case C2OP:
3439       c2op_assemble(i,i_regs);break;
3440     case FCONV:
3441       fconv_assemble(i,i_regs);break;
3442     case FLOAT:
3443       float_assemble(i,i_regs);break;
3444     case FCOMP:
3445       fcomp_assemble(i,i_regs);break;
3446     case MULTDIV:
3447       multdiv_assemble(i,i_regs);break;
3448     case MOV:
3449       mov_assemble(i,i_regs);break;
3450     case SYSCALL:
3451     case HLECALL:
3452     case INTCALL:
3453     case SPAN:
3454     case UJUMP:
3455     case RJUMP:
3456     case CJUMP:
3457     case SJUMP:
3458     case FJUMP:
3459       SysPrintf("Jump in the delay slot.  This is probably a bug.\n");
3460   }
3461   is_delayslot=0;
3462 }
3463
3464 // Is the branch target a valid internal jump?
3465 int internal_branch(uint64_t i_is32,int addr)
3466 {
3467   if(addr&1) return 0; // Indirect (register) jump
3468   if(addr>=start && addr<start+slen*4-4)
3469   {
3470     //int t=(addr-start)>>2;
3471     // Delay slots are not valid branch targets
3472     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3473     // 64 -> 32 bit transition requires a recompile
3474     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3475     {
3476       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3477       else printf("optimizable: yes\n");
3478     }*/
3479     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3480     return 1;
3481   }
3482   return 0;
3483 }
3484
3485 #ifndef wb_invalidate
3486 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3487   uint64_t u,uint64_t uu)
3488 {
3489   int hr;
3490   for(hr=0;hr<HOST_REGS;hr++) {
3491     if(hr!=EXCLUDE_REG) {
3492       if(pre[hr]!=entry[hr]) {
3493         if(pre[hr]>=0) {
3494           if((dirty>>hr)&1) {
3495             if(get_reg(entry,pre[hr])<0) {
3496               if(pre[hr]<64) {
3497                 if(!((u>>pre[hr])&1)) {
3498                   emit_storereg(pre[hr],hr);
3499                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3500                     emit_sarimm(hr,31,hr);
3501                     emit_storereg(pre[hr]|64,hr);
3502                   }
3503                 }
3504               }else{
3505                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3506                   emit_storereg(pre[hr],hr);
3507                 }
3508               }
3509             }
3510           }
3511         }
3512       }
3513     }
3514   }
3515   // Move from one register to another (no writeback)
3516   for(hr=0;hr<HOST_REGS;hr++) {
3517     if(hr!=EXCLUDE_REG) {
3518       if(pre[hr]!=entry[hr]) {
3519         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3520           int nr;
3521           if((nr=get_reg(entry,pre[hr]))>=0) {
3522             emit_mov(hr,nr);
3523           }
3524         }
3525       }
3526     }
3527   }
3528 }
3529 #endif
3530
3531 // Load the specified registers
3532 // This only loads the registers given as arguments because
3533 // we don't want to load things that will be overwritten
3534 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3535 {
3536   int hr;
3537   // Load 32-bit regs
3538   for(hr=0;hr<HOST_REGS;hr++) {
3539     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3540       if(entry[hr]!=regmap[hr]) {
3541         if(regmap[hr]==rs1||regmap[hr]==rs2)
3542         {
3543           if(regmap[hr]==0) {
3544             emit_zeroreg(hr);
3545           }
3546           else
3547           {
3548             emit_loadreg(regmap[hr],hr);
3549           }
3550         }
3551       }
3552     }
3553   }
3554   //Load 64-bit regs
3555   for(hr=0;hr<HOST_REGS;hr++) {
3556     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3557       if(entry[hr]!=regmap[hr]) {
3558         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3559         {
3560           assert(regmap[hr]!=64);
3561           if((is32>>(regmap[hr]&63))&1) {
3562             int lr=get_reg(regmap,regmap[hr]-64);
3563             if(lr>=0)
3564               emit_sarimm(lr,31,hr);
3565             else
3566               emit_loadreg(regmap[hr],hr);
3567           }
3568           else
3569           {
3570             emit_loadreg(regmap[hr],hr);
3571           }
3572         }
3573       }
3574     }
3575   }
3576 }
3577
3578 // Load registers prior to the start of a loop
3579 // so that they are not loaded within the loop
3580 static void loop_preload(signed char pre[],signed char entry[])
3581 {
3582   int hr;
3583   for(hr=0;hr<HOST_REGS;hr++) {
3584     if(hr!=EXCLUDE_REG) {
3585       if(pre[hr]!=entry[hr]) {
3586         if(entry[hr]>=0) {
3587           if(get_reg(pre,entry[hr])<0) {
3588             assem_debug("loop preload:\n");
3589             //printf("loop preload: %d\n",hr);
3590             if(entry[hr]==0) {
3591               emit_zeroreg(hr);
3592             }
3593             else if(entry[hr]<TEMPREG)
3594             {
3595               emit_loadreg(entry[hr],hr);
3596             }
3597             else if(entry[hr]-64<TEMPREG)
3598             {
3599               emit_loadreg(entry[hr],hr);
3600             }
3601           }
3602         }
3603       }
3604     }
3605   }
3606 }
3607
3608 // Generate address for load/store instruction
3609 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
3610 void address_generation(int i,struct regstat *i_regs,signed char entry[])
3611 {
3612   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
3613     int ra=-1;
3614     int agr=AGEN1+(i&1);
3615     if(itype[i]==LOAD) {
3616       ra=get_reg(i_regs->regmap,rt1[i]);
3617       if(ra<0) ra=get_reg(i_regs->regmap,-1);
3618       assert(ra>=0);
3619     }
3620     if(itype[i]==LOADLR) {
3621       ra=get_reg(i_regs->regmap,FTEMP);
3622     }
3623     if(itype[i]==STORE||itype[i]==STORELR) {
3624       ra=get_reg(i_regs->regmap,agr);
3625       if(ra<0) ra=get_reg(i_regs->regmap,-1);
3626     }
3627     if(itype[i]==C1LS||itype[i]==C2LS) {
3628       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
3629         ra=get_reg(i_regs->regmap,FTEMP);
3630       else { // SWC1/SDC1/SWC2/SDC2
3631         ra=get_reg(i_regs->regmap,agr);
3632         if(ra<0) ra=get_reg(i_regs->regmap,-1);
3633       }
3634     }
3635     int rs=get_reg(i_regs->regmap,rs1[i]);
3636     if(ra>=0) {
3637       int offset=imm[i];
3638       int c=(i_regs->wasconst>>rs)&1;
3639       if(rs1[i]==0) {
3640         // Using r0 as a base address
3641         if(!entry||entry[ra]!=agr) {
3642           if (opcode[i]==0x22||opcode[i]==0x26) {
3643             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3644           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3645             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3646           }else{
3647             emit_movimm(offset,ra);
3648           }
3649         } // else did it in the previous cycle
3650       }
3651       else if(rs<0) {
3652         if(!entry||entry[ra]!=rs1[i])
3653           emit_loadreg(rs1[i],ra);
3654         //if(!entry||entry[ra]!=rs1[i])
3655         //  printf("poor load scheduling!\n");
3656       }
3657       else if(c) {
3658         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
3659           if(!entry||entry[ra]!=agr) {
3660             if (opcode[i]==0x22||opcode[i]==0x26) {
3661               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3662             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3663               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3664             }else{
3665               #ifdef HOST_IMM_ADDR32
3666               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32)) // LWC1/LDC1/LWC2/LDC2
3667               #endif
3668               emit_movimm(constmap[i][rs]+offset,ra);
3669               regs[i].loadedconst|=1<<ra;
3670             }
3671           } // else did it in the previous cycle
3672         } // else load_consts already did it
3673       }
3674       if(offset&&!c&&rs1[i]) {
3675         if(rs>=0) {
3676           emit_addimm(rs,offset,ra);
3677         }else{
3678           emit_addimm(ra,offset,ra);
3679         }
3680       }
3681     }
3682   }
3683   // Preload constants for next instruction
3684   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
3685     int agr,ra;
3686     // Actual address
3687     agr=AGEN1+((i+1)&1);
3688     ra=get_reg(i_regs->regmap,agr);
3689     if(ra>=0) {
3690       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
3691       int offset=imm[i+1];
3692       int c=(regs[i+1].wasconst>>rs)&1;
3693       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
3694         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3695           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3696         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3697           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3698         }else{
3699           #ifdef HOST_IMM_ADDR32
3700           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32)) // LWC1/LDC1/LWC2/LDC2
3701           #endif
3702           emit_movimm(constmap[i+1][rs]+offset,ra);
3703           regs[i+1].loadedconst|=1<<ra;
3704         }
3705       }
3706       else if(rs1[i+1]==0) {
3707         // Using r0 as a base address
3708         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3709           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3710         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3711           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3712         }else{
3713           emit_movimm(offset,ra);
3714         }
3715       }
3716     }
3717   }
3718 }
3719
3720 static int get_final_value(int hr, int i, int *value)
3721 {
3722   int reg=regs[i].regmap[hr];
3723   while(i<slen-1) {
3724     if(regs[i+1].regmap[hr]!=reg) break;
3725     if(!((regs[i+1].isconst>>hr)&1)) break;
3726     if(bt[i+1]) break;
3727     i++;
3728   }
3729   if(i<slen-1) {
3730     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
3731       *value=constmap[i][hr];
3732       return 1;
3733     }
3734     if(!bt[i+1]) {
3735       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
3736         // Load in delay slot, out-of-order execution
3737         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
3738         {
3739           // Precompute load address
3740           *value=constmap[i][hr]+imm[i+2];
3741           return 1;
3742         }
3743       }
3744       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
3745       {
3746         // Precompute load address
3747         *value=constmap[i][hr]+imm[i+1];
3748         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
3749         return 1;
3750       }
3751     }
3752   }
3753   *value=constmap[i][hr];
3754   //printf("c=%x\n",(int)constmap[i][hr]);
3755   if(i==slen-1) return 1;
3756   if(reg<64) {
3757     return !((unneeded_reg[i+1]>>reg)&1);
3758   }else{
3759     return !((unneeded_reg_upper[i+1]>>reg)&1);
3760   }
3761 }
3762
3763 // Load registers with known constants
3764 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
3765 {
3766   int hr,hr2;
3767   // propagate loaded constant flags
3768   if(i==0||bt[i])
3769     regs[i].loadedconst=0;
3770   else {
3771     for(hr=0;hr<HOST_REGS;hr++) {
3772       if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
3773          &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
3774       {
3775         regs[i].loadedconst|=1<<hr;
3776       }
3777     }
3778   }
3779   // Load 32-bit regs
3780   for(hr=0;hr<HOST_REGS;hr++) {
3781     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3782       //if(entry[hr]!=regmap[hr]) {
3783       if(!((regs[i].loadedconst>>hr)&1)) {
3784         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
3785           int value,similar=0;
3786           if(get_final_value(hr,i,&value)) {
3787             // see if some other register has similar value
3788             for(hr2=0;hr2<HOST_REGS;hr2++) {
3789               if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
3790                 if(is_similar_value(value,constmap[i][hr2])) {
3791                   similar=1;
3792                   break;
3793                 }
3794               }
3795             }
3796             if(similar) {
3797               int value2;
3798               if(get_final_value(hr2,i,&value2)) // is this needed?
3799                 emit_movimm_from(value2,hr2,value,hr);
3800               else
3801                 emit_movimm(value,hr);
3802             }
3803             else if(value==0) {
3804               emit_zeroreg(hr);
3805             }
3806             else {
3807               emit_movimm(value,hr);
3808             }
3809           }
3810           regs[i].loadedconst|=1<<hr;
3811         }
3812       }
3813     }
3814   }
3815   // Load 64-bit regs
3816   for(hr=0;hr<HOST_REGS;hr++) {
3817     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3818       //if(entry[hr]!=regmap[hr]) {
3819       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
3820         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
3821           if((is32>>(regmap[hr]&63))&1) {
3822             int lr=get_reg(regmap,regmap[hr]-64);
3823             assert(lr>=0);
3824             emit_sarimm(lr,31,hr);
3825           }
3826           else
3827           {
3828             int value;
3829             if(get_final_value(hr,i,&value)) {
3830               if(value==0) {
3831                 emit_zeroreg(hr);
3832               }
3833               else {
3834                 emit_movimm(value,hr);
3835               }
3836             }
3837           }
3838         }
3839       }
3840     }
3841   }
3842 }
3843 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
3844 {
3845   int hr;
3846   // Load 32-bit regs
3847   for(hr=0;hr<HOST_REGS;hr++) {
3848     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
3849       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
3850         int value=constmap[i][hr];
3851         if(value==0) {
3852           emit_zeroreg(hr);
3853         }
3854         else {
3855           emit_movimm(value,hr);
3856         }
3857       }
3858     }
3859   }
3860   // Load 64-bit regs
3861   for(hr=0;hr<HOST_REGS;hr++) {
3862     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
3863       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
3864         if((is32>>(regmap[hr]&63))&1) {
3865           int lr=get_reg(regmap,regmap[hr]-64);
3866           assert(lr>=0);
3867           emit_sarimm(lr,31,hr);
3868         }
3869         else
3870         {
3871           int value=constmap[i][hr];
3872           if(value==0) {
3873             emit_zeroreg(hr);
3874           }
3875           else {
3876             emit_movimm(value,hr);
3877           }
3878         }
3879       }
3880     }
3881   }
3882 }
3883
3884 // Write out all dirty registers (except cycle count)
3885 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
3886 {
3887   int hr;
3888   for(hr=0;hr<HOST_REGS;hr++) {
3889     if(hr!=EXCLUDE_REG) {
3890       if(i_regmap[hr]>0) {
3891         if(i_regmap[hr]!=CCREG) {
3892           if((i_dirty>>hr)&1) {
3893             if(i_regmap[hr]<64) {
3894               emit_storereg(i_regmap[hr],hr);
3895             }else{
3896               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
3897                 emit_storereg(i_regmap[hr],hr);
3898               }
3899             }
3900           }
3901         }
3902       }
3903     }
3904   }
3905 }
3906 // Write out dirty registers that we need to reload (pair with load_needed_regs)
3907 // This writes the registers not written by store_regs_bt
3908 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
3909 {
3910   int hr;
3911   int t=(addr-start)>>2;
3912   for(hr=0;hr<HOST_REGS;hr++) {
3913     if(hr!=EXCLUDE_REG) {
3914       if(i_regmap[hr]>0) {
3915         if(i_regmap[hr]!=CCREG) {
3916           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
3917             if((i_dirty>>hr)&1) {
3918               if(i_regmap[hr]<64) {
3919                 emit_storereg(i_regmap[hr],hr);
3920               }else{
3921                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
3922                   emit_storereg(i_regmap[hr],hr);
3923                 }
3924               }
3925             }
3926           }
3927         }
3928       }
3929     }
3930   }
3931 }
3932
3933 // Load all registers (except cycle count)
3934 void load_all_regs(signed char i_regmap[])
3935 {
3936   int hr;
3937   for(hr=0;hr<HOST_REGS;hr++) {
3938     if(hr!=EXCLUDE_REG) {
3939       if(i_regmap[hr]==0) {
3940         emit_zeroreg(hr);
3941       }
3942       else
3943       if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
3944       {
3945         emit_loadreg(i_regmap[hr],hr);
3946       }
3947     }
3948   }
3949 }
3950
3951 // Load all current registers also needed by next instruction
3952 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
3953 {
3954   int hr;
3955   for(hr=0;hr<HOST_REGS;hr++) {
3956     if(hr!=EXCLUDE_REG) {
3957       if(get_reg(next_regmap,i_regmap[hr])>=0) {
3958         if(i_regmap[hr]==0) {
3959           emit_zeroreg(hr);
3960         }
3961         else
3962         if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
3963         {
3964           emit_loadreg(i_regmap[hr],hr);
3965         }
3966       }
3967     }
3968   }
3969 }
3970
3971 // Load all regs, storing cycle count if necessary
3972 void load_regs_entry(int t)
3973 {
3974   int hr;
3975   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
3976   else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
3977   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
3978     emit_storereg(CCREG,HOST_CCREG);
3979   }
3980   // Load 32-bit regs
3981   for(hr=0;hr<HOST_REGS;hr++) {
3982     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
3983       if(regs[t].regmap_entry[hr]==0) {
3984         emit_zeroreg(hr);
3985       }
3986       else if(regs[t].regmap_entry[hr]!=CCREG)
3987       {
3988         emit_loadreg(regs[t].regmap_entry[hr],hr);
3989       }
3990     }
3991   }
3992   // Load 64-bit regs
3993   for(hr=0;hr<HOST_REGS;hr++) {
3994     if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
3995       assert(regs[t].regmap_entry[hr]!=64);
3996       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
3997         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
3998         if(lr<0) {
3999           emit_loadreg(regs[t].regmap_entry[hr],hr);
4000         }
4001         else
4002         {
4003           emit_sarimm(lr,31,hr);
4004         }
4005       }
4006       else
4007       {
4008         emit_loadreg(regs[t].regmap_entry[hr],hr);
4009       }
4010     }
4011   }
4012 }
4013
4014 // Store dirty registers prior to branch
4015 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4016 {
4017   if(internal_branch(i_is32,addr))
4018   {
4019     int t=(addr-start)>>2;
4020     int hr;
4021     for(hr=0;hr<HOST_REGS;hr++) {
4022       if(hr!=EXCLUDE_REG) {
4023         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4024           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4025             if((i_dirty>>hr)&1) {
4026               if(i_regmap[hr]<64) {
4027                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4028                   emit_storereg(i_regmap[hr],hr);
4029                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4030                     #ifdef DESTRUCTIVE_WRITEBACK
4031                     emit_sarimm(hr,31,hr);
4032                     emit_storereg(i_regmap[hr]|64,hr);
4033                     #else
4034                     emit_sarimm(hr,31,HOST_TEMPREG);
4035                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4036                     #endif
4037                   }
4038                 }
4039               }else{
4040                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4041                   emit_storereg(i_regmap[hr],hr);
4042                 }
4043               }
4044             }
4045           }
4046         }
4047       }
4048     }
4049   }
4050   else
4051   {
4052     // Branch out of this block, write out all dirty regs
4053     wb_dirtys(i_regmap,i_is32,i_dirty);
4054   }
4055 }
4056
4057 // Load all needed registers for branch target
4058 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4059 {
4060   //if(addr>=start && addr<(start+slen*4))
4061   if(internal_branch(i_is32,addr))
4062   {
4063     int t=(addr-start)>>2;
4064     int hr;
4065     // Store the cycle count before loading something else
4066     if(i_regmap[HOST_CCREG]!=CCREG) {
4067       assert(i_regmap[HOST_CCREG]==-1);
4068     }
4069     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4070       emit_storereg(CCREG,HOST_CCREG);
4071     }
4072     // Load 32-bit regs
4073     for(hr=0;hr<HOST_REGS;hr++) {
4074       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4075         #ifdef DESTRUCTIVE_WRITEBACK
4076         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4077         #else
4078         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4079         #endif
4080           if(regs[t].regmap_entry[hr]==0) {
4081             emit_zeroreg(hr);
4082           }
4083           else if(regs[t].regmap_entry[hr]!=CCREG)
4084           {
4085             emit_loadreg(regs[t].regmap_entry[hr],hr);
4086           }
4087         }
4088       }
4089     }
4090     //Load 64-bit regs
4091     for(hr=0;hr<HOST_REGS;hr++) {
4092       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4093         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4094           assert(regs[t].regmap_entry[hr]!=64);
4095           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4096             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4097             if(lr<0) {
4098               emit_loadreg(regs[t].regmap_entry[hr],hr);
4099             }
4100             else
4101             {
4102               emit_sarimm(lr,31,hr);
4103             }
4104           }
4105           else
4106           {
4107             emit_loadreg(regs[t].regmap_entry[hr],hr);
4108           }
4109         }
4110         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4111           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4112           assert(lr>=0);
4113           emit_sarimm(lr,31,hr);
4114         }
4115       }
4116     }
4117   }
4118 }
4119
4120 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4121 {
4122   if(addr>=start && addr<start+slen*4-4)
4123   {
4124     int t=(addr-start)>>2;
4125     int hr;
4126     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4127     for(hr=0;hr<HOST_REGS;hr++)
4128     {
4129       if(hr!=EXCLUDE_REG)
4130       {
4131         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4132         {
4133           if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4134           {
4135             return 0;
4136           }
4137           else
4138           if((i_dirty>>hr)&1)
4139           {
4140             if(i_regmap[hr]<TEMPREG)
4141             {
4142               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4143                 return 0;
4144             }
4145             else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4146             {
4147               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4148                 return 0;
4149             }
4150           }
4151         }
4152         else // Same register but is it 32-bit or dirty?
4153         if(i_regmap[hr]>=0)
4154         {
4155           if(!((regs[t].dirty>>hr)&1))
4156           {
4157             if((i_dirty>>hr)&1)
4158             {
4159               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4160               {
4161                 //printf("%x: dirty no match\n",addr);
4162                 return 0;
4163               }
4164             }
4165           }
4166           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4167           {
4168             //printf("%x: is32 no match\n",addr);
4169             return 0;
4170           }
4171         }
4172       }
4173     }
4174     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4175     // Delay slots are not valid branch targets
4176     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4177     // Delay slots require additional processing, so do not match
4178     if(is_ds[t]) return 0;
4179   }
4180   else
4181   {
4182     int hr;
4183     for(hr=0;hr<HOST_REGS;hr++)
4184     {
4185       if(hr!=EXCLUDE_REG)
4186       {
4187         if(i_regmap[hr]>=0)
4188         {
4189           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4190           {
4191             if((i_dirty>>hr)&1)
4192             {
4193               return 0;
4194             }
4195           }
4196         }
4197       }
4198     }
4199   }
4200   return 1;
4201 }
4202
4203 // Used when a branch jumps into the delay slot of another branch
4204 void ds_assemble_entry(int i)
4205 {
4206   int t=(ba[i]-start)>>2;
4207   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4208   assem_debug("Assemble delay slot at %x\n",ba[i]);
4209   assem_debug("<->\n");
4210   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4211     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4212   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4213   address_generation(t,&regs[t],regs[t].regmap_entry);
4214   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4215     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4216   cop1_usable=0;
4217   is_delayslot=0;
4218   switch(itype[t]) {
4219     case ALU:
4220       alu_assemble(t,&regs[t]);break;
4221     case IMM16:
4222       imm16_assemble(t,&regs[t]);break;
4223     case SHIFT:
4224       shift_assemble(t,&regs[t]);break;
4225     case SHIFTIMM:
4226       shiftimm_assemble(t,&regs[t]);break;
4227     case LOAD:
4228       load_assemble(t,&regs[t]);break;
4229     case LOADLR:
4230       loadlr_assemble(t,&regs[t]);break;
4231     case STORE:
4232       store_assemble(t,&regs[t]);break;
4233     case STORELR:
4234       storelr_assemble(t,&regs[t]);break;
4235     case COP0:
4236       cop0_assemble(t,&regs[t]);break;
4237     case COP1:
4238       cop1_assemble(t,&regs[t]);break;
4239     case C1LS:
4240       c1ls_assemble(t,&regs[t]);break;
4241     case COP2:
4242       cop2_assemble(t,&regs[t]);break;
4243     case C2LS:
4244       c2ls_assemble(t,&regs[t]);break;
4245     case C2OP:
4246       c2op_assemble(t,&regs[t]);break;
4247     case FCONV:
4248       fconv_assemble(t,&regs[t]);break;
4249     case FLOAT:
4250       float_assemble(t,&regs[t]);break;
4251     case FCOMP:
4252       fcomp_assemble(t,&regs[t]);break;
4253     case MULTDIV:
4254       multdiv_assemble(t,&regs[t]);break;
4255     case MOV:
4256       mov_assemble(t,&regs[t]);break;
4257     case SYSCALL:
4258     case HLECALL:
4259     case INTCALL:
4260     case SPAN:
4261     case UJUMP:
4262     case RJUMP:
4263     case CJUMP:
4264     case SJUMP:
4265     case FJUMP:
4266       SysPrintf("Jump in the delay slot.  This is probably a bug.\n");
4267   }
4268   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4269   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4270   if(internal_branch(regs[t].is32,ba[i]+4))
4271     assem_debug("branch: internal\n");
4272   else
4273     assem_debug("branch: external\n");
4274   assert(internal_branch(regs[t].is32,ba[i]+4));
4275   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4276   emit_jmp(0);
4277 }
4278
4279 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4280 {
4281   int count;
4282   int jaddr;
4283   int idle=0;
4284   int t=0;
4285   if(itype[i]==RJUMP)
4286   {
4287     *adj=0;
4288   }
4289   //if(ba[i]>=start && ba[i]<(start+slen*4))
4290   if(internal_branch(branch_regs[i].is32,ba[i]))
4291   {
4292     t=(ba[i]-start)>>2;
4293     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4294     else *adj=ccadj[t];
4295   }
4296   else
4297   {
4298     *adj=0;
4299   }
4300   count=ccadj[i];
4301   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4302     // Idle loop
4303     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4304     idle=(int)out;
4305     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4306     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4307     jaddr=(int)out;
4308     emit_jmp(0);
4309   }
4310   else if(*adj==0||invert) {
4311     int cycles=CLOCK_ADJUST(count+2);
4312     // faster loop HACK
4313     if (t&&*adj) {
4314       int rel=t-i;
4315       if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
4316         cycles=CLOCK_ADJUST(*adj)+count+2-*adj;
4317     }
4318     emit_addimm_and_set_flags(cycles,HOST_CCREG);
4319     jaddr=(int)out;
4320     emit_jns(0);
4321   }
4322   else
4323   {
4324     emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
4325     jaddr=(int)out;
4326     emit_jns(0);
4327   }
4328   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4329 }
4330
4331 void do_ccstub(int n)
4332 {
4333   literal_pool(256);
4334   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4335   set_jump_target(stubs[n][1],(int)out);
4336   int i=stubs[n][4];
4337   if(stubs[n][6]==NULLDS) {
4338     // Delay slot instruction is nullified ("likely" branch)
4339     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4340   }
4341   else if(stubs[n][6]!=TAKEN) {
4342     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4343   }
4344   else {
4345     if(internal_branch(branch_regs[i].is32,ba[i]))
4346       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4347   }
4348   if(stubs[n][5]!=-1)
4349   {
4350     // Save PC as return address
4351     emit_movimm(stubs[n][5],EAX);
4352     emit_writeword(EAX,(int)&pcaddr);
4353   }
4354   else
4355   {
4356     // Return address depends on which way the branch goes
4357     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4358     {
4359       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4360       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4361       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4362       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4363       if(rs1[i]==0)
4364       {
4365         s1l=s2l;s1h=s2h;
4366         s2l=s2h=-1;
4367       }
4368       else if(rs2[i]==0)
4369       {
4370         s2l=s2h=-1;
4371       }
4372       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4373         s1h=s2h=-1;
4374       }
4375       assert(s1l>=0);
4376       #ifdef DESTRUCTIVE_WRITEBACK
4377       if(rs1[i]) {
4378         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4379           emit_loadreg(rs1[i],s1l);
4380       }
4381       else {
4382         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4383           emit_loadreg(rs2[i],s1l);
4384       }
4385       if(s2l>=0)
4386         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4387           emit_loadreg(rs2[i],s2l);
4388       #endif
4389       int hr=0;
4390       int addr=-1,alt=-1,ntaddr=-1;
4391       while(hr<HOST_REGS)
4392       {
4393         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4394            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4395            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4396         {
4397           addr=hr++;break;
4398         }
4399         hr++;
4400       }
4401       while(hr<HOST_REGS)
4402       {
4403         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4404            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4405            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4406         {
4407           alt=hr++;break;
4408         }
4409         hr++;
4410       }
4411       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4412       {
4413         while(hr<HOST_REGS)
4414         {
4415           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4416              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4417              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4418           {
4419             ntaddr=hr;break;
4420           }
4421           hr++;
4422         }
4423         assert(hr<HOST_REGS);
4424       }
4425       if((opcode[i]&0x2f)==4) // BEQ
4426       {
4427         #ifdef HAVE_CMOV_IMM
4428         if(s1h<0) {
4429           if(s2l>=0) emit_cmp(s1l,s2l);
4430           else emit_test(s1l,s1l);
4431           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4432         }
4433         else
4434         #endif
4435         {
4436           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4437           if(s1h>=0) {
4438             if(s2h>=0) emit_cmp(s1h,s2h);
4439             else emit_test(s1h,s1h);
4440             emit_cmovne_reg(alt,addr);
4441           }
4442           if(s2l>=0) emit_cmp(s1l,s2l);
4443           else emit_test(s1l,s1l);
4444           emit_cmovne_reg(alt,addr);
4445         }
4446       }
4447       if((opcode[i]&0x2f)==5) // BNE
4448       {
4449         #ifdef HAVE_CMOV_IMM
4450         if(s1h<0) {
4451           if(s2l>=0) emit_cmp(s1l,s2l);
4452           else emit_test(s1l,s1l);
4453           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4454         }
4455         else
4456         #endif
4457         {
4458           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4459           if(s1h>=0) {
4460             if(s2h>=0) emit_cmp(s1h,s2h);
4461             else emit_test(s1h,s1h);
4462             emit_cmovne_reg(alt,addr);
4463           }
4464           if(s2l>=0) emit_cmp(s1l,s2l);
4465           else emit_test(s1l,s1l);
4466           emit_cmovne_reg(alt,addr);
4467         }
4468       }
4469       if((opcode[i]&0x2f)==6) // BLEZ
4470       {
4471         //emit_movimm(ba[i],alt);
4472         //emit_movimm(start+i*4+8,addr);
4473         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4474         emit_cmpimm(s1l,1);
4475         if(s1h>=0) emit_mov(addr,ntaddr);
4476         emit_cmovl_reg(alt,addr);
4477         if(s1h>=0) {
4478           emit_test(s1h,s1h);
4479           emit_cmovne_reg(ntaddr,addr);
4480           emit_cmovs_reg(alt,addr);
4481         }
4482       }
4483       if((opcode[i]&0x2f)==7) // BGTZ
4484       {
4485         //emit_movimm(ba[i],addr);
4486         //emit_movimm(start+i*4+8,ntaddr);
4487         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4488         emit_cmpimm(s1l,1);
4489         if(s1h>=0) emit_mov(addr,alt);
4490         emit_cmovl_reg(ntaddr,addr);
4491         if(s1h>=0) {
4492           emit_test(s1h,s1h);
4493           emit_cmovne_reg(alt,addr);
4494           emit_cmovs_reg(ntaddr,addr);
4495         }
4496       }
4497       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4498       {
4499         //emit_movimm(ba[i],alt);
4500         //emit_movimm(start+i*4+8,addr);
4501         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4502         if(s1h>=0) emit_test(s1h,s1h);
4503         else emit_test(s1l,s1l);
4504         emit_cmovs_reg(alt,addr);
4505       }
4506       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4507       {
4508         //emit_movimm(ba[i],addr);
4509         //emit_movimm(start+i*4+8,alt);
4510         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4511         if(s1h>=0) emit_test(s1h,s1h);
4512         else emit_test(s1l,s1l);
4513         emit_cmovs_reg(alt,addr);
4514       }
4515       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4516         if(source[i]&0x10000) // BC1T
4517         {
4518           //emit_movimm(ba[i],alt);
4519           //emit_movimm(start+i*4+8,addr);
4520           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4521           emit_testimm(s1l,0x800000);
4522           emit_cmovne_reg(alt,addr);
4523         }
4524         else // BC1F
4525         {
4526           //emit_movimm(ba[i],addr);
4527           //emit_movimm(start+i*4+8,alt);
4528           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4529           emit_testimm(s1l,0x800000);
4530           emit_cmovne_reg(alt,addr);
4531         }
4532       }
4533       emit_writeword(addr,(int)&pcaddr);
4534     }
4535     else
4536     if(itype[i]==RJUMP)
4537     {
4538       int r=get_reg(branch_regs[i].regmap,rs1[i]);
4539       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4540         r=get_reg(branch_regs[i].regmap,RTEMP);
4541       }
4542       emit_writeword(r,(int)&pcaddr);
4543     }
4544     else {SysPrintf("Unknown branch type in do_ccstub\n");exit(1);}
4545   }
4546   // Update cycle count
4547   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4548   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
4549   emit_call((int)cc_interrupt);
4550   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
4551   if(stubs[n][6]==TAKEN) {
4552     if(internal_branch(branch_regs[i].is32,ba[i]))
4553       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4554     else if(itype[i]==RJUMP) {
4555       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4556         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4557       else
4558         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4559     }
4560   }else if(stubs[n][6]==NOTTAKEN) {
4561     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4562     else load_all_regs(branch_regs[i].regmap);
4563   }else if(stubs[n][6]==NULLDS) {
4564     // Delay slot instruction is nullified ("likely" branch)
4565     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4566     else load_all_regs(regs[i].regmap);
4567   }else{
4568     load_all_regs(branch_regs[i].regmap);
4569   }
4570   emit_jmp(stubs[n][2]); // return address
4571
4572   /* This works but uses a lot of memory...
4573   emit_readword((int)&last_count,ECX);
4574   emit_add(HOST_CCREG,ECX,EAX);
4575   emit_writeword(EAX,(int)&Count);
4576   emit_call((int)gen_interupt);
4577   emit_readword((int)&Count,HOST_CCREG);
4578   emit_readword((int)&next_interupt,EAX);
4579   emit_readword((int)&pending_exception,EBX);
4580   emit_writeword(EAX,(int)&last_count);
4581   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
4582   emit_test(EBX,EBX);
4583   int jne_instr=(int)out;
4584   emit_jne(0);
4585   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
4586   load_all_regs(branch_regs[i].regmap);
4587   emit_jmp(stubs[n][2]); // return address
4588   set_jump_target(jne_instr,(int)out);
4589   emit_readword((int)&pcaddr,EAX);
4590   // Call get_addr_ht instead of doing the hash table here.
4591   // This code is executed infrequently and takes up a lot of space
4592   // so smaller is better.
4593   emit_storereg(CCREG,HOST_CCREG);
4594   emit_pushreg(EAX);
4595   emit_call((int)get_addr_ht);
4596   emit_loadreg(CCREG,HOST_CCREG);
4597   emit_addimm(ESP,4,ESP);
4598   emit_jmpreg(EAX);*/
4599 }
4600
4601 static void add_to_linker(int addr,int target,int ext)
4602 {
4603   link_addr[linkcount][0]=addr;
4604   link_addr[linkcount][1]=target;
4605   link_addr[linkcount][2]=ext;
4606   linkcount++;
4607 }
4608
4609 static void ujump_assemble_write_ra(int i)
4610 {
4611   int rt;
4612   unsigned int return_address;
4613   rt=get_reg(branch_regs[i].regmap,31);
4614   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4615   //assert(rt>=0);
4616   return_address=start+i*4+8;
4617   if(rt>=0) {
4618     #ifdef USE_MINI_HT
4619     if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
4620       int temp=-1; // note: must be ds-safe
4621       #ifdef HOST_TEMPREG
4622       temp=HOST_TEMPREG;
4623       #endif
4624       if(temp>=0) do_miniht_insert(return_address,rt,temp);
4625       else emit_movimm(return_address,rt);
4626     }
4627     else
4628     #endif
4629     {
4630       #ifdef REG_PREFETCH
4631       if(temp>=0)
4632       {
4633         if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4634       }
4635       #endif
4636       emit_movimm(return_address,rt); // PC into link register
4637       #ifdef IMM_PREFETCH
4638       emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
4639       #endif
4640     }
4641   }
4642 }
4643
4644 void ujump_assemble(int i,struct regstat *i_regs)
4645 {
4646   int ra_done=0;
4647   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
4648   address_generation(i+1,i_regs,regs[i].regmap_entry);
4649   #ifdef REG_PREFETCH
4650   int temp=get_reg(branch_regs[i].regmap,PTEMP);
4651   if(rt1[i]==31&&temp>=0)
4652   {
4653     signed char *i_regmap=i_regs->regmap;
4654     int return_address=start+i*4+8;
4655     if(get_reg(branch_regs[i].regmap,31)>0)
4656     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4657   }
4658   #endif
4659   if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
4660     ujump_assemble_write_ra(i); // writeback ra for DS
4661     ra_done=1;
4662   }
4663   ds_assemble(i+1,i_regs);
4664   uint64_t bc_unneeded=branch_regs[i].u;
4665   uint64_t bc_unneeded_upper=branch_regs[i].uu;
4666   bc_unneeded|=1|(1LL<<rt1[i]);
4667   bc_unneeded_upper|=1|(1LL<<rt1[i]);
4668   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
4669                 bc_unneeded,bc_unneeded_upper);
4670   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
4671   if(!ra_done&&rt1[i]==31)
4672     ujump_assemble_write_ra(i);
4673   int cc,adj;
4674   cc=get_reg(branch_regs[i].regmap,CCREG);
4675   assert(cc==HOST_CCREG);
4676   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4677   #ifdef REG_PREFETCH
4678   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
4679   #endif
4680   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
4681   if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
4682   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4683   if(internal_branch(branch_regs[i].is32,ba[i]))
4684     assem_debug("branch: internal\n");
4685   else
4686     assem_debug("branch: external\n");
4687   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
4688     ds_assemble_entry(i);
4689   }
4690   else {
4691     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
4692     emit_jmp(0);
4693   }
4694 }
4695
4696 static void rjump_assemble_write_ra(int i)
4697 {
4698   int rt,return_address;
4699   assert(rt1[i+1]!=rt1[i]);
4700   assert(rt2[i+1]!=rt1[i]);
4701   rt=get_reg(branch_regs[i].regmap,rt1[i]);
4702   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4703   assert(rt>=0);
4704   return_address=start+i*4+8;
4705   #ifdef REG_PREFETCH
4706   if(temp>=0)
4707   {
4708     if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4709   }
4710   #endif
4711   emit_movimm(return_address,rt); // PC into link register
4712   #ifdef IMM_PREFETCH
4713   emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
4714   #endif
4715 }
4716
4717 void rjump_assemble(int i,struct regstat *i_regs)
4718 {
4719   int temp;
4720   int rs,cc;
4721   int ra_done=0;
4722   rs=get_reg(branch_regs[i].regmap,rs1[i]);
4723   assert(rs>=0);
4724   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4725     // Delay slot abuse, make a copy of the branch address register
4726     temp=get_reg(branch_regs[i].regmap,RTEMP);
4727     assert(temp>=0);
4728     assert(regs[i].regmap[temp]==RTEMP);
4729     emit_mov(rs,temp);
4730     rs=temp;
4731   }
4732   address_generation(i+1,i_regs,regs[i].regmap_entry);
4733   #ifdef REG_PREFETCH
4734   if(rt1[i]==31)
4735   {
4736     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
4737       signed char *i_regmap=i_regs->regmap;
4738       int return_address=start+i*4+8;
4739       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4740     }
4741   }
4742   #endif
4743   #ifdef USE_MINI_HT
4744   if(rs1[i]==31) {
4745     int rh=get_reg(regs[i].regmap,RHASH);
4746     if(rh>=0) do_preload_rhash(rh);
4747   }
4748   #endif
4749   if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
4750     rjump_assemble_write_ra(i);
4751     ra_done=1;
4752   }
4753   ds_assemble(i+1,i_regs);
4754   uint64_t bc_unneeded=branch_regs[i].u;
4755   uint64_t bc_unneeded_upper=branch_regs[i].uu;
4756   bc_unneeded|=1|(1LL<<rt1[i]);
4757   bc_unneeded_upper|=1|(1LL<<rt1[i]);
4758   bc_unneeded&=~(1LL<<rs1[i]);
4759   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
4760                 bc_unneeded,bc_unneeded_upper);
4761   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
4762   if(!ra_done&&rt1[i]!=0)
4763     rjump_assemble_write_ra(i);
4764   cc=get_reg(branch_regs[i].regmap,CCREG);
4765   assert(cc==HOST_CCREG);
4766   (void)cc;
4767   #ifdef USE_MINI_HT
4768   int rh=get_reg(branch_regs[i].regmap,RHASH);
4769   int ht=get_reg(branch_regs[i].regmap,RHTBL);
4770   if(rs1[i]==31) {
4771     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
4772     do_preload_rhtbl(ht);
4773     do_rhash(rs,rh);
4774   }
4775   #endif
4776   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
4777   #ifdef DESTRUCTIVE_WRITEBACK
4778   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
4779     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
4780       emit_loadreg(rs1[i],rs);
4781     }
4782   }
4783   #endif
4784   #ifdef REG_PREFETCH
4785   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
4786   #endif
4787   #ifdef USE_MINI_HT
4788   if(rs1[i]==31) {
4789     do_miniht_load(ht,rh);
4790   }
4791   #endif
4792   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
4793   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
4794   //assert(adj==0);
4795   emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
4796   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
4797   if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
4798     // special case for RFE
4799     emit_jmp(0);
4800   else
4801     emit_jns(0);
4802   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
4803   #ifdef USE_MINI_HT
4804   if(rs1[i]==31) {
4805     do_miniht_jump(rs,rh,ht);
4806   }
4807   else
4808   #endif
4809   {
4810     //if(rs!=EAX) emit_mov(rs,EAX);
4811     //emit_jmp((int)jump_vaddr_eax);
4812     emit_jmp(jump_vaddr_reg[rs]);
4813   }
4814   /* Check hash table
4815   temp=!rs;
4816   emit_mov(rs,temp);
4817   emit_shrimm(rs,16,rs);
4818   emit_xor(temp,rs,rs);
4819   emit_movzwl_reg(rs,rs);
4820   emit_shlimm(rs,4,rs);
4821   emit_cmpmem_indexed((int)hash_table,rs,temp);
4822   emit_jne((int)out+14);
4823   emit_readword_indexed((int)hash_table+4,rs,rs);
4824   emit_jmpreg(rs);
4825   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
4826   emit_addimm_no_flags(8,rs);
4827   emit_jeq((int)out-17);
4828   // No hit on hash table, call compiler
4829   emit_pushreg(temp);
4830 //DEBUG >
4831 #ifdef DEBUG_CYCLE_COUNT
4832   emit_readword((int)&last_count,ECX);
4833   emit_add(HOST_CCREG,ECX,HOST_CCREG);
4834   emit_readword((int)&next_interupt,ECX);
4835   emit_writeword(HOST_CCREG,(int)&Count);
4836   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
4837   emit_writeword(ECX,(int)&last_count);
4838 #endif
4839 //DEBUG <
4840   emit_storereg(CCREG,HOST_CCREG);
4841   emit_call((int)get_addr);
4842   emit_loadreg(CCREG,HOST_CCREG);
4843   emit_addimm(ESP,4,ESP);
4844   emit_jmpreg(EAX);*/
4845   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4846   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
4847   #endif
4848 }
4849
4850 void cjump_assemble(int i,struct regstat *i_regs)
4851 {
4852   signed char *i_regmap=i_regs->regmap;
4853   int cc;
4854   int match;
4855   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4856   assem_debug("match=%d\n",match);
4857   int s1h,s1l,s2h,s2l;
4858   int prev_cop1_usable=cop1_usable;
4859   int unconditional=0,nop=0;
4860   int only32=0;
4861   int invert=0;
4862   int internal=internal_branch(branch_regs[i].is32,ba[i]);
4863   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
4864   if(!match) invert=1;
4865   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4866   if(i>(ba[i]-start)>>2) invert=1;
4867   #endif
4868
4869   if(ooo[i]) {
4870     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4871     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4872     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4873     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4874   }
4875   else {
4876     s1l=get_reg(i_regmap,rs1[i]);
4877     s1h=get_reg(i_regmap,rs1[i]|64);
4878     s2l=get_reg(i_regmap,rs2[i]);
4879     s2h=get_reg(i_regmap,rs2[i]|64);
4880   }
4881   if(rs1[i]==0&&rs2[i]==0)
4882   {
4883     if(opcode[i]&1) nop=1;
4884     else unconditional=1;
4885     //assert(opcode[i]!=5);
4886     //assert(opcode[i]!=7);
4887     //assert(opcode[i]!=0x15);
4888     //assert(opcode[i]!=0x17);
4889   }
4890   else if(rs1[i]==0)
4891   {
4892     s1l=s2l;s1h=s2h;
4893     s2l=s2h=-1;
4894     only32=(regs[i].was32>>rs2[i])&1;
4895   }
4896   else if(rs2[i]==0)
4897   {
4898     s2l=s2h=-1;
4899     only32=(regs[i].was32>>rs1[i])&1;
4900   }
4901   else {
4902     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
4903   }
4904
4905   if(ooo[i]) {
4906     // Out of order execution (delay slot first)
4907     //printf("OOOE\n");
4908     address_generation(i+1,i_regs,regs[i].regmap_entry);
4909     ds_assemble(i+1,i_regs);
4910     int adj;
4911     uint64_t bc_unneeded=branch_regs[i].u;
4912     uint64_t bc_unneeded_upper=branch_regs[i].uu;
4913     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
4914     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
4915     bc_unneeded|=1;
4916     bc_unneeded_upper|=1;
4917     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
4918                   bc_unneeded,bc_unneeded_upper);
4919     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
4920     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
4921     cc=get_reg(branch_regs[i].regmap,CCREG);
4922     assert(cc==HOST_CCREG);
4923     if(unconditional)
4924       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4925     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
4926     //assem_debug("cycle count (adj)\n");
4927     if(unconditional) {
4928       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
4929       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
4930         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
4931         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4932         if(internal)
4933           assem_debug("branch: internal\n");
4934         else
4935           assem_debug("branch: external\n");
4936         if(internal&&is_ds[(ba[i]-start)>>2]) {
4937           ds_assemble_entry(i);
4938         }
4939         else {
4940           add_to_linker((int)out,ba[i],internal);
4941           emit_jmp(0);
4942         }
4943         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4944         if(((u_int)out)&7) emit_addnop(0);
4945         #endif
4946       }
4947     }
4948     else if(nop) {
4949       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
4950       int jaddr=(int)out;
4951       emit_jns(0);
4952       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
4953     }
4954     else {
4955       int taken=0,nottaken=0,nottaken1=0;
4956       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
4957       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
4958       if(!only32)
4959       {
4960         assert(s1h>=0);
4961         if(opcode[i]==4) // BEQ
4962         {
4963           if(s2h>=0) emit_cmp(s1h,s2h);
4964           else emit_test(s1h,s1h);
4965           nottaken1=(int)out;
4966           emit_jne(1);
4967         }
4968         if(opcode[i]==5) // BNE
4969         {
4970           if(s2h>=0) emit_cmp(s1h,s2h);
4971           else emit_test(s1h,s1h);
4972           if(invert) taken=(int)out;
4973           else add_to_linker((int)out,ba[i],internal);
4974           emit_jne(0);
4975         }
4976         if(opcode[i]==6) // BLEZ
4977         {
4978           emit_test(s1h,s1h);
4979           if(invert) taken=(int)out;
4980           else add_to_linker((int)out,ba[i],internal);
4981           emit_js(0);
4982           nottaken1=(int)out;
4983           emit_jne(1);
4984         }
4985         if(opcode[i]==7) // BGTZ
4986         {
4987           emit_test(s1h,s1h);
4988           nottaken1=(int)out;
4989           emit_js(1);
4990           if(invert) taken=(int)out;
4991           else add_to_linker((int)out,ba[i],internal);
4992           emit_jne(0);
4993         }
4994       } // if(!only32)
4995
4996       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4997       assert(s1l>=0);
4998       if(opcode[i]==4) // BEQ
4999       {
5000         if(s2l>=0) emit_cmp(s1l,s2l);
5001         else emit_test(s1l,s1l);
5002         if(invert){
5003           nottaken=(int)out;
5004           emit_jne(1);
5005         }else{
5006           add_to_linker((int)out,ba[i],internal);
5007           emit_jeq(0);
5008         }
5009       }
5010       if(opcode[i]==5) // BNE
5011       {
5012         if(s2l>=0) emit_cmp(s1l,s2l);
5013         else emit_test(s1l,s1l);
5014         if(invert){
5015           nottaken=(int)out;
5016           emit_jeq(1);
5017         }else{
5018           add_to_linker((int)out,ba[i],internal);
5019           emit_jne(0);
5020         }
5021       }
5022       if(opcode[i]==6) // BLEZ
5023       {
5024         emit_cmpimm(s1l,1);
5025         if(invert){
5026           nottaken=(int)out;
5027           emit_jge(1);
5028         }else{
5029           add_to_linker((int)out,ba[i],internal);
5030           emit_jl(0);
5031         }
5032       }
5033       if(opcode[i]==7) // BGTZ
5034       {
5035         emit_cmpimm(s1l,1);
5036         if(invert){
5037           nottaken=(int)out;
5038           emit_jl(1);
5039         }else{
5040           add_to_linker((int)out,ba[i],internal);
5041           emit_jge(0);
5042         }
5043       }
5044       if(invert) {
5045         if(taken) set_jump_target(taken,(int)out);
5046         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5047         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5048           if(adj) {
5049             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5050             add_to_linker((int)out,ba[i],internal);
5051           }else{
5052             emit_addnop(13);
5053             add_to_linker((int)out,ba[i],internal*2);
5054           }
5055           emit_jmp(0);
5056         }else
5057         #endif
5058         {
5059           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5060           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5061           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5062           if(internal)
5063             assem_debug("branch: internal\n");
5064           else
5065             assem_debug("branch: external\n");
5066           if(internal&&is_ds[(ba[i]-start)>>2]) {
5067             ds_assemble_entry(i);
5068           }
5069           else {
5070             add_to_linker((int)out,ba[i],internal);
5071             emit_jmp(0);
5072           }
5073         }
5074         set_jump_target(nottaken,(int)out);
5075       }
5076
5077       if(nottaken1) set_jump_target(nottaken1,(int)out);
5078       if(adj) {
5079         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5080       }
5081     } // (!unconditional)
5082   } // if(ooo)
5083   else
5084   {
5085     // In-order execution (branch first)
5086     //if(likely[i]) printf("IOL\n");
5087     //else
5088     //printf("IOE\n");
5089     int taken=0,nottaken=0,nottaken1=0;
5090     if(!unconditional&&!nop) {
5091       if(!only32)
5092       {
5093         assert(s1h>=0);
5094         if((opcode[i]&0x2f)==4) // BEQ
5095         {
5096           if(s2h>=0) emit_cmp(s1h,s2h);
5097           else emit_test(s1h,s1h);
5098           nottaken1=(int)out;
5099           emit_jne(2);
5100         }
5101         if((opcode[i]&0x2f)==5) // BNE
5102         {
5103           if(s2h>=0) emit_cmp(s1h,s2h);
5104           else emit_test(s1h,s1h);
5105           taken=(int)out;
5106           emit_jne(1);
5107         }
5108         if((opcode[i]&0x2f)==6) // BLEZ
5109         {
5110           emit_test(s1h,s1h);
5111           taken=(int)out;
5112           emit_js(1);
5113           nottaken1=(int)out;
5114           emit_jne(2);
5115         }
5116         if((opcode[i]&0x2f)==7) // BGTZ
5117         {
5118           emit_test(s1h,s1h);
5119           nottaken1=(int)out;
5120           emit_js(2);
5121           taken=(int)out;
5122           emit_jne(1);
5123         }
5124       } // if(!only32)
5125
5126       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5127       assert(s1l>=0);
5128       if((opcode[i]&0x2f)==4) // BEQ
5129       {
5130         if(s2l>=0) emit_cmp(s1l,s2l);
5131         else emit_test(s1l,s1l);
5132         nottaken=(int)out;
5133         emit_jne(2);
5134       }
5135       if((opcode[i]&0x2f)==5) // BNE
5136       {
5137         if(s2l>=0) emit_cmp(s1l,s2l);
5138         else emit_test(s1l,s1l);
5139         nottaken=(int)out;
5140         emit_jeq(2);
5141       }
5142       if((opcode[i]&0x2f)==6) // BLEZ
5143       {
5144         emit_cmpimm(s1l,1);
5145         nottaken=(int)out;
5146         emit_jge(2);
5147       }
5148       if((opcode[i]&0x2f)==7) // BGTZ
5149       {
5150         emit_cmpimm(s1l,1);
5151         nottaken=(int)out;
5152         emit_jl(2);
5153       }
5154     } // if(!unconditional)
5155     int adj;
5156     uint64_t ds_unneeded=branch_regs[i].u;
5157     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5158     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5159     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5160     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5161     ds_unneeded|=1;
5162     ds_unneeded_upper|=1;
5163     // branch taken
5164     if(!nop) {
5165       if(taken) set_jump_target(taken,(int)out);
5166       assem_debug("1:\n");
5167       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5168                     ds_unneeded,ds_unneeded_upper);
5169       // load regs
5170       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5171       address_generation(i+1,&branch_regs[i],0);
5172       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5173       ds_assemble(i+1,&branch_regs[i]);
5174       cc=get_reg(branch_regs[i].regmap,CCREG);
5175       if(cc==-1) {
5176         emit_loadreg(CCREG,cc=HOST_CCREG);
5177         // CHECK: Is the following instruction (fall thru) allocated ok?
5178       }
5179       assert(cc==HOST_CCREG);
5180       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5181       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5182       assem_debug("cycle count (adj)\n");
5183       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5184       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5185       if(internal)
5186         assem_debug("branch: internal\n");
5187       else
5188         assem_debug("branch: external\n");
5189       if(internal&&is_ds[(ba[i]-start)>>2]) {
5190         ds_assemble_entry(i);
5191       }
5192       else {
5193         add_to_linker((int)out,ba[i],internal);
5194         emit_jmp(0);
5195       }
5196     }
5197     // branch not taken
5198     cop1_usable=prev_cop1_usable;
5199     if(!unconditional) {
5200       if(nottaken1) set_jump_target(nottaken1,(int)out);
5201       set_jump_target(nottaken,(int)out);
5202       assem_debug("2:\n");
5203       if(!likely[i]) {
5204         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5205                       ds_unneeded,ds_unneeded_upper);
5206         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5207         address_generation(i+1,&branch_regs[i],0);
5208         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5209         ds_assemble(i+1,&branch_regs[i]);
5210       }
5211       cc=get_reg(branch_regs[i].regmap,CCREG);
5212       if(cc==-1&&!likely[i]) {
5213         // Cycle count isn't in a register, temporarily load it then write it out
5214         emit_loadreg(CCREG,HOST_CCREG);
5215         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5216         int jaddr=(int)out;
5217         emit_jns(0);
5218         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5219         emit_storereg(CCREG,HOST_CCREG);
5220       }
5221       else{
5222         cc=get_reg(i_regmap,CCREG);
5223         assert(cc==HOST_CCREG);
5224         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5225         int jaddr=(int)out;
5226         emit_jns(0);
5227         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5228       }
5229     }
5230   }
5231 }
5232
5233 void sjump_assemble(int i,struct regstat *i_regs)
5234 {
5235   signed char *i_regmap=i_regs->regmap;
5236   int cc;
5237   int match;
5238   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5239   assem_debug("smatch=%d\n",match);
5240   int s1h,s1l;
5241   int prev_cop1_usable=cop1_usable;
5242   int unconditional=0,nevertaken=0;
5243   int only32=0;
5244   int invert=0;
5245   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5246   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5247   if(!match) invert=1;
5248   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5249   if(i>(ba[i]-start)>>2) invert=1;
5250   #endif
5251
5252   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5253   //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5254
5255   if(ooo[i]) {
5256     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5257     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5258   }
5259   else {
5260     s1l=get_reg(i_regmap,rs1[i]);
5261     s1h=get_reg(i_regmap,rs1[i]|64);
5262   }
5263   if(rs1[i]==0)
5264   {
5265     if(opcode2[i]&1) unconditional=1;
5266     else nevertaken=1;
5267     // These are never taken (r0 is never less than zero)
5268     //assert(opcode2[i]!=0);
5269     //assert(opcode2[i]!=2);
5270     //assert(opcode2[i]!=0x10);
5271     //assert(opcode2[i]!=0x12);
5272   }
5273   else {
5274     only32=(regs[i].was32>>rs1[i])&1;
5275   }
5276
5277   if(ooo[i]) {
5278     // Out of order execution (delay slot first)
5279     //printf("OOOE\n");
5280     address_generation(i+1,i_regs,regs[i].regmap_entry);
5281     ds_assemble(i+1,i_regs);
5282     int adj;
5283     uint64_t bc_unneeded=branch_regs[i].u;
5284     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5285     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5286     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5287     bc_unneeded|=1;
5288     bc_unneeded_upper|=1;
5289     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5290                   bc_unneeded,bc_unneeded_upper);
5291     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5292     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5293     if(rt1[i]==31) {
5294       int rt,return_address;
5295       rt=get_reg(branch_regs[i].regmap,31);
5296       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5297       if(rt>=0) {
5298         // Save the PC even if the branch is not taken
5299         return_address=start+i*4+8;
5300         emit_movimm(return_address,rt); // PC into link register
5301         #ifdef IMM_PREFETCH
5302         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5303         #endif
5304       }
5305     }
5306     cc=get_reg(branch_regs[i].regmap,CCREG);
5307     assert(cc==HOST_CCREG);
5308     if(unconditional)
5309       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5310     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5311     assem_debug("cycle count (adj)\n");
5312     if(unconditional) {
5313       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5314       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5315         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5316         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5317         if(internal)
5318           assem_debug("branch: internal\n");
5319         else
5320           assem_debug("branch: external\n");
5321         if(internal&&is_ds[(ba[i]-start)>>2]) {
5322           ds_assemble_entry(i);
5323         }
5324         else {
5325           add_to_linker((int)out,ba[i],internal);
5326           emit_jmp(0);
5327         }
5328         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5329         if(((u_int)out)&7) emit_addnop(0);
5330         #endif
5331       }
5332     }
5333     else if(nevertaken) {
5334       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5335       int jaddr=(int)out;
5336       emit_jns(0);
5337       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5338     }
5339     else {
5340       int nottaken=0;
5341       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5342       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5343       if(!only32)
5344       {
5345         assert(s1h>=0);
5346         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5347         {
5348           emit_test(s1h,s1h);
5349           if(invert){
5350             nottaken=(int)out;
5351             emit_jns(1);
5352           }else{
5353             add_to_linker((int)out,ba[i],internal);
5354             emit_js(0);
5355           }
5356         }
5357         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5358         {
5359           emit_test(s1h,s1h);
5360           if(invert){
5361             nottaken=(int)out;
5362             emit_js(1);
5363           }else{
5364             add_to_linker((int)out,ba[i],internal);
5365             emit_jns(0);
5366           }
5367         }
5368       } // if(!only32)
5369       else
5370       {
5371         assert(s1l>=0);
5372         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5373         {
5374           emit_test(s1l,s1l);
5375           if(invert){
5376             nottaken=(int)out;
5377             emit_jns(1);
5378           }else{
5379             add_to_linker((int)out,ba[i],internal);
5380             emit_js(0);
5381           }
5382         }
5383         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5384         {
5385           emit_test(s1l,s1l);
5386           if(invert){
5387             nottaken=(int)out;
5388             emit_js(1);
5389           }else{
5390             add_to_linker((int)out,ba[i],internal);
5391             emit_jns(0);
5392           }
5393         }
5394       } // if(!only32)
5395
5396       if(invert) {
5397         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5398         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5399           if(adj) {
5400             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5401             add_to_linker((int)out,ba[i],internal);
5402           }else{
5403             emit_addnop(13);
5404             add_to_linker((int)out,ba[i],internal*2);
5405           }
5406           emit_jmp(0);
5407         }else
5408         #endif
5409         {
5410           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5411           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5412           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5413           if(internal)
5414             assem_debug("branch: internal\n");
5415           else
5416             assem_debug("branch: external\n");
5417           if(internal&&is_ds[(ba[i]-start)>>2]) {
5418             ds_assemble_entry(i);
5419           }
5420           else {
5421             add_to_linker((int)out,ba[i],internal);
5422             emit_jmp(0);
5423           }
5424         }
5425         set_jump_target(nottaken,(int)out);
5426       }
5427
5428       if(adj) {
5429         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5430       }
5431     } // (!unconditional)
5432   } // if(ooo)
5433   else
5434   {
5435     // In-order execution (branch first)
5436     //printf("IOE\n");
5437     int nottaken=0;
5438     if(rt1[i]==31) {
5439       int rt,return_address;
5440       rt=get_reg(branch_regs[i].regmap,31);
5441       if(rt>=0) {
5442         // Save the PC even if the branch is not taken
5443         return_address=start+i*4+8;
5444         emit_movimm(return_address,rt); // PC into link register
5445         #ifdef IMM_PREFETCH
5446         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5447         #endif
5448       }
5449     }
5450     if(!unconditional) {
5451       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5452       if(!only32)
5453       {
5454         assert(s1h>=0);
5455         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5456         {
5457           emit_test(s1h,s1h);
5458           nottaken=(int)out;
5459           emit_jns(1);
5460         }
5461         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5462         {
5463           emit_test(s1h,s1h);
5464           nottaken=(int)out;
5465           emit_js(1);
5466         }
5467       } // if(!only32)
5468       else
5469       {
5470         assert(s1l>=0);
5471         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5472         {
5473           emit_test(s1l,s1l);
5474           nottaken=(int)out;
5475           emit_jns(1);
5476         }
5477         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5478         {
5479           emit_test(s1l,s1l);
5480           nottaken=(int)out;
5481           emit_js(1);
5482         }
5483       }
5484     } // if(!unconditional)
5485     int adj;
5486     uint64_t ds_unneeded=branch_regs[i].u;
5487     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5488     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5489     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5490     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5491     ds_unneeded|=1;
5492     ds_unneeded_upper|=1;
5493     // branch taken
5494     if(!nevertaken) {
5495       //assem_debug("1:\n");
5496       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5497                     ds_unneeded,ds_unneeded_upper);
5498       // load regs
5499       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5500       address_generation(i+1,&branch_regs[i],0);
5501       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5502       ds_assemble(i+1,&branch_regs[i]);
5503       cc=get_reg(branch_regs[i].regmap,CCREG);
5504       if(cc==-1) {
5505         emit_loadreg(CCREG,cc=HOST_CCREG);
5506         // CHECK: Is the following instruction (fall thru) allocated ok?
5507       }
5508       assert(cc==HOST_CCREG);
5509       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5510       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5511       assem_debug("cycle count (adj)\n");
5512       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5513       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5514       if(internal)
5515         assem_debug("branch: internal\n");
5516       else
5517         assem_debug("branch: external\n");
5518       if(internal&&is_ds[(ba[i]-start)>>2]) {
5519         ds_assemble_entry(i);
5520       }
5521       else {
5522         add_to_linker((int)out,ba[i],internal);
5523         emit_jmp(0);
5524       }
5525     }
5526     // branch not taken
5527     cop1_usable=prev_cop1_usable;
5528     if(!unconditional) {
5529       set_jump_target(nottaken,(int)out);
5530       assem_debug("1:\n");
5531       if(!likely[i]) {
5532         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5533                       ds_unneeded,ds_unneeded_upper);
5534         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5535         address_generation(i+1,&branch_regs[i],0);
5536         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5537         ds_assemble(i+1,&branch_regs[i]);
5538       }
5539       cc=get_reg(branch_regs[i].regmap,CCREG);
5540       if(cc==-1&&!likely[i]) {
5541         // Cycle count isn't in a register, temporarily load it then write it out
5542         emit_loadreg(CCREG,HOST_CCREG);
5543         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5544         int jaddr=(int)out;
5545         emit_jns(0);
5546         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5547         emit_storereg(CCREG,HOST_CCREG);
5548       }
5549       else{
5550         cc=get_reg(i_regmap,CCREG);
5551         assert(cc==HOST_CCREG);
5552         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5553         int jaddr=(int)out;
5554         emit_jns(0);
5555         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5556       }
5557     }
5558   }
5559 }
5560
5561 void fjump_assemble(int i,struct regstat *i_regs)
5562 {
5563   signed char *i_regmap=i_regs->regmap;
5564   int cc;
5565   int match;
5566   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5567   assem_debug("fmatch=%d\n",match);
5568   int fs,cs;
5569   int eaddr;
5570   int invert=0;
5571   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5572   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5573   if(!match) invert=1;
5574   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5575   if(i>(ba[i]-start)>>2) invert=1;
5576   #endif
5577
5578   if(ooo[i]) {
5579     fs=get_reg(branch_regs[i].regmap,FSREG);
5580     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
5581   }
5582   else {
5583     fs=get_reg(i_regmap,FSREG);
5584   }
5585
5586   // Check cop1 unusable
5587   if(!cop1_usable) {
5588     cs=get_reg(i_regmap,CSREG);
5589     assert(cs>=0);
5590     emit_testimm(cs,0x20000000);
5591     eaddr=(int)out;
5592     emit_jeq(0);
5593     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
5594     cop1_usable=1;
5595   }
5596
5597   if(ooo[i]) {
5598     // Out of order execution (delay slot first)
5599     //printf("OOOE\n");
5600     ds_assemble(i+1,i_regs);
5601     int adj;
5602     uint64_t bc_unneeded=branch_regs[i].u;
5603     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5604     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5605     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5606     bc_unneeded|=1;
5607     bc_unneeded_upper|=1;
5608     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5609                   bc_unneeded,bc_unneeded_upper);
5610     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5611     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5612     cc=get_reg(branch_regs[i].regmap,CCREG);
5613     assert(cc==HOST_CCREG);
5614     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5615     assem_debug("cycle count (adj)\n");
5616     if(1) {
5617       int nottaken=0;
5618       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5619       if(1) {
5620         assert(fs>=0);
5621         emit_testimm(fs,0x800000);
5622         if(source[i]&0x10000) // BC1T
5623         {
5624           if(invert){
5625             nottaken=(int)out;
5626             emit_jeq(1);
5627           }else{
5628             add_to_linker((int)out,ba[i],internal);
5629             emit_jne(0);
5630           }
5631         }
5632         else // BC1F
5633           if(invert){
5634             nottaken=(int)out;
5635             emit_jne(1);
5636           }else{
5637             add_to_linker((int)out,ba[i],internal);
5638             emit_jeq(0);
5639           }
5640         {
5641         }
5642       } // if(!only32)
5643
5644       if(invert) {
5645         if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5646         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5647         else if(match) emit_addnop(13);
5648         #endif
5649         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5650         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5651         if(internal)
5652           assem_debug("branch: internal\n");
5653         else
5654           assem_debug("branch: external\n");
5655         if(internal&&is_ds[(ba[i]-start)>>2]) {
5656           ds_assemble_entry(i);
5657         }
5658         else {
5659           add_to_linker((int)out,ba[i],internal);
5660           emit_jmp(0);
5661         }
5662         set_jump_target(nottaken,(int)out);
5663       }
5664
5665       if(adj) {
5666         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5667       }
5668     } // (!unconditional)
5669   } // if(ooo)
5670   else
5671   {
5672     // In-order execution (branch first)
5673     //printf("IOE\n");
5674     int nottaken=0;
5675     if(1) {
5676       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5677       if(1) {
5678         assert(fs>=0);
5679         emit_testimm(fs,0x800000);
5680         if(source[i]&0x10000) // BC1T
5681         {
5682           nottaken=(int)out;
5683           emit_jeq(1);
5684         }
5685         else // BC1F
5686         {
5687           nottaken=(int)out;
5688           emit_jne(1);
5689         }
5690       }
5691     } // if(!unconditional)
5692     int adj;
5693     uint64_t ds_unneeded=branch_regs[i].u;
5694     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5695     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5696     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5697     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5698     ds_unneeded|=1;
5699     ds_unneeded_upper|=1;
5700     // branch taken
5701     //assem_debug("1:\n");
5702     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5703                   ds_unneeded,ds_unneeded_upper);
5704     // load regs
5705     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5706     address_generation(i+1,&branch_regs[i],0);
5707     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5708     ds_assemble(i+1,&branch_regs[i]);
5709     cc=get_reg(branch_regs[i].regmap,CCREG);
5710     if(cc==-1) {
5711       emit_loadreg(CCREG,cc=HOST_CCREG);
5712       // CHECK: Is the following instruction (fall thru) allocated ok?
5713     }
5714     assert(cc==HOST_CCREG);
5715     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5716     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5717     assem_debug("cycle count (adj)\n");
5718     if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5719     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5720     if(internal)
5721       assem_debug("branch: internal\n");
5722     else
5723       assem_debug("branch: external\n");
5724     if(internal&&is_ds[(ba[i]-start)>>2]) {
5725       ds_assemble_entry(i);
5726     }
5727     else {
5728       add_to_linker((int)out,ba[i],internal);
5729       emit_jmp(0);
5730     }
5731
5732     // branch not taken
5733     if(1) { // <- FIXME (don't need this)
5734       set_jump_target(nottaken,(int)out);
5735       assem_debug("1:\n");
5736       if(!likely[i]) {
5737         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5738                       ds_unneeded,ds_unneeded_upper);
5739         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5740         address_generation(i+1,&branch_regs[i],0);
5741         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5742         ds_assemble(i+1,&branch_regs[i]);
5743       }
5744       cc=get_reg(branch_regs[i].regmap,CCREG);
5745       if(cc==-1&&!likely[i]) {
5746         // Cycle count isn't in a register, temporarily load it then write it out
5747         emit_loadreg(CCREG,HOST_CCREG);
5748         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5749         int jaddr=(int)out;
5750         emit_jns(0);
5751         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5752         emit_storereg(CCREG,HOST_CCREG);
5753       }
5754       else{
5755         cc=get_reg(i_regmap,CCREG);
5756         assert(cc==HOST_CCREG);
5757         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5758         int jaddr=(int)out;
5759         emit_jns(0);
5760         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5761       }
5762     }
5763   }
5764 }
5765
5766 static void pagespan_assemble(int i,struct regstat *i_regs)
5767 {
5768   int s1l=get_reg(i_regs->regmap,rs1[i]);
5769   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
5770   int s2l=get_reg(i_regs->regmap,rs2[i]);
5771   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
5772   int taken=0;
5773   int nottaken=0;
5774   int unconditional=0;
5775   if(rs1[i]==0)
5776   {
5777     s1l=s2l;s1h=s2h;
5778     s2l=s2h=-1;
5779   }
5780   else if(rs2[i]==0)
5781   {
5782     s2l=s2h=-1;
5783   }
5784   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
5785     s1h=s2h=-1;
5786   }
5787   int hr=0;
5788   int addr=-1,alt=-1,ntaddr=-1;
5789   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5790   else {
5791     while(hr<HOST_REGS)
5792     {
5793       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5794          (i_regs->regmap[hr]&63)!=rs1[i] &&
5795          (i_regs->regmap[hr]&63)!=rs2[i] )
5796       {
5797         addr=hr++;break;
5798       }
5799       hr++;
5800     }
5801   }
5802   while(hr<HOST_REGS)
5803   {
5804     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5805        (i_regs->regmap[hr]&63)!=rs1[i] &&
5806        (i_regs->regmap[hr]&63)!=rs2[i] )
5807     {
5808       alt=hr++;break;
5809     }
5810     hr++;
5811   }
5812   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5813   {
5814     while(hr<HOST_REGS)
5815     {
5816       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5817          (i_regs->regmap[hr]&63)!=rs1[i] &&
5818          (i_regs->regmap[hr]&63)!=rs2[i] )
5819       {
5820         ntaddr=hr;break;
5821       }
5822       hr++;
5823     }
5824   }
5825   assert(hr<HOST_REGS);
5826   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
5827     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
5828   }
5829   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5830   if(opcode[i]==2) // J
5831   {
5832     unconditional=1;
5833   }
5834   if(opcode[i]==3) // JAL
5835   {
5836     // TODO: mini_ht
5837     int rt=get_reg(i_regs->regmap,31);
5838     emit_movimm(start+i*4+8,rt);
5839     unconditional=1;
5840   }
5841   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
5842   {
5843     emit_mov(s1l,addr);
5844     if(opcode2[i]==9) // JALR
5845     {
5846       int rt=get_reg(i_regs->regmap,rt1[i]);
5847       emit_movimm(start+i*4+8,rt);
5848     }
5849   }
5850   if((opcode[i]&0x3f)==4) // BEQ
5851   {
5852     if(rs1[i]==rs2[i])
5853     {
5854       unconditional=1;
5855     }
5856     else
5857     #ifdef HAVE_CMOV_IMM
5858     if(s1h<0) {
5859       if(s2l>=0) emit_cmp(s1l,s2l);
5860       else emit_test(s1l,s1l);
5861       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5862     }
5863     else
5864     #endif
5865     {
5866       assert(s1l>=0);
5867       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5868       if(s1h>=0) {
5869         if(s2h>=0) emit_cmp(s1h,s2h);
5870         else emit_test(s1h,s1h);
5871         emit_cmovne_reg(alt,addr);
5872       }
5873       if(s2l>=0) emit_cmp(s1l,s2l);
5874       else emit_test(s1l,s1l);
5875       emit_cmovne_reg(alt,addr);
5876     }
5877   }
5878   if((opcode[i]&0x3f)==5) // BNE
5879   {
5880     #ifdef HAVE_CMOV_IMM
5881     if(s1h<0) {
5882       if(s2l>=0) emit_cmp(s1l,s2l);
5883       else emit_test(s1l,s1l);
5884       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5885     }
5886     else
5887     #endif
5888     {
5889       assert(s1l>=0);
5890       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5891       if(s1h>=0) {
5892         if(s2h>=0) emit_cmp(s1h,s2h);
5893         else emit_test(s1h,s1h);
5894         emit_cmovne_reg(alt,addr);
5895       }
5896       if(s2l>=0) emit_cmp(s1l,s2l);
5897       else emit_test(s1l,s1l);
5898       emit_cmovne_reg(alt,addr);
5899     }
5900   }
5901   if((opcode[i]&0x3f)==0x14) // BEQL
5902   {
5903     if(s1h>=0) {
5904       if(s2h>=0) emit_cmp(s1h,s2h);
5905       else emit_test(s1h,s1h);
5906       nottaken=(int)out;
5907       emit_jne(0);
5908     }
5909     if(s2l>=0) emit_cmp(s1l,s2l);
5910     else emit_test(s1l,s1l);
5911     if(nottaken) set_jump_target(nottaken,(int)out);
5912     nottaken=(int)out;
5913     emit_jne(0);
5914   }
5915   if((opcode[i]&0x3f)==0x15) // BNEL
5916   {
5917     if(s1h>=0) {
5918       if(s2h>=0) emit_cmp(s1h,s2h);
5919       else emit_test(s1h,s1h);
5920       taken=(int)out;
5921       emit_jne(0);
5922     }
5923     if(s2l>=0) emit_cmp(s1l,s2l);
5924     else emit_test(s1l,s1l);
5925     nottaken=(int)out;
5926     emit_jeq(0);
5927     if(taken) set_jump_target(taken,(int)out);
5928   }
5929   if((opcode[i]&0x3f)==6) // BLEZ
5930   {
5931     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5932     emit_cmpimm(s1l,1);
5933     if(s1h>=0) emit_mov(addr,ntaddr);
5934     emit_cmovl_reg(alt,addr);
5935     if(s1h>=0) {
5936       emit_test(s1h,s1h);
5937       emit_cmovne_reg(ntaddr,addr);
5938       emit_cmovs_reg(alt,addr);
5939     }
5940   }
5941   if((opcode[i]&0x3f)==7) // BGTZ
5942   {
5943     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5944     emit_cmpimm(s1l,1);
5945     if(s1h>=0) emit_mov(addr,alt);
5946     emit_cmovl_reg(ntaddr,addr);
5947     if(s1h>=0) {
5948       emit_test(s1h,s1h);
5949       emit_cmovne_reg(alt,addr);
5950       emit_cmovs_reg(ntaddr,addr);
5951     }
5952   }
5953   if((opcode[i]&0x3f)==0x16) // BLEZL
5954   {
5955     assert((opcode[i]&0x3f)!=0x16);
5956   }
5957   if((opcode[i]&0x3f)==0x17) // BGTZL
5958   {
5959     assert((opcode[i]&0x3f)!=0x17);
5960   }
5961   assert(opcode[i]!=1); // BLTZ/BGEZ
5962
5963   //FIXME: Check CSREG
5964   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5965     if((source[i]&0x30000)==0) // BC1F
5966     {
5967       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5968       emit_testimm(s1l,0x800000);
5969       emit_cmovne_reg(alt,addr);
5970     }
5971     if((source[i]&0x30000)==0x10000) // BC1T
5972     {
5973       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5974       emit_testimm(s1l,0x800000);
5975       emit_cmovne_reg(alt,addr);
5976     }
5977     if((source[i]&0x30000)==0x20000) // BC1FL
5978     {
5979       emit_testimm(s1l,0x800000);
5980       nottaken=(int)out;
5981       emit_jne(0);
5982     }
5983     if((source[i]&0x30000)==0x30000) // BC1TL
5984     {
5985       emit_testimm(s1l,0x800000);
5986       nottaken=(int)out;
5987       emit_jeq(0);
5988     }
5989   }
5990
5991   assert(i_regs->regmap[HOST_CCREG]==CCREG);
5992   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
5993   if(likely[i]||unconditional)
5994   {
5995     emit_movimm(ba[i],HOST_BTREG);
5996   }
5997   else if(addr!=HOST_BTREG)
5998   {
5999     emit_mov(addr,HOST_BTREG);
6000   }
6001   void *branch_addr=out;
6002   emit_jmp(0);
6003   int target_addr=start+i*4+5;
6004   void *stub=out;
6005   void *compiled_target_addr=check_addr(target_addr);
6006   emit_extjump_ds((int)branch_addr,target_addr);
6007   if(compiled_target_addr) {
6008     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6009     add_link(target_addr,stub);
6010   }
6011   else set_jump_target((int)branch_addr,(int)stub);
6012   if(likely[i]) {
6013     // Not-taken path
6014     set_jump_target((int)nottaken,(int)out);
6015     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6016     void *branch_addr=out;
6017     emit_jmp(0);
6018     int target_addr=start+i*4+8;
6019     void *stub=out;
6020     void *compiled_target_addr=check_addr(target_addr);
6021     emit_extjump_ds((int)branch_addr,target_addr);
6022     if(compiled_target_addr) {
6023       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6024       add_link(target_addr,stub);
6025     }
6026     else set_jump_target((int)branch_addr,(int)stub);
6027   }
6028 }
6029
6030 // Assemble the delay slot for the above
6031 static void pagespan_ds()
6032 {
6033   assem_debug("initial delay slot:\n");
6034   u_int vaddr=start+1;
6035   u_int page=get_page(vaddr);
6036   u_int vpage=get_vpage(vaddr);
6037   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6038   do_dirty_stub_ds();
6039   ll_add(jump_in+page,vaddr,(void *)out);
6040   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6041   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6042     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6043   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6044     emit_writeword(HOST_BTREG,(int)&branch_target);
6045   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6046   address_generation(0,&regs[0],regs[0].regmap_entry);
6047   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6048     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6049   cop1_usable=0;
6050   is_delayslot=0;
6051   switch(itype[0]) {
6052     case ALU:
6053       alu_assemble(0,&regs[0]);break;
6054     case IMM16:
6055       imm16_assemble(0,&regs[0]);break;
6056     case SHIFT:
6057       shift_assemble(0,&regs[0]);break;
6058     case SHIFTIMM:
6059       shiftimm_assemble(0,&regs[0]);break;
6060     case LOAD:
6061       load_assemble(0,&regs[0]);break;
6062     case LOADLR:
6063       loadlr_assemble(0,&regs[0]);break;
6064     case STORE:
6065       store_assemble(0,&regs[0]);break;
6066     case STORELR:
6067       storelr_assemble(0,&regs[0]);break;
6068     case COP0:
6069       cop0_assemble(0,&regs[0]);break;
6070     case COP1:
6071       cop1_assemble(0,&regs[0]);break;
6072     case C1LS:
6073       c1ls_assemble(0,&regs[0]);break;
6074     case COP2:
6075       cop2_assemble(0,&regs[0]);break;
6076     case C2LS:
6077       c2ls_assemble(0,&regs[0]);break;
6078     case C2OP:
6079       c2op_assemble(0,&regs[0]);break;
6080     case FCONV:
6081       fconv_assemble(0,&regs[0]);break;
6082     case FLOAT:
6083       float_assemble(0,&regs[0]);break;
6084     case FCOMP:
6085       fcomp_assemble(0,&regs[0]);break;
6086     case MULTDIV:
6087       multdiv_assemble(0,&regs[0]);break;
6088     case MOV:
6089       mov_assemble(0,&regs[0]);break;
6090     case SYSCALL:
6091     case HLECALL:
6092     case INTCALL:
6093     case SPAN:
6094     case UJUMP:
6095     case RJUMP:
6096     case CJUMP:
6097     case SJUMP:
6098     case FJUMP:
6099       SysPrintf("Jump in the delay slot.  This is probably a bug.\n");
6100   }
6101   int btaddr=get_reg(regs[0].regmap,BTREG);
6102   if(btaddr<0) {
6103     btaddr=get_reg(regs[0].regmap,-1);
6104     emit_readword((int)&branch_target,btaddr);
6105   }
6106   assert(btaddr!=HOST_CCREG);
6107   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6108 #ifdef HOST_IMM8
6109   emit_movimm(start+4,HOST_TEMPREG);
6110   emit_cmp(btaddr,HOST_TEMPREG);
6111 #else
6112   emit_cmpimm(btaddr,start+4);
6113 #endif
6114   int branch=(int)out;
6115   emit_jeq(0);
6116   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6117   emit_jmp(jump_vaddr_reg[btaddr]);
6118   set_jump_target(branch,(int)out);
6119   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6120   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6121 }
6122
6123 // Basic liveness analysis for MIPS registers
6124 void unneeded_registers(int istart,int iend,int r)
6125 {
6126   int i;
6127   uint64_t u,uu,gte_u,b,bu,gte_bu;
6128   uint64_t temp_u,temp_uu,temp_gte_u=0;
6129   uint64_t tdep;
6130   uint64_t gte_u_unknown=0;
6131   if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
6132     gte_u_unknown=~0ll;
6133   if(iend==slen-1) {
6134     u=1;uu=1;
6135     gte_u=gte_u_unknown;
6136   }else{
6137     u=unneeded_reg[iend+1];
6138     uu=unneeded_reg_upper[iend+1];
6139     u=1;uu=1;
6140     gte_u=gte_unneeded[iend+1];
6141   }
6142
6143   for (i=iend;i>=istart;i--)
6144   {
6145     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6146     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6147     {
6148       // If subroutine call, flag return address as a possible branch target
6149       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6150
6151       if(ba[i]<start || ba[i]>=(start+slen*4))
6152       {
6153         // Branch out of this block, flush all regs
6154         u=1;
6155         uu=1;
6156         gte_u=gte_u_unknown;
6157         /* Hexagon hack
6158         if(itype[i]==UJUMP&&rt1[i]==31)
6159         {
6160           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6161         }
6162         if(itype[i]==RJUMP&&rs1[i]==31)
6163         {
6164           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6165         }
6166         if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6167           if(itype[i]==UJUMP&&rt1[i]==31)
6168           {
6169             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6170             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6171           }
6172           if(itype[i]==RJUMP&&rs1[i]==31)
6173           {
6174             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6175             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6176           }
6177         }*/
6178         branch_unneeded_reg[i]=u;
6179         branch_unneeded_reg_upper[i]=uu;
6180         // Merge in delay slot
6181         tdep=(~uu>>rt1[i+1])&1;
6182         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6183         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6184         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6185         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6186         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6187         u|=1;uu|=1;
6188         gte_u|=gte_rt[i+1];
6189         gte_u&=~gte_rs[i+1];
6190         // If branch is "likely" (and conditional)
6191         // then we skip the delay slot on the fall-thru path
6192         if(likely[i]) {
6193           if(i<slen-1) {
6194             u&=unneeded_reg[i+2];
6195             uu&=unneeded_reg_upper[i+2];
6196             gte_u&=gte_unneeded[i+2];
6197           }
6198           else
6199           {
6200             u=1;
6201             uu=1;
6202             gte_u=gte_u_unknown;
6203           }
6204         }
6205       }
6206       else
6207       {
6208         // Internal branch, flag target
6209         bt[(ba[i]-start)>>2]=1;
6210         if(ba[i]<=start+i*4) {
6211           // Backward branch
6212           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6213           {
6214             // Unconditional branch
6215             temp_u=1;temp_uu=1;
6216             temp_gte_u=0;
6217           } else {
6218             // Conditional branch (not taken case)
6219             temp_u=unneeded_reg[i+2];
6220             temp_uu=unneeded_reg_upper[i+2];
6221             temp_gte_u&=gte_unneeded[i+2];
6222           }
6223           // Merge in delay slot
6224           tdep=(~temp_uu>>rt1[i+1])&1;
6225           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6226           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6227           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6228           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6229           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6230           temp_u|=1;temp_uu|=1;
6231           temp_gte_u|=gte_rt[i+1];
6232           temp_gte_u&=~gte_rs[i+1];
6233           // If branch is "likely" (and conditional)
6234           // then we skip the delay slot on the fall-thru path
6235           if(likely[i]) {
6236             if(i<slen-1) {
6237               temp_u&=unneeded_reg[i+2];
6238               temp_uu&=unneeded_reg_upper[i+2];
6239               temp_gte_u&=gte_unneeded[i+2];
6240             }
6241             else
6242             {
6243               temp_u=1;
6244               temp_uu=1;
6245               temp_gte_u=gte_u_unknown;
6246             }
6247           }
6248           tdep=(~temp_uu>>rt1[i])&1;
6249           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6250           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6251           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6252           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6253           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6254           temp_u|=1;temp_uu|=1;
6255           temp_gte_u|=gte_rt[i];
6256           temp_gte_u&=~gte_rs[i];
6257           unneeded_reg[i]=temp_u;
6258           unneeded_reg_upper[i]=temp_uu;
6259           gte_unneeded[i]=temp_gte_u;
6260           // Only go three levels deep.  This recursion can take an
6261           // excessive amount of time if there are a lot of nested loops.
6262           if(r<2) {
6263             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6264           }else{
6265             unneeded_reg[(ba[i]-start)>>2]=1;
6266             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6267             gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6268           }
6269         } /*else*/ if(1) {
6270           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6271           {
6272             // Unconditional branch
6273             u=unneeded_reg[(ba[i]-start)>>2];
6274             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6275             gte_u=gte_unneeded[(ba[i]-start)>>2];
6276             branch_unneeded_reg[i]=u;
6277             branch_unneeded_reg_upper[i]=uu;
6278         //u=1;
6279         //uu=1;
6280         //branch_unneeded_reg[i]=u;
6281         //branch_unneeded_reg_upper[i]=uu;
6282             // Merge in delay slot
6283             tdep=(~uu>>rt1[i+1])&1;
6284             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6285             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6286             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6287             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6288             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6289             u|=1;uu|=1;
6290             gte_u|=gte_rt[i+1];
6291             gte_u&=~gte_rs[i+1];
6292           } else {
6293             // Conditional branch
6294             b=unneeded_reg[(ba[i]-start)>>2];
6295             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6296             gte_bu=gte_unneeded[(ba[i]-start)>>2];
6297             branch_unneeded_reg[i]=b;
6298             branch_unneeded_reg_upper[i]=bu;
6299         //b=1;
6300         //bu=1;
6301         //branch_unneeded_reg[i]=b;
6302         //branch_unneeded_reg_upper[i]=bu;
6303             // Branch delay slot
6304             tdep=(~uu>>rt1[i+1])&1;
6305             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6306             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6307             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6308             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6309             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6310             b|=1;bu|=1;
6311             gte_bu|=gte_rt[i+1];
6312             gte_bu&=~gte_rs[i+1];
6313             // If branch is "likely" then we skip the
6314             // delay slot on the fall-thru path
6315             if(likely[i]) {
6316               u=b;
6317               uu=bu;
6318               gte_u=gte_bu;
6319               if(i<slen-1) {
6320                 u&=unneeded_reg[i+2];
6321                 uu&=unneeded_reg_upper[i+2];
6322                 gte_u&=gte_unneeded[i+2];
6323         //u=1;
6324         //uu=1;
6325               }
6326             } else {
6327               u&=b;
6328               uu&=bu;
6329               gte_u&=gte_bu;
6330         //u=1;
6331         //uu=1;
6332             }
6333             if(i<slen-1) {
6334               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6335               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6336         //branch_unneeded_reg[i]=1;
6337         //branch_unneeded_reg_upper[i]=1;
6338             } else {
6339               branch_unneeded_reg[i]=1;
6340               branch_unneeded_reg_upper[i]=1;
6341             }
6342           }
6343         }
6344       }
6345     }
6346     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6347     {
6348       // SYSCALL instruction (software interrupt)
6349       u=1;
6350       uu=1;
6351     }
6352     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6353     {
6354       // ERET instruction (return from interrupt)
6355       u=1;
6356       uu=1;
6357     }
6358     //u=uu=1; // DEBUG
6359     tdep=(~uu>>rt1[i])&1;
6360     // Written registers are unneeded
6361     u|=1LL<<rt1[i];
6362     u|=1LL<<rt2[i];
6363     uu|=1LL<<rt1[i];
6364     uu|=1LL<<rt2[i];
6365     gte_u|=gte_rt[i];
6366     // Accessed registers are needed
6367     u&=~(1LL<<rs1[i]);
6368     u&=~(1LL<<rs2[i]);
6369     uu&=~(1LL<<us1[i]);
6370     uu&=~(1LL<<us2[i]);
6371     gte_u&=~gte_rs[i];
6372     if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
6373       gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
6374     // Source-target dependencies
6375     uu&=~(tdep<<dep1[i]);
6376     uu&=~(tdep<<dep2[i]);
6377     // R0 is always unneeded
6378     u|=1;uu|=1;
6379     // Save it
6380     unneeded_reg[i]=u;
6381     unneeded_reg_upper[i]=uu;
6382     gte_unneeded[i]=gte_u;
6383     /*
6384     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6385     printf("U:");
6386     int r;
6387     for(r=1;r<=CCREG;r++) {
6388       if((unneeded_reg[i]>>r)&1) {
6389         if(r==HIREG) printf(" HI");
6390         else if(r==LOREG) printf(" LO");
6391         else printf(" r%d",r);
6392       }
6393     }
6394     printf(" UU:");
6395     for(r=1;r<=CCREG;r++) {
6396       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6397         if(r==HIREG) printf(" HI");
6398         else if(r==LOREG) printf(" LO");
6399         else printf(" r%d",r);
6400       }
6401     }
6402     printf("\n");*/
6403   }
6404   for (i=iend;i>=istart;i--)
6405   {
6406     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6407   }
6408 }
6409
6410 // Write back dirty registers as soon as we will no longer modify them,
6411 // so that we don't end up with lots of writes at the branches.
6412 void clean_registers(int istart,int iend,int wr)
6413 {
6414   int i;
6415   int r;
6416   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
6417   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
6418   if(iend==slen-1) {
6419     will_dirty_i=will_dirty_next=0;
6420     wont_dirty_i=wont_dirty_next=0;
6421   }else{
6422     will_dirty_i=will_dirty_next=will_dirty[iend+1];
6423     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
6424   }
6425   for (i=iend;i>=istart;i--)
6426   {
6427     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6428     {
6429       if(ba[i]<start || ba[i]>=(start+slen*4))
6430       {
6431         // Branch out of this block, flush all regs
6432         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6433         {
6434           // Unconditional branch
6435           will_dirty_i=0;
6436           wont_dirty_i=0;
6437           // Merge in delay slot (will dirty)
6438           for(r=0;r<HOST_REGS;r++) {
6439             if(r!=EXCLUDE_REG) {
6440               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6441               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6442               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6443               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6444               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6445               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6446               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6447               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6448               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6449               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6450               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6451               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6452               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6453               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6454             }
6455           }
6456         }
6457         else
6458         {
6459           // Conditional branch
6460           will_dirty_i=0;
6461           wont_dirty_i=wont_dirty_next;
6462           // Merge in delay slot (will dirty)
6463           for(r=0;r<HOST_REGS;r++) {
6464             if(r!=EXCLUDE_REG) {
6465               if(!likely[i]) {
6466                 // Might not dirty if likely branch is not taken
6467                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6468                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6469                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6470                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6471                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6472                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
6473                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6474                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6475                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6476                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6477                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6478                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6479                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6480                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6481               }
6482             }
6483           }
6484         }
6485         // Merge in delay slot (wont dirty)
6486         for(r=0;r<HOST_REGS;r++) {
6487           if(r!=EXCLUDE_REG) {
6488             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6489             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6490             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6491             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6492             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6493             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6494             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6495             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6496             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6497             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6498           }
6499         }
6500         if(wr) {
6501           #ifndef DESTRUCTIVE_WRITEBACK
6502           branch_regs[i].dirty&=wont_dirty_i;
6503           #endif
6504           branch_regs[i].dirty|=will_dirty_i;
6505         }
6506       }
6507       else
6508       {
6509         // Internal branch
6510         if(ba[i]<=start+i*4) {
6511           // Backward branch
6512           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6513           {
6514             // Unconditional branch
6515             temp_will_dirty=0;
6516             temp_wont_dirty=0;
6517             // Merge in delay slot (will dirty)
6518             for(r=0;r<HOST_REGS;r++) {
6519               if(r!=EXCLUDE_REG) {
6520                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6521                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6522                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6523                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6524                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6525                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6526                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6527                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6528                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6529                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6530                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6531                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6532                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6533                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6534               }
6535             }
6536           } else {
6537             // Conditional branch (not taken case)
6538             temp_will_dirty=will_dirty_next;
6539             temp_wont_dirty=wont_dirty_next;
6540             // Merge in delay slot (will dirty)
6541             for(r=0;r<HOST_REGS;r++) {
6542               if(r!=EXCLUDE_REG) {
6543                 if(!likely[i]) {
6544                   // Will not dirty if likely branch is not taken
6545                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6546                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6547                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6548                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6549                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6550                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
6551                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6552                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6553                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6554                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6555                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6556                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6557                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6558                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6559                 }
6560               }
6561             }
6562           }
6563           // Merge in delay slot (wont dirty)
6564           for(r=0;r<HOST_REGS;r++) {
6565             if(r!=EXCLUDE_REG) {
6566               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
6567               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
6568               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
6569               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
6570               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6571               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
6572               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
6573               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
6574               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
6575               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6576             }
6577           }
6578           // Deal with changed mappings
6579           if(i<iend) {
6580             for(r=0;r<HOST_REGS;r++) {
6581               if(r!=EXCLUDE_REG) {
6582                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
6583                   temp_will_dirty&=~(1<<r);
6584                   temp_wont_dirty&=~(1<<r);
6585                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6586                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6587                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6588                   } else {
6589                     temp_will_dirty|=1<<r;
6590                     temp_wont_dirty|=1<<r;
6591                   }
6592                 }
6593               }
6594             }
6595           }
6596           if(wr) {
6597             will_dirty[i]=temp_will_dirty;
6598             wont_dirty[i]=temp_wont_dirty;
6599             clean_registers((ba[i]-start)>>2,i-1,0);
6600           }else{
6601             // Limit recursion.  It can take an excessive amount
6602             // of time if there are a lot of nested loops.
6603             will_dirty[(ba[i]-start)>>2]=0;
6604             wont_dirty[(ba[i]-start)>>2]=-1;
6605           }
6606         }
6607         /*else*/ if(1)
6608         {
6609           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6610           {
6611             // Unconditional branch
6612             will_dirty_i=0;
6613             wont_dirty_i=0;
6614           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6615             for(r=0;r<HOST_REGS;r++) {
6616               if(r!=EXCLUDE_REG) {
6617                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6618                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
6619                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6620                 }
6621                 if(branch_regs[i].regmap[r]>=0) {
6622                   will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6623                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6624                 }
6625               }
6626             }
6627           //}
6628             // Merge in delay slot
6629             for(r=0;r<HOST_REGS;r++) {
6630               if(r!=EXCLUDE_REG) {
6631                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6632                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6633                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6634                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6635                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6636                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6637                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6638                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6639                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6640                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6641                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6642                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6643                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6644                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6645               }
6646             }
6647           } else {
6648             // Conditional branch
6649             will_dirty_i=will_dirty_next;
6650             wont_dirty_i=wont_dirty_next;
6651           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6652             for(r=0;r<HOST_REGS;r++) {
6653               if(r!=EXCLUDE_REG) {
6654                 signed char target_reg=branch_regs[i].regmap[r];
6655                 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6656                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6657                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6658                 }
6659                 else if(target_reg>=0) {
6660                   will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6661                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6662                 }
6663                 // Treat delay slot as part of branch too
6664                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6665                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6666                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6667                 }
6668                 else
6669                 {
6670                   will_dirty[i+1]&=~(1<<r);
6671                 }*/
6672               }
6673             }
6674           //}
6675             // Merge in delay slot
6676             for(r=0;r<HOST_REGS;r++) {
6677               if(r!=EXCLUDE_REG) {
6678                 if(!likely[i]) {
6679                   // Might not dirty if likely branch is not taken
6680                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6681                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6682                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6683                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6684                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6685                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6686                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6687                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6688                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6689                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6690                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6691                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6692                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6693                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6694                 }
6695               }
6696             }
6697           }
6698           // Merge in delay slot (won't dirty)
6699           for(r=0;r<HOST_REGS;r++) {
6700             if(r!=EXCLUDE_REG) {
6701               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6702               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6703               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6704               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6705               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6706               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6707               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6708               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6709               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6710               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6711             }
6712           }
6713           if(wr) {
6714             #ifndef DESTRUCTIVE_WRITEBACK
6715             branch_regs[i].dirty&=wont_dirty_i;
6716             #endif
6717             branch_regs[i].dirty|=will_dirty_i;
6718           }
6719         }
6720       }
6721     }
6722     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6723     {
6724       // SYSCALL instruction (software interrupt)
6725       will_dirty_i=0;
6726       wont_dirty_i=0;
6727     }
6728     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6729     {
6730       // ERET instruction (return from interrupt)
6731       will_dirty_i=0;
6732       wont_dirty_i=0;
6733     }
6734     will_dirty_next=will_dirty_i;
6735     wont_dirty_next=wont_dirty_i;
6736     for(r=0;r<HOST_REGS;r++) {
6737       if(r!=EXCLUDE_REG) {
6738         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6739         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6740         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6741         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6742         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6743         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6744         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6745         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6746         if(i>istart) {
6747           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
6748           {
6749             // Don't store a register immediately after writing it,
6750             // may prevent dual-issue.
6751             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
6752             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
6753           }
6754         }
6755       }
6756     }
6757     // Save it
6758     will_dirty[i]=will_dirty_i;
6759     wont_dirty[i]=wont_dirty_i;
6760     // Mark registers that won't be dirtied as not dirty
6761     if(wr) {
6762       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
6763       for(r=0;r<HOST_REGS;r++) {
6764         if((will_dirty_i>>r)&1) {
6765           printf(" r%d",r);
6766         }
6767       }
6768       printf("\n");*/
6769
6770       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
6771         regs[i].dirty|=will_dirty_i;
6772         #ifndef DESTRUCTIVE_WRITEBACK
6773         regs[i].dirty&=wont_dirty_i;
6774         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6775         {
6776           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
6777             for(r=0;r<HOST_REGS;r++) {
6778               if(r!=EXCLUDE_REG) {
6779                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
6780                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
6781                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6782               }
6783             }
6784           }
6785         }
6786         else
6787         {
6788           if(i<iend) {
6789             for(r=0;r<HOST_REGS;r++) {
6790               if(r!=EXCLUDE_REG) {
6791                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
6792                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
6793                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6794               }
6795             }
6796           }
6797         }
6798         #endif
6799       //}
6800     }
6801     // Deal with changed mappings
6802     temp_will_dirty=will_dirty_i;
6803     temp_wont_dirty=wont_dirty_i;
6804     for(r=0;r<HOST_REGS;r++) {
6805       if(r!=EXCLUDE_REG) {
6806         int nr;
6807         if(regs[i].regmap[r]==regmap_pre[i][r]) {
6808           if(wr) {
6809             #ifndef DESTRUCTIVE_WRITEBACK
6810             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6811             #endif
6812             regs[i].wasdirty|=will_dirty_i&(1<<r);
6813           }
6814         }
6815         else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
6816           // Register moved to a different register
6817           will_dirty_i&=~(1<<r);
6818           wont_dirty_i&=~(1<<r);
6819           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
6820           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
6821           if(wr) {
6822             #ifndef DESTRUCTIVE_WRITEBACK
6823             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6824             #endif
6825             regs[i].wasdirty|=will_dirty_i&(1<<r);
6826           }
6827         }
6828         else {
6829           will_dirty_i&=~(1<<r);
6830           wont_dirty_i&=~(1<<r);
6831           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6832             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6833             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6834           } else {
6835             wont_dirty_i|=1<<r;
6836             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
6837           }
6838         }
6839       }
6840     }
6841   }
6842 }
6843
6844 #ifdef DISASM
6845   /* disassembly */
6846 void disassemble_inst(int i)
6847 {
6848     if (bt[i]) printf("*"); else printf(" ");
6849     switch(itype[i]) {
6850       case UJUMP:
6851         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6852       case CJUMP:
6853         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
6854       case SJUMP:
6855         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
6856       case FJUMP:
6857         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6858       case RJUMP:
6859         if (opcode[i]==0x9&&rt1[i]!=31)
6860           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
6861         else
6862           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
6863         break;
6864       case SPAN:
6865         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
6866       case IMM16:
6867         if(opcode[i]==0xf) //LUI
6868           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
6869         else
6870           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
6871         break;
6872       case LOAD:
6873       case LOADLR:
6874         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
6875         break;
6876       case STORE:
6877       case STORELR:
6878         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
6879         break;
6880       case ALU:
6881       case SHIFT:
6882         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
6883         break;
6884       case MULTDIV:
6885         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
6886         break;
6887       case SHIFTIMM:
6888         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
6889         break;
6890       case MOV:
6891         if((opcode2[i]&0x1d)==0x10)
6892           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
6893         else if((opcode2[i]&0x1d)==0x11)
6894           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
6895         else
6896           printf (" %x: %s\n",start+i*4,insn[i]);
6897         break;
6898       case COP0:
6899         if(opcode2[i]==0)
6900           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
6901         else if(opcode2[i]==4)
6902           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
6903         else printf (" %x: %s\n",start+i*4,insn[i]);
6904         break;
6905       case COP1:
6906         if(opcode2[i]<3)
6907           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
6908         else if(opcode2[i]>3)
6909           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
6910         else printf (" %x: %s\n",start+i*4,insn[i]);
6911         break;
6912       case COP2:
6913         if(opcode2[i]<3)
6914           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
6915         else if(opcode2[i]>3)
6916           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
6917         else printf (" %x: %s\n",start+i*4,insn[i]);
6918         break;
6919       case C1LS:
6920         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
6921         break;
6922       case C2LS:
6923         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
6924         break;
6925       case INTCALL:
6926         printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6927         break;
6928       default:
6929         //printf (" %s %8x\n",insn[i],source[i]);
6930         printf (" %x: %s\n",start+i*4,insn[i]);
6931     }
6932 }
6933 #else
6934 static void disassemble_inst(int i) {}
6935 #endif // DISASM
6936
6937 #define DRC_TEST_VAL 0x74657374
6938
6939 static int new_dynarec_test(void)
6940 {
6941   int (*testfunc)(void) = (void *)out;
6942   int ret;
6943   emit_movimm(DRC_TEST_VAL,0); // test
6944   emit_jmpreg(14);
6945   literal_pool(0);
6946 #ifdef __arm__
6947   __clear_cache((void *)testfunc, out);
6948 #endif
6949   SysPrintf("testing if we can run recompiled code..\n");
6950   ret = testfunc();
6951   if (ret == DRC_TEST_VAL)
6952     SysPrintf("test passed.\n");
6953   else
6954     SysPrintf("test failed: %08x\n", ret);
6955   out=(u_char *)BASE_ADDR;
6956   return ret == DRC_TEST_VAL;
6957 }
6958
6959 // clear the state completely, instead of just marking
6960 // things invalid like invalidate_all_pages() does
6961 void new_dynarec_clear_full()
6962 {
6963   int n;
6964   out=(u_char *)BASE_ADDR;
6965   memset(invalid_code,1,sizeof(invalid_code));
6966   memset(hash_table,0xff,sizeof(hash_table));
6967   memset(mini_ht,-1,sizeof(mini_ht));
6968   memset(restore_candidate,0,sizeof(restore_candidate));
6969   memset(shadow,0,sizeof(shadow));
6970   copy=shadow;
6971   expirep=16384; // Expiry pointer, +2 blocks
6972   pending_exception=0;
6973   literalcount=0;
6974   stop_after_jal=0;
6975   inv_code_start=inv_code_end=~0;
6976   // TLB
6977   for(n=0;n<4096;n++) ll_clear(jump_in+n);
6978   for(n=0;n<4096;n++) ll_clear(jump_out+n);
6979   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6980 }
6981
6982 void new_dynarec_init()
6983 {
6984   SysPrintf("Init new dynarec\n");
6985   out=(u_char *)BASE_ADDR;
6986 #if BASE_ADDR_FIXED
6987   if (mmap (out, 1<<TARGET_SIZE_2,
6988             PROT_READ | PROT_WRITE | PROT_EXEC,
6989             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
6990             -1, 0) <= 0) {
6991     SysPrintf("mmap() failed: %s\n", strerror(errno));
6992   }
6993 #else
6994   // not all systems allow execute in data segment by default
6995   if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
6996     SysPrintf("mprotect() failed: %s\n", strerror(errno));
6997 #endif
6998   cycle_multiplier=200;
6999   new_dynarec_clear_full();
7000 #ifdef HOST_IMM8
7001   // Copy this into local area so we don't have to put it in every literal pool
7002   invc_ptr=invalid_code;
7003 #endif
7004   arch_init();
7005   new_dynarec_test();
7006 #ifndef RAM_FIXED
7007   ram_offset=(u_int)rdram-0x80000000;
7008 #endif
7009   if (ram_offset!=0)
7010     SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
7011 }
7012
7013 void new_dynarec_cleanup()
7014 {
7015   int n;
7016   #if BASE_ADDR_FIXED
7017   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {SysPrintf("munmap() failed\n");}
7018   #endif
7019   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7020   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7021   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7022   #ifdef ROM_COPY
7023   if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
7024   #endif
7025 }
7026
7027 static u_int *get_source_start(u_int addr, u_int *limit)
7028 {
7029   if (addr < 0x00200000 ||
7030     (0xa0000000 <= addr && addr < 0xa0200000)) {
7031     // used for BIOS calls mostly?
7032     *limit = (addr&0xa0000000)|0x00200000;
7033     return (u_int *)((u_int)rdram + (addr&0x1fffff));
7034   }
7035   else if (!Config.HLE && (
7036     /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7037     (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7038     // BIOS
7039     *limit = (addr & 0xfff00000) | 0x80000;
7040     return (u_int *)((u_int)psxR + (addr&0x7ffff));
7041   }
7042   else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
7043     *limit = (addr & 0x80600000) + 0x00200000;
7044     return (u_int *)((u_int)rdram + (addr&0x1fffff));
7045   }
7046   return NULL;
7047 }
7048
7049 static u_int scan_for_ret(u_int addr)
7050 {
7051   u_int limit = 0;
7052   u_int *mem;
7053
7054   mem = get_source_start(addr, &limit);
7055   if (mem == NULL)
7056     return addr;
7057
7058   if (limit > addr + 0x1000)
7059     limit = addr + 0x1000;
7060   for (; addr < limit; addr += 4, mem++) {
7061     if (*mem == 0x03e00008) // jr $ra
7062       return addr + 8;
7063   }
7064   return addr;
7065 }
7066
7067 struct savestate_block {
7068   uint32_t addr;
7069   uint32_t regflags;
7070 };
7071
7072 static int addr_cmp(const void *p1_, const void *p2_)
7073 {
7074   const struct savestate_block *p1 = p1_, *p2 = p2_;
7075   return p1->addr - p2->addr;
7076 }
7077
7078 int new_dynarec_save_blocks(void *save, int size)
7079 {
7080   struct savestate_block *blocks = save;
7081   int maxcount = size / sizeof(blocks[0]);
7082   struct savestate_block tmp_blocks[1024];
7083   struct ll_entry *head;
7084   int p, s, d, o, bcnt;
7085   u_int addr;
7086
7087   o = 0;
7088   for (p = 0; p < sizeof(jump_in) / sizeof(jump_in[0]); p++) {
7089     bcnt = 0;
7090     for (head = jump_in[p]; head != NULL; head = head->next) {
7091       tmp_blocks[bcnt].addr = head->vaddr;
7092       tmp_blocks[bcnt].regflags = head->reg_sv_flags;
7093       bcnt++;
7094     }
7095     if (bcnt < 1)
7096       continue;
7097     qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
7098
7099     addr = tmp_blocks[0].addr;
7100     for (s = d = 0; s < bcnt; s++) {
7101       if (tmp_blocks[s].addr < addr)
7102         continue;
7103       if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
7104         tmp_blocks[d++] = tmp_blocks[s];
7105       addr = scan_for_ret(tmp_blocks[s].addr);
7106     }
7107
7108     if (o + d > maxcount)
7109       d = maxcount - o;
7110     memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
7111     o += d;
7112   }
7113
7114   return o * sizeof(blocks[0]);
7115 }
7116
7117 void new_dynarec_load_blocks(const void *save, int size)
7118 {
7119   const struct savestate_block *blocks = save;
7120   int count = size / sizeof(blocks[0]);
7121   u_int regs_save[32];
7122   uint32_t f;
7123   int i, b;
7124
7125   get_addr(psxRegs.pc);
7126
7127   // change GPRs for speculation to at least partially work..
7128   memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
7129   for (i = 1; i < 32; i++)
7130     psxRegs.GPR.r[i] = 0x80000000;
7131
7132   for (b = 0; b < count; b++) {
7133     for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7134       if (f & 1)
7135         psxRegs.GPR.r[i] = 0x1f800000;
7136     }
7137
7138     get_addr(blocks[b].addr);
7139
7140     for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7141       if (f & 1)
7142         psxRegs.GPR.r[i] = 0x80000000;
7143     }
7144   }
7145
7146   memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
7147 }
7148
7149 int new_recompile_block(int addr)
7150 {
7151   u_int pagelimit = 0;
7152   u_int state_rflags = 0;
7153   int i;
7154
7155   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7156   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7157   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7158   //if(debug)
7159   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7160   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7161   /*if(Count>=312978186) {
7162     rlist();
7163   }*/
7164   //rlist();
7165
7166   // this is just for speculation
7167   for (i = 1; i < 32; i++) {
7168     if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
7169       state_rflags |= 1 << i;
7170   }
7171
7172   start = (u_int)addr&~3;
7173   //assert(((u_int)addr&1)==0);
7174   new_dynarec_did_compile=1;
7175   if (Config.HLE && start == 0x80001000) // hlecall
7176   {
7177     // XXX: is this enough? Maybe check hleSoftCall?
7178     u_int beginning=(u_int)out;
7179     u_int page=get_page(start);
7180     invalid_code[start>>12]=0;
7181     emit_movimm(start,0);
7182     emit_writeword(0,(int)&pcaddr);
7183     emit_jmp((int)new_dyna_leave);
7184     literal_pool(0);
7185 #ifdef __arm__
7186     __clear_cache((void *)beginning,out);
7187 #endif
7188     ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
7189     return 0;
7190   }
7191
7192   source = get_source_start(start, &pagelimit);
7193   if (source == NULL) {
7194     SysPrintf("Compile at bogus memory address: %08x\n", addr);
7195     exit(1);
7196   }
7197
7198   /* Pass 1: disassemble */
7199   /* Pass 2: register dependencies, branch targets */
7200   /* Pass 3: register allocation */
7201   /* Pass 4: branch dependencies */
7202   /* Pass 5: pre-alloc */
7203   /* Pass 6: optimize clean/dirty state */
7204   /* Pass 7: flag 32-bit registers */
7205   /* Pass 8: assembly */
7206   /* Pass 9: linker */
7207   /* Pass 10: garbage collection / free memory */
7208
7209   int j;
7210   int done=0;
7211   unsigned int type,op,op2;
7212
7213   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7214
7215   /* Pass 1 disassembly */
7216
7217   for(i=0;!done;i++) {
7218     bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7219     minimum_free_regs[i]=0;
7220     opcode[i]=op=source[i]>>26;
7221     switch(op)
7222     {
7223       case 0x00: strcpy(insn[i],"special"); type=NI;
7224         op2=source[i]&0x3f;
7225         switch(op2)
7226         {
7227           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7228           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7229           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7230           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7231           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7232           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7233           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7234           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7235           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7236           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7237           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7238           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7239           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7240           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7241           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7242           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7243           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7244           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7245           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7246           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7247           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7248           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7249           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7250           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7251           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7252           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7253           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7254           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7255           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7256           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7257           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7258           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7259           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7260           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7261           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7262 #if 0
7263           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7264           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7265           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7266           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7267           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7268           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7269           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7270           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7271           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7272           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7273           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7274           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7275           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7276           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7277           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7278           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7279           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7280 #endif
7281         }
7282         break;
7283       case 0x01: strcpy(insn[i],"regimm"); type=NI;
7284         op2=(source[i]>>16)&0x1f;
7285         switch(op2)
7286         {
7287           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7288           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7289           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7290           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7291           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7292           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7293           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7294           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7295           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7296           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7297           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7298           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7299           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7300           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7301         }
7302         break;
7303       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7304       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7305       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7306       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7307       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7308       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7309       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7310       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7311       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7312       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7313       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7314       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7315       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7316       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7317       case 0x10: strcpy(insn[i],"cop0"); type=NI;
7318         op2=(source[i]>>21)&0x1f;
7319         switch(op2)
7320         {
7321           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7322           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7323           case 0x10: strcpy(insn[i],"tlb"); type=NI;
7324           switch(source[i]&0x3f)
7325           {
7326             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
7327             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
7328             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
7329             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
7330             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
7331             //case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
7332           }
7333         }
7334         break;
7335       case 0x11: strcpy(insn[i],"cop1"); type=NI;
7336         op2=(source[i]>>21)&0x1f;
7337         switch(op2)
7338         {
7339           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
7340           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
7341           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
7342           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
7343           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
7344           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
7345           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
7346           switch((source[i]>>16)&0x3)
7347           {
7348             case 0x00: strcpy(insn[i],"BC1F"); break;
7349             case 0x01: strcpy(insn[i],"BC1T"); break;
7350             case 0x02: strcpy(insn[i],"BC1FL"); break;
7351             case 0x03: strcpy(insn[i],"BC1TL"); break;
7352           }
7353           break;
7354           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
7355           switch(source[i]&0x3f)
7356           {
7357             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
7358             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
7359             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
7360             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
7361             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
7362             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
7363             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
7364             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
7365             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
7366             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
7367             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
7368             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
7369             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
7370             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
7371             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
7372             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
7373             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
7374             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
7375             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
7376             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
7377             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
7378             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
7379             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
7380             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
7381             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
7382             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
7383             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
7384             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
7385             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
7386             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
7387             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
7388             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
7389             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
7390             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
7391             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
7392           }
7393           break;
7394           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
7395           switch(source[i]&0x3f)
7396           {
7397             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
7398             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
7399             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
7400             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
7401             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
7402             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
7403             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
7404             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
7405             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
7406             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
7407             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
7408             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
7409             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
7410             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
7411             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
7412             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
7413             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
7414             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
7415             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
7416             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
7417             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
7418             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
7419             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
7420             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
7421             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
7422             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
7423             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
7424             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
7425             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
7426             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
7427             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
7428             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
7429             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
7430             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
7431             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
7432           }
7433           break;
7434           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
7435           switch(source[i]&0x3f)
7436           {
7437             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
7438             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
7439           }
7440           break;
7441           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
7442           switch(source[i]&0x3f)
7443           {
7444             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
7445             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
7446           }
7447           break;
7448         }
7449         break;
7450 #if 0
7451       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7452       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7453       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7454       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7455       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7456       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7457       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7458       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
7459 #endif
7460       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7461       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7462       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7463       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7464       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7465       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7466       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
7467 #if 0
7468       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
7469 #endif
7470       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
7471       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
7472       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
7473       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
7474 #if 0
7475       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
7476       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
7477 #endif
7478       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
7479       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
7480       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
7481       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
7482 #if 0
7483       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
7484       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
7485       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
7486 #endif
7487       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
7488       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
7489 #if 0
7490       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
7491       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
7492       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
7493 #endif
7494       case 0x12: strcpy(insn[i],"COP2"); type=NI;
7495         op2=(source[i]>>21)&0x1f;
7496         //if (op2 & 0x10) {
7497         if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
7498           if (gte_handlers[source[i]&0x3f]!=NULL) {
7499             if (gte_regnames[source[i]&0x3f]!=NULL)
7500               strcpy(insn[i],gte_regnames[source[i]&0x3f]);
7501             else
7502               snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
7503             type=C2OP;
7504           }
7505         }
7506         else switch(op2)
7507         {
7508           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
7509           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
7510           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
7511           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
7512         }
7513         break;
7514       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
7515       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
7516       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
7517       default: strcpy(insn[i],"???"); type=NI;
7518         SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
7519         break;
7520     }
7521     itype[i]=type;
7522     opcode2[i]=op2;
7523     /* Get registers/immediates */
7524     lt1[i]=0;
7525     us1[i]=0;
7526     us2[i]=0;
7527     dep1[i]=0;
7528     dep2[i]=0;
7529     gte_rs[i]=gte_rt[i]=0;
7530     switch(type) {
7531       case LOAD:
7532         rs1[i]=(source[i]>>21)&0x1f;
7533         rs2[i]=0;
7534         rt1[i]=(source[i]>>16)&0x1f;
7535         rt2[i]=0;
7536         imm[i]=(short)source[i];
7537         break;
7538       case STORE:
7539       case STORELR:
7540         rs1[i]=(source[i]>>21)&0x1f;
7541         rs2[i]=(source[i]>>16)&0x1f;
7542         rt1[i]=0;
7543         rt2[i]=0;
7544         imm[i]=(short)source[i];
7545         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
7546         break;
7547       case LOADLR:
7548         // LWL/LWR only load part of the register,
7549         // therefore the target register must be treated as a source too
7550         rs1[i]=(source[i]>>21)&0x1f;
7551         rs2[i]=(source[i]>>16)&0x1f;
7552         rt1[i]=(source[i]>>16)&0x1f;
7553         rt2[i]=0;
7554         imm[i]=(short)source[i];
7555         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
7556         if(op==0x26) dep1[i]=rt1[i]; // LWR
7557         break;
7558       case IMM16:
7559         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
7560         else rs1[i]=(source[i]>>21)&0x1f;
7561         rs2[i]=0;
7562         rt1[i]=(source[i]>>16)&0x1f;
7563         rt2[i]=0;
7564         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
7565           imm[i]=(unsigned short)source[i];
7566         }else{
7567           imm[i]=(short)source[i];
7568         }
7569         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
7570         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
7571         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
7572         break;
7573       case UJUMP:
7574         rs1[i]=0;
7575         rs2[i]=0;
7576         rt1[i]=0;
7577         rt2[i]=0;
7578         // The JAL instruction writes to r31.
7579         if (op&1) {
7580           rt1[i]=31;
7581         }
7582         rs2[i]=CCREG;
7583         break;
7584       case RJUMP:
7585         rs1[i]=(source[i]>>21)&0x1f;
7586         rs2[i]=0;
7587         rt1[i]=0;
7588         rt2[i]=0;
7589         // The JALR instruction writes to rd.
7590         if (op2&1) {
7591           rt1[i]=(source[i]>>11)&0x1f;
7592         }
7593         rs2[i]=CCREG;
7594         break;
7595       case CJUMP:
7596         rs1[i]=(source[i]>>21)&0x1f;
7597         rs2[i]=(source[i]>>16)&0x1f;
7598         rt1[i]=0;
7599         rt2[i]=0;
7600         if(op&2) { // BGTZ/BLEZ
7601           rs2[i]=0;
7602         }
7603         us1[i]=rs1[i];
7604         us2[i]=rs2[i];
7605         likely[i]=op>>4;
7606         break;
7607       case SJUMP:
7608         rs1[i]=(source[i]>>21)&0x1f;
7609         rs2[i]=CCREG;
7610         rt1[i]=0;
7611         rt2[i]=0;
7612         us1[i]=rs1[i];
7613         if(op2&0x10) { // BxxAL
7614           rt1[i]=31;
7615           // NOTE: If the branch is not taken, r31 is still overwritten
7616         }
7617         likely[i]=(op2&2)>>1;
7618         break;
7619       case FJUMP:
7620         rs1[i]=FSREG;
7621         rs2[i]=CSREG;
7622         rt1[i]=0;
7623         rt2[i]=0;
7624         likely[i]=((source[i])>>17)&1;
7625         break;
7626       case ALU:
7627         rs1[i]=(source[i]>>21)&0x1f; // source
7628         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
7629         rt1[i]=(source[i]>>11)&0x1f; // destination
7630         rt2[i]=0;
7631         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7632           us1[i]=rs1[i];us2[i]=rs2[i];
7633         }
7634         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7635           dep1[i]=rs1[i];dep2[i]=rs2[i];
7636         }
7637         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
7638           dep1[i]=rs1[i];dep2[i]=rs2[i];
7639         }
7640         break;
7641       case MULTDIV:
7642         rs1[i]=(source[i]>>21)&0x1f; // source
7643         rs2[i]=(source[i]>>16)&0x1f; // divisor
7644         rt1[i]=HIREG;
7645         rt2[i]=LOREG;
7646         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7647           us1[i]=rs1[i];us2[i]=rs2[i];
7648         }
7649         break;
7650       case MOV:
7651         rs1[i]=0;
7652         rs2[i]=0;
7653         rt1[i]=0;
7654         rt2[i]=0;
7655         if(op2==0x10) rs1[i]=HIREG; // MFHI
7656         if(op2==0x11) rt1[i]=HIREG; // MTHI
7657         if(op2==0x12) rs1[i]=LOREG; // MFLO
7658         if(op2==0x13) rt1[i]=LOREG; // MTLO
7659         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
7660         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
7661         dep1[i]=rs1[i];
7662         break;
7663       case SHIFT:
7664         rs1[i]=(source[i]>>16)&0x1f; // target of shift
7665         rs2[i]=(source[i]>>21)&0x1f; // shift amount
7666         rt1[i]=(source[i]>>11)&0x1f; // destination
7667         rt2[i]=0;
7668         // DSLLV/DSRLV/DSRAV are 64-bit
7669         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
7670         break;
7671       case SHIFTIMM:
7672         rs1[i]=(source[i]>>16)&0x1f;
7673         rs2[i]=0;
7674         rt1[i]=(source[i]>>11)&0x1f;
7675         rt2[i]=0;
7676         imm[i]=(source[i]>>6)&0x1f;
7677         // DSxx32 instructions
7678         if(op2>=0x3c) imm[i]|=0x20;
7679         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
7680         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
7681         break;
7682       case COP0:
7683         rs1[i]=0;
7684         rs2[i]=0;
7685         rt1[i]=0;
7686         rt2[i]=0;
7687         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
7688         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
7689         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
7690         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
7691         break;
7692       case COP1:
7693         rs1[i]=0;
7694         rs2[i]=0;
7695         rt1[i]=0;
7696         rt2[i]=0;
7697         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7698         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7699         if(op2==5) us1[i]=rs1[i]; // DMTC1
7700         rs2[i]=CSREG;
7701         break;
7702       case COP2:
7703         rs1[i]=0;
7704         rs2[i]=0;
7705         rt1[i]=0;
7706         rt2[i]=0;
7707         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
7708         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
7709         rs2[i]=CSREG;
7710         int gr=(source[i]>>11)&0x1F;
7711         switch(op2)
7712         {
7713           case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
7714           case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
7715           case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
7716           case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
7717         }
7718         break;
7719       case C1LS:
7720         rs1[i]=(source[i]>>21)&0x1F;
7721         rs2[i]=CSREG;
7722         rt1[i]=0;
7723         rt2[i]=0;
7724         imm[i]=(short)source[i];
7725         break;
7726       case C2LS:
7727         rs1[i]=(source[i]>>21)&0x1F;
7728         rs2[i]=0;
7729         rt1[i]=0;
7730         rt2[i]=0;
7731         imm[i]=(short)source[i];
7732         if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7733         else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7734         break;
7735       case C2OP:
7736         rs1[i]=0;
7737         rs2[i]=0;
7738         rt1[i]=0;
7739         rt2[i]=0;
7740         gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7741         gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7742         gte_rt[i]|=1ll<<63; // every op changes flags
7743         if((source[i]&0x3f)==GTE_MVMVA) {
7744           int v = (source[i] >> 15) & 3;
7745           gte_rs[i]&=~0xe3fll;
7746           if(v==3) gte_rs[i]|=0xe00ll;
7747           else gte_rs[i]|=3ll<<(v*2);
7748         }
7749         break;
7750       case FLOAT:
7751       case FCONV:
7752         rs1[i]=0;
7753         rs2[i]=CSREG;
7754         rt1[i]=0;
7755         rt2[i]=0;
7756         break;
7757       case FCOMP:
7758         rs1[i]=FSREG;
7759         rs2[i]=CSREG;
7760         rt1[i]=FSREG;
7761         rt2[i]=0;
7762         break;
7763       case SYSCALL:
7764       case HLECALL:
7765       case INTCALL:
7766         rs1[i]=CCREG;
7767         rs2[i]=0;
7768         rt1[i]=0;
7769         rt2[i]=0;
7770         break;
7771       default:
7772         rs1[i]=0;
7773         rs2[i]=0;
7774         rt1[i]=0;
7775         rt2[i]=0;
7776     }
7777     /* Calculate branch target addresses */
7778     if(type==UJUMP)
7779       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
7780     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
7781       ba[i]=start+i*4+8; // Ignore never taken branch
7782     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
7783       ba[i]=start+i*4+8; // Ignore never taken branch
7784     else if(type==CJUMP||type==SJUMP||type==FJUMP)
7785       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7786     else ba[i]=-1;
7787     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
7788       int do_in_intrp=0;
7789       // branch in delay slot?
7790       if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7791         // don't handle first branch and call interpreter if it's hit
7792         SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
7793         do_in_intrp=1;
7794       }
7795       // basic load delay detection
7796       else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
7797         int t=(ba[i-1]-start)/4;
7798         if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
7799           // jump target wants DS result - potential load delay effect
7800           SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
7801           do_in_intrp=1;
7802           bt[t+1]=1; // expected return from interpreter
7803         }
7804         else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
7805               !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
7806           // v0 overwrite like this is a sign of trouble, bail out
7807           SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
7808           do_in_intrp=1;
7809         }
7810       }
7811       if(do_in_intrp) {
7812         rs1[i-1]=CCREG;
7813         rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
7814         ba[i-1]=-1;
7815         itype[i-1]=INTCALL;
7816         done=2;
7817         i--; // don't compile the DS
7818       }
7819     }
7820     /* Is this the end of the block? */
7821     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
7822       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
7823         done=2;
7824       }
7825       else {
7826         if(stop_after_jal) done=1;
7827         // Stop on BREAK
7828         if((source[i+1]&0xfc00003f)==0x0d) done=1;
7829       }
7830       // Don't recompile stuff that's already compiled
7831       if(check_addr(start+i*4+4)) done=1;
7832       // Don't get too close to the limit
7833       if(i>MAXBLOCK/2) done=1;
7834     }
7835     if(itype[i]==SYSCALL&&stop_after_jal) done=1;
7836     if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
7837     if(done==2) {
7838       // Does the block continue due to a branch?
7839       for(j=i-1;j>=0;j--)
7840       {
7841         if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
7842         if(ba[j]==start+i*4+4) done=j=0;
7843         if(ba[j]==start+i*4+8) done=j=0;
7844       }
7845     }
7846     //assert(i<MAXBLOCK-1);
7847     if(start+i*4==pagelimit-4) done=1;
7848     assert(start+i*4<pagelimit);
7849     if (i==MAXBLOCK-1) done=1;
7850     // Stop if we're compiling junk
7851     if(itype[i]==NI&&opcode[i]==0x11) {
7852       done=stop_after_jal=1;
7853       SysPrintf("Disabled speculative precompilation\n");
7854     }
7855   }
7856   slen=i;
7857   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
7858     if(start+i*4==pagelimit) {
7859       itype[i-1]=SPAN;
7860     }
7861   }
7862   assert(slen>0);
7863
7864   /* Pass 2 - Register dependencies and branch targets */
7865
7866   unneeded_registers(0,slen-1,0);
7867
7868   /* Pass 3 - Register allocation */
7869
7870   struct regstat current; // Current register allocations/status
7871   current.is32=1;
7872   current.dirty=0;
7873   current.u=unneeded_reg[0];
7874   current.uu=unneeded_reg_upper[0];
7875   clear_all_regs(current.regmap);
7876   alloc_reg(&current,0,CCREG);
7877   dirty_reg(&current,CCREG);
7878   current.isconst=0;
7879   current.wasconst=0;
7880   current.waswritten=0;
7881   int ds=0;
7882   int cc=0;
7883   int hr=-1;
7884
7885   if((u_int)addr&1) {
7886     // First instruction is delay slot
7887     cc=-1;
7888     bt[1]=1;
7889     ds=1;
7890     unneeded_reg[0]=1;
7891     unneeded_reg_upper[0]=1;
7892     current.regmap[HOST_BTREG]=BTREG;
7893   }
7894
7895   for(i=0;i<slen;i++)
7896   {
7897     if(bt[i])
7898     {
7899       int hr;
7900       for(hr=0;hr<HOST_REGS;hr++)
7901       {
7902         // Is this really necessary?
7903         if(current.regmap[hr]==0) current.regmap[hr]=-1;
7904       }
7905       current.isconst=0;
7906       current.waswritten=0;
7907     }
7908     if(i>1)
7909     {
7910       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7911       {
7912         if(rs1[i-2]==0||rs2[i-2]==0)
7913         {
7914           if(rs1[i-2]) {
7915             current.is32|=1LL<<rs1[i-2];
7916             int hr=get_reg(current.regmap,rs1[i-2]|64);
7917             if(hr>=0) current.regmap[hr]=-1;
7918           }
7919           if(rs2[i-2]) {
7920             current.is32|=1LL<<rs2[i-2];
7921             int hr=get_reg(current.regmap,rs2[i-2]|64);
7922             if(hr>=0) current.regmap[hr]=-1;
7923           }
7924         }
7925       }
7926     }
7927     current.is32=-1LL;
7928
7929     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7930     regs[i].wasconst=current.isconst;
7931     regs[i].was32=current.is32;
7932     regs[i].wasdirty=current.dirty;
7933     regs[i].loadedconst=0;
7934     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
7935       if(i+1<slen) {
7936         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
7937         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
7938         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
7939         current.u|=1;
7940         current.uu|=1;
7941       } else {
7942         current.u=1;
7943         current.uu=1;
7944       }
7945     } else {
7946       if(i+1<slen) {
7947         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
7948         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
7949         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
7950         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
7951         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
7952         current.u|=1;
7953         current.uu|=1;
7954       } else { SysPrintf("oops, branch at end of block with no delay slot\n");exit(1); }
7955     }
7956     is_ds[i]=ds;
7957     if(ds) {
7958       ds=0; // Skip delay slot, already allocated as part of branch
7959       // ...but we need to alloc it in case something jumps here
7960       if(i+1<slen) {
7961         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
7962         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
7963       }else{
7964         current.u=branch_unneeded_reg[i-1];
7965         current.uu=branch_unneeded_reg_upper[i-1];
7966       }
7967       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
7968       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
7969       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
7970       current.u|=1;
7971       current.uu|=1;
7972       struct regstat temp;
7973       memcpy(&temp,&current,sizeof(current));
7974       temp.wasdirty=temp.dirty;
7975       temp.was32=temp.is32;
7976       // TODO: Take into account unconditional branches, as below
7977       delayslot_alloc(&temp,i);
7978       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7979       regs[i].wasdirty=temp.wasdirty;
7980       regs[i].was32=temp.was32;
7981       regs[i].dirty=temp.dirty;
7982       regs[i].is32=temp.is32;
7983       regs[i].isconst=0;
7984       regs[i].wasconst=0;
7985       current.isconst=0;
7986       // Create entry (branch target) regmap
7987       for(hr=0;hr<HOST_REGS;hr++)
7988       {
7989         int r=temp.regmap[hr];
7990         if(r>=0) {
7991           if(r!=regmap_pre[i][hr]) {
7992             regs[i].regmap_entry[hr]=-1;
7993           }
7994           else
7995           {
7996             if(r<64){
7997               if((current.u>>r)&1) {
7998                 regs[i].regmap_entry[hr]=-1;
7999                 regs[i].regmap[hr]=-1;
8000                 //Don't clear regs in the delay slot as the branch might need them
8001                 //current.regmap[hr]=-1;
8002               }else
8003                 regs[i].regmap_entry[hr]=r;
8004             }
8005             else {
8006               if((current.uu>>(r&63))&1) {
8007                 regs[i].regmap_entry[hr]=-1;
8008                 regs[i].regmap[hr]=-1;
8009                 //Don't clear regs in the delay slot as the branch might need them
8010                 //current.regmap[hr]=-1;
8011               }else
8012                 regs[i].regmap_entry[hr]=r;
8013             }
8014           }
8015         } else {
8016           // First instruction expects CCREG to be allocated
8017           if(i==0&&hr==HOST_CCREG)
8018             regs[i].regmap_entry[hr]=CCREG;
8019           else
8020             regs[i].regmap_entry[hr]=-1;
8021         }
8022       }
8023     }
8024     else { // Not delay slot
8025       switch(itype[i]) {
8026         case UJUMP:
8027           //current.isconst=0; // DEBUG
8028           //current.wasconst=0; // DEBUG
8029           //regs[i].wasconst=0; // DEBUG
8030           clear_const(&current,rt1[i]);
8031           alloc_cc(&current,i);
8032           dirty_reg(&current,CCREG);
8033           if (rt1[i]==31) {
8034             alloc_reg(&current,i,31);
8035             dirty_reg(&current,31);
8036             //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8037             //assert(rt1[i+1]!=rt1[i]);
8038             #ifdef REG_PREFETCH
8039             alloc_reg(&current,i,PTEMP);
8040             #endif
8041             //current.is32|=1LL<<rt1[i];
8042           }
8043           ooo[i]=1;
8044           delayslot_alloc(&current,i+1);
8045           //current.isconst=0; // DEBUG
8046           ds=1;
8047           //printf("i=%d, isconst=%x\n",i,current.isconst);
8048           break;
8049         case RJUMP:
8050           //current.isconst=0;
8051           //current.wasconst=0;
8052           //regs[i].wasconst=0;
8053           clear_const(&current,rs1[i]);
8054           clear_const(&current,rt1[i]);
8055           alloc_cc(&current,i);
8056           dirty_reg(&current,CCREG);
8057           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8058             alloc_reg(&current,i,rs1[i]);
8059             if (rt1[i]!=0) {
8060               alloc_reg(&current,i,rt1[i]);
8061               dirty_reg(&current,rt1[i]);
8062               assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
8063               assert(rt1[i+1]!=rt1[i]);
8064               #ifdef REG_PREFETCH
8065               alloc_reg(&current,i,PTEMP);
8066               #endif
8067             }
8068             #ifdef USE_MINI_HT
8069             if(rs1[i]==31) { // JALR
8070               alloc_reg(&current,i,RHASH);
8071               #ifndef HOST_IMM_ADDR32
8072               alloc_reg(&current,i,RHTBL);
8073               #endif
8074             }
8075             #endif
8076             delayslot_alloc(&current,i+1);
8077           } else {
8078             // The delay slot overwrites our source register,
8079             // allocate a temporary register to hold the old value.
8080             current.isconst=0;
8081             current.wasconst=0;
8082             regs[i].wasconst=0;
8083             delayslot_alloc(&current,i+1);
8084             current.isconst=0;
8085             alloc_reg(&current,i,RTEMP);
8086           }
8087           //current.isconst=0; // DEBUG
8088           ooo[i]=1;
8089           ds=1;
8090           break;
8091         case CJUMP:
8092           //current.isconst=0;
8093           //current.wasconst=0;
8094           //regs[i].wasconst=0;
8095           clear_const(&current,rs1[i]);
8096           clear_const(&current,rs2[i]);
8097           if((opcode[i]&0x3E)==4) // BEQ/BNE
8098           {
8099             alloc_cc(&current,i);
8100             dirty_reg(&current,CCREG);
8101             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8102             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8103             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8104             {
8105               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8106               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8107             }
8108             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8109                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8110               // The delay slot overwrites one of our conditions.
8111               // Allocate the branch condition registers instead.
8112               current.isconst=0;
8113               current.wasconst=0;
8114               regs[i].wasconst=0;
8115               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8116               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8117               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8118               {
8119                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8120                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8121               }
8122             }
8123             else
8124             {
8125               ooo[i]=1;
8126               delayslot_alloc(&current,i+1);
8127             }
8128           }
8129           else
8130           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8131           {
8132             alloc_cc(&current,i);
8133             dirty_reg(&current,CCREG);
8134             alloc_reg(&current,i,rs1[i]);
8135             if(!(current.is32>>rs1[i]&1))
8136             {
8137               alloc_reg64(&current,i,rs1[i]);
8138             }
8139             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8140               // The delay slot overwrites one of our conditions.
8141               // Allocate the branch condition registers instead.
8142               current.isconst=0;
8143               current.wasconst=0;
8144               regs[i].wasconst=0;
8145               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8146               if(!((current.is32>>rs1[i])&1))
8147               {
8148                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8149               }
8150             }
8151             else
8152             {
8153               ooo[i]=1;
8154               delayslot_alloc(&current,i+1);
8155             }
8156           }
8157           else
8158           // Don't alloc the delay slot yet because we might not execute it
8159           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8160           {
8161             current.isconst=0;
8162             current.wasconst=0;
8163             regs[i].wasconst=0;
8164             alloc_cc(&current,i);
8165             dirty_reg(&current,CCREG);
8166             alloc_reg(&current,i,rs1[i]);
8167             alloc_reg(&current,i,rs2[i]);
8168             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8169             {
8170               alloc_reg64(&current,i,rs1[i]);
8171               alloc_reg64(&current,i,rs2[i]);
8172             }
8173           }
8174           else
8175           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8176           {
8177             current.isconst=0;
8178             current.wasconst=0;
8179             regs[i].wasconst=0;
8180             alloc_cc(&current,i);
8181             dirty_reg(&current,CCREG);
8182             alloc_reg(&current,i,rs1[i]);
8183             if(!(current.is32>>rs1[i]&1))
8184             {
8185               alloc_reg64(&current,i,rs1[i]);
8186             }
8187           }
8188           ds=1;
8189           //current.isconst=0;
8190           break;
8191         case SJUMP:
8192           //current.isconst=0;
8193           //current.wasconst=0;
8194           //regs[i].wasconst=0;
8195           clear_const(&current,rs1[i]);
8196           clear_const(&current,rt1[i]);
8197           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8198           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8199           {
8200             alloc_cc(&current,i);
8201             dirty_reg(&current,CCREG);
8202             alloc_reg(&current,i,rs1[i]);
8203             if(!(current.is32>>rs1[i]&1))
8204             {
8205               alloc_reg64(&current,i,rs1[i]);
8206             }
8207             if (rt1[i]==31) { // BLTZAL/BGEZAL
8208               alloc_reg(&current,i,31);
8209               dirty_reg(&current,31);
8210               //#ifdef REG_PREFETCH
8211               //alloc_reg(&current,i,PTEMP);
8212               //#endif
8213               //current.is32|=1LL<<rt1[i];
8214             }
8215             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
8216                ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
8217               // Allocate the branch condition registers instead.
8218               current.isconst=0;
8219               current.wasconst=0;
8220               regs[i].wasconst=0;
8221               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8222               if(!((current.is32>>rs1[i])&1))
8223               {
8224                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8225               }
8226             }
8227             else
8228             {
8229               ooo[i]=1;
8230               delayslot_alloc(&current,i+1);
8231             }
8232           }
8233           else
8234           // Don't alloc the delay slot yet because we might not execute it
8235           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8236           {
8237             current.isconst=0;
8238             current.wasconst=0;
8239             regs[i].wasconst=0;
8240             alloc_cc(&current,i);
8241             dirty_reg(&current,CCREG);
8242             alloc_reg(&current,i,rs1[i]);
8243             if(!(current.is32>>rs1[i]&1))
8244             {
8245               alloc_reg64(&current,i,rs1[i]);
8246             }
8247           }
8248           ds=1;
8249           //current.isconst=0;
8250           break;
8251         case FJUMP:
8252           current.isconst=0;
8253           current.wasconst=0;
8254           regs[i].wasconst=0;
8255           if(likely[i]==0) // BC1F/BC1T
8256           {
8257             // TODO: Theoretically we can run out of registers here on x86.
8258             // The delay slot can allocate up to six, and we need to check
8259             // CSREG before executing the delay slot.  Possibly we can drop
8260             // the cycle count and then reload it after checking that the
8261             // FPU is in a usable state, or don't do out-of-order execution.
8262             alloc_cc(&current,i);
8263             dirty_reg(&current,CCREG);
8264             alloc_reg(&current,i,FSREG);
8265             alloc_reg(&current,i,CSREG);
8266             if(itype[i+1]==FCOMP) {
8267               // The delay slot overwrites the branch condition.
8268               // Allocate the branch condition registers instead.
8269               alloc_cc(&current,i);
8270               dirty_reg(&current,CCREG);
8271               alloc_reg(&current,i,CSREG);
8272               alloc_reg(&current,i,FSREG);
8273             }
8274             else {
8275               ooo[i]=1;
8276               delayslot_alloc(&current,i+1);
8277               alloc_reg(&current,i+1,CSREG);
8278             }
8279           }
8280           else
8281           // Don't alloc the delay slot yet because we might not execute it
8282           if(likely[i]) // BC1FL/BC1TL
8283           {
8284             alloc_cc(&current,i);
8285             dirty_reg(&current,CCREG);
8286             alloc_reg(&current,i,CSREG);
8287             alloc_reg(&current,i,FSREG);
8288           }
8289           ds=1;
8290           current.isconst=0;
8291           break;
8292         case IMM16:
8293           imm16_alloc(&current,i);
8294           break;
8295         case LOAD:
8296         case LOADLR:
8297           load_alloc(&current,i);
8298           break;
8299         case STORE:
8300         case STORELR:
8301           store_alloc(&current,i);
8302           break;
8303         case ALU:
8304           alu_alloc(&current,i);
8305           break;
8306         case SHIFT:
8307           shift_alloc(&current,i);
8308           break;
8309         case MULTDIV:
8310           multdiv_alloc(&current,i);
8311           break;
8312         case SHIFTIMM:
8313           shiftimm_alloc(&current,i);
8314           break;
8315         case MOV:
8316           mov_alloc(&current,i);
8317           break;
8318         case COP0:
8319           cop0_alloc(&current,i);
8320           break;
8321         case COP1:
8322         case COP2:
8323           cop1_alloc(&current,i);
8324           break;
8325         case C1LS:
8326           c1ls_alloc(&current,i);
8327           break;
8328         case C2LS:
8329           c2ls_alloc(&current,i);
8330           break;
8331         case C2OP:
8332           c2op_alloc(&current,i);
8333           break;
8334         case FCONV:
8335           fconv_alloc(&current,i);
8336           break;
8337         case FLOAT:
8338           float_alloc(&current,i);
8339           break;
8340         case FCOMP:
8341           fcomp_alloc(&current,i);
8342           break;
8343         case SYSCALL:
8344         case HLECALL:
8345         case INTCALL:
8346           syscall_alloc(&current,i);
8347           break;
8348         case SPAN:
8349           pagespan_alloc(&current,i);
8350           break;
8351       }
8352
8353       // Drop the upper half of registers that have become 32-bit
8354       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
8355       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8356         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8357         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8358         current.uu|=1;
8359       } else {
8360         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
8361         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8362         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8363         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8364         current.uu|=1;
8365       }
8366
8367       // Create entry (branch target) regmap
8368       for(hr=0;hr<HOST_REGS;hr++)
8369       {
8370         int r,or;
8371         r=current.regmap[hr];
8372         if(r>=0) {
8373           if(r!=regmap_pre[i][hr]) {
8374             // TODO: delay slot (?)
8375             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
8376             if(or<0||(r&63)>=TEMPREG){
8377               regs[i].regmap_entry[hr]=-1;
8378             }
8379             else
8380             {
8381               // Just move it to a different register
8382               regs[i].regmap_entry[hr]=r;
8383               // If it was dirty before, it's still dirty
8384               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
8385             }
8386           }
8387           else
8388           {
8389             // Unneeded
8390             if(r==0){
8391               regs[i].regmap_entry[hr]=0;
8392             }
8393             else
8394             if(r<64){
8395               if((current.u>>r)&1) {
8396                 regs[i].regmap_entry[hr]=-1;
8397                 //regs[i].regmap[hr]=-1;
8398                 current.regmap[hr]=-1;
8399               }else
8400                 regs[i].regmap_entry[hr]=r;
8401             }
8402             else {
8403               if((current.uu>>(r&63))&1) {
8404                 regs[i].regmap_entry[hr]=-1;
8405                 //regs[i].regmap[hr]=-1;
8406                 current.regmap[hr]=-1;
8407               }else
8408                 regs[i].regmap_entry[hr]=r;
8409             }
8410           }
8411         } else {
8412           // Branches expect CCREG to be allocated at the target
8413           if(regmap_pre[i][hr]==CCREG)
8414             regs[i].regmap_entry[hr]=CCREG;
8415           else
8416             regs[i].regmap_entry[hr]=-1;
8417         }
8418       }
8419       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8420     }
8421
8422     if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
8423       current.waswritten|=1<<rs1[i-1];
8424     current.waswritten&=~(1<<rt1[i]);
8425     current.waswritten&=~(1<<rt2[i]);
8426     if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
8427       current.waswritten&=~(1<<rs1[i]);
8428
8429     /* Branch post-alloc */
8430     if(i>0)
8431     {
8432       current.was32=current.is32;
8433       current.wasdirty=current.dirty;
8434       switch(itype[i-1]) {
8435         case UJUMP:
8436           memcpy(&branch_regs[i-1],&current,sizeof(current));
8437           branch_regs[i-1].isconst=0;
8438           branch_regs[i-1].wasconst=0;
8439           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8440           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8441           alloc_cc(&branch_regs[i-1],i-1);
8442           dirty_reg(&branch_regs[i-1],CCREG);
8443           if(rt1[i-1]==31) { // JAL
8444             alloc_reg(&branch_regs[i-1],i-1,31);
8445             dirty_reg(&branch_regs[i-1],31);
8446             branch_regs[i-1].is32|=1LL<<31;
8447           }
8448           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8449           memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
8450           break;
8451         case RJUMP:
8452           memcpy(&branch_regs[i-1],&current,sizeof(current));
8453           branch_regs[i-1].isconst=0;
8454           branch_regs[i-1].wasconst=0;
8455           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8456           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8457           alloc_cc(&branch_regs[i-1],i-1);
8458           dirty_reg(&branch_regs[i-1],CCREG);
8459           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
8460           if(rt1[i-1]!=0) { // JALR
8461             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
8462             dirty_reg(&branch_regs[i-1],rt1[i-1]);
8463             branch_regs[i-1].is32|=1LL<<rt1[i-1];
8464           }
8465           #ifdef USE_MINI_HT
8466           if(rs1[i-1]==31) { // JALR
8467             alloc_reg(&branch_regs[i-1],i-1,RHASH);
8468             #ifndef HOST_IMM_ADDR32
8469             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
8470             #endif
8471           }
8472           #endif
8473           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8474           memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
8475           break;
8476         case CJUMP:
8477           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
8478           {
8479             alloc_cc(&current,i-1);
8480             dirty_reg(&current,CCREG);
8481             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
8482                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
8483               // The delay slot overwrote one of our conditions
8484               // Delay slot goes after the test (in order)
8485               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8486               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8487               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8488               current.u|=1;
8489               current.uu|=1;
8490               delayslot_alloc(&current,i);
8491               current.isconst=0;
8492             }
8493             else
8494             {
8495               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8496               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8497               // Alloc the branch condition registers
8498               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
8499               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
8500               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
8501               {
8502                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
8503                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
8504               }
8505             }
8506             memcpy(&branch_regs[i-1],&current,sizeof(current));
8507             branch_regs[i-1].isconst=0;
8508             branch_regs[i-1].wasconst=0;
8509             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
8510             memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
8511           }
8512           else
8513           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
8514           {
8515             alloc_cc(&current,i-1);
8516             dirty_reg(&current,CCREG);
8517             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
8518               // The delay slot overwrote the branch condition
8519               // Delay slot goes after the test (in order)
8520               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8521               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8522               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8523               current.u|=1;
8524               current.uu|=1;
8525               delayslot_alloc(&current,i);
8526               current.isconst=0;
8527             }
8528             else
8529             {
8530               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
8531               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
8532               // Alloc the branch condition register
8533               alloc_reg(&current,i-1,rs1[i-1]);
8534               if(!(current.is32>>rs1[i-1]&1))
8535               {
8536                 alloc_reg64(&current,i-1,rs1[i-1]);
8537               }
8538             }
8539             memcpy(&branch_regs[i-1],&current,sizeof(current));
8540             branch_regs[i-1].isconst=0;
8541             branch_regs[i-1].wasconst=0;
8542             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
8543             memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
8544           }
8545           else
8546           // Alloc the delay slot in case the branch is taken
8547           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
8548           {
8549             memcpy(&branch_regs[i-1],&current,sizeof(current));
8550             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8551             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8552             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8553             alloc_cc(&branch_regs[i-1],i);
8554             dirty_reg(&branch_regs[i-1],CCREG);
8555             delayslot_alloc(&branch_regs[i-1],i);
8556             branch_regs[i-1].isconst=0;
8557             alloc_reg(&current,i,CCREG); // Not taken path
8558             dirty_reg(&current,CCREG);
8559             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8560           }
8561           else
8562           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
8563           {
8564             memcpy(&branch_regs[i-1],&current,sizeof(current));
8565             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8566             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8567             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8568             alloc_cc(&branch_regs[i-1],i);
8569             dirty_reg(&branch_regs[i-1],CCREG);
8570             delayslot_alloc(&branch_regs[i-1],i);
8571             branch_regs[i-1].isconst=0;
8572             alloc_reg(&current,i,CCREG); // Not taken path
8573             dirty_reg(&current,CCREG);
8574             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8575           }
8576           break;
8577         case SJUMP:
8578           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
8579           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
8580           {
8581             alloc_cc(&current,i-1);
8582             dirty_reg(&current,CCREG);
8583             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
8584               // The delay slot overwrote the branch condition
8585               // Delay slot goes after the test (in order)
8586               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8587               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8588               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8589               current.u|=1;
8590               current.uu|=1;
8591               delayslot_alloc(&current,i);
8592               current.isconst=0;
8593             }
8594             else
8595             {
8596               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
8597               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
8598               // Alloc the branch condition register
8599               alloc_reg(&current,i-1,rs1[i-1]);
8600               if(!(current.is32>>rs1[i-1]&1))
8601               {
8602                 alloc_reg64(&current,i-1,rs1[i-1]);
8603               }
8604             }
8605             memcpy(&branch_regs[i-1],&current,sizeof(current));
8606             branch_regs[i-1].isconst=0;
8607             branch_regs[i-1].wasconst=0;
8608             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
8609             memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
8610           }
8611           else
8612           // Alloc the delay slot in case the branch is taken
8613           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
8614           {
8615             memcpy(&branch_regs[i-1],&current,sizeof(current));
8616             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8617             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8618             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8619             alloc_cc(&branch_regs[i-1],i);
8620             dirty_reg(&branch_regs[i-1],CCREG);
8621             delayslot_alloc(&branch_regs[i-1],i);
8622             branch_regs[i-1].isconst=0;
8623             alloc_reg(&current,i,CCREG); // Not taken path
8624             dirty_reg(&current,CCREG);
8625             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8626           }
8627           // FIXME: BLTZAL/BGEZAL
8628           if(opcode2[i-1]&0x10) { // BxxZAL
8629             alloc_reg(&branch_regs[i-1],i-1,31);
8630             dirty_reg(&branch_regs[i-1],31);
8631             branch_regs[i-1].is32|=1LL<<31;
8632           }
8633           break;
8634         case FJUMP:
8635           if(likely[i-1]==0) // BC1F/BC1T
8636           {
8637             alloc_cc(&current,i-1);
8638             dirty_reg(&current,CCREG);
8639             if(itype[i]==FCOMP) {
8640               // The delay slot overwrote the branch condition
8641               // Delay slot goes after the test (in order)
8642               delayslot_alloc(&current,i);
8643               current.isconst=0;
8644             }
8645             else
8646             {
8647               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
8648               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
8649               // Alloc the branch condition register
8650               alloc_reg(&current,i-1,FSREG);
8651             }
8652             memcpy(&branch_regs[i-1],&current,sizeof(current));
8653             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
8654           }
8655           else // BC1FL/BC1TL
8656           {
8657             // Alloc the delay slot in case the branch is taken
8658             memcpy(&branch_regs[i-1],&current,sizeof(current));
8659             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8660             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8661             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8662             alloc_cc(&branch_regs[i-1],i);
8663             dirty_reg(&branch_regs[i-1],CCREG);
8664             delayslot_alloc(&branch_regs[i-1],i);
8665             branch_regs[i-1].isconst=0;
8666             alloc_reg(&current,i,CCREG); // Not taken path
8667             dirty_reg(&current,CCREG);
8668             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8669           }
8670           break;
8671       }
8672
8673       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
8674       {
8675         if(rt1[i-1]==31) // JAL/JALR
8676         {
8677           // Subroutine call will return here, don't alloc any registers
8678           current.is32=1;
8679           current.dirty=0;
8680           clear_all_regs(current.regmap);
8681           alloc_reg(&current,i,CCREG);
8682           dirty_reg(&current,CCREG);
8683         }
8684         else if(i+1<slen)
8685         {
8686           // Internal branch will jump here, match registers to caller
8687           current.is32=0x3FFFFFFFFLL;
8688           current.dirty=0;
8689           clear_all_regs(current.regmap);
8690           alloc_reg(&current,i,CCREG);
8691           dirty_reg(&current,CCREG);
8692           for(j=i-1;j>=0;j--)
8693           {
8694             if(ba[j]==start+i*4+4) {
8695               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
8696               current.is32=branch_regs[j].is32;
8697               current.dirty=branch_regs[j].dirty;
8698               break;
8699             }
8700           }
8701           while(j>=0) {
8702             if(ba[j]==start+i*4+4) {
8703               for(hr=0;hr<HOST_REGS;hr++) {
8704                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
8705                   current.regmap[hr]=-1;
8706                 }
8707                 current.is32&=branch_regs[j].is32;
8708                 current.dirty&=branch_regs[j].dirty;
8709               }
8710             }
8711             j--;
8712           }
8713         }
8714       }
8715     }
8716
8717     // Count cycles in between branches
8718     ccadj[i]=cc;
8719     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
8720     {
8721       cc=0;
8722     }
8723 #if !defined(DRC_DBG)
8724     else if(itype[i]==C2OP&&gte_cycletab[source[i]&0x3f]>2)
8725     {
8726       // GTE runs in parallel until accessed, divide by 2 for a rough guess
8727       cc+=gte_cycletab[source[i]&0x3f]/2;
8728     }
8729     else if(/*itype[i]==LOAD||itype[i]==STORE||*/itype[i]==C1LS) // load,store causes weird timing issues
8730     {
8731       cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
8732     }
8733     else if(i>1&&itype[i]==STORE&&itype[i-1]==STORE&&itype[i-2]==STORE&&!bt[i])
8734     {
8735       cc+=4;
8736     }
8737     else if(itype[i]==C2LS)
8738     {
8739       cc+=4;
8740     }
8741 #endif
8742     else
8743     {
8744       cc++;
8745     }
8746
8747     flush_dirty_uppers(&current);
8748     if(!is_ds[i]) {
8749       regs[i].is32=current.is32;
8750       regs[i].dirty=current.dirty;
8751       regs[i].isconst=current.isconst;
8752       memcpy(constmap[i],current_constmap,sizeof(current_constmap));
8753     }
8754     for(hr=0;hr<HOST_REGS;hr++) {
8755       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
8756         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
8757           regs[i].wasconst&=~(1<<hr);
8758         }
8759       }
8760     }
8761     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
8762     regs[i].waswritten=current.waswritten;
8763   }
8764
8765   /* Pass 4 - Cull unused host registers */
8766
8767   uint64_t nr=0;
8768
8769   for (i=slen-1;i>=0;i--)
8770   {
8771     int hr;
8772     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
8773     {
8774       if(ba[i]<start || ba[i]>=(start+slen*4))
8775       {
8776         // Branch out of this block, don't need anything
8777         nr=0;
8778       }
8779       else
8780       {
8781         // Internal branch
8782         // Need whatever matches the target
8783         nr=0;
8784         int t=(ba[i]-start)>>2;
8785         for(hr=0;hr<HOST_REGS;hr++)
8786         {
8787           if(regs[i].regmap_entry[hr]>=0) {
8788             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
8789           }
8790         }
8791       }
8792       // Conditional branch may need registers for following instructions
8793       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
8794       {
8795         if(i<slen-2) {
8796           nr|=needed_reg[i+2];
8797           for(hr=0;hr<HOST_REGS;hr++)
8798           {
8799             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
8800             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
8801           }
8802         }
8803       }
8804       // Don't need stuff which is overwritten
8805       //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8806       //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8807       // Merge in delay slot
8808       for(hr=0;hr<HOST_REGS;hr++)
8809       {
8810         if(!likely[i]) {
8811           // These are overwritten unless the branch is "likely"
8812           // and the delay slot is nullified if not taken
8813           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8814           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8815         }
8816         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8817         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8818         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
8819         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
8820         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8821         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8822         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
8823         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
8824         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
8825           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8826           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8827         }
8828         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
8829           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8830           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8831         }
8832         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
8833           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8834           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8835         }
8836       }
8837     }
8838     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
8839     {
8840       // SYSCALL instruction (software interrupt)
8841       nr=0;
8842     }
8843     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
8844     {
8845       // ERET instruction (return from interrupt)
8846       nr=0;
8847     }
8848     else // Non-branch
8849     {
8850       if(i<slen-1) {
8851         for(hr=0;hr<HOST_REGS;hr++) {
8852           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
8853           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
8854           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8855           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8856         }
8857       }
8858     }
8859     for(hr=0;hr<HOST_REGS;hr++)
8860     {
8861       // Overwritten registers are not needed
8862       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8863       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8864       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8865       // Source registers are needed
8866       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8867       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8868       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
8869       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
8870       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8871       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8872       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
8873       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
8874       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
8875         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8876         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8877       }
8878       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
8879         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8880         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8881       }
8882       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
8883         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8884         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8885       }
8886       // Don't store a register immediately after writing it,
8887       // may prevent dual-issue.
8888       // But do so if this is a branch target, otherwise we
8889       // might have to load the register before the branch.
8890       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
8891         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
8892            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
8893           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8894           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8895         }
8896         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
8897            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
8898           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8899           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8900         }
8901       }
8902     }
8903     // Cycle count is needed at branches.  Assume it is needed at the target too.
8904     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
8905       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8906       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8907     }
8908     // Save it
8909     needed_reg[i]=nr;
8910
8911     // Deallocate unneeded registers
8912     for(hr=0;hr<HOST_REGS;hr++)
8913     {
8914       if(!((nr>>hr)&1)) {
8915         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
8916         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
8917            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
8918            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
8919         {
8920           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
8921           {
8922             if(likely[i]) {
8923               regs[i].regmap[hr]=-1;
8924               regs[i].isconst&=~(1<<hr);
8925               if(i<slen-2) {
8926                 regmap_pre[i+2][hr]=-1;
8927                 regs[i+2].wasconst&=~(1<<hr);
8928               }
8929             }
8930           }
8931         }
8932         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
8933         {
8934           int d1=0,d2=0,map=0,temp=0;
8935           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
8936           {
8937             d1=dep1[i+1];
8938             d2=dep2[i+1];
8939           }
8940           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
8941              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
8942             map=INVCP;
8943           }
8944           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
8945              itype[i+1]==C1LS || itype[i+1]==C2LS)
8946             temp=FTEMP;
8947           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
8948              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
8949              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
8950              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
8951              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
8952              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
8953              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
8954              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
8955              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
8956              regs[i].regmap[hr]!=map )
8957           {
8958             regs[i].regmap[hr]=-1;
8959             regs[i].isconst&=~(1<<hr);
8960             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
8961                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
8962                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
8963                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
8964                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
8965                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
8966                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
8967                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8968                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
8969                branch_regs[i].regmap[hr]!=map)
8970             {
8971               branch_regs[i].regmap[hr]=-1;
8972               branch_regs[i].regmap_entry[hr]=-1;
8973               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
8974               {
8975                 if(!likely[i]&&i<slen-2) {
8976                   regmap_pre[i+2][hr]=-1;
8977                   regs[i+2].wasconst&=~(1<<hr);
8978                 }
8979               }
8980             }
8981           }
8982         }
8983         else
8984         {
8985           // Non-branch
8986           if(i>0)
8987           {
8988             int d1=0,d2=0,map=-1,temp=-1;
8989             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
8990             {
8991               d1=dep1[i];
8992               d2=dep2[i];
8993             }
8994             if(itype[i]==STORE || itype[i]==STORELR ||
8995                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
8996               map=INVCP;
8997             }
8998             if(itype[i]==LOADLR || itype[i]==STORELR ||
8999                itype[i]==C1LS || itype[i]==C2LS)
9000               temp=FTEMP;
9001             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9002                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9003                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9004                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9005                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9006                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9007             {
9008               if(i<slen-1&&!is_ds[i]) {
9009                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9010                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9011                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9012                 {
9013                   SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9014                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9015                 }
9016                 regmap_pre[i+1][hr]=-1;
9017                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9018                 regs[i+1].wasconst&=~(1<<hr);
9019               }
9020               regs[i].regmap[hr]=-1;
9021               regs[i].isconst&=~(1<<hr);
9022             }
9023           }
9024         }
9025       }
9026     }
9027   }
9028
9029   /* Pass 5 - Pre-allocate registers */
9030
9031   // If a register is allocated during a loop, try to allocate it for the
9032   // entire loop, if possible.  This avoids loading/storing registers
9033   // inside of the loop.
9034
9035   signed char f_regmap[HOST_REGS];
9036   clear_all_regs(f_regmap);
9037   for(i=0;i<slen-1;i++)
9038   {
9039     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9040     {
9041       if(ba[i]>=start && ba[i]<(start+i*4))
9042       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9043       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9044       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9045       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9046       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9047       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9048       {
9049         int t=(ba[i]-start)>>2;
9050         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9051         if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
9052         for(hr=0;hr<HOST_REGS;hr++)
9053         {
9054           if(regs[i].regmap[hr]>64) {
9055             if(!((regs[i].dirty>>hr)&1))
9056               f_regmap[hr]=regs[i].regmap[hr];
9057             else f_regmap[hr]=-1;
9058           }
9059           else if(regs[i].regmap[hr]>=0) {
9060             if(f_regmap[hr]!=regs[i].regmap[hr]) {
9061               // dealloc old register
9062               int n;
9063               for(n=0;n<HOST_REGS;n++)
9064               {
9065                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9066               }
9067               // and alloc new one
9068               f_regmap[hr]=regs[i].regmap[hr];
9069             }
9070           }
9071           if(branch_regs[i].regmap[hr]>64) {
9072             if(!((branch_regs[i].dirty>>hr)&1))
9073               f_regmap[hr]=branch_regs[i].regmap[hr];
9074             else f_regmap[hr]=-1;
9075           }
9076           else if(branch_regs[i].regmap[hr]>=0) {
9077             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9078               // dealloc old register
9079               int n;
9080               for(n=0;n<HOST_REGS;n++)
9081               {
9082                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9083               }
9084               // and alloc new one
9085               f_regmap[hr]=branch_regs[i].regmap[hr];
9086             }
9087           }
9088           if(ooo[i]) {
9089             if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9090               f_regmap[hr]=branch_regs[i].regmap[hr];
9091           }else{
9092             if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
9093               f_regmap[hr]=branch_regs[i].regmap[hr];
9094           }
9095           // Avoid dirty->clean transition
9096           #ifdef DESTRUCTIVE_WRITEBACK
9097           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9098           #endif
9099           // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9100           // case above, however it's always a good idea.  We can't hoist the
9101           // load if the register was already allocated, so there's no point
9102           // wasting time analyzing most of these cases.  It only "succeeds"
9103           // when the mapping was different and the load can be replaced with
9104           // a mov, which is of negligible benefit.  So such cases are
9105           // skipped below.
9106           if(f_regmap[hr]>0) {
9107             if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
9108               int r=f_regmap[hr];
9109               for(j=t;j<=i;j++)
9110               {
9111                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9112                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9113                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9114                 if(r>63) {
9115                   // NB This can exclude the case where the upper-half
9116                   // register is lower numbered than the lower-half
9117                   // register.  Not sure if it's worth fixing...
9118                   if(get_reg(regs[j].regmap,r&63)<0) break;
9119                   if(get_reg(regs[j].regmap_entry,r&63)<0) break;
9120                   if(regs[j].is32&(1LL<<(r&63))) break;
9121                 }
9122                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9123                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9124                   int k;
9125                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9126                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9127                     if(r>63) {
9128                       if(get_reg(regs[i].regmap,r&63)<0) break;
9129                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9130                     }
9131                     k=i;
9132                     while(k>1&&regs[k-1].regmap[hr]==-1) {
9133                       if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9134                         //printf("no free regs for store %x\n",start+(k-1)*4);
9135                         break;
9136                       }
9137                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9138                         //printf("no-match due to different register\n");
9139                         break;
9140                       }
9141                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9142                         //printf("no-match due to branch\n");
9143                         break;
9144                       }
9145                       // call/ret fast path assumes no registers allocated
9146                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
9147                         break;
9148                       }
9149                       if(r>63) {
9150                         // NB This can exclude the case where the upper-half
9151                         // register is lower numbered than the lower-half
9152                         // register.  Not sure if it's worth fixing...
9153                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
9154                         if(regs[k-1].is32&(1LL<<(r&63))) break;
9155                       }
9156                       k--;
9157                     }
9158                     if(i<slen-1) {
9159                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9160                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9161                         //printf("bad match after branch\n");
9162                         break;
9163                       }
9164                     }
9165                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
9166                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
9167                       while(k<i) {
9168                         regs[k].regmap_entry[hr]=f_regmap[hr];
9169                         regs[k].regmap[hr]=f_regmap[hr];
9170                         regmap_pre[k+1][hr]=f_regmap[hr];
9171                         regs[k].wasdirty&=~(1<<hr);
9172                         regs[k].dirty&=~(1<<hr);
9173                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
9174                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
9175                         regs[k].wasconst&=~(1<<hr);
9176                         regs[k].isconst&=~(1<<hr);
9177                         k++;
9178                       }
9179                     }
9180                     else {
9181                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9182                       break;
9183                     }
9184                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9185                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
9186                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
9187                       regs[i].regmap_entry[hr]=f_regmap[hr];
9188                       regs[i].regmap[hr]=f_regmap[hr];
9189                       regs[i].wasdirty&=~(1<<hr);
9190                       regs[i].dirty&=~(1<<hr);
9191                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
9192                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
9193                       regs[i].wasconst&=~(1<<hr);
9194                       regs[i].isconst&=~(1<<hr);
9195                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9196                       branch_regs[i].wasdirty&=~(1<<hr);
9197                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
9198                       branch_regs[i].regmap[hr]=f_regmap[hr];
9199                       branch_regs[i].dirty&=~(1<<hr);
9200                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
9201                       branch_regs[i].wasconst&=~(1<<hr);
9202                       branch_regs[i].isconst&=~(1<<hr);
9203                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9204                         regmap_pre[i+2][hr]=f_regmap[hr];
9205                         regs[i+2].wasdirty&=~(1<<hr);
9206                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
9207                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9208                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
9209                       }
9210                     }
9211                   }
9212                   for(k=t;k<j;k++) {
9213                     // Alloc register clean at beginning of loop,
9214                     // but may dirty it in pass 6
9215                     regs[k].regmap_entry[hr]=f_regmap[hr];
9216                     regs[k].regmap[hr]=f_regmap[hr];
9217                     regs[k].dirty&=~(1<<hr);
9218                     regs[k].wasconst&=~(1<<hr);
9219                     regs[k].isconst&=~(1<<hr);
9220                     if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
9221                       branch_regs[k].regmap_entry[hr]=f_regmap[hr];
9222                       branch_regs[k].regmap[hr]=f_regmap[hr];
9223                       branch_regs[k].dirty&=~(1<<hr);
9224                       branch_regs[k].wasconst&=~(1<<hr);
9225                       branch_regs[k].isconst&=~(1<<hr);
9226                       if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
9227                         regmap_pre[k+2][hr]=f_regmap[hr];
9228                         regs[k+2].wasdirty&=~(1<<hr);
9229                         assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
9230                           (regs[k+2].was32&(1LL<<f_regmap[hr])));
9231                       }
9232                     }
9233                     else
9234                     {
9235                       regmap_pre[k+1][hr]=f_regmap[hr];
9236                       regs[k+1].wasdirty&=~(1<<hr);
9237                     }
9238                   }
9239                   if(regs[j].regmap[hr]==f_regmap[hr])
9240                     regs[j].regmap_entry[hr]=f_regmap[hr];
9241                   break;
9242                 }
9243                 if(j==i) break;
9244                 if(regs[j].regmap[hr]>=0)
9245                   break;
9246                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9247                   //printf("no-match due to different register\n");
9248                   break;
9249                 }
9250                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9251                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9252                   break;
9253                 }
9254                 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
9255                 {
9256                   // Stop on unconditional branch
9257                   break;
9258                 }
9259                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
9260                 {
9261                   if(ooo[j]) {
9262                     if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
9263                       break;
9264                   }else{
9265                     if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
9266                       break;
9267                   }
9268                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
9269                     //printf("no-match due to different register (branch)\n");
9270                     break;
9271                   }
9272                 }
9273                 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
9274                   //printf("No free regs for store %x\n",start+j*4);
9275                   break;
9276                 }
9277                 if(f_regmap[hr]>=64) {
9278                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
9279                     break;
9280                   }
9281                   else
9282                   {
9283                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
9284                       break;
9285                     }
9286                   }
9287                 }
9288               }
9289             }
9290           }
9291         }
9292       }
9293     }else{
9294       // Non branch or undetermined branch target
9295       for(hr=0;hr<HOST_REGS;hr++)
9296       {
9297         if(hr!=EXCLUDE_REG) {
9298           if(regs[i].regmap[hr]>64) {
9299             if(!((regs[i].dirty>>hr)&1))
9300               f_regmap[hr]=regs[i].regmap[hr];
9301           }
9302           else if(regs[i].regmap[hr]>=0) {
9303             if(f_regmap[hr]!=regs[i].regmap[hr]) {
9304               // dealloc old register
9305               int n;
9306               for(n=0;n<HOST_REGS;n++)
9307               {
9308                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9309               }
9310               // and alloc new one
9311               f_regmap[hr]=regs[i].regmap[hr];
9312             }
9313           }
9314         }
9315       }
9316       // Try to restore cycle count at branch targets
9317       if(bt[i]) {
9318         for(j=i;j<slen-1;j++) {
9319           if(regs[j].regmap[HOST_CCREG]!=-1) break;
9320           if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
9321             //printf("no free regs for store %x\n",start+j*4);
9322             break;
9323           }
9324         }
9325         if(regs[j].regmap[HOST_CCREG]==CCREG) {
9326           int k=i;
9327           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
9328           while(k<j) {
9329             regs[k].regmap_entry[HOST_CCREG]=CCREG;
9330             regs[k].regmap[HOST_CCREG]=CCREG;
9331             regmap_pre[k+1][HOST_CCREG]=CCREG;
9332             regs[k+1].wasdirty|=1<<HOST_CCREG;
9333             regs[k].dirty|=1<<HOST_CCREG;
9334             regs[k].wasconst&=~(1<<HOST_CCREG);
9335             regs[k].isconst&=~(1<<HOST_CCREG);
9336             k++;
9337           }
9338           regs[j].regmap_entry[HOST_CCREG]=CCREG;
9339         }
9340         // Work backwards from the branch target
9341         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
9342         {
9343           //printf("Extend backwards\n");
9344           int k;
9345           k=i;
9346           while(regs[k-1].regmap[HOST_CCREG]==-1) {
9347             if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9348               //printf("no free regs for store %x\n",start+(k-1)*4);
9349               break;
9350             }
9351             k--;
9352           }
9353           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
9354             //printf("Extend CC, %x ->\n",start+k*4);
9355             while(k<=i) {
9356               regs[k].regmap_entry[HOST_CCREG]=CCREG;
9357               regs[k].regmap[HOST_CCREG]=CCREG;
9358               regmap_pre[k+1][HOST_CCREG]=CCREG;
9359               regs[k+1].wasdirty|=1<<HOST_CCREG;
9360               regs[k].dirty|=1<<HOST_CCREG;
9361               regs[k].wasconst&=~(1<<HOST_CCREG);
9362               regs[k].isconst&=~(1<<HOST_CCREG);
9363               k++;
9364             }
9365           }
9366           else {
9367             //printf("Fail Extend CC, %x ->\n",start+k*4);
9368           }
9369         }
9370       }
9371       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
9372          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
9373          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
9374          itype[i]!=FCONV&&itype[i]!=FCOMP)
9375       {
9376         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
9377       }
9378     }
9379   }
9380
9381   // Cache memory offset or tlb map pointer if a register is available
9382   #ifndef HOST_IMM_ADDR32
9383   #ifndef RAM_OFFSET
9384   if(0)
9385   #endif
9386   {
9387     int earliest_available[HOST_REGS];
9388     int loop_start[HOST_REGS];
9389     int score[HOST_REGS];
9390     int end[HOST_REGS];
9391     int reg=ROREG;
9392
9393     // Init
9394     for(hr=0;hr<HOST_REGS;hr++) {
9395       score[hr]=0;earliest_available[hr]=0;
9396       loop_start[hr]=MAXBLOCK;
9397     }
9398     for(i=0;i<slen-1;i++)
9399     {
9400       // Can't do anything if no registers are available
9401       if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
9402         for(hr=0;hr<HOST_REGS;hr++) {
9403           score[hr]=0;earliest_available[hr]=i+1;
9404           loop_start[hr]=MAXBLOCK;
9405         }
9406       }
9407       if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
9408         if(!ooo[i]) {
9409           if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
9410             for(hr=0;hr<HOST_REGS;hr++) {
9411               score[hr]=0;earliest_available[hr]=i+1;
9412               loop_start[hr]=MAXBLOCK;
9413             }
9414           }
9415         }else{
9416           if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
9417             for(hr=0;hr<HOST_REGS;hr++) {
9418               score[hr]=0;earliest_available[hr]=i+1;
9419               loop_start[hr]=MAXBLOCK;
9420             }
9421           }
9422         }
9423       }
9424       // Mark unavailable registers
9425       for(hr=0;hr<HOST_REGS;hr++) {
9426         if(regs[i].regmap[hr]>=0) {
9427           score[hr]=0;earliest_available[hr]=i+1;
9428           loop_start[hr]=MAXBLOCK;
9429         }
9430         if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
9431           if(branch_regs[i].regmap[hr]>=0) {
9432             score[hr]=0;earliest_available[hr]=i+2;
9433             loop_start[hr]=MAXBLOCK;
9434           }
9435         }
9436       }
9437       // No register allocations after unconditional jumps
9438       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
9439       {
9440         for(hr=0;hr<HOST_REGS;hr++) {
9441           score[hr]=0;earliest_available[hr]=i+2;
9442           loop_start[hr]=MAXBLOCK;
9443         }
9444         i++; // Skip delay slot too
9445         //printf("skip delay slot: %x\n",start+i*4);
9446       }
9447       else
9448       // Possible match
9449       if(itype[i]==LOAD||itype[i]==LOADLR||
9450          itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
9451         for(hr=0;hr<HOST_REGS;hr++) {
9452           if(hr!=EXCLUDE_REG) {
9453             end[hr]=i-1;
9454             for(j=i;j<slen-1;j++) {
9455               if(regs[j].regmap[hr]>=0) break;
9456               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
9457                 if(branch_regs[j].regmap[hr]>=0) break;
9458                 if(ooo[j]) {
9459                   if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
9460                 }else{
9461                   if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
9462                 }
9463               }
9464               else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
9465               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
9466                 int t=(ba[j]-start)>>2;
9467                 if(t<j&&t>=earliest_available[hr]) {
9468                   if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
9469                     // Score a point for hoisting loop invariant
9470                     if(t<loop_start[hr]) loop_start[hr]=t;
9471                     //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
9472                     score[hr]++;
9473                     end[hr]=j;
9474                   }
9475                 }
9476                 else if(t<j) {
9477                   if(regs[t].regmap[hr]==reg) {
9478                     // Score a point if the branch target matches this register
9479                     score[hr]++;
9480                     end[hr]=j;
9481                   }
9482                 }
9483                 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
9484                    itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
9485                   score[hr]++;
9486                   end[hr]=j;
9487                 }
9488               }
9489               if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
9490               {
9491                 // Stop on unconditional branch
9492                 break;
9493               }
9494               else
9495               if(itype[j]==LOAD||itype[j]==LOADLR||
9496                  itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
9497                 score[hr]++;
9498                 end[hr]=j;
9499               }
9500             }
9501           }
9502         }
9503         // Find highest score and allocate that register
9504         int maxscore=0;
9505         for(hr=0;hr<HOST_REGS;hr++) {
9506           if(hr!=EXCLUDE_REG) {
9507             if(score[hr]>score[maxscore]) {
9508               maxscore=hr;
9509               //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
9510             }
9511           }
9512         }
9513         if(score[maxscore]>1)
9514         {
9515           if(i<loop_start[maxscore]) loop_start[maxscore]=i;
9516           for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
9517             //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
9518             assert(regs[j].regmap[maxscore]<0);
9519             if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
9520             regs[j].regmap[maxscore]=reg;
9521             regs[j].dirty&=~(1<<maxscore);
9522             regs[j].wasconst&=~(1<<maxscore);
9523             regs[j].isconst&=~(1<<maxscore);
9524             if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
9525               branch_regs[j].regmap[maxscore]=reg;
9526               branch_regs[j].wasdirty&=~(1<<maxscore);
9527               branch_regs[j].dirty&=~(1<<maxscore);
9528               branch_regs[j].wasconst&=~(1<<maxscore);
9529               branch_regs[j].isconst&=~(1<<maxscore);
9530               if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
9531                 regmap_pre[j+2][maxscore]=reg;
9532                 regs[j+2].wasdirty&=~(1<<maxscore);
9533               }
9534               // loop optimization (loop_preload)
9535               int t=(ba[j]-start)>>2;
9536               if(t==loop_start[maxscore]) {
9537                 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
9538                   regs[t].regmap_entry[maxscore]=reg;
9539               }
9540             }
9541             else
9542             {
9543               if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
9544                 regmap_pre[j+1][maxscore]=reg;
9545                 regs[j+1].wasdirty&=~(1<<maxscore);
9546               }
9547             }
9548           }
9549           i=j-1;
9550           if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
9551           for(hr=0;hr<HOST_REGS;hr++) {
9552             score[hr]=0;earliest_available[hr]=i+i;
9553             loop_start[hr]=MAXBLOCK;
9554           }
9555         }
9556       }
9557     }
9558   }
9559   #endif
9560
9561   // This allocates registers (if possible) one instruction prior
9562   // to use, which can avoid a load-use penalty on certain CPUs.
9563   for(i=0;i<slen-1;i++)
9564   {
9565     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
9566     {
9567       if(!bt[i+1])
9568       {
9569         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
9570            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
9571         {
9572           if(rs1[i+1]) {
9573             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
9574             {
9575               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9576               {
9577                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9578                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9579                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9580                 regs[i].isconst&=~(1<<hr);
9581                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9582                 constmap[i][hr]=constmap[i+1][hr];
9583                 regs[i+1].wasdirty&=~(1<<hr);
9584                 regs[i].dirty&=~(1<<hr);
9585               }
9586             }
9587           }
9588           if(rs2[i+1]) {
9589             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
9590             {
9591               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9592               {
9593                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9594                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9595                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9596                 regs[i].isconst&=~(1<<hr);
9597                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9598                 constmap[i][hr]=constmap[i+1][hr];
9599                 regs[i+1].wasdirty&=~(1<<hr);
9600                 regs[i].dirty&=~(1<<hr);
9601               }
9602             }
9603           }
9604           // Preload target address for load instruction (non-constant)
9605           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9606             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
9607             {
9608               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9609               {
9610                 regs[i].regmap[hr]=rs1[i+1];
9611                 regmap_pre[i+1][hr]=rs1[i+1];
9612                 regs[i+1].regmap_entry[hr]=rs1[i+1];
9613                 regs[i].isconst&=~(1<<hr);
9614                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9615                 constmap[i][hr]=constmap[i+1][hr];
9616                 regs[i+1].wasdirty&=~(1<<hr);
9617                 regs[i].dirty&=~(1<<hr);
9618               }
9619             }
9620           }
9621           // Load source into target register
9622           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9623             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
9624             {
9625               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9626               {
9627                 regs[i].regmap[hr]=rs1[i+1];
9628                 regmap_pre[i+1][hr]=rs1[i+1];
9629                 regs[i+1].regmap_entry[hr]=rs1[i+1];
9630                 regs[i].isconst&=~(1<<hr);
9631                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9632                 constmap[i][hr]=constmap[i+1][hr];
9633                 regs[i+1].wasdirty&=~(1<<hr);
9634                 regs[i].dirty&=~(1<<hr);
9635               }
9636             }
9637           }
9638           // Address for store instruction (non-constant)
9639           if(itype[i+1]==STORE||itype[i+1]==STORELR
9640              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
9641             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9642               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
9643               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
9644               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
9645               assert(hr>=0);
9646               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9647               {
9648                 regs[i].regmap[hr]=rs1[i+1];
9649                 regmap_pre[i+1][hr]=rs1[i+1];
9650                 regs[i+1].regmap_entry[hr]=rs1[i+1];
9651                 regs[i].isconst&=~(1<<hr);
9652                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9653                 constmap[i][hr]=constmap[i+1][hr];
9654                 regs[i+1].wasdirty&=~(1<<hr);
9655                 regs[i].dirty&=~(1<<hr);
9656               }
9657             }
9658           }
9659           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
9660             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9661               int nr;
9662               hr=get_reg(regs[i+1].regmap,FTEMP);
9663               assert(hr>=0);
9664               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9665               {
9666                 regs[i].regmap[hr]=rs1[i+1];
9667                 regmap_pre[i+1][hr]=rs1[i+1];
9668                 regs[i+1].regmap_entry[hr]=rs1[i+1];
9669                 regs[i].isconst&=~(1<<hr);
9670                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9671                 constmap[i][hr]=constmap[i+1][hr];
9672                 regs[i+1].wasdirty&=~(1<<hr);
9673                 regs[i].dirty&=~(1<<hr);
9674               }
9675               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
9676               {
9677                 // move it to another register
9678                 regs[i+1].regmap[hr]=-1;
9679                 regmap_pre[i+2][hr]=-1;
9680                 regs[i+1].regmap[nr]=FTEMP;
9681                 regmap_pre[i+2][nr]=FTEMP;
9682                 regs[i].regmap[nr]=rs1[i+1];
9683                 regmap_pre[i+1][nr]=rs1[i+1];
9684                 regs[i+1].regmap_entry[nr]=rs1[i+1];
9685                 regs[i].isconst&=~(1<<nr);
9686                 regs[i+1].isconst&=~(1<<nr);
9687                 regs[i].dirty&=~(1<<nr);
9688                 regs[i+1].wasdirty&=~(1<<nr);
9689                 regs[i+1].dirty&=~(1<<nr);
9690                 regs[i+2].wasdirty&=~(1<<nr);
9691               }
9692             }
9693           }
9694           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
9695             if(itype[i+1]==LOAD)
9696               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
9697             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
9698               hr=get_reg(regs[i+1].regmap,FTEMP);
9699             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
9700               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
9701               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
9702             }
9703             if(hr>=0&&regs[i].regmap[hr]<0) {
9704               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
9705               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
9706                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
9707                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
9708                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
9709                 regs[i].isconst&=~(1<<hr);
9710                 regs[i+1].wasdirty&=~(1<<hr);
9711                 regs[i].dirty&=~(1<<hr);
9712               }
9713             }
9714           }
9715         }
9716       }
9717     }
9718   }
9719
9720   /* Pass 6 - Optimize clean/dirty state */
9721   clean_registers(0,slen-1,1);
9722
9723   /* Pass 7 - Identify 32-bit registers */
9724   for (i=slen-1;i>=0;i--)
9725   {
9726     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9727     {
9728       // Conditional branch
9729       if((source[i]>>16)!=0x1000&&i<slen-2) {
9730         // Mark this address as a branch target since it may be called
9731         // upon return from interrupt
9732         bt[i+2]=1;
9733       }
9734     }
9735   }
9736
9737   if(itype[slen-1]==SPAN) {
9738     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
9739   }
9740
9741 #ifdef DISASM
9742   /* Debug/disassembly */
9743   for(i=0;i<slen;i++)
9744   {
9745     printf("U:");
9746     int r;
9747     for(r=1;r<=CCREG;r++) {
9748       if((unneeded_reg[i]>>r)&1) {
9749         if(r==HIREG) printf(" HI");
9750         else if(r==LOREG) printf(" LO");
9751         else printf(" r%d",r);
9752       }
9753     }
9754     printf("\n");
9755     #if defined(__i386__) || defined(__x86_64__)
9756     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
9757     #endif
9758     #ifdef __arm__
9759     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
9760     #endif
9761     printf("needs: ");
9762     if(needed_reg[i]&1) printf("eax ");
9763     if((needed_reg[i]>>1)&1) printf("ecx ");
9764     if((needed_reg[i]>>2)&1) printf("edx ");
9765     if((needed_reg[i]>>3)&1) printf("ebx ");
9766     if((needed_reg[i]>>5)&1) printf("ebp ");
9767     if((needed_reg[i]>>6)&1) printf("esi ");
9768     if((needed_reg[i]>>7)&1) printf("edi ");
9769     printf("\n");
9770     #if defined(__i386__) || defined(__x86_64__)
9771     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
9772     printf("dirty: ");
9773     if(regs[i].wasdirty&1) printf("eax ");
9774     if((regs[i].wasdirty>>1)&1) printf("ecx ");
9775     if((regs[i].wasdirty>>2)&1) printf("edx ");
9776     if((regs[i].wasdirty>>3)&1) printf("ebx ");
9777     if((regs[i].wasdirty>>5)&1) printf("ebp ");
9778     if((regs[i].wasdirty>>6)&1) printf("esi ");
9779     if((regs[i].wasdirty>>7)&1) printf("edi ");
9780     #endif
9781     #ifdef __arm__
9782     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
9783     printf("dirty: ");
9784     if(regs[i].wasdirty&1) printf("r0 ");
9785     if((regs[i].wasdirty>>1)&1) printf("r1 ");
9786     if((regs[i].wasdirty>>2)&1) printf("r2 ");
9787     if((regs[i].wasdirty>>3)&1) printf("r3 ");
9788     if((regs[i].wasdirty>>4)&1) printf("r4 ");
9789     if((regs[i].wasdirty>>5)&1) printf("r5 ");
9790     if((regs[i].wasdirty>>6)&1) printf("r6 ");
9791     if((regs[i].wasdirty>>7)&1) printf("r7 ");
9792     if((regs[i].wasdirty>>8)&1) printf("r8 ");
9793     if((regs[i].wasdirty>>9)&1) printf("r9 ");
9794     if((regs[i].wasdirty>>10)&1) printf("r10 ");
9795     if((regs[i].wasdirty>>12)&1) printf("r12 ");
9796     #endif
9797     printf("\n");
9798     disassemble_inst(i);
9799     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
9800     #if defined(__i386__) || defined(__x86_64__)
9801     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
9802     if(regs[i].dirty&1) printf("eax ");
9803     if((regs[i].dirty>>1)&1) printf("ecx ");
9804     if((regs[i].dirty>>2)&1) printf("edx ");
9805     if((regs[i].dirty>>3)&1) printf("ebx ");
9806     if((regs[i].dirty>>5)&1) printf("ebp ");
9807     if((regs[i].dirty>>6)&1) printf("esi ");
9808     if((regs[i].dirty>>7)&1) printf("edi ");
9809     #endif
9810     #ifdef __arm__
9811     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
9812     if(regs[i].dirty&1) printf("r0 ");
9813     if((regs[i].dirty>>1)&1) printf("r1 ");
9814     if((regs[i].dirty>>2)&1) printf("r2 ");
9815     if((regs[i].dirty>>3)&1) printf("r3 ");
9816     if((regs[i].dirty>>4)&1) printf("r4 ");
9817     if((regs[i].dirty>>5)&1) printf("r5 ");
9818     if((regs[i].dirty>>6)&1) printf("r6 ");
9819     if((regs[i].dirty>>7)&1) printf("r7 ");
9820     if((regs[i].dirty>>8)&1) printf("r8 ");
9821     if((regs[i].dirty>>9)&1) printf("r9 ");
9822     if((regs[i].dirty>>10)&1) printf("r10 ");
9823     if((regs[i].dirty>>12)&1) printf("r12 ");
9824     #endif
9825     printf("\n");
9826     if(regs[i].isconst) {
9827       printf("constants: ");
9828       #if defined(__i386__) || defined(__x86_64__)
9829       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
9830       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
9831       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
9832       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
9833       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
9834       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
9835       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
9836       #endif
9837       #ifdef __arm__
9838       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
9839       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
9840       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
9841       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
9842       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
9843       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
9844       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
9845       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
9846       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
9847       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
9848       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
9849       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
9850       #endif
9851       printf("\n");
9852     }
9853     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
9854       #if defined(__i386__) || defined(__x86_64__)
9855       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
9856       if(branch_regs[i].dirty&1) printf("eax ");
9857       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
9858       if((branch_regs[i].dirty>>2)&1) printf("edx ");
9859       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
9860       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
9861       if((branch_regs[i].dirty>>6)&1) printf("esi ");
9862       if((branch_regs[i].dirty>>7)&1) printf("edi ");
9863       #endif
9864       #ifdef __arm__
9865       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
9866       if(branch_regs[i].dirty&1) printf("r0 ");
9867       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
9868       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
9869       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
9870       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
9871       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
9872       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
9873       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
9874       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
9875       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
9876       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
9877       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
9878       #endif
9879     }
9880   }
9881 #endif // DISASM
9882
9883   /* Pass 8 - Assembly */
9884   linkcount=0;stubcount=0;
9885   ds=0;is_delayslot=0;
9886   cop1_usable=0;
9887   uint64_t is32_pre=0;
9888   u_int dirty_pre=0;
9889   u_int beginning=(u_int)out;
9890   if((u_int)addr&1) {
9891     ds=1;
9892     pagespan_ds();
9893   }
9894   u_int instr_addr0_override=0;
9895
9896   if (start == 0x80030000) {
9897     // nasty hack for fastbios thing
9898     // override block entry to this code
9899     instr_addr0_override=(u_int)out;
9900     emit_movimm(start,0);
9901     // abuse io address var as a flag that we
9902     // have already returned here once
9903     emit_readword((int)&address,1);
9904     emit_writeword(0,(int)&pcaddr);
9905     emit_writeword(0,(int)&address);
9906     emit_cmp(0,1);
9907     emit_jne((int)new_dyna_leave);
9908   }
9909   for(i=0;i<slen;i++)
9910   {
9911     //if(ds) printf("ds: ");
9912     disassemble_inst(i);
9913     if(ds) {
9914       ds=0; // Skip delay slot
9915       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
9916       instr_addr[i]=0;
9917     } else {
9918       speculate_register_values(i);
9919       #ifndef DESTRUCTIVE_WRITEBACK
9920       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
9921       {
9922         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
9923               unneeded_reg[i],unneeded_reg_upper[i]);
9924       }
9925       if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
9926         is32_pre=branch_regs[i].is32;
9927         dirty_pre=branch_regs[i].dirty;
9928       }else{
9929         is32_pre=regs[i].is32;
9930         dirty_pre=regs[i].dirty;
9931       }
9932       #endif
9933       // write back
9934       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
9935       {
9936         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
9937                       unneeded_reg[i],unneeded_reg_upper[i]);
9938         loop_preload(regmap_pre[i],regs[i].regmap_entry);
9939       }
9940       // branch target entry point
9941       instr_addr[i]=(u_int)out;
9942       assem_debug("<->\n");
9943       // load regs
9944       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
9945         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
9946       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
9947       address_generation(i,&regs[i],regs[i].regmap_entry);
9948       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
9949       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9950       {
9951         // Load the delay slot registers if necessary
9952         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
9953           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
9954         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
9955           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
9956         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
9957           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
9958       }
9959       else if(i+1<slen)
9960       {
9961         // Preload registers for following instruction
9962         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
9963           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
9964             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
9965         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
9966           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
9967             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
9968       }
9969       // TODO: if(is_ooo(i)) address_generation(i+1);
9970       if(itype[i]==CJUMP||itype[i]==FJUMP)
9971         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
9972       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
9973         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
9974       if(bt[i]) cop1_usable=0;
9975       // assemble
9976       switch(itype[i]) {
9977         case ALU:
9978           alu_assemble(i,&regs[i]);break;
9979         case IMM16:
9980           imm16_assemble(i,&regs[i]);break;
9981         case SHIFT:
9982           shift_assemble(i,&regs[i]);break;
9983         case SHIFTIMM:
9984           shiftimm_assemble(i,&regs[i]);break;
9985         case LOAD:
9986           load_assemble(i,&regs[i]);break;
9987         case LOADLR:
9988           loadlr_assemble(i,&regs[i]);break;
9989         case STORE:
9990           store_assemble(i,&regs[i]);break;
9991         case STORELR:
9992           storelr_assemble(i,&regs[i]);break;
9993         case COP0:
9994           cop0_assemble(i,&regs[i]);break;
9995         case COP1:
9996           cop1_assemble(i,&regs[i]);break;
9997         case C1LS:
9998           c1ls_assemble(i,&regs[i]);break;
9999         case COP2:
10000           cop2_assemble(i,&regs[i]);break;
10001         case C2LS:
10002           c2ls_assemble(i,&regs[i]);break;
10003         case C2OP:
10004           c2op_assemble(i,&regs[i]);break;
10005         case FCONV:
10006           fconv_assemble(i,&regs[i]);break;
10007         case FLOAT:
10008           float_assemble(i,&regs[i]);break;
10009         case FCOMP:
10010           fcomp_assemble(i,&regs[i]);break;
10011         case MULTDIV:
10012           multdiv_assemble(i,&regs[i]);break;
10013         case MOV:
10014           mov_assemble(i,&regs[i]);break;
10015         case SYSCALL:
10016           syscall_assemble(i,&regs[i]);break;
10017         case HLECALL:
10018           hlecall_assemble(i,&regs[i]);break;
10019         case INTCALL:
10020           intcall_assemble(i,&regs[i]);break;
10021         case UJUMP:
10022           ujump_assemble(i,&regs[i]);ds=1;break;
10023         case RJUMP:
10024           rjump_assemble(i,&regs[i]);ds=1;break;
10025         case CJUMP:
10026           cjump_assemble(i,&regs[i]);ds=1;break;
10027         case SJUMP:
10028           sjump_assemble(i,&regs[i]);ds=1;break;
10029         case FJUMP:
10030           fjump_assemble(i,&regs[i]);ds=1;break;
10031         case SPAN:
10032           pagespan_assemble(i,&regs[i]);break;
10033       }
10034       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10035         literal_pool(1024);
10036       else
10037         literal_pool_jumpover(256);
10038     }
10039   }
10040   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10041   // If the block did not end with an unconditional branch,
10042   // add a jump to the next instruction.
10043   if(i>1) {
10044     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10045       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10046       assert(i==slen);
10047       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10048         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10049         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10050           emit_loadreg(CCREG,HOST_CCREG);
10051         emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
10052       }
10053       else if(!likely[i-2])
10054       {
10055         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10056         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10057       }
10058       else
10059       {
10060         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10061         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10062       }
10063       add_to_linker((int)out,start+i*4,0);
10064       emit_jmp(0);
10065     }
10066   }
10067   else
10068   {
10069     assert(i>0);
10070     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10071     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10072     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10073       emit_loadreg(CCREG,HOST_CCREG);
10074     emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
10075     add_to_linker((int)out,start+i*4,0);
10076     emit_jmp(0);
10077   }
10078
10079   // TODO: delay slot stubs?
10080   // Stubs
10081   for(i=0;i<stubcount;i++)
10082   {
10083     switch(stubs[i][0])
10084     {
10085       case LOADB_STUB:
10086       case LOADH_STUB:
10087       case LOADW_STUB:
10088       case LOADD_STUB:
10089       case LOADBU_STUB:
10090       case LOADHU_STUB:
10091         do_readstub(i);break;
10092       case STOREB_STUB:
10093       case STOREH_STUB:
10094       case STOREW_STUB:
10095       case STORED_STUB:
10096         do_writestub(i);break;
10097       case CC_STUB:
10098         do_ccstub(i);break;
10099       case INVCODE_STUB:
10100         do_invstub(i);break;
10101       case FP_STUB:
10102         do_cop1stub(i);break;
10103       case STORELR_STUB:
10104         do_unalignedwritestub(i);break;
10105     }
10106   }
10107
10108   if (instr_addr0_override)
10109     instr_addr[0] = instr_addr0_override;
10110
10111   /* Pass 9 - Linker */
10112   for(i=0;i<linkcount;i++)
10113   {
10114     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10115     literal_pool(64);
10116     if(!link_addr[i][2])
10117     {
10118       void *stub=out;
10119       void *addr=check_addr(link_addr[i][1]);
10120       emit_extjump(link_addr[i][0],link_addr[i][1]);
10121       if(addr) {
10122         set_jump_target(link_addr[i][0],(int)addr);
10123         add_link(link_addr[i][1],stub);
10124       }
10125       else set_jump_target(link_addr[i][0],(int)stub);
10126     }
10127     else
10128     {
10129       // Internal branch
10130       int target=(link_addr[i][1]-start)>>2;
10131       assert(target>=0&&target<slen);
10132       assert(instr_addr[target]);
10133       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10134       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10135       //#else
10136       set_jump_target(link_addr[i][0],instr_addr[target]);
10137       //#endif
10138     }
10139   }
10140   // External Branch Targets (jump_in)
10141   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10142   for(i=0;i<slen;i++)
10143   {
10144     if(bt[i]||i==0)
10145     {
10146       if(instr_addr[i]) // TODO - delay slots (=null)
10147       {
10148         u_int vaddr=start+i*4;
10149         u_int page=get_page(vaddr);
10150         u_int vpage=get_vpage(vaddr);
10151         literal_pool(256);
10152         {
10153           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10154           assem_debug("jump_in: %x\n",start+i*4);
10155           ll_add(jump_dirty+vpage,vaddr,(void *)out);
10156           int entry_point=do_dirty_stub(i);
10157           ll_add_flags(jump_in+page,vaddr,state_rflags,(void *)entry_point);
10158           // If there was an existing entry in the hash table,
10159           // replace it with the new address.
10160           // Don't add new entries.  We'll insert the
10161           // ones that actually get used in check_addr().
10162           u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10163           if(ht_bin[0]==vaddr) {
10164             ht_bin[1]=entry_point;
10165           }
10166           if(ht_bin[2]==vaddr) {
10167             ht_bin[3]=entry_point;
10168           }
10169         }
10170       }
10171     }
10172   }
10173   // Write out the literal pool if necessary
10174   literal_pool(0);
10175   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10176   // Align code
10177   if(((u_int)out)&7) emit_addnop(13);
10178   #endif
10179   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10180   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10181   memcpy(copy,source,slen*4);
10182   copy+=slen*4;
10183
10184   #ifdef __arm__
10185   __clear_cache((void *)beginning,out);
10186   #endif
10187
10188   // If we're within 256K of the end of the buffer,
10189   // start over from the beginning. (Is 256K enough?)
10190   if((u_int)out>(u_int)BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
10191
10192   // Trap writes to any of the pages we compiled
10193   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10194     invalid_code[i]=0;
10195   }
10196   inv_code_start=inv_code_end=~0;
10197
10198   // for PCSX we need to mark all mirrors too
10199   if(get_page(start)<(RAM_SIZE>>12))
10200     for(i=start>>12;i<=(start+slen*4)>>12;i++)
10201       invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
10202       invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
10203       invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
10204
10205   /* Pass 10 - Free memory by expiring oldest blocks */
10206
10207   int end=((((int)out-(int)BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
10208   while(expirep!=end)
10209   {
10210     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
10211     int base=(int)BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
10212     inv_debug("EXP: Phase %d\n",expirep);
10213     switch((expirep>>11)&3)
10214     {
10215       case 0:
10216         // Clear jump_in and jump_dirty
10217         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
10218         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
10219         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
10220         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
10221         break;
10222       case 1:
10223         // Clear pointers
10224         ll_kill_pointers(jump_out[expirep&2047],base,shift);
10225         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
10226         break;
10227       case 2:
10228         // Clear hash table
10229         for(i=0;i<32;i++) {
10230           u_int *ht_bin=hash_table[((expirep&2047)<<5)+i];
10231           if((ht_bin[3]>>shift)==(base>>shift) ||
10232              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10233             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
10234             ht_bin[2]=ht_bin[3]=-1;
10235           }
10236           if((ht_bin[1]>>shift)==(base>>shift) ||
10237              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10238             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
10239             ht_bin[0]=ht_bin[2];
10240             ht_bin[1]=ht_bin[3];
10241             ht_bin[2]=ht_bin[3]=-1;
10242           }
10243         }
10244         break;
10245       case 3:
10246         // Clear jump_out
10247         #ifdef __arm__
10248         if((expirep&2047)==0)
10249           do_clear_cache();
10250         #endif
10251         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
10252         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
10253         break;
10254     }
10255     expirep=(expirep+1)&65535;
10256   }
10257   return 0;
10258 }
10259
10260 // vim:shiftwidth=2:expandtab