drc: try to support w^x platforms like iOS

[pcsx_rearmed.git] / libpcsxcore / new_dynarec / assem_arm.h

diff --git a/libpcsxcore/new_dynarec/assem_arm.h b/libpcsxcore/new_dynarec/assem_arm.h
index 5060095..acf65bd 100644 (file)
--- a/libpcsxcore/new_dynarec/assem_arm.h
+++ b/libpcsxcore/new_dynarec/assem_arm.h
@@ -5,21 +5,10 @@
 
 #define HOST_IMM8 1
 #define HAVE_CMOV_IMM 1
-#define CORTEX_A8_BRANCH_PREDICTION_HACK 1
-#define USE_MINI_HT 1
-//#define REG_PREFETCH 1
-#define DISABLE_TLB 1
-//#define MUPEN64
-#define FORCE32 1
-#define DISABLE_COP1 1
-#define PCSX 1
+#define HAVE_CONDITIONAL_CALL 1
 #define RAM_SIZE 0x200000
 
-#ifdef FORCE32
 #define REG_SHIFT 2
-#else
-#define REG_SHIFT 3
-#endif
 
 /* ARM calling convention:
    r0-r3, r12: caller-save
@@ -47,8 +36,13 @@
 
 extern char *invc_ptr;
 
-#define BASE_ADDR 0x1000000 // Code generator target address
 #define TARGET_SIZE_2 24 // 2^24 = 16 megabytes
 
-// This is defined in linkage_arm.s, but gcc -O3 likes this better
-#define rdram ((unsigned int *)0x80000000)
+// Code generator target address
+#if BASE_ADDR_FIXED
+// "round" address helpful for debug
+#define BASE_ADDR 0x1000000
+#else
+extern char translation_cache[1 << TARGET_SIZE_2];
+#define BASE_ADDR (u_int)translation_cache
+#endif