cdrom: change pause timing again

[pcsx_rearmed.git] / libpcsxcore / psxinterpreter.c

diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c
index 2ffab69..3060853 100644 (file)
--- a/libpcsxcore/psxinterpreter.c
+++ b/libpcsxcore/psxinterpreter.c
@@ -176,25 +176,21 @@ static int execBreakCheck(psxRegisters *regs, u32 pc)
 // get an opcode without triggering exceptions or affecting cache
 u32 intFakeFetch(u32 pc)
 {
-       u8 *base = psxMemRLUT[pc >> 16];
-       u32 *code;
-       if (unlikely(base == INVALID_PTR))
+       u32 *code = (u32 *)psxm(pc & ~0x3, 0);
+       if (unlikely(code == INVALID_PTR))
                return 0; // nop
-       code = (u32 *)(base + (pc & 0xfffc));
        return SWAP32(*code);
 
 }
 
 static u32 INT_ATTR fetchNoCache(psxRegisters *regs, u8 **memRLUT, u32 pc)
 {
-       u8 *base = memRLUT[pc >> 16];
-       u32 *code;
-       if (unlikely(base == INVALID_PTR)) {
+       u32 *code = (u32 *)psxm_lut(pc & ~0x3, 0, memRLUT);
+       if (unlikely(code == INVALID_PTR)) {
                SysPrintf("game crash @%08x, ra=%08x\n", pc, regs->GPR.n.ra);
                intException(regs, pc, R3000E_IBE << 2);
                return 0; // execute as nop
        }
-       code = (u32 *)(base + (pc & 0xfffc));
        return SWAP32(*code);
 }
 
@@ -217,14 +213,12 @@ static u32 INT_ATTR fetchICache(psxRegisters *regs, u8 **memRLUT, u32 pc)
 
                if (((entry->tag ^ pc) & 0xfffffff0) != 0 || pc < entry->tag)
                {
-                       const u8 *base = memRLUT[pc >> 16];
-                       const u32 *code;
-                       if (unlikely(base == INVALID_PTR)) {
+                       const u32 *code = (u32 *)psxm_lut(pc & ~0xf, 0, memRLUT);
+                       if (unlikely(code == INVALID_PTR)) {
                                SysPrintf("game crash @%08x, ra=%08x\n", pc, regs->GPR.n.ra);
                                intException(regs, pc, R3000E_IBE << 2);
                                return 0; // execute as nop
                        }
-                       code = (u32 *)(base + (pc & 0xfff0));
 
                        entry->tag = pc;
                        // treat as 4 words, although other configurations are said to be possible
@@ -875,12 +869,12 @@ OP(psxLWR) { doLWR(regs_, _Rt_, _oB_); }
 OP(psxLWLe) { if (checkLD(regs_, _oB_ & ~3, 0)) doLWL(regs_, _Rt_, _oB_); }
 OP(psxLWRe) { if (checkLD(regs_, _oB_     , 0)) doLWR(regs_, _Rt_, _oB_); }
 
-OP(psxSB) { psxMemWrite8 (_oB_, _rRt_ &   0xff); }
-OP(psxSH) { psxMemWrite16(_oB_, _rRt_ & 0xffff); }
+OP(psxSB) { psxMemWrite8 (_oB_, _rRt_); }
+OP(psxSH) { psxMemWrite16(_oB_, _rRt_); }
 OP(psxSW) { psxMemWrite32(_oB_, _rRt_); }
 
-OP(psxSBe) { if (checkST(regs_, _oB_, 0)) psxMemWrite8 (_oB_, _rRt_ &   0xff); }
-OP(psxSHe) { if (checkST(regs_, _oB_, 1)) psxMemWrite16(_oB_, _rRt_ & 0xffff); }
+OP(psxSBe) { if (checkST(regs_, _oB_, 0)) psxMemWrite8 (_oB_, _rRt_); }
+OP(psxSHe) { if (checkST(regs_, _oB_, 1)) psxMemWrite16(_oB_, _rRt_); }
 OP(psxSWe) { if (checkST(regs_, _oB_, 3)) psxMemWrite32(_oB_, _rRt_); }
 
 static void doSWL(psxRegisters *regs, u32 rt, u32 addr) {
@@ -964,8 +958,14 @@ void MTC0(psxRegisters *regs_, int reg, u32 val) {
                case 7:
                        if ((regs_->CP0.n.DCIC ^ val) & 0xff800000)
                                log_unhandled("DCIC: %08x->%08x\n", regs_->CP0.n.DCIC, val);
-                       // fallthrough
+                       goto default_;
+               case 3:
+                       if (regs_->CP0.n.BPC != val)
+                               log_unhandled("BPC: %08x->%08x\n", regs_->CP0.n.BPC, val);
+                       goto default_;
+
                default:
+               default_:
                        regs_->CP0.r[reg] = val;
                        break;
        }