X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=pcsx_rearmed.git;a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Flinkage_arm.S;h=95af8b4e5ee77da21c8a8b48a45e46de97b9f851;hp=0c5b20557123bf4e405aa883cdd66bc80a18c9d3;hb=8f2bb0cbd20c00475196d1efb72103b65e57bc66;hpb=b861c0a92c13df8a8b3c59b87ad7924a3861a5ac

diff --git a/libpcsxcore/new_dynarec/linkage_arm.S b/libpcsxcore/new_dynarec/linkage_arm.S
index 0c5b2055..95af8b4e 100644
--- a/libpcsxcore/new_dynarec/linkage_arm.S
+++ b/libpcsxcore/new_dynarec/linkage_arm.S
@@ -116,12 +116,12 @@ ptr_hash_table:
 #endif
 
 .macro load_varadr reg var
-#if defined(__ARM_ARCH_7A__) && !defined(__PIC__)
+#if defined(HAVE_ARMV7) && !defined(__PIC__)
 	movw	\reg, #:lower16:\var
 	movt	\reg, #:upper16:\var
-#elif defined(__ARM_ARCH_7A__) && defined(__MACH__)
-	movw	\reg, #:lower16:(\var-(1678f+4))
-	movt	\reg, #:upper16:(\var-(1678f+4))
+#elif defined(HAVE_ARMV7) && defined(__MACH__)
+	movw	\reg, #:lower16:(\var-(1678f+8))
+	movt	\reg, #:upper16:(\var-(1678f+8))
 1678:
 	add	\reg, pc
 #else
@@ -130,9 +130,9 @@ ptr_hash_table:
 .endm
 
 .macro load_varadr_ext reg var
-#if defined(__ARM_ARCH_7A__) && defined(__MACH__) && defined(__PIC__)
-	movw	\reg, #:lower16:(ptr_\var-(1678f+4))
-	movt	\reg, #:upper16:(ptr_\var-(1678f+4))
+#if defined(HAVE_ARMV7) && defined(__MACH__) && defined(__PIC__)
+	movw	\reg, #:lower16:(ptr_\var-(1678f+8))
+	movt	\reg, #:upper16:(ptr_\var-(1678f+8))
 1678:
 	ldr	\reg, [pc, \reg]
 #else
@@ -141,7 +141,7 @@ ptr_hash_table:
 .endm
 
 .macro mov_16 reg imm
-#ifdef __ARM_ARCH_7A__
+#ifdef HAVE_ARMV7
 	movw	\reg, #\imm
 #else
 	mov	\reg, #(\imm & 0x00ff)
@@ -150,7 +150,7 @@ ptr_hash_table:
 .endm
 
 .macro mov_24 reg imm
-#ifdef __ARM_ARCH_7A__
+#ifdef HAVE_ARMV7
 	movw	\reg, #(\imm & 0xffff)
 	movt	\reg, #(\imm >> 16)
 #else
@@ -184,14 +184,10 @@ ptr_hash_table:
 1:
 	movs	r4, r5
 	beq	2f
-	ldr	r3, [r5]
-	ldr	r5, [r4, #12]
+	ldr	r3, [r5]	 /* ll_entry .vaddr */
+	ldrd	r4, r5, [r4, #8] /* ll_entry .next, .addr */
 	teq	r3, r0
 	bne	1b
-	ldr	r3, [r4, #4]
-	ldr	r4, [r4, #8]
-	tst	r3, r3
-	bne	1b
 	teq	r4, r6
 	moveq	pc, r4 /* Stale i-cache */
 	mov	r8, r4
@@ -573,72 +569,72 @@ FUNCTION(new_dyna_leave):
 
 	.align	2
 FUNCTION(invalidate_addr_r0):
-	stmia	fp, {r0, r1, r2, r3, r12, lr}
+	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
 	b	invalidate_addr_call
 	.size	invalidate_addr_r0, .-invalidate_addr_r0
 	.align	2
 FUNCTION(invalidate_addr_r1):
-	stmia	fp, {r0, r1, r2, r3, r12, lr}
+	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
 	mov	r0, r1
 	b	invalidate_addr_call
 	.size	invalidate_addr_r1, .-invalidate_addr_r1
 	.align	2
 FUNCTION(invalidate_addr_r2):
-	stmia	fp, {r0, r1, r2, r3, r12, lr}
+	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
 	mov	r0, r2
 	b	invalidate_addr_call
 	.size	invalidate_addr_r2, .-invalidate_addr_r2
 	.align	2
 FUNCTION(invalidate_addr_r3):
-	stmia	fp, {r0, r1, r2, r3, r12, lr}
+	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
 	mov	r0, r3
 	b	invalidate_addr_call
 	.size	invalidate_addr_r3, .-invalidate_addr_r3
 	.align	2
 FUNCTION(invalidate_addr_r4):
-	stmia	fp, {r0, r1, r2, r3, r12, lr}
+	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
 	mov	r0, r4
 	b	invalidate_addr_call
 	.size	invalidate_addr_r4, .-invalidate_addr_r4
 	.align	2
 FUNCTION(invalidate_addr_r5):
-	stmia	fp, {r0, r1, r2, r3, r12, lr}
+	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
 	mov	r0, r5
 	b	invalidate_addr_call
 	.size	invalidate_addr_r5, .-invalidate_addr_r5
 	.align	2
 FUNCTION(invalidate_addr_r6):
-	stmia	fp, {r0, r1, r2, r3, r12, lr}
+	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
 	mov	r0, r6
 	b	invalidate_addr_call
 	.size	invalidate_addr_r6, .-invalidate_addr_r6
 	.align	2
 FUNCTION(invalidate_addr_r7):
-	stmia	fp, {r0, r1, r2, r3, r12, lr}
+	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
 	mov	r0, r7
 	b	invalidate_addr_call
 	.size	invalidate_addr_r7, .-invalidate_addr_r7
 	.align	2
 FUNCTION(invalidate_addr_r8):
-	stmia	fp, {r0, r1, r2, r3, r12, lr}
+	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
 	mov	r0, r8
 	b	invalidate_addr_call
 	.size	invalidate_addr_r8, .-invalidate_addr_r8
 	.align	2
 FUNCTION(invalidate_addr_r9):
-	stmia	fp, {r0, r1, r2, r3, r12, lr}
+	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
 	mov	r0, r9
 	b	invalidate_addr_call
 	.size	invalidate_addr_r9, .-invalidate_addr_r9
 	.align	2
 FUNCTION(invalidate_addr_r10):
-	stmia	fp, {r0, r1, r2, r3, r12, lr}
+	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
 	mov	r0, r10
 	b	invalidate_addr_call
 	.size	invalidate_addr_r10, .-invalidate_addr_r10
 	.align	2
 FUNCTION(invalidate_addr_r12):
-	stmia	fp, {r0, r1, r2, r3, r12, lr}
+	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
 	mov	r0, r12
 	.size	invalidate_addr_r12, .-invalidate_addr_r12
 	.align	2
@@ -648,7 +644,7 @@ invalidate_addr_call:
 	cmp	r0, r12
 	cmpcs   lr, r0
 	blcc	invalidate_addr
-	ldmia	fp, {r0, r1, r2, r3, r12, pc}
+	ldmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
 	.size	invalidate_addr_call, .-invalidate_addr_call
 
 	.align	2
@@ -694,7 +690,7 @@ FUNCTION(jump_handler_read8):
 
 FUNCTION(jump_handler_read16):
 	add     r1, #0x1000/4*4              @ shift to r16 part
-	pcsx_read_mem ldrbcc, 1
+	pcsx_read_mem ldrhcc, 1
 
 FUNCTION(jump_handler_read32):
 	pcsx_read_mem ldrcc, 2