6003a768 |
1 | \r |
619b1824 |
2 | // This file is part of the Cyclone 68000 Emulator\r |
3 | \r |
d9d77995 |
4 | // Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r |
5 | // Copyright (c) 2005-2011 GraÅžvydas "notaz" Ignotas (notasas (at) gmail.com)\r |
c41b9b97 |
6 | \r |
619b1824 |
7 | // This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r |
8 | // You can choose the license that has the most advantages for you.\r |
9 | \r |
10 | // SVN repository can be found at http://code.google.com/p/cyclone68000/\r |
11 | \r |
d9d77995 |
12 | \r |
6003a768 |
13 | #include "app.h"\r |
14 | \r |
d9d77995 |
15 | // in/out address in r0, trashes all temp regs\r |
16 | static void CheckPc(void)\r |
6003a768 |
17 | {\r |
d9d77995 |
18 | #if USE_CHECKPC_CALLBACK\r |
19 | #ifdef MEMHANDLERS_DIRECT_PREFIX\r |
20 | ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r |
21 | #else\r |
22 | ot(";@ Check Memory Base+pc\n");\r |
23 | ot(" mov lr,pc\n");\r |
6003a768 |
24 | ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r |
6003a768 |
25 | ot("\n");\r |
d9d77995 |
26 | #endif\r |
27 | #endif\r |
6003a768 |
28 | }\r |
29 | \r |
d9d77995 |
30 | // Push 32-bit value in r1 - trashes r0-r3,r12,lr\r |
6003a768 |
31 | void OpPush32()\r |
32 | {\r |
33 | ot(";@ Push r1 onto stack\n");\r |
34 | ot(" ldr r0,[r7,#0x3c]\n");\r |
35 | ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r |
36 | ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r |
37 | MemHandler(1,2);\r |
38 | ot("\n");\r |
39 | }\r |
40 | \r |
d9d77995 |
41 | // Push SR - trashes r0-r3,r12,lr\r |
6003a768 |
42 | void OpPushSr(int high)\r |
43 | {\r |
44 | ot(";@ Push SR:\n");\r |
45 | OpFlagsToReg(high);\r |
46 | ot(" ldr r0,[r7,#0x3c]\n");\r |
47 | ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r |
48 | ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r |
49 | MemHandler(1,1);\r |
50 | ot("\n");\r |
51 | }\r |
52 | \r |
53 | // Pop SR - trashes r0-r3\r |
54 | static void PopSr(int high)\r |
55 | {\r |
56 | ot(";@ Pop SR:\n");\r |
57 | ot(" ldr r0,[r7,#0x3c]\n");\r |
58 | ot(" add r1,r0,#2 ;@ Postincrement A7\n");\r |
59 | ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r |
60 | MemHandler(0,1);\r |
61 | ot("\n");\r |
62 | OpRegToFlags(high);\r |
63 | }\r |
64 | \r |
d9d77995 |
65 | // Pop PC - trashes r0-r3\r |
6003a768 |
66 | static void PopPc()\r |
67 | {\r |
68 | ot(";@ Pop PC:\n");\r |
69 | ot(" ldr r0,[r7,#0x3c]\n");\r |
70 | ot(" add r1,r0,#4 ;@ Postincrement A7\n");\r |
71 | ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r |
72 | MemHandler(0,2);\r |
d9d77995 |
73 | ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r |
74 | ot(" add r0,r0,r1 ;@ Memory Base+PC\n");\r |
6003a768 |
75 | ot("\n");\r |
76 | CheckPc();\r |
d9d77995 |
77 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
78 | ot(" mov r4,r0\n");\r |
79 | #else\r |
80 | ot(" bic r4,r0,#1\n");\r |
81 | #endif\r |
6003a768 |
82 | }\r |
83 | \r |
84 | int OpTrap(int op)\r |
85 | {\r |
86 | int use=0;\r |
87 | \r |
88 | use=op&~0xf;\r |
89 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
90 | \r |
d9d77995 |
91 | OpStart(op,0x10);\r |
6003a768 |
92 | ot(" and r0,r8,#0xf ;@ Get trap number\n");\r |
d9d77995 |
93 | ot(" orr r0,r0,#0x20 ;@ 32+n\n");\r |
6003a768 |
94 | ot(" bl Exception\n");\r |
95 | ot("\n");\r |
96 | \r |
d9d77995 |
97 | Cycles=38; OpEnd(0x10);\r |
6003a768 |
98 | \r |
99 | return 0;\r |
100 | }\r |
101 | \r |
102 | // --------------------- Opcodes 0x4e50+ ---------------------\r |
103 | int OpLink(int op)\r |
104 | {\r |
d9d77995 |
105 | int use=0,reg;\r |
6003a768 |
106 | \r |
107 | use=op&~7;\r |
d9d77995 |
108 | reg=op&7;\r |
109 | if (reg==7) use=op;\r |
6003a768 |
110 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
111 | \r |
d9d77995 |
112 | OpStart(op,0x10);\r |
6003a768 |
113 | \r |
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114 | if(reg!=7) {\r |
115 | ot(";@ Get An\n");\r |
116 | EaCalc(11, 7, 8, 2, 1);\r |
117 | EaRead(11, 1, 8, 2, 7, 1);\r |
118 | }\r |
6003a768 |
119 | \r |
120 | ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r |
121 | ot(" sub r0,r0,#4 ;@ A7-=4\n");\r |
d9d77995 |
122 | ot(" mov r8,r0 ;@ abuse r8\n");\r |
123 | if(reg==7) ot(" mov r1,r0\n");\r |
6003a768 |
124 | ot("\n");\r |
125 | \r |
126 | ot(";@ Write An to Stack\n");\r |
127 | MemHandler(1,2);\r |
128 | \r |
129 | ot(";@ Save to An\n");\r |
d9d77995 |
130 | if(reg!=7)\r |
131 | EaWrite(11,8, 8, 2, 7, 1);\r |
6003a768 |
132 | \r |
133 | ot(";@ Get offset:\n");\r |
d9d77995 |
134 | EaCalc(0,0,0x3c,1); // abused r8 is ok because of imm EA\r |
135 | EaRead(0,0,0x3c,1,0);\r |
6003a768 |
136 | \r |
d9d77995 |
137 | ot(" add r8,r8,r0 ;@ Add offset to A7\n");\r |
138 | ot(" str r8,[r7,#0x3c]\n");\r |
6003a768 |
139 | ot("\n");\r |
140 | \r |
141 | Cycles=16;\r |
d9d77995 |
142 | OpEnd(0x10);\r |
6003a768 |
143 | return 0;\r |
144 | }\r |
145 | \r |
146 | // --------------------- Opcodes 0x4e58+ ---------------------\r |
147 | int OpUnlk(int op)\r |
148 | {\r |
149 | int use=0;\r |
150 | \r |
151 | use=op&~7;\r |
152 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
153 | \r |
d9d77995 |
154 | OpStart(op,0x10);\r |
6003a768 |
155 | \r |
156 | ot(";@ Get An\n");\r |
d9d77995 |
157 | EaCalc(11, 0xf, 8, 2, 1);\r |
158 | EaRead(11, 0, 8, 2, 0xf, 1);\r |
6003a768 |
159 | \r |
d9d77995 |
160 | ot(" add r8,r0,#4 ;@ A7+=4, abuse r8\n");\r |
6003a768 |
161 | ot("\n");\r |
162 | ot(";@ Pop An from stack:\n");\r |
163 | MemHandler(0,2);\r |
164 | ot("\n");\r |
d9d77995 |
165 | ot(" str r8,[r7,#0x3c] ;@ Save A7\n");\r |
6003a768 |
166 | ot("\n");\r |
167 | ot(";@ An = value from stack:\n");\r |
d9d77995 |
168 | EaWrite(11, 0, 8, 2, 7, 1);\r |
169 | \r |
6003a768 |
170 | Cycles=12;\r |
d9d77995 |
171 | OpEnd(0x10);\r |
6003a768 |
172 | return 0;\r |
173 | }\r |
174 | \r |
175 | // --------------------- Opcodes 0x4e70+ ---------------------\r |
d9d77995 |
176 | // 01001110 01110ttt\r |
6003a768 |
177 | int Op4E70(int op)\r |
178 | {\r |
179 | int type=0;\r |
180 | \r |
d9d77995 |
181 | type=op&7; // reset/nop/stop/rte/rtd/rts/trapv/rtr\r |
6003a768 |
182 | \r |
d9d77995 |
183 | switch (type)\r |
6003a768 |
184 | {\r |
d9d77995 |
185 | case 1: // nop\r |
186 | OpStart(op);\r |
187 | Cycles=4;\r |
6003a768 |
188 | OpEnd();\r |
189 | return 0;\r |
6003a768 |
190 | \r |
d9d77995 |
191 | case 3: // rte\r |
192 | OpStart(op,0x10,0,0,1); Cycles=20;\r |
193 | PopSr(1);\r |
6003a768 |
194 | PopPc();\r |
d9d77995 |
195 | ot(" ldr r1,[r7,#0x44] ;@ reload SR high\n");\r |
196 | SuperChange(op,1);\r |
197 | #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO || EMULATE_HALT\r |
198 | ot(" ldr r1,[r7,#0x58]\n");\r |
199 | ot(" bic r1,r1,#0x0c ;@ clear 'not processing instruction' and 'doing addr error' bits\n");\r |
200 | ot(" str r1,[r7,#0x58]\n");\r |
201 | #endif\r |
202 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
203 | ot(" tst r4,#1 ;@ address error?\n");\r |
204 | ot(" bne ExceptionAddressError_r_prg_r4\n");\r |
205 | #endif\r |
206 | opend_check_interrupt = 1;\r |
207 | opend_check_trace = 1;\r |
208 | OpEnd(0x10,0);\r |
209 | return 0;\r |
210 | \r |
211 | case 5: // rts\r |
212 | OpStart(op,0x10); Cycles=16;\r |
213 | PopPc();\r |
214 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
215 | ot(" tst r4,#1 ;@ address error?\n");\r |
216 | ot(" bne ExceptionAddressError_r_prg_r4\n");\r |
217 | #endif\r |
218 | OpEnd(0x10);\r |
219 | return 0;\r |
220 | \r |
221 | case 6: // trapv\r |
222 | OpStart(op,0x10,0,1); Cycles=4;\r |
223 | ot(" tst r10,#0x10000000\n");\r |
224 | ot(" subne r5,r5,#%i\n",34);\r |
225 | ot(" movne r0,#7 ;@ TRAPV exception\n");\r |
226 | ot(" blne Exception\n");\r |
227 | opend_op_changes_cycles = 1;\r |
228 | OpEnd(0x10,0);\r |
6003a768 |
229 | return 0;\r |
6003a768 |
230 | \r |
d9d77995 |
231 | case 7: // rtr\r |
232 | OpStart(op,0x10); Cycles=20;\r |
233 | PopSr(0);\r |
234 | PopPc();\r |
235 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
236 | ot(" tst r4,#1 ;@ address error?\n");\r |
237 | ot(" bne ExceptionAddressError_r_prg_r4\n");\r |
238 | #endif\r |
239 | OpEnd(0x10);\r |
240 | return 0;\r |
241 | \r |
242 | default:\r |
243 | return 1;\r |
244 | }\r |
6003a768 |
245 | }\r |
246 | \r |
247 | // --------------------- Opcodes 0x4e80+ ---------------------\r |
d9d77995 |
248 | // Emit a Jsr/Jmp opcode, 01001110 1meeeeee\r |
6003a768 |
249 | int OpJsr(int op)\r |
250 | {\r |
251 | int use=0;\r |
252 | int sea=0;\r |
253 | \r |
254 | sea=op&0x003f;\r |
255 | \r |
256 | // See if we can do this opcode:\r |
257 | if (EaCanRead(sea,-1)==0) return 1;\r |
258 | \r |
d9d77995 |
259 | use=OpBase(op,0);\r |
6003a768 |
260 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
261 | \r |
d9d77995 |
262 | OpStart(op,(op&0x40)?0:0x10);\r |
6003a768 |
263 | \r |
d9d77995 |
264 | ot(" ldr r11,[r7,#0x60] ;@ Get Memory base\n");\r |
6003a768 |
265 | ot("\n");\r |
d9d77995 |
266 | EaCalc(12,0x003f,sea,0);\r |
6003a768 |
267 | \r |
d9d77995 |
268 | ot(";@ Jump - Get new PC from r12\n");\r |
269 | ot(" add r0,r12,r11 ;@ Memory Base + New PC\n");\r |
270 | ot("\n");\r |
271 | CheckPc();\r |
272 | if (!(op&0x40))\r |
6003a768 |
273 | {\r |
d9d77995 |
274 | ot(" ldr r2,[r7,#0x3c]\n");\r |
275 | ot(" sub r1,r4,r11 ;@ r1 = Old PC\n");\r |
6003a768 |
276 | }\r |
d9d77995 |
277 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
278 | // jsr prefetches next instruction before pushing old PC,\r |
279 | // according to http://pasti.fxatari.com/68kdocs/68kPrefetch.html\r |
280 | ot(" mov r4,r0\n");\r |
281 | ot(" tst r4,#1 ;@ address error?\n");\r |
282 | ot(" bne ExceptionAddressError_r_prg_r4\n");\r |
283 | #else\r |
284 | ot(" bic r4,r0,#1\n");\r |
285 | #endif\r |
6003a768 |
286 | \r |
d9d77995 |
287 | if (!(op&0x40))\r |
288 | {\r |
289 | ot(";@ Push old PC onto stack\n");\r |
290 | ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r |
291 | ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r |
292 | MemHandler(1,2);\r |
6003a768 |
293 | }\r |
294 | \r |
d9d77995 |
295 | Cycles=(op&0x40) ? 4 : 12;\r |
296 | Cycles+=Ea_add_ns((op&0x40) ? g_jmp_cycle_table : g_jsr_cycle_table, sea);\r |
6003a768 |
297 | \r |
d9d77995 |
298 | OpEnd((op&0x40)?0:0x10);\r |
6003a768 |
299 | \r |
300 | return 0;\r |
301 | }\r |
302 | \r |
303 | // --------------------- Opcodes 0x50c8+ ---------------------\r |
304 | \r |
305 | // ARM version of 68000 condition codes:\r |
d9d77995 |
306 | static const char * const Cond[16]=\r |
6003a768 |
307 | {\r |
308 | "", "", "hi","ls","cc","cs","ne","eq",\r |
309 | "vc","vs","pl","mi","ge","lt","gt","le"\r |
310 | };\r |
311 | \r |
312 | // Emit a Dbra opcode, 0101cccc 11001nnn vv\r |
313 | int OpDbra(int op)\r |
314 | {\r |
315 | int use=0;\r |
316 | int cc=0;\r |
317 | \r |
318 | use=op&~7; // Use same handler\r |
319 | cc=(op>>8)&15;\r |
320 | \r |
321 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
d9d77995 |
322 | OpStart(op);\r |
6003a768 |
323 | \r |
d9d77995 |
324 | switch (cc)\r |
6003a768 |
325 | {\r |
d9d77995 |
326 | case 0: // T\r |
327 | case 1: // F\r |
328 | break;\r |
329 | case 2: // hi\r |
330 | ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r |
331 | ot(" beq DbraTrue\n\n");\r |
332 | break;\r |
333 | case 3: // ls\r |
334 | ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r |
335 | ot(" bne DbraTrue\n\n");\r |
336 | break;\r |
337 | default:\r |
338 | ot(";@ Is the condition true?\n");\r |
339 | ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r |
340 | ot(";@ If so, don't dbra\n");\r |
341 | ot(" b%s DbraTrue\n\n",Cond[cc]);\r |
342 | break;\r |
6003a768 |
343 | }\r |
344 | \r |
d9d77995 |
345 | if (cc!=0)\r |
346 | {\r |
347 | ot(";@ Decrement Dn.w\n");\r |
348 | ot(" and r1,r8,#0x0007\n");\r |
349 | ot(" mov r1,r1,lsl #2\n");\r |
350 | ot(" ldrsh r0,[r7,r1]\n");\r |
351 | ot(" sub r0,r0,#1\n");\r |
352 | ot(" strh r0,[r7,r1]\n");\r |
353 | ot("\n");\r |
6003a768 |
354 | \r |
d9d77995 |
355 | ot(";@ Check if Dn.w is -1\n");\r |
356 | ot(" cmn r0,#1\n");\r |
357 | \r |
358 | #if (USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA) || EMULATE_ADDRESS_ERRORS_JUMP\r |
359 | ot(" beq DbraMin1\n");\r |
360 | ot("\n");\r |
361 | \r |
362 | ot(";@ Get Branch offset:\n");\r |
363 | ot(" ldrsh r0,[r4]\n");\r |
364 | ot(" add r0,r4,r0 ;@ r0 = New PC\n");\r |
365 | CheckPc();\r |
366 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
367 | ot(" mov r4,r0\n");\r |
368 | ot(" tst r4,#1 ;@ address error?\n");\r |
369 | ot(" bne ExceptionAddressError_r_prg_r4\n");\r |
370 | #else\r |
371 | ot(" bic r4,r0,#1\n");\r |
372 | #endif\r |
373 | #else\r |
374 | ot("\n");\r |
375 | ot(";@ Get Branch offset:\n");\r |
376 | ot(" ldrnesh r0,[r4]\n");\r |
377 | ot(" addeq r4,r4,#2 ;@ Skip branch offset\n");\r |
378 | ot(" subeq r5,r5,#4 ;@ additional cycles\n");\r |
379 | ot(" addne r4,r4,r0 ;@ r4 = New PC\n");\r |
380 | ot(" bic r4,r4,#1\n"); // we do not emulate address errors\r |
381 | ot("\n");\r |
382 | #endif\r |
383 | Cycles=12-2;\r |
384 | OpEnd();\r |
385 | }\r |
6003a768 |
386 | \r |
d9d77995 |
387 | //if (cc==0||cc>=2)\r |
388 | if (op==0x50c8)\r |
389 | {\r |
390 | ot(";@ condition true:\n");\r |
391 | ot("DbraTrue%s\n", ms?"":":");\r |
392 | ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r |
393 | ot("\n");\r |
394 | Cycles=12;\r |
395 | OpEnd();\r |
396 | }\r |
397 | \r |
398 | #if (USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA) || EMULATE_ADDRESS_ERRORS_JUMP\r |
399 | if (op==0x51c8)\r |
400 | {\r |
401 | ot(";@ Dn.w is -1:\n");\r |
402 | ot("DbraMin1%s\n", ms?"":":");\r |
403 | ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r |
404 | ot("\n");\r |
405 | Cycles=12+2;\r |
406 | OpEnd();\r |
407 | }\r |
408 | #endif\r |
6003a768 |
409 | \r |
410 | return 0;\r |
411 | }\r |
412 | \r |
413 | // --------------------- Opcodes 0x6000+ ---------------------\r |
414 | // Emit a Branch opcode 0110cccc nn (cccc=condition)\r |
415 | int OpBranch(int op)\r |
416 | {\r |
d9d77995 |
417 | int size=0,use=0,checkpc=0;\r |
6003a768 |
418 | int offset=0;\r |
419 | int cc=0;\r |
d9d77995 |
420 | const char *asr_r11="";\r |
6003a768 |
421 | \r |
422 | offset=(char)(op&0xff);\r |
423 | cc=(op>>8)&15;\r |
424 | \r |
425 | // Special offsets:\r |
426 | if (offset==0) size=1;\r |
427 | if (offset==-1) size=2;\r |
428 | \r |
d9d77995 |
429 | if (size==2) size=0; // 000 model does not support long displacement\r |
6003a768 |
430 | if (size) use=op; // 16-bit or 32-bit\r |
431 | else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches\r |
432 | \r |
433 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
d9d77995 |
434 | OpStart(op,size?0x10:0);\r |
435 | Cycles=10; // Assume branch taken\r |
6003a768 |
436 | \r |
d9d77995 |
437 | switch (cc)\r |
6003a768 |
438 | {\r |
d9d77995 |
439 | case 0: // T\r |
440 | case 1: // F\r |
441 | break;\r |
442 | case 2: // hi\r |
443 | ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r |
444 | ot(" bne BccDontBranch%i\n\n",8<<size);\r |
445 | break;\r |
446 | case 3: // ls\r |
447 | ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r |
448 | ot(" beq BccDontBranch%i\n\n",8<<size);\r |
449 | break;\r |
450 | default:\r |
451 | ot(";@ Is the condition true?\n");\r |
452 | ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r |
453 | ot(" b%s BccDontBranch%i\n\n",Cond[cc^1],8<<size);\r |
454 | break;\r |
6003a768 |
455 | }\r |
456 | \r |
d9d77995 |
457 | if (size) \r |
6003a768 |
458 | {\r |
d9d77995 |
459 | if (size<2)\r |
460 | {\r |
461 | ot(" ldrsh r11,[r4] ;@ Fetch Branch offset\n");\r |
462 | }\r |
463 | else\r |
464 | {\r |
465 | ot(" ldrh r2,[r4] ;@ Fetch Branch offset\n");\r |
466 | ot(" ldrh r11,[r4,#2]\n");\r |
467 | ot(" orr r11,r11,r2,lsl #16\n");\r |
468 | }\r |
6003a768 |
469 | }\r |
470 | else\r |
471 | {\r |
d9d77995 |
472 | ot(" mov r11,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");\r |
473 | asr_r11=",asr #24";\r |
6003a768 |
474 | }\r |
475 | \r |
476 | ot(";@ Branch taken - Add on r0 to PC\n");\r |
477 | \r |
478 | if (cc==1)\r |
479 | {\r |
480 | ot(";@ Bsr - remember old PC\n");\r |
d9d77995 |
481 | ot(" ldr r12,[r7,#0x60] ;@ Get Memory base\n");\r |
482 | ot(" ldr r2,[r7,#0x3c]\n");\r |
483 | ot(" sub r1,r4,r12 ;@ r1 = Old PC\n");\r |
484 | if (size) ot(" add r1,r1,#%d\n",1<<size);\r |
6003a768 |
485 | ot("\n");\r |
d9d77995 |
486 | ot(";@ Push r1 onto stack\n");\r |
487 | ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r |
488 | ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r |
489 | MemHandler(1,2);\r |
6003a768 |
490 | ot("\n");\r |
d9d77995 |
491 | Cycles=18; // always 18\r |
6003a768 |
492 | }\r |
493 | \r |
d9d77995 |
494 | ot(" add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r |
495 | \r |
496 | #if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8\r |
497 | if (offset!=0 && offset!=-1) checkpc=1;\r |
498 | #endif\r |
499 | #if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_16\r |
500 | if (offset==0) checkpc=1;\r |
501 | #endif\r |
502 | #if USE_CHECKPC_CALLBACK\r |
503 | if (offset==-1) checkpc=1;\r |
504 | #endif\r |
505 | if (checkpc) CheckPc();\r |
506 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
507 | ot(" mov r4,r0\n");\r |
508 | ot(" tst r4,#1 ;@ address error?\n");\r |
509 | ot(" bne ExceptionAddressError_r_prg_r4\n");\r |
510 | #else\r |
511 | ot(" bic r4,r0,#1\n");\r |
512 | #endif\r |
513 | ot("\n");\r |
6003a768 |
514 | \r |
d9d77995 |
515 | OpEnd(size?0x10:0);\r |
6003a768 |
516 | \r |
d9d77995 |
517 | // since all "DontBranch" code is same for every size, output only once\r |
518 | if (cc>=2&&(op&0xff00)==0x6700)\r |
6003a768 |
519 | {\r |
d9d77995 |
520 | ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");\r |
521 | if (size) ot(" add r4,r4,#%d\n",1<<size);\r |
522 | Cycles+=(size==1) ? 2 : -2; // Branch not taken\r |
523 | OpEnd(0);\r |
6003a768 |
524 | }\r |
525 | \r |
526 | return 0;\r |
527 | }\r |
528 | \r |