f27b1cea |
1 | /* |
f89d8471 |
2 | * (C) GraÅžvydas "notaz" Ignotas, 2009-2010 |
3 | * |
4 | * This work is licensed under the terms of any of these licenses |
5 | * (at your option): |
6 | * - GNU GPL, version 2 or later. |
7 | * - GNU LGPL, version 2.1 or later. |
8 | * - MAME license. |
9 | * See the COPYING file in the top-level directory. |
10 | * |
f27b1cea |
11 | * <random_info=mem_map> |
12 | * 00000000-029fffff linux (42MB) |
13 | * 02a00000-02dfffff fb (4MB, 153600B really used) |
14 | * 02e00000-02ffffff sound dma (2MB) |
15 | * 03000000-03ffffff MPEGDEC (?, 16MB) |
16 | * </random_info> |
17 | */ |
f89d8471 |
18 | |
fa8d1331 |
19 | #include <stdio.h> |
20 | #include <stdlib.h> |
21 | #include <string.h> |
fa8d1331 |
22 | #include <sys/types.h> |
23 | #include <sys/stat.h> |
24 | #include <fcntl.h> |
25 | #include <sys/mman.h> |
26 | #include <unistd.h> |
27 | #include <sys/ioctl.h> |
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28 | #include <linux/soundcard.h> |
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29 | |
30 | #include "soc.h" |
31 | #include "plat_gp2x.h" |
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32 | #include "pollux_set.h" |
a86e9a3e |
33 | #include "../plat.h" |
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34 | |
afdbb7c8 |
35 | static int battdev = -1, mixerdev = -1; |
36 | static int cpu_clock_allowed; |
9a5a0dc9 |
37 | static unsigned short saved_memtimex[2]; |
afdbb7c8 |
38 | static unsigned int saved_video_regs[2][6]; |
7ceadd99 |
39 | static unsigned int timer_drift; // count per real second |
afdbb7c8 |
40 | |
41 | #ifndef ARRAY_SIZE |
42 | #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) |
43 | #endif |
44 | |
7ceadd99 |
45 | /* note: both PLLs are programmed the same way, |
46 | * the databook incorrectly states that PLL1 differs */ |
47 | static int decode_pll(unsigned int reg) |
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48 | { |
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49 | long long v; |
50 | int p, m, s; |
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51 | |
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52 | p = (reg >> 18) & 0x3f; |
53 | m = (reg >> 8) & 0x3ff; |
54 | s = reg & 0xff; |
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55 | |
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56 | if (p == 0) |
57 | p = 1; |
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58 | |
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59 | v = 27000000; // master clock |
60 | v = v * m / (p << s); |
61 | return v; |
fa8d1331 |
62 | } |
63 | |
9a5a0dc9 |
64 | /* RAM timings */ |
65 | static void set_ram_timings(void) |
66 | { |
67 | pollux_set_fromenv(memregs, "POLLUX_RAM_TIMINGS"); |
68 | } |
69 | |
70 | static void unset_ram_timings(void) |
71 | { |
72 | int i; |
73 | |
74 | memregs[0x14802>>1] = saved_memtimex[0]; |
75 | memregs[0x14804>>1] = saved_memtimex[1] | 0x8000; |
76 | |
77 | for (i = 0; i < 0x100000; i++) |
78 | if (!(memregs[0x14804>>1] & 0x8000)) |
79 | break; |
80 | |
81 | printf("RAM timings reset to startup values.\n"); |
82 | } |
83 | |
7ceadd99 |
84 | #define TIMER_BASE3 0x1980 |
85 | #define TIMER_REG(x) memregl[(TIMER_BASE3 + x) >> 2] |
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86 | |
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87 | static unsigned int gp2x_get_ticks_us_(void) |
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88 | { |
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89 | unsigned int div = TIMER_REG(0x08) & 3; |
90 | TIMER_REG(0x08) = 0x48 | div; /* run timer, latch value */ |
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91 | return TIMER_REG(0); |
fa8d1331 |
92 | } |
93 | |
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94 | static unsigned int gp2x_get_ticks_ms_(void) |
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95 | { |
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96 | /* approximate /= 1000 */ |
97 | unsigned long long v64; |
98 | v64 = (unsigned long long)gp2x_get_ticks_us_() * 4294968; |
99 | return v64 >> 32; |
fa8d1331 |
100 | } |
101 | |
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102 | static void timer_cleanup(void) |
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103 | { |
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104 | TIMER_REG(0x40) = 0x0c; /* be sure clocks are on */ |
105 | TIMER_REG(0x08) = 0x23; /* stop the timer, clear irq in case it's pending */ |
106 | TIMER_REG(0x00) = 0; /* clear counter */ |
107 | TIMER_REG(0x40) = 0; /* clocks off */ |
108 | TIMER_REG(0x44) = 0; /* dividers back to default */ |
fa8d1331 |
109 | } |
110 | |
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111 | static void save_multiple_regs(unsigned int *dest, int base, int count) |
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112 | { |
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113 | const volatile unsigned int *regs = memregl + base / 4; |
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114 | int i; |
115 | |
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116 | for (i = 0; i < count; i++) |
117 | dest[i] = regs[i]; |
053bef76 |
118 | } |
119 | |
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120 | static void restore_multiple_regs(int base, const unsigned int *src, int count) |
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121 | { |
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122 | volatile unsigned int *regs = memregl + base / 4; |
123 | int i; |
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124 | |
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125 | for (i = 0; i < count; i++) |
126 | regs[i] = src[i]; |
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127 | } |
128 | |
f679add7 |
129 | int pollux_get_real_snd_rate(int req_rate) |
130 | { |
131 | int clk0_src, clk1_src, rate, div; |
132 | |
133 | clk0_src = (memregl[0xdbc4>>2] >> 1) & 7; |
134 | clk1_src = (memregl[0xdbc8>>2] >> 1) & 7; |
135 | if (clk0_src > 1 || clk1_src != 7) { |
136 | fprintf(stderr, "get_real_snd_rate: bad clk sources: %d %d\n", clk0_src, clk1_src); |
137 | return req_rate; |
138 | } |
139 | |
140 | rate = decode_pll(clk0_src ? memregl[0xf008>>2] : memregl[0xf004>>2]); |
141 | |
142 | // apply divisors |
11166a22 |
143 | div = ((memregl[0xdbc4>>2] >> 4) & 0x3f) + 1; |
f679add7 |
144 | rate /= div; |
11166a22 |
145 | div = ((memregl[0xdbc8>>2] >> 4) & 0x3f) + 1; |
f679add7 |
146 | rate /= div; |
147 | rate /= 64; |
148 | |
149 | //printf("rate %d\n", rate); |
150 | rate -= rate * timer_drift / 1000000; |
151 | printf("adjusted rate: %d\n", rate); |
152 | |
153 | if (rate < 8000-1000 || rate > 44100+1000) { |
154 | fprintf(stderr, "get_real_snd_rate: got bad rate: %d\n", rate); |
155 | return req_rate; |
156 | } |
157 | |
158 | return rate; |
159 | } |
160 | |
afdbb7c8 |
161 | /* newer API */ |
162 | static int pollux_cpu_clock_get(void) |
163 | { |
164 | return decode_pll(memregl[0xf004>>2]) / 1000000; |
165 | } |
166 | |
167 | int pollux_cpu_clock_set(int mhz) |
168 | { |
169 | int adiv, mdiv, pdiv, sdiv = 0; |
170 | int i, vf000, vf004; |
171 | |
172 | if (!cpu_clock_allowed) |
173 | return -1; |
174 | if (mhz == pollux_cpu_clock_get()) |
175 | return 0; |
176 | |
177 | // m = MDIV, p = PDIV, s = SDIV |
178 | #define SYS_CLK_FREQ 27 |
179 | pdiv = 9; |
180 | mdiv = (mhz * pdiv) / SYS_CLK_FREQ; |
181 | if (mdiv & ~0x3ff) |
182 | return -1; |
183 | vf004 = (pdiv<<18) | (mdiv<<8) | sdiv; |
184 | |
185 | // attempt to keep the AHB divider close to 250, but not higher |
186 | for (adiv = 1; mhz / adiv > 250; adiv++) |
187 | ; |
188 | |
189 | vf000 = memregl[0xf000>>2]; |
190 | vf000 = (vf000 & ~0x3c0) | ((adiv - 1) << 6); |
191 | memregl[0xf000>>2] = vf000; |
192 | memregl[0xf004>>2] = vf004; |
193 | memregl[0xf07c>>2] |= 0x8000; |
194 | for (i = 0; (memregl[0xf07c>>2] & 0x8000) && i < 0x100000; i++) |
195 | ; |
196 | |
197 | printf("clock set to %dMHz, AHB set to %dMHz\n", mhz, mhz / adiv); |
198 | return 0; |
199 | } |
200 | |
201 | static int pollux_bat_capacity_get(void) |
202 | { |
203 | unsigned short magic_val = 0; |
204 | |
205 | if (battdev < 0) |
206 | return -1; |
207 | if (read(battdev, &magic_val, sizeof(magic_val)) != sizeof(magic_val)) |
208 | return -1; |
209 | switch (magic_val) { |
210 | default: |
211 | case 1: return 100; |
212 | case 2: return 66; |
213 | case 3: return 40; |
214 | case 4: return 0; |
215 | } |
216 | } |
217 | |
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218 | static int step_volume(int *volume, int diff) |
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219 | { |
afdbb7c8 |
220 | int ret, val; |
221 | |
222 | if (mixerdev < 0) |
223 | return -1; |
224 | |
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225 | *volume += diff; |
226 | if (*volume > 255) |
227 | *volume = 255; |
228 | else if (*volume < 0) |
229 | *volume = 0; |
230 | |
231 | val = *volume; |
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232 | val |= val << 8; |
233 | |
234 | ret = ioctl(mixerdev, SOUND_MIXER_WRITE_PCM, &val); |
7ceadd99 |
235 | if (ret == -1) { |
afdbb7c8 |
236 | perror("WRITE_PCM"); |
7ceadd99 |
237 | return ret; |
238 | } |
afdbb7c8 |
239 | |
7ceadd99 |
240 | return 0; |
afdbb7c8 |
241 | } |
242 | |
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243 | void pollux_init(void) |
afdbb7c8 |
244 | { |
245 | int rate, timer_div, timer_div2; |
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246 | |
247 | memdev = open("/dev/mem", O_RDWR); |
248 | if (memdev == -1) { |
249 | perror("open(/dev/mem) failed"); |
250 | exit(1); |
251 | } |
252 | |
253 | memregs = mmap(0, 0x20000, PROT_READ|PROT_WRITE, MAP_SHARED, |
254 | memdev, 0xc0000000); |
255 | if (memregs == MAP_FAILED) { |
256 | perror("mmap(memregs) failed"); |
257 | exit(1); |
258 | } |
259 | memregl = (volatile void *)memregs; |
260 | |
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261 | saved_memtimex[0] = memregs[0x14802>>1]; |
262 | saved_memtimex[1] = memregs[0x14804>>1]; |
263 | |
264 | set_ram_timings(); |
265 | |
afdbb7c8 |
266 | // save video regs of both MLCs |
267 | save_multiple_regs(saved_video_regs[0], 0x4058, ARRAY_SIZE(saved_video_regs[0])); |
268 | save_multiple_regs(saved_video_regs[1], 0x4458, ARRAY_SIZE(saved_video_regs[1])); |
269 | |
270 | /* some firmwares have sys clk on PLL0, we can't adjust CPU clock |
271 | * by reprogramming the PLL0 then, as it overclocks system bus */ |
272 | if ((memregl[0xf000>>2] & 0x03000030) == 0x01000000) |
273 | cpu_clock_allowed = 1; |
274 | else { |
275 | cpu_clock_allowed = 0; |
276 | fprintf(stderr, "unexpected PLL config (%08x), overclocking disabled\n", |
277 | memregl[0xf000>>2]); |
278 | } |
279 | |
280 | /* find what PLL1 runs at, for the timer */ |
281 | rate = decode_pll(memregl[0xf008>>2]); |
282 | printf("PLL1 @ %dHz\n", rate); |
283 | |
284 | /* setup timer */ |
285 | timer_div = (rate + 500000) / 1000000; |
286 | timer_div2 = 0; |
287 | while (timer_div > 256) { |
288 | timer_div /= 2; |
289 | timer_div2++; |
290 | } |
291 | if (1 <= timer_div && timer_div <= 256 && timer_div2 < 4) { |
292 | int timer_rate = (rate >> timer_div2) / timer_div; |
293 | if (TIMER_REG(0x08) & 8) { |
294 | fprintf(stderr, "warning: timer in use, overriding!\n"); |
295 | timer_cleanup(); |
296 | } |
7ceadd99 |
297 | timer_drift = timer_rate - 1000000; |
298 | if (timer_drift != 0) |
299 | fprintf(stderr, "warning: timer drift %d us\n", |
300 | timer_drift); |
afdbb7c8 |
301 | |
302 | timer_div2 = (timer_div2 + 3) & 3; |
303 | TIMER_REG(0x44) = ((timer_div - 1) << 4) | 2; /* using PLL1 */ |
304 | TIMER_REG(0x40) = 0x0c; /* clocks on */ |
305 | TIMER_REG(0x08) = 0x68 | timer_div2; /* run timer, clear irq, latch value */ |
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306 | |
307 | gp2x_get_ticks_ms = gp2x_get_ticks_ms_; |
308 | gp2x_get_ticks_us = gp2x_get_ticks_us_; |
afdbb7c8 |
309 | } |
7ceadd99 |
310 | else { |
afdbb7c8 |
311 | fprintf(stderr, "warning: could not make use of timer\n"); |
312 | |
7ceadd99 |
313 | // those functions are actually not good at all on Wiz kernel |
314 | gp2x_get_ticks_ms = plat_get_ticks_ms_good; |
315 | gp2x_get_ticks_us = plat_get_ticks_us_good; |
316 | } |
317 | |
afdbb7c8 |
318 | battdev = open("/dev/pollux_batt", O_RDONLY); |
319 | if (battdev < 0) |
320 | perror("Warning: could't open pollux_batt"); |
321 | |
afdbb7c8 |
322 | mixerdev = open("/dev/mixer", O_RDWR); |
323 | if (mixerdev == -1) |
324 | perror("open(/dev/mixer)"); |
325 | |
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326 | plat_target.cpu_clock_get = pollux_cpu_clock_get; |
327 | plat_target.cpu_clock_set = pollux_cpu_clock_set; |
328 | plat_target.bat_capacity_get = pollux_bat_capacity_get; |
329 | plat_target.step_volume = step_volume; |
afdbb7c8 |
330 | } |
d572cbad |
331 | |
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332 | void pollux_finish(void) |
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333 | { |
334 | timer_cleanup(); |
335 | |
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336 | unset_ram_timings(); |
337 | |
afdbb7c8 |
338 | restore_multiple_regs(0x4058, saved_video_regs[0], |
339 | ARRAY_SIZE(saved_video_regs[0])); |
340 | restore_multiple_regs(0x4458, saved_video_regs[1], |
341 | ARRAY_SIZE(saved_video_regs[1])); |
342 | memregl[0x4058>>2] |= 0x10; |
343 | memregl[0x4458>>2] |= 0x10; |
344 | |
345 | if (battdev >= 0) |
346 | close(battdev); |
347 | if (mixerdev >= 0) |
348 | close(mixerdev); |
349 | munmap((void *)memregs, 0x20000); |
350 | close(memdev); |
351 | } |