Commit | Line | Data |
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6f1edc3c PC |
1 | #include <lightrec.h> |
2 | #include <stdbool.h> | |
3 | #include <stdio.h> | |
4 | #include <unistd.h> | |
5 | #include <signal.h> | |
c174cf6a | 6 | #include <assert.h> |
6f1edc3c PC |
7 | |
8 | #include "../cdrom.h" | |
9 | #include "../gpu.h" | |
10 | #include "../gte.h" | |
11 | #include "../mdec.h" | |
12 | #include "../psxdma.h" | |
13 | #include "../psxhw.h" | |
14 | #include "../psxmem.h" | |
15 | #include "../r3000a.h" | |
f2100c3d | 16 | #include "../psxinterpreter.h" |
6c62131f | 17 | #include "../new_dynarec/events.h" |
6f1edc3c PC |
18 | |
19 | #include "../frontend/main.h" | |
20 | ||
f8548105 | 21 | #include "mem.h" |
70939d49 | 22 | #include "plugin.h" |
f8548105 | 23 | |
46a38bda | 24 | #if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM) |
25 | #error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)" | |
26 | #endif | |
27 | ||
6f1edc3c PC |
28 | #define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0) |
29 | ||
30 | #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ | |
31 | # define LE32TOH(x) __builtin_bswap32(x) | |
32 | # define HTOLE32(x) __builtin_bswap32(x) | |
33 | # define LE16TOH(x) __builtin_bswap16(x) | |
34 | # define HTOLE16(x) __builtin_bswap16(x) | |
35 | #else | |
36 | # define LE32TOH(x) (x) | |
37 | # define HTOLE32(x) (x) | |
38 | # define LE16TOH(x) (x) | |
39 | # define HTOLE16(x) (x) | |
40 | #endif | |
41 | ||
42 | #ifdef __GNUC__ | |
43 | # define likely(x) __builtin_expect(!!(x),1) | |
44 | # define unlikely(x) __builtin_expect(!!(x),0) | |
45 | #else | |
46 | # define likely(x) (x) | |
47 | # define unlikely(x) (x) | |
48 | #endif | |
49 | ||
630b122b | 50 | psxRegisters psxRegs; |
51 | Rcnt rcnts[4]; | |
52 | ||
6f1edc3c PC |
53 | static struct lightrec_state *lightrec_state; |
54 | ||
55 | static char *name = "retroarch.exe"; | |
56 | ||
57 | static bool use_lightrec_interpreter; | |
6b02f240 | 58 | static bool use_pcsx_interpreter; |
6c62131f | 59 | static bool block_stepping; |
c174cf6a | 60 | static u32 cycle_mult_to_pcsx; // 22.10 fractional |
61 | static u32 cycle_mult_from_pcsx; | |
6f1edc3c | 62 | |
6f1edc3c PC |
63 | enum my_cp2_opcodes { |
64 | OP_CP2_RTPS = 0x01, | |
65 | OP_CP2_NCLIP = 0x06, | |
66 | OP_CP2_OP = 0x0c, | |
67 | OP_CP2_DPCS = 0x10, | |
68 | OP_CP2_INTPL = 0x11, | |
69 | OP_CP2_MVMVA = 0x12, | |
70 | OP_CP2_NCDS = 0x13, | |
71 | OP_CP2_CDP = 0x14, | |
72 | OP_CP2_NCDT = 0x16, | |
73 | OP_CP2_NCCS = 0x1b, | |
74 | OP_CP2_CC = 0x1c, | |
75 | OP_CP2_NCS = 0x1e, | |
76 | OP_CP2_NCT = 0x20, | |
77 | OP_CP2_SQR = 0x28, | |
78 | OP_CP2_DCPL = 0x29, | |
79 | OP_CP2_DPCT = 0x2a, | |
80 | OP_CP2_AVSZ3 = 0x2d, | |
81 | OP_CP2_AVSZ4 = 0x2e, | |
82 | OP_CP2_RTPT = 0x30, | |
83 | OP_CP2_GPF = 0x3d, | |
84 | OP_CP2_GPL = 0x3e, | |
85 | OP_CP2_NCCT = 0x3f, | |
86 | }; | |
87 | ||
88 | static void (*cp2_ops[])(struct psxCP2Regs *) = { | |
89 | [OP_CP2_RTPS] = gteRTPS, | |
90 | [OP_CP2_RTPS] = gteRTPS, | |
91 | [OP_CP2_NCLIP] = gteNCLIP, | |
92 | [OP_CP2_OP] = gteOP, | |
93 | [OP_CP2_DPCS] = gteDPCS, | |
94 | [OP_CP2_INTPL] = gteINTPL, | |
95 | [OP_CP2_MVMVA] = gteMVMVA, | |
96 | [OP_CP2_NCDS] = gteNCDS, | |
97 | [OP_CP2_CDP] = gteCDP, | |
98 | [OP_CP2_NCDT] = gteNCDT, | |
99 | [OP_CP2_NCCS] = gteNCCS, | |
100 | [OP_CP2_CC] = gteCC, | |
101 | [OP_CP2_NCS] = gteNCS, | |
102 | [OP_CP2_NCT] = gteNCT, | |
103 | [OP_CP2_SQR] = gteSQR, | |
104 | [OP_CP2_DCPL] = gteDCPL, | |
105 | [OP_CP2_DPCT] = gteDPCT, | |
106 | [OP_CP2_AVSZ3] = gteAVSZ3, | |
107 | [OP_CP2_AVSZ4] = gteAVSZ4, | |
108 | [OP_CP2_RTPT] = gteRTPT, | |
109 | [OP_CP2_GPF] = gteGPF, | |
110 | [OP_CP2_GPL] = gteGPL, | |
111 | [OP_CP2_NCCT] = gteNCCT, | |
112 | }; | |
113 | ||
114 | static char cache_buf[64 * 1024]; | |
115 | ||
0733c3ab | 116 | static void cop2_op(struct lightrec_state *state, u32 func) |
6f1edc3c | 117 | { |
0733c3ab | 118 | struct lightrec_registers *regs = lightrec_get_registers(state); |
6f1edc3c | 119 | |
0733c3ab | 120 | psxRegs.code = func; |
6f1edc3c | 121 | |
0733c3ab PC |
122 | if (unlikely(!cp2_ops[func & 0x3f])) { |
123 | fprintf(stderr, "Invalid CP2 function %u\n", func); | |
124 | } else { | |
125 | /* This works because regs->cp2c comes right after regs->cp2d, | |
126 | * so it can be cast to a pcsxCP2Regs pointer. */ | |
127 | cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d); | |
128 | } | |
6f1edc3c PC |
129 | } |
130 | ||
2bf88032 PC |
131 | static bool has_interrupt(void) |
132 | { | |
6ce0b00a PC |
133 | struct lightrec_registers *regs = lightrec_get_registers(lightrec_state); |
134 | ||
2bf88032 | 135 | return ((psxHu32(0x1070) & psxHu32(0x1074)) && |
6ce0b00a PC |
136 | (regs->cp0[12] & 0x401) == 0x401) || |
137 | (regs->cp0[12] & regs->cp0[13] & 0x0300); | |
2bf88032 PC |
138 | } |
139 | ||
c174cf6a | 140 | static u32 cycles_pcsx_to_lightrec(u32 c) |
f4f9f2a4 | 141 | { |
c174cf6a | 142 | assert((u64)c * cycle_mult_from_pcsx <= (u32)-1); |
143 | return c * cycle_mult_from_pcsx >> 10; | |
144 | } | |
2bf88032 | 145 | |
c174cf6a | 146 | static void lightrec_tansition_to_pcsx(struct lightrec_state *state) |
147 | { | |
148 | psxRegs.cycle += lightrec_current_cycle_count(state) * cycle_mult_to_pcsx >> 10; | |
149 | lightrec_reset_cycle_count(state, 0); | |
150 | } | |
151 | ||
152 | static void lightrec_tansition_from_pcsx(struct lightrec_state *state) | |
153 | { | |
154 | s32 cycles_left = next_interupt - psxRegs.cycle; | |
155 | ||
156 | if (block_stepping || cycles_left <= 0 || has_interrupt()) | |
2bf88032 | 157 | lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT); |
c174cf6a | 158 | else { |
159 | lightrec_set_target_cycle_count(state, | |
160 | cycles_pcsx_to_lightrec(cycles_left)); | |
161 | } | |
f4f9f2a4 PC |
162 | } |
163 | ||
6b02f240 | 164 | static void hw_write_byte(struct lightrec_state *state, |
165 | u32 op, void *host, u32 mem, u8 val) | |
6f1edc3c | 166 | { |
c174cf6a | 167 | lightrec_tansition_to_pcsx(state); |
6f1edc3c PC |
168 | |
169 | psxHwWrite8(mem, val); | |
6f1edc3c | 170 | |
c174cf6a | 171 | lightrec_tansition_from_pcsx(state); |
6f1edc3c PC |
172 | } |
173 | ||
6b02f240 | 174 | static void hw_write_half(struct lightrec_state *state, |
175 | u32 op, void *host, u32 mem, u16 val) | |
6f1edc3c | 176 | { |
c174cf6a | 177 | lightrec_tansition_to_pcsx(state); |
6f1edc3c PC |
178 | |
179 | psxHwWrite16(mem, val); | |
6f1edc3c | 180 | |
c174cf6a | 181 | lightrec_tansition_from_pcsx(state); |
6f1edc3c PC |
182 | } |
183 | ||
6b02f240 | 184 | static void hw_write_word(struct lightrec_state *state, |
185 | u32 op, void *host, u32 mem, u32 val) | |
6f1edc3c | 186 | { |
c174cf6a | 187 | lightrec_tansition_to_pcsx(state); |
6f1edc3c PC |
188 | |
189 | psxHwWrite32(mem, val); | |
6f1edc3c | 190 | |
c174cf6a | 191 | lightrec_tansition_from_pcsx(state); |
6f1edc3c PC |
192 | } |
193 | ||
6b02f240 | 194 | static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem) |
6f1edc3c PC |
195 | { |
196 | u8 val; | |
197 | ||
c174cf6a | 198 | lightrec_tansition_to_pcsx(state); |
6f1edc3c | 199 | |
6f1edc3c | 200 | val = psxHwRead8(mem); |
f4f9f2a4 | 201 | |
c174cf6a | 202 | lightrec_tansition_from_pcsx(state); |
6f1edc3c PC |
203 | |
204 | return val; | |
205 | } | |
206 | ||
6b02f240 | 207 | static u16 hw_read_half(struct lightrec_state *state, |
208 | u32 op, void *host, u32 mem) | |
6f1edc3c PC |
209 | { |
210 | u16 val; | |
211 | ||
c174cf6a | 212 | lightrec_tansition_to_pcsx(state); |
6f1edc3c | 213 | |
6f1edc3c | 214 | val = psxHwRead16(mem); |
f4f9f2a4 | 215 | |
c174cf6a | 216 | lightrec_tansition_from_pcsx(state); |
6f1edc3c PC |
217 | |
218 | return val; | |
219 | } | |
220 | ||
6b02f240 | 221 | static u32 hw_read_word(struct lightrec_state *state, |
222 | u32 op, void *host, u32 mem) | |
6f1edc3c PC |
223 | { |
224 | u32 val; | |
225 | ||
c174cf6a | 226 | lightrec_tansition_to_pcsx(state); |
6f1edc3c | 227 | |
6f1edc3c | 228 | val = psxHwRead32(mem); |
f4f9f2a4 | 229 | |
c174cf6a | 230 | lightrec_tansition_from_pcsx(state); |
6f1edc3c PC |
231 | |
232 | return val; | |
233 | } | |
234 | ||
235 | static struct lightrec_mem_map_ops hw_regs_ops = { | |
236 | .sb = hw_write_byte, | |
237 | .sh = hw_write_half, | |
238 | .sw = hw_write_word, | |
239 | .lb = hw_read_byte, | |
240 | .lh = hw_read_half, | |
241 | .lw = hw_read_word, | |
242 | }; | |
243 | ||
244 | static u32 cache_ctrl; | |
245 | ||
6b02f240 | 246 | static void cache_ctrl_write_word(struct lightrec_state *state, |
247 | u32 op, void *host, u32 mem, u32 val) | |
6f1edc3c PC |
248 | { |
249 | cache_ctrl = val; | |
250 | } | |
251 | ||
6b02f240 | 252 | static u32 cache_ctrl_read_word(struct lightrec_state *state, |
253 | u32 op, void *host, u32 mem) | |
6f1edc3c PC |
254 | { |
255 | return cache_ctrl; | |
256 | } | |
257 | ||
258 | static struct lightrec_mem_map_ops cache_ctrl_ops = { | |
259 | .sw = cache_ctrl_write_word, | |
260 | .lw = cache_ctrl_read_word, | |
261 | }; | |
262 | ||
263 | static struct lightrec_mem_map lightrec_map[] = { | |
264 | [PSX_MAP_KERNEL_USER_RAM] = { | |
265 | /* Kernel and user memory */ | |
266 | .pc = 0x00000000, | |
267 | .length = 0x200000, | |
268 | }, | |
269 | [PSX_MAP_BIOS] = { | |
270 | /* BIOS */ | |
271 | .pc = 0x1fc00000, | |
272 | .length = 0x80000, | |
273 | }, | |
274 | [PSX_MAP_SCRATCH_PAD] = { | |
275 | /* Scratch pad */ | |
276 | .pc = 0x1f800000, | |
277 | .length = 0x400, | |
278 | }, | |
279 | [PSX_MAP_PARALLEL_PORT] = { | |
280 | /* Parallel port */ | |
281 | .pc = 0x1f000000, | |
282 | .length = 0x10000, | |
283 | }, | |
284 | [PSX_MAP_HW_REGISTERS] = { | |
285 | /* Hardware registers */ | |
286 | .pc = 0x1f801000, | |
287 | .length = 0x2000, | |
288 | .ops = &hw_regs_ops, | |
289 | }, | |
290 | [PSX_MAP_CACHE_CONTROL] = { | |
291 | /* Cache control */ | |
292 | .pc = 0x5ffe0130, | |
293 | .length = 4, | |
294 | .ops = &cache_ctrl_ops, | |
295 | }, | |
296 | ||
297 | /* Mirrors of the kernel/user memory */ | |
298 | [PSX_MAP_MIRROR1] = { | |
299 | .pc = 0x00200000, | |
300 | .length = 0x200000, | |
301 | .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM], | |
302 | }, | |
303 | [PSX_MAP_MIRROR2] = { | |
304 | .pc = 0x00400000, | |
305 | .length = 0x200000, | |
306 | .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM], | |
307 | }, | |
308 | [PSX_MAP_MIRROR3] = { | |
309 | .pc = 0x00600000, | |
310 | .length = 0x200000, | |
311 | .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM], | |
312 | }, | |
f8548105 PC |
313 | [PSX_MAP_CODE_BUFFER] = { |
314 | .length = CODE_BUFFER_SIZE, | |
315 | }, | |
6f1edc3c PC |
316 | }; |
317 | ||
0733c3ab PC |
318 | static void lightrec_enable_ram(struct lightrec_state *state, bool enable) |
319 | { | |
320 | if (enable) | |
321 | memcpy(psxM, cache_buf, sizeof(cache_buf)); | |
322 | else | |
323 | memcpy(cache_buf, psxM, sizeof(cache_buf)); | |
324 | } | |
325 | ||
ba3814c1 PC |
326 | static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size) |
327 | { | |
328 | switch (size) { | |
329 | case 8: | |
330 | switch (kaddr) { | |
331 | case 0x1f801040: | |
332 | case 0x1f801050: | |
333 | case 0x1f801800: | |
334 | case 0x1f801801: | |
335 | case 0x1f801802: | |
336 | case 0x1f801803: | |
337 | return false; | |
338 | default: | |
339 | return true; | |
340 | } | |
341 | case 16: | |
342 | switch (kaddr) { | |
343 | case 0x1f801040: | |
344 | case 0x1f801044: | |
345 | case 0x1f801048: | |
346 | case 0x1f80104a: | |
347 | case 0x1f80104e: | |
348 | case 0x1f801050: | |
349 | case 0x1f801054: | |
350 | case 0x1f80105a: | |
351 | case 0x1f80105e: | |
352 | case 0x1f801100: | |
353 | case 0x1f801104: | |
354 | case 0x1f801108: | |
355 | case 0x1f801110: | |
356 | case 0x1f801114: | |
357 | case 0x1f801118: | |
358 | case 0x1f801120: | |
359 | case 0x1f801124: | |
360 | case 0x1f801128: | |
361 | return false; | |
362 | case 0x1f801070: | |
363 | case 0x1f801074: | |
364 | return !is_write; | |
365 | default: | |
cdfa3536 | 366 | return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00; |
ba3814c1 PC |
367 | } |
368 | default: | |
369 | switch (kaddr) { | |
370 | case 0x1f801040: | |
371 | case 0x1f801050: | |
372 | case 0x1f801100: | |
373 | case 0x1f801104: | |
374 | case 0x1f801108: | |
375 | case 0x1f801110: | |
376 | case 0x1f801114: | |
377 | case 0x1f801118: | |
378 | case 0x1f801120: | |
379 | case 0x1f801124: | |
380 | case 0x1f801128: | |
381 | case 0x1f801810: | |
382 | case 0x1f801814: | |
383 | case 0x1f801820: | |
384 | case 0x1f801824: | |
385 | return false; | |
386 | case 0x1f801070: | |
387 | case 0x1f801074: | |
388 | case 0x1f801088: | |
389 | case 0x1f801098: | |
390 | case 0x1f8010a8: | |
391 | case 0x1f8010b8: | |
392 | case 0x1f8010c8: | |
393 | case 0x1f8010e8: | |
394 | case 0x1f8010f4: | |
395 | return !is_write; | |
396 | default: | |
397 | return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00; | |
398 | } | |
399 | } | |
400 | } | |
401 | ||
323bb280 AL |
402 | #if defined(HW_DOL) || defined(HW_RVL) |
403 | static void lightrec_code_inv(void *ptr, uint32_t len) | |
404 | { | |
405 | extern void DCFlushRange(void *ptr, u32 len); | |
406 | extern void ICInvalidateRange(void *ptr, u32 len); | |
407 | ||
408 | DCFlushRange(ptr, len); | |
409 | ICInvalidateRange(ptr, len); | |
410 | } | |
411 | #elif defined(HW_WUP) | |
412 | static void lightrec_code_inv(void *ptr, uint32_t len) | |
413 | { | |
414 | wiiu_clear_cache(ptr, (void *)((uintptr_t)ptr + len)); | |
415 | } | |
416 | #endif | |
417 | ||
6f1edc3c | 418 | static const struct lightrec_ops lightrec_ops = { |
0733c3ab PC |
419 | .cop2_op = cop2_op, |
420 | .enable_ram = lightrec_enable_ram, | |
ba3814c1 | 421 | .hw_direct = lightrec_can_hw_direct, |
323bb280 AL |
422 | #if defined(HW_DOL) || defined(HW_RVL) || defined(HW_WUP) |
423 | .code_inv = lightrec_code_inv, | |
424 | #endif | |
6f1edc3c PC |
425 | }; |
426 | ||
427 | static int lightrec_plugin_init(void) | |
428 | { | |
429 | lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM; | |
430 | lightrec_map[PSX_MAP_BIOS].address = psxR; | |
431 | lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH; | |
6ce0b00a | 432 | lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000; |
6f1edc3c PC |
433 | lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP; |
434 | ||
479d58cf PC |
435 | if (LIGHTREC_CUSTOM_MAP) { |
436 | lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000; | |
437 | lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000; | |
438 | lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000; | |
f8548105 | 439 | lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer; |
479d58cf PC |
440 | } |
441 | ||
6f1edc3c | 442 | use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER"); |
6f1edc3c PC |
443 | |
444 | lightrec_state = lightrec_init(name, | |
445 | lightrec_map, ARRAY_SIZE(lightrec_map), | |
446 | &lightrec_ops); | |
447 | ||
9361a5aa EC |
448 | // fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n", |
449 | // (uintptr_t) psxM, | |
450 | // (uintptr_t) psxP, | |
451 | // (uintptr_t) psxR, | |
452 | // (uintptr_t) psxH); | |
6f1edc3c PC |
453 | |
454 | #ifndef _WIN32 | |
455 | signal(SIGPIPE, exit); | |
456 | #endif | |
457 | return 0; | |
458 | } | |
459 | ||
d0abba5d | 460 | static void lightrec_plugin_execute_internal(bool block_only) |
6f1edc3c | 461 | { |
6c62131f | 462 | struct lightrec_registers *regs; |
c174cf6a | 463 | u32 flags, cycles_pcsx; |
6f1edc3c | 464 | |
6c62131f | 465 | regs = lightrec_get_registers(lightrec_state); |
466 | gen_interupt((psxCP0Regs *)regs->cp0); | |
c174cf6a | 467 | cycles_pcsx = next_interupt - psxRegs.cycle; |
468 | assert((s32)cycles_pcsx > 0); | |
2bf88032 | 469 | |
ba3814c1 | 470 | // step during early boot so that 0x80030000 fastboot hack works |
6c62131f | 471 | block_stepping = block_only; |
d0abba5d | 472 | if (block_only) |
c174cf6a | 473 | cycles_pcsx = 0; |
ba3814c1 | 474 | |
6b02f240 | 475 | if (use_pcsx_interpreter) { |
f2100c3d | 476 | intExecuteBlock(0); |
6b02f240 | 477 | } else { |
c174cf6a | 478 | u32 cycles_lightrec = cycles_pcsx_to_lightrec(cycles_pcsx); |
ba3814c1 | 479 | if (unlikely(use_lightrec_interpreter)) { |
6b02f240 | 480 | psxRegs.pc = lightrec_run_interpreter(lightrec_state, |
ba3814c1 | 481 | psxRegs.pc, |
c174cf6a | 482 | cycles_lightrec); |
ba3814c1 | 483 | } else { |
2bf88032 | 484 | psxRegs.pc = lightrec_execute(lightrec_state, |
c174cf6a | 485 | psxRegs.pc, cycles_lightrec); |
ba3814c1 | 486 | } |
6f1edc3c | 487 | |
c174cf6a | 488 | lightrec_tansition_to_pcsx(lightrec_state); |
6f1edc3c | 489 | |
6b02f240 | 490 | flags = lightrec_exit_flags(lightrec_state); |
6f1edc3c | 491 | |
6b02f240 | 492 | if (flags & LIGHTREC_EXIT_SEGFAULT) { |
493 | fprintf(stderr, "Exiting at cycle 0x%08x\n", | |
494 | psxRegs.cycle); | |
495 | exit(1); | |
496 | } | |
6f1edc3c | 497 | |
6b02f240 | 498 | if (flags & LIGHTREC_EXIT_SYSCALL) |
6c62131f | 499 | psxException(0x20, 0, (psxCP0Regs *)regs->cp0); |
2bf88032 | 500 | } |
6f1edc3c | 501 | |
6c62131f | 502 | if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) { |
6f1edc3c | 503 | /* Handle software interrupts */ |
6c62131f | 504 | regs->cp0[13] &= ~0x7c; |
505 | psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0); | |
6f1edc3c | 506 | } |
6f1edc3c PC |
507 | } |
508 | ||
509 | static void lightrec_plugin_execute(void) | |
510 | { | |
511 | extern int stop; | |
512 | ||
513 | while (!stop) | |
d0abba5d | 514 | lightrec_plugin_execute_internal(false); |
d0abba5d | 515 | } |
516 | ||
f3bc907d | 517 | static void lightrec_plugin_execute_block(enum blockExecCaller caller) |
d0abba5d | 518 | { |
519 | lightrec_plugin_execute_internal(true); | |
6f1edc3c PC |
520 | } |
521 | ||
522 | static void lightrec_plugin_clear(u32 addr, u32 size) | |
523 | { | |
8c9468f1 ZC |
524 | if (addr == 0 && size == UINT32_MAX) |
525 | lightrec_invalidate_all(lightrec_state); | |
526 | else | |
527 | /* size * 4: PCSX uses DMA units */ | |
528 | lightrec_invalidate(lightrec_state, addr, size * 4); | |
6f1edc3c PC |
529 | } |
530 | ||
20196899 | 531 | static void lightrec_plugin_sync_regs_to_pcsx(void); |
532 | static void lightrec_plugin_sync_regs_from_pcsx(void); | |
533 | ||
534 | static void lightrec_plugin_notify(enum R3000Anote note, void *data) | |
7a811716 | 535 | { |
7a811716 | 536 | switch (note) |
537 | { | |
20196899 | 538 | case R3000ACPU_NOTIFY_CACHE_ISOLATED: |
539 | case R3000ACPU_NOTIFY_CACHE_UNISOLATED: | |
540 | /* not used, lightrec calls lightrec_enable_ram() instead */ | |
541 | break; | |
542 | case R3000ACPU_NOTIFY_BEFORE_SAVE: | |
543 | lightrec_plugin_sync_regs_to_pcsx(); | |
544 | break; | |
545 | case R3000ACPU_NOTIFY_AFTER_LOAD: | |
546 | lightrec_plugin_sync_regs_from_pcsx(); | |
547 | break; | |
548 | } | |
7a811716 | 549 | } |
630b122b | 550 | |
551 | static void lightrec_plugin_apply_config() | |
552 | { | |
c174cf6a | 553 | u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT |
554 | ? Config.cycle_multiplier_override : Config.cycle_multiplier; | |
555 | assert(cycle_mult); | |
556 | cycle_mult_to_pcsx = (cycle_mult * 1024 + 199) / 200; | |
557 | cycle_mult_from_pcsx = (200 * 1024 + cycle_mult/2) / cycle_mult; | |
630b122b | 558 | } |
7a811716 | 559 | |
6f1edc3c PC |
560 | static void lightrec_plugin_shutdown(void) |
561 | { | |
562 | lightrec_destroy(lightrec_state); | |
563 | } | |
564 | ||
565 | static void lightrec_plugin_reset(void) | |
566 | { | |
0733c3ab PC |
567 | struct lightrec_registers *regs; |
568 | ||
0733c3ab PC |
569 | regs = lightrec_get_registers(lightrec_state); |
570 | ||
03535202 PC |
571 | /* Invalidate all blocks */ |
572 | lightrec_invalidate_all(lightrec_state); | |
573 | ||
574 | /* Reset registers */ | |
575 | memset(regs, 0, sizeof(*regs)); | |
576 | ||
0733c3ab PC |
577 | regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1 |
578 | regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A | |
6f1edc3c PC |
579 | } |
580 | ||
20196899 | 581 | static void lightrec_plugin_sync_regs_from_pcsx(void) |
6962f770 PC |
582 | { |
583 | struct lightrec_registers *regs; | |
584 | ||
585 | regs = lightrec_get_registers(lightrec_state); | |
586 | memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c)); | |
587 | memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0)); | |
588 | memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr)); | |
589 | ||
590 | lightrec_invalidate_all(lightrec_state); | |
591 | } | |
592 | ||
20196899 | 593 | static void lightrec_plugin_sync_regs_to_pcsx(void) |
6962f770 PC |
594 | { |
595 | struct lightrec_registers *regs; | |
596 | ||
597 | regs = lightrec_get_registers(lightrec_state); | |
598 | memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c)); | |
599 | memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0)); | |
600 | memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr)); | |
601 | } | |
602 | ||
6f1edc3c PC |
603 | R3000Acpu psxRec = |
604 | { | |
605 | lightrec_plugin_init, | |
606 | lightrec_plugin_reset, | |
607 | lightrec_plugin_execute, | |
608 | lightrec_plugin_execute_block, | |
609 | lightrec_plugin_clear, | |
7a811716 | 610 | lightrec_plugin_notify, |
630b122b | 611 | lightrec_plugin_apply_config, |
6f1edc3c PC |
612 | lightrec_plugin_shutdown, |
613 | }; |