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1 | #define HOST_REGS 13 |
2 | #define HOST_CCREG 10 |
3 | #define HOST_BTREG 8 |
4 | #define EXCLUDE_REG 11 |
5 | |
6 | #define HOST_IMM8 1 |
7 | #define HAVE_CMOV_IMM 1 |
8 | #define CORTEX_A8_BRANCH_PREDICTION_HACK 1 |
9 | #define USE_MINI_HT 1 |
10 | //#define REG_PREFETCH 1 |
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11 | #define HAVE_CONDITIONAL_CALL 1 |
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12 | #define DISABLE_TLB 1 |
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13 | //#define MUPEN64 |
14 | #define FORCE32 1 |
15 | #define DISABLE_COP1 1 |
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16 | #define PCSX 1 |
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17 | #define RAM_SIZE 0x200000 |
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18 | |
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19 | #ifndef __ARM_ARCH_7A__ |
20 | #define ARMv5_ONLY |
21 | //#undef CORTEX_A8_BRANCH_PREDICTION_HACK |
22 | //#undef USE_MINI_HT |
23 | #endif |
24 | |
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25 | #ifndef BASE_ADDR_FIXED |
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26 | #define BASE_ADDR_FIXED 0 |
27 | #endif |
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28 | |
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29 | #ifdef FORCE32 |
30 | #define REG_SHIFT 2 |
31 | #else |
32 | #define REG_SHIFT 3 |
33 | #endif |
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34 | |
35 | /* ARM calling convention: |
36 | r0-r3, r12: caller-save |
37 | r4-r11: callee-save */ |
38 | |
39 | #define ARG1_REG 0 |
40 | #define ARG2_REG 1 |
41 | #define ARG3_REG 2 |
42 | #define ARG4_REG 3 |
43 | |
44 | /* GCC register naming convention: |
45 | r10 = sl (base) |
46 | r11 = fp (frame pointer) |
47 | r12 = ip (scratch) |
48 | r13 = sp (stack pointer) |
49 | r14 = lr (link register) |
50 | r15 = pc (program counter) */ |
51 | |
52 | #define FP 11 |
53 | #define LR 14 |
54 | #define HOST_TEMPREG 14 |
55 | |
56 | // Note: FP is set to &dynarec_local when executing generated code. |
57 | // Thus the local variables are actually global and not on the stack. |
58 | |
59 | extern char *invc_ptr; |
60 | |
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61 | #define TARGET_SIZE_2 24 // 2^24 = 16 megabytes |
62 | |
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63 | // Code generator target address |
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64 | #if BASE_ADDR_FIXED |
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65 | // "round" address helpful for debug |
66 | #define BASE_ADDR 0x1000000 |
67 | #else |
68 | extern char translation_cache[1 << TARGET_SIZE_2]; |
69 | #define BASE_ADDR translation_cache |
70 | #endif |