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1 | #ifndef __EMU_IF_H__ |
2 | #define __EMU_IF_H__ |
3 | |
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4 | #include "../../new_dynarec.h" |
5 | #include "../../../r3000a.h" |
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6 | |
7 | extern char invalid_code[0x100000]; |
8 | |
9 | /* weird stuff */ |
10 | #define EAX 0 |
11 | #define ECX 1 |
12 | |
13 | /* same as psxRegs */ |
14 | extern int reg[]; |
15 | |
16 | /* same as psxRegs.GPR.n.* */ |
17 | extern int hi, lo; |
18 | |
19 | /* same as psxRegs.CP0.n.* */ |
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20 | extern int reg_cop0[]; |
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21 | #define Status psxRegs.CP0.n.Status |
22 | #define Cause psxRegs.CP0.n.Cause |
23 | #define EPC psxRegs.CP0.n.EPC |
24 | #define BadVAddr psxRegs.CP0.n.BadVAddr |
25 | #define Context psxRegs.CP0.n.Context |
26 | #define EntryHi psxRegs.CP0.n.EntryHi |
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27 | #define Count psxRegs.cycle // psxRegs.CP0.n.Count |
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28 | |
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29 | /* COP2/GTE */ |
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30 | enum gte_opcodes { |
31 | GTE_RTPS = 0x01, |
32 | GTE_NCLIP = 0x06, |
33 | GTE_OP = 0x0c, |
34 | GTE_DPCS = 0x10, |
35 | GTE_INTPL = 0x11, |
36 | GTE_MVMVA = 0x12, |
37 | GTE_NCDS = 0x13, |
38 | GTE_CDP = 0x14, |
39 | GTE_NCDT = 0x16, |
40 | GTE_NCCS = 0x1b, |
41 | GTE_CC = 0x1c, |
42 | GTE_NCS = 0x1e, |
43 | GTE_NCT = 0x20, |
44 | GTE_SQR = 0x28, |
45 | GTE_DCPL = 0x29, |
46 | GTE_DPCT = 0x2a, |
47 | GTE_AVSZ3 = 0x2d, |
48 | GTE_AVSZ4 = 0x2e, |
49 | GTE_RTPT = 0x30, |
50 | GTE_GPF = 0x3d, |
51 | GTE_GPL = 0x3e, |
52 | GTE_NCCT = 0x3f, |
53 | }; |
54 | |
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55 | extern int reg_cop2d[], reg_cop2c[]; |
56 | extern void *gte_handlers[64]; |
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57 | extern void *gte_handlers_nf[64]; |
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58 | extern const char *gte_regnames[64]; |
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59 | extern const char gte_cycletab[64]; |
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60 | extern const uint64_t gte_reg_reads[64]; |
61 | extern const uint64_t gte_reg_writes[64]; |
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62 | |
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63 | /* dummy */ |
64 | extern int FCR0, FCR31; |
65 | |
66 | /* mem */ |
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67 | extern void *mem_rtab; |
68 | extern void *mem_wtab; |
69 | |
70 | void jump_handler_read8(u32 addr, u32 *table, u32 cycles); |
71 | void jump_handler_read16(u32 addr, u32 *table, u32 cycles); |
72 | void jump_handler_read32(u32 addr, u32 *table, u32 cycles); |
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73 | void jump_handler_write8(u32 addr, u32 data, u32 cycles, u32 *table); |
74 | void jump_handler_write16(u32 addr, u32 data, u32 cycles, u32 *table); |
75 | void jump_handler_write32(u32 addr, u32 data, u32 cycles, u32 *table); |
76 | void jump_handler_write_h(u32 addr, u32 data, u32 cycles, void *handler); |
77 | void jump_handle_swl(u32 addr, u32 data, u32 cycles); |
78 | void jump_handle_swr(u32 addr, u32 data, u32 cycles); |
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79 | void rcnt0_read_count_m0(u32 addr, u32, u32 cycles); |
80 | void rcnt0_read_count_m1(u32 addr, u32, u32 cycles); |
81 | void rcnt1_read_count_m0(u32 addr, u32, u32 cycles); |
82 | void rcnt1_read_count_m1(u32 addr, u32, u32 cycles); |
83 | void rcnt2_read_count_m0(u32 addr, u32, u32 cycles); |
84 | void rcnt2_read_count_m1(u32 addr, u32, u32 cycles); |
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85 | |
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86 | extern unsigned int address; |
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87 | extern void *psxH_ptr; |
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88 | extern void *zeromem_ptr; |
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89 | extern void *scratch_buf_ptr; |
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90 | |
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91 | // same as invalid_code, just a region for ram write checks (inclusive) |
92 | extern u32 inv_code_start, inv_code_end; |
93 | |
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94 | /* cycles/irqs */ |
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95 | extern u32 next_interupt; |
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96 | extern int pending_exception; |
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97 | |
98 | /* called by drc */ |
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99 | void pcsx_mtc0(u32 reg, u32 val); |
100 | void pcsx_mtc0_ds(u32 reg, u32 val); |
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101 | |
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102 | /* misc */ |
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103 | extern void (*psxHLEt[])(); |
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104 | |
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105 | extern void SysPrintf(const char *fmt, ...); |
106 | |
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107 | #ifdef RAM_FIXED |
108 | #define rdram ((u_int)0x80000000) |
109 | #else |
110 | #define rdram ((u_int)psxM) |
111 | #endif |
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112 | |
113 | #endif /* __EMU_IF_H__ */ |