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1 | #include "new_dynarec.h" |
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2 | #include "../r3000a.h" |
3 | |
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4 | extern int dynarec_local[]; |
5 | |
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6 | /* same as psxRegs.GPR.n.* */ |
7 | extern int hi, lo; |
8 | |
9 | /* same as psxRegs.CP0.n.* */ |
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10 | extern int reg_cop0[]; |
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11 | |
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12 | /* COP2/GTE */ |
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13 | enum gte_opcodes { |
14 | GTE_RTPS = 0x01, |
15 | GTE_NCLIP = 0x06, |
16 | GTE_OP = 0x0c, |
17 | GTE_DPCS = 0x10, |
18 | GTE_INTPL = 0x11, |
19 | GTE_MVMVA = 0x12, |
20 | GTE_NCDS = 0x13, |
21 | GTE_CDP = 0x14, |
22 | GTE_NCDT = 0x16, |
23 | GTE_NCCS = 0x1b, |
24 | GTE_CC = 0x1c, |
25 | GTE_NCS = 0x1e, |
26 | GTE_NCT = 0x20, |
27 | GTE_SQR = 0x28, |
28 | GTE_DCPL = 0x29, |
29 | GTE_DPCT = 0x2a, |
30 | GTE_AVSZ3 = 0x2d, |
31 | GTE_AVSZ4 = 0x2e, |
32 | GTE_RTPT = 0x30, |
33 | GTE_GPF = 0x3d, |
34 | GTE_GPL = 0x3e, |
35 | GTE_NCCT = 0x3f, |
36 | }; |
37 | |
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38 | extern int reg_cop2d[], reg_cop2c[]; |
39 | extern void *gte_handlers[64]; |
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40 | extern void *gte_handlers_nf[64]; |
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41 | extern const char *gte_regnames[64]; |
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42 | extern const uint64_t gte_reg_reads[64]; |
43 | extern const uint64_t gte_reg_writes[64]; |
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44 | |
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45 | /* mem */ |
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46 | extern void *mem_rtab; |
47 | extern void *mem_wtab; |
48 | |
49 | void jump_handler_read8(u32 addr, u32 *table, u32 cycles); |
50 | void jump_handler_read16(u32 addr, u32 *table, u32 cycles); |
51 | void jump_handler_read32(u32 addr, u32 *table, u32 cycles); |
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52 | void jump_handler_write8(u32 addr, u32 data, u32 cycles, u32 *table); |
53 | void jump_handler_write16(u32 addr, u32 data, u32 cycles, u32 *table); |
54 | void jump_handler_write32(u32 addr, u32 data, u32 cycles, u32 *table); |
55 | void jump_handler_write_h(u32 addr, u32 data, u32 cycles, void *handler); |
56 | void jump_handle_swl(u32 addr, u32 data, u32 cycles); |
57 | void jump_handle_swr(u32 addr, u32 data, u32 cycles); |
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58 | u32 rcnt0_read_count_m0(u32 addr, u32, u32 cycles); |
59 | u32 rcnt0_read_count_m1(u32 addr, u32, u32 cycles); |
60 | u32 rcnt1_read_count_m0(u32 addr, u32, u32 cycles); |
61 | u32 rcnt1_read_count_m1(u32 addr, u32, u32 cycles); |
62 | u32 rcnt2_read_count_m0(u32 addr, u32, u32 cycles); |
63 | u32 rcnt2_read_count_m1(u32 addr, u32, u32 cycles); |
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64 | |
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65 | extern unsigned int address; |
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66 | extern unsigned int hack_addr; |
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67 | extern void *psxH_ptr; |
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68 | extern void *zeromem_ptr; |
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69 | extern void *scratch_buf_ptr; |
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70 | |
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71 | // same as invalid_code, just a region for ram write checks (inclusive) |
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72 | // (psx/guest address range) |
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73 | extern u32 inv_code_start, inv_code_end; |
74 | |
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75 | /* cycles/irqs */ |
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76 | extern u32 next_interupt; |
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77 | extern int pending_exception; |
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78 | |
79 | /* called by drc */ |
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80 | void pcsx_mtc0(u32 reg, u32 val); |
81 | void pcsx_mtc0_ds(u32 reg, u32 val); |
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82 | |
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83 | /* misc */ |
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84 | extern void SysPrintf(const char *fmt, ...); |
85 | |