57871462 |
1 | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * |
7e605697 |
2 | * linkage_arm.s for PCSX * |
0bbd1454 |
3 | * Copyright (C) 2009-2011 Ari64 * |
b1f89e6f |
4 | * Copyright (C) 2010-2013 GraÅžvydas "notaz" Ignotas * |
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5 | * * |
6 | * This program is free software; you can redistribute it and/or modify * |
7 | * it under the terms of the GNU General Public License as published by * |
8 | * the Free Software Foundation; either version 2 of the License, or * |
9 | * (at your option) any later version. * |
10 | * * |
11 | * This program is distributed in the hope that it will be useful, * |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
14 | * GNU General Public License for more details. * |
15 | * * |
16 | * You should have received a copy of the GNU General Public License * |
17 | * along with this program; if not, write to the * |
18 | * Free Software Foundation, Inc., * |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * |
20 | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ |
b021ee75 |
21 | |
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22 | #include "arm_features.h" |
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23 | #include "new_dynarec_config.h" |
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24 | #include "linkage_offsets.h" |
25 | |
26 | |
27 | #ifdef __MACH__ |
28 | #define dynarec_local ESYM(dynarec_local) |
048fcced |
29 | #define ndrc_add_jump_out ESYM(ndrc_add_jump_out) |
bfdecce3 |
30 | #define ndrc_try_restore_block ESYM(ndrc_try_restore_block) |
048fcced |
31 | #define ndrc_get_addr_ht ESYM(ndrc_get_addr_ht) |
32 | #define ndrc_get_addr_ht_param ESYM(ndrc_get_addr_ht_param) |
bdbf4466 |
33 | #define ndrc_write_invalidate_one ESYM(ndrc_write_invalidate_one) |
b1f89e6f |
34 | #define gen_interupt ESYM(gen_interupt) |
630b122b |
35 | #define gteCheckStallRaw ESYM(gteCheckStallRaw) |
467357cc |
36 | #define psxException ESYM(psxException) |
b1f89e6f |
37 | #endif |
f95a77f7 |
38 | |
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39 | .bss |
40 | .align 4 |
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41 | .global dynarec_local |
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42 | .type dynarec_local, %object |
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43 | .size dynarec_local, LO_dynarec_local_size |
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44 | dynarec_local: |
b1f89e6f |
45 | .space LO_dynarec_local_size |
46 | |
47 | #define DRC_VAR_(name, vname, size_) \ |
48 | vname = dynarec_local + LO_##name; \ |
49 | .global vname; \ |
50 | .type vname, %object; \ |
51 | .size vname, size_ |
52 | |
53 | #define DRC_VAR(name, size_) \ |
54 | DRC_VAR_(name, ESYM(name), size_) |
55 | |
56 | DRC_VAR(next_interupt, 4) |
57 | DRC_VAR(cycle_count, 4) |
58 | DRC_VAR(last_count, 4) |
59 | DRC_VAR(pending_exception, 4) |
60 | DRC_VAR(stop, 4) |
630b122b |
61 | DRC_VAR(branch_target, 4) |
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62 | DRC_VAR(address, 4) |
7c8454e3 |
63 | DRC_VAR(hack_addr, 4) |
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64 | DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs) |
f95a77f7 |
65 | |
66 | /* psxRegs */ |
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67 | @DRC_VAR(reg, 128) |
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68 | DRC_VAR(lo, 4) |
69 | DRC_VAR(hi, 4) |
70 | DRC_VAR(reg_cop0, 128) |
71 | DRC_VAR(reg_cop2d, 128) |
72 | DRC_VAR(reg_cop2c, 128) |
73 | DRC_VAR(pcaddr, 4) |
74 | @DRC_VAR(code, 4) |
75 | @DRC_VAR(cycle, 4) |
76 | @DRC_VAR(interrupt, 4) |
77 | @DRC_VAR(intCycle, 256) |
78 | |
79 | DRC_VAR(rcnts, 7*4*4) |
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80 | DRC_VAR(inv_code_start, 4) |
81 | DRC_VAR(inv_code_end, 4) |
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82 | DRC_VAR(mem_rtab, 4) |
83 | DRC_VAR(mem_wtab, 4) |
84 | DRC_VAR(psxH_ptr, 4) |
85 | DRC_VAR(zeromem_ptr, 4) |
630b122b |
86 | DRC_VAR(invc_ptr, 4) |
c6d5790c |
87 | DRC_VAR(scratch_buf_ptr, 4) |
630b122b |
88 | DRC_VAR(ram_offset, 4) |
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89 | DRC_VAR(mini_ht, 256) |
63cb0298 |
90 | |
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91 | |
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92 | .syntax unified |
93 | .text |
94 | .align 2 |
95 | |
665f33e1 |
96 | #ifndef HAVE_ARMV5 |
97 | .macro blx rd |
98 | mov lr, pc |
99 | bx \rd |
100 | .endm |
101 | #endif |
102 | |
c67af2ac |
103 | .macro load_varadr reg var |
0e4ad319 |
104 | #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN) |
1f4e070a |
105 | movw \reg, #:lower16:(\var-(1678f+8)) |
106 | movt \reg, #:upper16:(\var-(1678f+8)) |
b861c0a9 |
107 | 1678: |
108 | add \reg, pc |
0e4ad319 |
109 | #elif defined(HAVE_ARMV7) && !defined(__PIC__) |
110 | movw \reg, #:lower16:\var |
111 | movt \reg, #:upper16:\var |
c67af2ac |
112 | #else |
274c4243 |
113 | ldr \reg, =\var |
c67af2ac |
114 | #endif |
274c4243 |
115 | .endm |
116 | |
b861c0a9 |
117 | .macro load_varadr_ext reg var |
0e4ad319 |
118 | #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN) |
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119 | movw \reg, #:lower16:(ptr_\var-(1678f+8)) |
120 | movt \reg, #:upper16:(ptr_\var-(1678f+8)) |
b861c0a9 |
121 | 1678: |
122 | ldr \reg, [pc, \reg] |
123 | #else |
124 | load_varadr \reg \var |
125 | #endif |
126 | .endm |
127 | |
b1be1eee |
128 | .macro mov_16 reg imm |
8f2bb0cb |
129 | #ifdef HAVE_ARMV7 |
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130 | movw \reg, #\imm |
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131 | #else |
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132 | mov \reg, #(\imm & 0x00ff) |
133 | orr \reg, #(\imm & 0xff00) |
c67af2ac |
134 | #endif |
b1be1eee |
135 | .endm |
136 | |
137 | .macro mov_24 reg imm |
8f2bb0cb |
138 | #ifdef HAVE_ARMV7 |
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139 | movw \reg, #(\imm & 0xffff) |
140 | movt \reg, #(\imm >> 16) |
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141 | #else |
b1be1eee |
142 | mov \reg, #(\imm & 0x0000ff) |
143 | orr \reg, #(\imm & 0x00ff00) |
144 | orr \reg, #(\imm & 0xff0000) |
c67af2ac |
145 | #endif |
b1be1eee |
146 | .endm |
147 | |
048fcced |
148 | FUNCTION(dyna_linker): |
149 | /* r0 = virtual target address */ |
150 | /* r1 = pointer to an instruction to patch */ |
d148d265 |
151 | #ifndef NO_WRITE_EXEC |
048fcced |
152 | ldr r7, [r1] |
153 | mov r4, r0 |
154 | add r6, r7, #2 |
155 | mov r5, r1 |
156 | lsl r6, r6, #8 |
157 | /* must not compile - that might expire the caller block */ |
158 | mov r1, #0 |
159 | bl ndrc_get_addr_ht_param |
160 | |
161 | movs r8, r0 |
162 | beq 0f |
163 | add r6, r5, r6, asr #6 /* old target */ |
bfdecce3 |
164 | teq r0, r6 |
165 | moveq pc, r0 /* Stale i-cache */ |
bfdecce3 |
166 | mov r0, r4 |
76f71c27 |
167 | mov r1, r6 |
048fcced |
168 | bl ndrc_add_jump_out |
169 | |
76f71c27 |
170 | sub r2, r8, r5 |
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171 | and r1, r7, #0xff000000 |
172 | lsl r2, r2, #6 |
173 | sub r1, r1, #2 |
174 | add r1, r1, r2, lsr #8 |
175 | str r1, [r5] |
76f71c27 |
176 | mov pc, r8 |
048fcced |
177 | 0: |
bfdecce3 |
178 | mov r0, r4 |
d148d265 |
179 | #else |
180 | /* XXX: should be able to do better than this... */ |
d148d265 |
181 | #endif |
048fcced |
182 | bl ndrc_get_addr_ht |
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183 | mov pc, r0 |
f9e37973 |
184 | .size dyna_linker, .-dyna_linker |
7139f3c8 |
185 | |
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186 | .align 2 |
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187 | FUNCTION(jump_vaddr_r1): |
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188 | mov r0, r1 |
048fcced |
189 | b jump_vaddr_r0 |
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190 | .size jump_vaddr_r1, .-jump_vaddr_r1 |
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191 | FUNCTION(jump_vaddr_r2): |
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192 | mov r0, r2 |
048fcced |
193 | b jump_vaddr_r0 |
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194 | .size jump_vaddr_r2, .-jump_vaddr_r2 |
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195 | FUNCTION(jump_vaddr_r3): |
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196 | mov r0, r3 |
048fcced |
197 | b jump_vaddr_r0 |
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198 | .size jump_vaddr_r3, .-jump_vaddr_r3 |
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199 | FUNCTION(jump_vaddr_r4): |
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200 | mov r0, r4 |
048fcced |
201 | b jump_vaddr_r0 |
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202 | .size jump_vaddr_r4, .-jump_vaddr_r4 |
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203 | FUNCTION(jump_vaddr_r5): |
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204 | mov r0, r5 |
048fcced |
205 | b jump_vaddr_r0 |
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206 | .size jump_vaddr_r5, .-jump_vaddr_r5 |
5c6457c3 |
207 | FUNCTION(jump_vaddr_r6): |
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208 | mov r0, r6 |
048fcced |
209 | b jump_vaddr_r0 |
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210 | .size jump_vaddr_r6, .-jump_vaddr_r6 |
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211 | FUNCTION(jump_vaddr_r8): |
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212 | mov r0, r8 |
048fcced |
213 | b jump_vaddr_r0 |
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214 | .size jump_vaddr_r8, .-jump_vaddr_r8 |
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215 | FUNCTION(jump_vaddr_r9): |
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216 | mov r0, r9 |
048fcced |
217 | b jump_vaddr_r0 |
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218 | .size jump_vaddr_r9, .-jump_vaddr_r9 |
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219 | FUNCTION(jump_vaddr_r10): |
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220 | mov r0, r10 |
048fcced |
221 | b jump_vaddr_r0 |
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222 | .size jump_vaddr_r10, .-jump_vaddr_r10 |
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223 | FUNCTION(jump_vaddr_r12): |
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224 | mov r0, r12 |
048fcced |
225 | b jump_vaddr_r0 |
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226 | .size jump_vaddr_r12, .-jump_vaddr_r12 |
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227 | FUNCTION(jump_vaddr_r7): |
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228 | add r0, r7, #0 |
229 | .size jump_vaddr_r7, .-jump_vaddr_r7 |
048fcced |
230 | FUNCTION(jump_vaddr_r0): |
231 | bl ndrc_get_addr_ht |
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232 | mov pc, r0 |
048fcced |
233 | .size jump_vaddr_r0, .-jump_vaddr_r0 |
7139f3c8 |
234 | |
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235 | .align 2 |
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236 | FUNCTION(cc_interrupt): |
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237 | ldr r0, [fp, #LO_last_count] |
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238 | mov r1, #0 |
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239 | add r10, r0, r10 |
b1f89e6f |
240 | str r1, [fp, #LO_pending_exception] |
b1f89e6f |
241 | str r10, [fp, #LO_cycle] /* PCSX cycles */ |
b0163e04 |
242 | @@ str r10, [fp, #LO_reg_cop0+36] /* Count - not on PSX */ |
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243 | mov r10, lr |
bfdecce3 |
244 | |
6c62131f |
245 | add r0, fp, #(LO_psxRegs + 34*4) /* CP0 */ |
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246 | bl gen_interupt |
247 | mov lr, r10 |
b1f89e6f |
248 | ldr r10, [fp, #LO_cycle] |
249 | ldr r0, [fp, #LO_next_interupt] |
250 | ldr r1, [fp, #LO_pending_exception] |
251 | ldr r2, [fp, #LO_stop] |
252 | str r0, [fp, #LO_last_count] |
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253 | sub r10, r10, r0 |
254 | tst r2, r2 |
b861c0a9 |
255 | ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc} |
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256 | tst r1, r1 |
257 | moveq pc, lr |
b1f89e6f |
258 | ldr r0, [fp, #LO_pcaddr] |
048fcced |
259 | bl ndrc_get_addr_ht |
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260 | mov pc, r0 |
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261 | .size cc_interrupt, .-cc_interrupt |
7139f3c8 |
262 | |
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263 | .align 2 |
5c6457c3 |
264 | FUNCTION(fp_exception): |
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265 | mov r2, #0x10000000 |
266 | .E7: |
b1f89e6f |
267 | ldr r1, [fp, #LO_reg_cop0+48] /* Status */ |
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268 | mov r3, #0x80000000 |
b1f89e6f |
269 | str r0, [fp, #LO_reg_cop0+56] /* EPC */ |
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270 | orr r1, #2 |
271 | add r2, r2, #0x2c |
b1f89e6f |
272 | str r1, [fp, #LO_reg_cop0+48] /* Status */ |
273 | str r2, [fp, #LO_reg_cop0+52] /* Cause */ |
7139f3c8 |
274 | add r0, r3, #0x80 |
048fcced |
275 | bl ndrc_get_addr_ht |
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276 | mov pc, r0 |
277 | .size fp_exception, .-fp_exception |
278 | .align 2 |
5c6457c3 |
279 | FUNCTION(fp_exception_ds): |
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280 | mov r2, #0x90000000 /* Set high bit if delay slot */ |
281 | b .E7 |
282 | .size fp_exception_ds, .-fp_exception_ds |
7139f3c8 |
283 | |
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284 | .align 2 |
467357cc |
285 | FUNCTION(jump_break_ds): |
286 | mov r0, #0x24 |
287 | mov r1, #1 |
288 | b call_psxException |
289 | FUNCTION(jump_break): |
290 | mov r0, #0x24 |
291 | mov r1, #0 |
292 | b call_psxException |
293 | FUNCTION(jump_syscall_ds): |
294 | mov r0, #0x20 |
6d79a06f |
295 | mov r1, #2 |
467357cc |
296 | b call_psxException |
5c6457c3 |
297 | FUNCTION(jump_syscall): |
467357cc |
298 | mov r0, #0x20 |
299 | mov r1, #0 |
300 | |
301 | call_psxException: |
302 | ldr r3, [fp, #LO_last_count] |
303 | str r2, [fp, #LO_pcaddr] |
304 | add r10, r3, r10 |
6c62131f |
305 | str r10, [fp, #LO_cycle] /* PCSX cycles */ |
306 | add r2, fp, #(LO_psxRegs + 34*4) /* CP0 */ |
467357cc |
307 | bl psxException |
7139f3c8 |
308 | |
b1f89e6f |
309 | /* note: psxException might do recursive recompiler call from it's HLE code, |
7139f3c8 |
310 | * so be ready for this */ |
630b122b |
311 | FUNCTION(jump_to_new_pc): |
b1f89e6f |
312 | ldr r1, [fp, #LO_next_interupt] |
313 | ldr r10, [fp, #LO_cycle] |
314 | ldr r0, [fp, #LO_pcaddr] |
822b27d1 |
315 | sub r10, r10, r1 |
b1f89e6f |
316 | str r1, [fp, #LO_last_count] |
048fcced |
317 | bl ndrc_get_addr_ht |
7139f3c8 |
318 | mov pc, r0 |
630b122b |
319 | .size jump_to_new_pc, .-jump_to_new_pc |
0d16cda2 |
320 | |
7139f3c8 |
321 | .align 2 |
5c6457c3 |
322 | FUNCTION(new_dyna_leave): |
b1f89e6f |
323 | ldr r0, [fp, #LO_last_count] |
7139f3c8 |
324 | add r12, fp, #28 |
325 | add r10, r0, r10 |
b1f89e6f |
326 | str r10, [fp, #LO_cycle] |
b021ee75 |
327 | ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc} |
7139f3c8 |
328 | .size new_dyna_leave, .-new_dyna_leave |
329 | |
0bbd1454 |
330 | .align 2 |
5c6457c3 |
331 | FUNCTION(invalidate_addr_r0): |
5df0e313 |
332 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
0bbd1454 |
333 | b invalidate_addr_call |
334 | .size invalidate_addr_r0, .-invalidate_addr_r0 |
335 | .align 2 |
5c6457c3 |
336 | FUNCTION(invalidate_addr_r1): |
5df0e313 |
337 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
338 | mov r0, r1 |
0bbd1454 |
339 | b invalidate_addr_call |
340 | .size invalidate_addr_r1, .-invalidate_addr_r1 |
341 | .align 2 |
5c6457c3 |
342 | FUNCTION(invalidate_addr_r2): |
5df0e313 |
343 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
344 | mov r0, r2 |
0bbd1454 |
345 | b invalidate_addr_call |
346 | .size invalidate_addr_r2, .-invalidate_addr_r2 |
347 | .align 2 |
5c6457c3 |
348 | FUNCTION(invalidate_addr_r3): |
5df0e313 |
349 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
350 | mov r0, r3 |
0bbd1454 |
351 | b invalidate_addr_call |
352 | .size invalidate_addr_r3, .-invalidate_addr_r3 |
353 | .align 2 |
5c6457c3 |
354 | FUNCTION(invalidate_addr_r4): |
5df0e313 |
355 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
356 | mov r0, r4 |
0bbd1454 |
357 | b invalidate_addr_call |
358 | .size invalidate_addr_r4, .-invalidate_addr_r4 |
359 | .align 2 |
5c6457c3 |
360 | FUNCTION(invalidate_addr_r5): |
5df0e313 |
361 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
362 | mov r0, r5 |
0bbd1454 |
363 | b invalidate_addr_call |
364 | .size invalidate_addr_r5, .-invalidate_addr_r5 |
365 | .align 2 |
5c6457c3 |
366 | FUNCTION(invalidate_addr_r6): |
5df0e313 |
367 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
368 | mov r0, r6 |
0bbd1454 |
369 | b invalidate_addr_call |
370 | .size invalidate_addr_r6, .-invalidate_addr_r6 |
371 | .align 2 |
5c6457c3 |
372 | FUNCTION(invalidate_addr_r7): |
5df0e313 |
373 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
374 | mov r0, r7 |
0bbd1454 |
375 | b invalidate_addr_call |
376 | .size invalidate_addr_r7, .-invalidate_addr_r7 |
377 | .align 2 |
5c6457c3 |
378 | FUNCTION(invalidate_addr_r8): |
5df0e313 |
379 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
380 | mov r0, r8 |
0bbd1454 |
381 | b invalidate_addr_call |
382 | .size invalidate_addr_r8, .-invalidate_addr_r8 |
383 | .align 2 |
5c6457c3 |
384 | FUNCTION(invalidate_addr_r9): |
5df0e313 |
385 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
386 | mov r0, r9 |
0bbd1454 |
387 | b invalidate_addr_call |
388 | .size invalidate_addr_r9, .-invalidate_addr_r9 |
389 | .align 2 |
5c6457c3 |
390 | FUNCTION(invalidate_addr_r10): |
5df0e313 |
391 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
392 | mov r0, r10 |
0bbd1454 |
393 | b invalidate_addr_call |
394 | .size invalidate_addr_r10, .-invalidate_addr_r10 |
395 | .align 2 |
5c6457c3 |
396 | FUNCTION(invalidate_addr_r12): |
5df0e313 |
397 | stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr} |
9be4ba64 |
398 | mov r0, r12 |
0bbd1454 |
399 | .size invalidate_addr_r12, .-invalidate_addr_r12 |
400 | .align 2 |
b1f89e6f |
401 | invalidate_addr_call: |
402 | ldr r12, [fp, #LO_inv_code_start] |
403 | ldr lr, [fp, #LO_inv_code_end] |
9be4ba64 |
404 | cmp r0, r12 |
405 | cmpcs lr, r0 |
bdbf4466 |
406 | blcc ndrc_write_invalidate_one |
5df0e313 |
407 | ldmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc} |
0bbd1454 |
408 | .size invalidate_addr_call, .-invalidate_addr_call |
409 | |
57871462 |
410 | .align 2 |
5c6457c3 |
411 | FUNCTION(new_dyna_start): |
b021ee75 |
412 | /* ip is stored to conform EABI alignment */ |
413 | stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr} |
630b122b |
414 | mov fp, r0 /* dynarec_local */ |
b1f89e6f |
415 | ldr r0, [fp, #LO_pcaddr] |
048fcced |
416 | bl ndrc_get_addr_ht |
b1f89e6f |
417 | ldr r1, [fp, #LO_next_interupt] |
418 | ldr r10, [fp, #LO_cycle] |
419 | str r1, [fp, #LO_last_count] |
7139f3c8 |
420 | sub r10, r10, r1 |
421 | mov pc, r0 |
57871462 |
422 | .size new_dyna_start, .-new_dyna_start |
7139f3c8 |
423 | |
7e605697 |
424 | /* --------------------------------------- */ |
7139f3c8 |
425 | |
7e605697 |
426 | .align 2 |
c6c3b1b3 |
427 | |
428 | .macro pcsx_read_mem readop tab_shift |
429 | /* r0 = address, r1 = handler_tab, r2 = cycles */ |
430 | lsl r3, r0, #20 |
431 | lsr r3, #(20+\tab_shift) |
b1f89e6f |
432 | ldr r12, [fp, #LO_last_count] |
c6c3b1b3 |
433 | ldr r1, [r1, r3, lsl #2] |
434 | add r2, r2, r12 |
435 | lsls r1, #1 |
436 | .if \tab_shift == 1 |
437 | lsl r3, #1 |
438 | \readop r0, [r1, r3] |
439 | .else |
440 | \readop r0, [r1, r3, lsl #\tab_shift] |
441 | .endif |
442 | movcc pc, lr |
b1f89e6f |
443 | str r2, [fp, #LO_cycle] |
c6c3b1b3 |
444 | bx r1 |
445 | .endm |
446 | |
5c6457c3 |
447 | FUNCTION(jump_handler_read8): |
c6c3b1b3 |
448 | add r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part |
b861c0a9 |
449 | pcsx_read_mem ldrbcc, 0 |
c6c3b1b3 |
450 | |
5c6457c3 |
451 | FUNCTION(jump_handler_read16): |
c6c3b1b3 |
452 | add r1, #0x1000/4*4 @ shift to r16 part |
10858959 |
453 | pcsx_read_mem ldrhcc, 1 |
c6c3b1b3 |
454 | |
5c6457c3 |
455 | FUNCTION(jump_handler_read32): |
c6c3b1b3 |
456 | pcsx_read_mem ldrcc, 2 |
457 | |
b96d3df7 |
458 | |
630b122b |
459 | .macro memhandler_post |
460 | ldr r0, [fp, #LO_next_interupt] |
461 | ldr r2, [fp, #LO_cycle] @ memhandlers can modify cc, like dma |
462 | str r0, [fp, #LO_last_count] |
463 | sub r0, r2, r0 |
464 | .endm |
465 | |
b96d3df7 |
466 | .macro pcsx_write_mem wrtop tab_shift |
467 | /* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */ |
468 | lsl r12,r0, #20 |
469 | lsr r12, #(20+\tab_shift) |
470 | ldr r3, [r3, r12, lsl #2] |
b1f89e6f |
471 | str r0, [fp, #LO_address] @ some handlers still need it.. |
b96d3df7 |
472 | lsls r3, #1 |
630b122b |
473 | mov r0, r2 @ cycle return in case of direct store |
b96d3df7 |
474 | .if \tab_shift == 1 |
475 | lsl r12, #1 |
476 | \wrtop r1, [r3, r12] |
477 | .else |
478 | \wrtop r1, [r3, r12, lsl #\tab_shift] |
479 | .endif |
480 | movcc pc, lr |
b1f89e6f |
481 | ldr r12, [fp, #LO_last_count] |
b96d3df7 |
482 | mov r0, r1 |
483 | add r2, r2, r12 |
b1f89e6f |
484 | str r2, [fp, #LO_cycle] |
630b122b |
485 | |
486 | str lr, [fp, #LO_saved_lr] |
b96d3df7 |
487 | blx r3 |
630b122b |
488 | ldr lr, [fp, #LO_saved_lr] |
b96d3df7 |
489 | |
630b122b |
490 | memhandler_post |
491 | bx lr |
b96d3df7 |
492 | .endm |
493 | |
5c6457c3 |
494 | FUNCTION(jump_handler_write8): |
b96d3df7 |
495 | add r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part |
b861c0a9 |
496 | pcsx_write_mem strbcc, 0 |
b96d3df7 |
497 | |
5c6457c3 |
498 | FUNCTION(jump_handler_write16): |
b96d3df7 |
499 | add r3, #0x1000/4*4 @ shift to r16 part |
b861c0a9 |
500 | pcsx_write_mem strhcc, 1 |
b96d3df7 |
501 | |
5c6457c3 |
502 | FUNCTION(jump_handler_write32): |
b96d3df7 |
503 | pcsx_write_mem strcc, 2 |
504 | |
5c6457c3 |
505 | FUNCTION(jump_handler_write_h): |
b96d3df7 |
506 | /* r0 = address, r1 = data, r2 = cycles, r3 = handler */ |
b1f89e6f |
507 | ldr r12, [fp, #LO_last_count] |
508 | str r0, [fp, #LO_address] @ some handlers still need it.. |
b96d3df7 |
509 | add r2, r2, r12 |
510 | mov r0, r1 |
b1f89e6f |
511 | str r2, [fp, #LO_cycle] |
630b122b |
512 | |
513 | str lr, [fp, #LO_saved_lr] |
b96d3df7 |
514 | blx r3 |
630b122b |
515 | ldr lr, [fp, #LO_saved_lr] |
b96d3df7 |
516 | |
630b122b |
517 | memhandler_post |
518 | bx lr |
b96d3df7 |
519 | |
5c6457c3 |
520 | FUNCTION(jump_handle_swl): |
b96d3df7 |
521 | /* r0 = address, r1 = data, r2 = cycles */ |
b1f89e6f |
522 | ldr r3, [fp, #LO_mem_wtab] |
b96d3df7 |
523 | mov r12,r0,lsr #12 |
524 | ldr r3, [r3, r12, lsl #2] |
525 | lsls r3, #1 |
526 | bcs 4f |
527 | add r3, r0, r3 |
528 | mov r0, r2 |
529 | tst r3, #2 |
530 | beq 101f |
531 | tst r3, #1 |
532 | beq 2f |
533 | 3: |
534 | str r1, [r3, #-3] |
535 | bx lr |
536 | 2: |
537 | lsr r2, r1, #8 |
538 | lsr r1, #24 |
539 | strh r2, [r3, #-2] |
540 | strb r1, [r3] |
541 | bx lr |
542 | 101: |
543 | tst r3, #1 |
544 | lsrne r1, #16 @ 1 |
545 | lsreq r12, r1, #24 @ 0 |
b861c0a9 |
546 | strhne r1, [r3, #-1] |
547 | strbeq r12, [r3] |
b96d3df7 |
548 | bx lr |
549 | 4: |
550 | mov r0, r2 |
63cb0298 |
551 | @ b abort |
b96d3df7 |
552 | bx lr @ TODO? |
553 | |
554 | |
5c6457c3 |
555 | FUNCTION(jump_handle_swr): |
b96d3df7 |
556 | /* r0 = address, r1 = data, r2 = cycles */ |
b1f89e6f |
557 | ldr r3, [fp, #LO_mem_wtab] |
b96d3df7 |
558 | mov r12,r0,lsr #12 |
559 | ldr r3, [r3, r12, lsl #2] |
560 | lsls r3, #1 |
561 | bcs 4f |
562 | add r3, r0, r3 |
563 | and r12,r3, #3 |
564 | mov r0, r2 |
565 | cmp r12,#2 |
b861c0a9 |
566 | strbgt r1, [r3] @ 3 |
567 | strheq r1, [r3] @ 2 |
b96d3df7 |
568 | cmp r12,#1 |
569 | strlt r1, [r3] @ 0 |
570 | bxne lr |
571 | lsr r2, r1, #8 @ 1 |
572 | strb r1, [r3] |
573 | strh r2, [r3, #1] |
574 | bx lr |
575 | 4: |
576 | mov r0, r2 |
63cb0298 |
577 | @ b abort |
b96d3df7 |
578 | bx lr @ TODO? |
579 | |
580 | |
b1be1eee |
581 | .macro rcntx_read_mode0 num |
582 | /* r0 = address, r2 = cycles */ |
b1f89e6f |
583 | ldr r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart |
b1be1eee |
584 | mov r0, r2, lsl #16 |
b861c0a9 |
585 | sub r0, r0, r3, lsl #16 |
b1be1eee |
586 | lsr r0, #16 |
587 | bx lr |
588 | .endm |
589 | |
5c6457c3 |
590 | FUNCTION(rcnt0_read_count_m0): |
b1be1eee |
591 | rcntx_read_mode0 0 |
592 | |
5c6457c3 |
593 | FUNCTION(rcnt1_read_count_m0): |
b1be1eee |
594 | rcntx_read_mode0 1 |
595 | |
5c6457c3 |
596 | FUNCTION(rcnt2_read_count_m0): |
b1be1eee |
597 | rcntx_read_mode0 2 |
598 | |
5c6457c3 |
599 | FUNCTION(rcnt0_read_count_m1): |
b1be1eee |
600 | /* r0 = address, r2 = cycles */ |
b1f89e6f |
601 | ldr r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart |
b1be1eee |
602 | mov_16 r1, 0x3334 |
603 | sub r2, r2, r3 |
604 | mul r0, r1, r2 @ /= 5 |
605 | lsr r0, #16 |
606 | bx lr |
607 | |
5c6457c3 |
608 | FUNCTION(rcnt1_read_count_m1): |
b1be1eee |
609 | /* r0 = address, r2 = cycles */ |
b1f89e6f |
610 | ldr r3, [fp, #LO_rcnts+6*4+7*4*1] |
b1be1eee |
611 | mov_24 r1, 0x1e6cde |
612 | sub r2, r2, r3 |
613 | umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd |
614 | bx lr |
615 | |
5c6457c3 |
616 | FUNCTION(rcnt2_read_count_m1): |
b1be1eee |
617 | /* r0 = address, r2 = cycles */ |
b1f89e6f |
618 | ldr r3, [fp, #LO_rcnts+6*4+7*4*2] |
b1be1eee |
619 | mov r0, r2, lsl #16-3 |
b861c0a9 |
620 | sub r0, r0, r3, lsl #16-3 |
b1be1eee |
621 | lsr r0, #16 @ /= 8 |
622 | bx lr |
623 | |
630b122b |
624 | FUNCTION(call_gteStall): |
625 | /* r0 = op_cycles, r1 = cycles */ |
626 | ldr r2, [fp, #LO_last_count] |
627 | str lr, [fp, #LO_saved_lr] |
628 | add r1, r1, r2 |
629 | str r1, [fp, #LO_cycle] |
630 | add r1, fp, #LO_psxRegs |
631 | bl gteCheckStallRaw |
632 | ldr lr, [fp, #LO_saved_lr] |
633 | add r10, r10, r0 |
634 | bx lr |
635 | |
9a6c6e37 |
636 | #ifdef HAVE_ARMV6 |
637 | |
638 | FUNCTION(get_reg): |
639 | ldr r12, [r0] |
640 | and r1, r1, #0xff |
641 | ldr r2, [r0, #4] |
642 | orr r1, r1, r1, lsl #8 |
643 | ldr r3, [r0, #8] |
644 | orr r1, r1, r1, lsl #16 @ searched char in every byte |
645 | ldrb r0, [r0, #12] @ last byte |
646 | eor r12, r12, r1 |
647 | eor r2, r2, r1 |
648 | eor r3, r3, r1 |
649 | cmp r0, r1, lsr #24 |
650 | mov r0, #12 |
651 | mvn r1, #0 @ r1=~0 |
652 | bxeq lr |
653 | orr r3, r3, #0xff000000 @ EXCLUDE_REG |
654 | uadd8 r0, r12, r1 @ add and set GE bits when not 0 (match) |
655 | mov r12, #0 |
656 | sel r0, r12, r1 @ 0 if no match, else ff in some byte |
657 | uadd8 r2, r2, r1 |
658 | sel r2, r12, r1 |
659 | uadd8 r3, r3, r1 |
660 | sel r3, r12, r1 |
661 | mov r12, #3 |
662 | clz r0, r0 @ 0, 8, 16, 24 or 32 |
663 | clz r2, r2 |
664 | clz r3, r3 |
665 | sub r0, r12, r0, lsr #3 @ 3, 2, 1, 0 or -1 |
666 | sub r2, r12, r2, lsr #3 |
667 | sub r3, r12, r3, lsr #3 |
668 | orr r2, r2, #4 |
669 | orr r3, r3, #8 |
670 | and r0, r0, r2 |
671 | and r0, r0, r3 |
672 | bx lr |
673 | |
674 | #endif /* HAVE_ARMV6 */ |
675 | |
7e605697 |
676 | @ vim:filetype=armasm |