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57871462 | 1 | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * |
2 | * Mupen64plus - new_dynarec.c * | |
20d507ba | 3 | * Copyright (C) 2009-2011 Ari64 * |
57871462 | 4 | * * |
5 | * This program is free software; you can redistribute it and/or modify * | |
6 | * it under the terms of the GNU General Public License as published by * | |
7 | * the Free Software Foundation; either version 2 of the License, or * | |
8 | * (at your option) any later version. * | |
9 | * * | |
10 | * This program is distributed in the hope that it will be useful, * | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
13 | * GNU General Public License for more details. * | |
14 | * * | |
15 | * You should have received a copy of the GNU General Public License * | |
16 | * along with this program; if not, write to the * | |
17 | * Free Software Foundation, Inc., * | |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * | |
19 | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ | |
20 | ||
21 | #include <stdlib.h> | |
22 | #include <stdint.h> //include for uint64_t | |
23 | #include <assert.h> | |
d848b60a | 24 | #include <errno.h> |
4600ba03 | 25 | #include <sys/mman.h> |
d148d265 | 26 | #ifdef __MACH__ |
27 | #include <libkern/OSCacheControl.h> | |
28 | #endif | |
1e212a25 | 29 | #ifdef _3DS |
30 | #include <3ds_utils.h> | |
31 | #endif | |
57871462 | 32 | |
d148d265 | 33 | #include "new_dynarec_config.h" |
630b122b | 34 | #include "../psxhle.h" |
35 | #include "../psxinterpreter.h" | |
36 | #include "../gte.h" | |
37 | #include "emu_if.h" // emulator interface | |
9a6c6e37 | 38 | #include "arm_features.h" |
630b122b | 39 | |
40 | #define noinline __attribute__((noinline,noclone)) | |
41 | #ifndef ARRAY_SIZE | |
42 | #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) | |
43 | #endif | |
44 | #ifndef min | |
45 | #define min(a, b) ((b) < (a) ? (b) : (a)) | |
46 | #endif | |
47 | #ifndef max | |
48 | #define max(a, b) ((b) > (a) ? (b) : (a)) | |
49 | #endif | |
57871462 | 50 | |
4600ba03 | 51 | //#define DISASM |
630b122b | 52 | //#define ASSEM_PRINT |
55cadc36 | 53 | //#define STAT_PRINT |
630b122b | 54 | |
55 | #ifdef ASSEM_PRINT | |
56 | #define assem_debug printf | |
57 | #else | |
4600ba03 | 58 | #define assem_debug(...) |
630b122b | 59 | #endif |
60 | //#define inv_debug printf | |
4600ba03 | 61 | #define inv_debug(...) |
57871462 | 62 | |
63 | #ifdef __i386__ | |
630b122b | 64 | #include "assem_x86.h" |
57871462 | 65 | #endif |
66 | #ifdef __x86_64__ | |
630b122b | 67 | #include "assem_x64.h" |
57871462 | 68 | #endif |
69 | #ifdef __arm__ | |
630b122b | 70 | #include "assem_arm.h" |
57871462 | 71 | #endif |
630b122b | 72 | #ifdef __aarch64__ |
73 | #include "assem_arm64.h" | |
73081f23 FJGG |
74 | #endif |
75 | ||
630b122b | 76 | #define RAM_SIZE 0x200000 |
57871462 | 77 | #define MAXBLOCK 4096 |
78 | #define MAX_OUTPUT_BLOCK_SIZE 262144 | |
432435ea | 79 | #define EXPIRITY_OFFSET (MAX_OUTPUT_BLOCK_SIZE * 2) |
80 | #define PAGE_COUNT 1024 | |
2573466a | 81 | |
b9e27215 | 82 | #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT) |
83 | #define INVALIDATE_USE_COND_CALL | |
84 | #endif | |
85 | ||
ab51e9e2 | 86 | #ifdef VITA |
87 | // apparently Vita has a 16MB limit, so either we cut tc in half, | |
88 | // or use this hack (it's a hack because tc size was designed to be power-of-2) | |
89 | #define TC_REDUCE_BYTES 4096 | |
90 | #else | |
91 | #define TC_REDUCE_BYTES 0 | |
92 | #endif | |
93 | ||
630b122b | 94 | struct ndrc_mem |
95 | { | |
ab51e9e2 | 96 | u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES]; |
630b122b | 97 | struct |
98 | { | |
99 | struct tramp_insns ops[2048 / sizeof(struct tramp_insns)]; | |
100 | const void *f[2048 / sizeof(void *)]; | |
101 | } tramp; | |
102 | }; | |
103 | ||
104 | #ifdef BASE_ADDR_DYNAMIC | |
105 | static struct ndrc_mem *ndrc; | |
106 | #else | |
107 | static struct ndrc_mem ndrc_ __attribute__((aligned(4096))); | |
108 | static struct ndrc_mem *ndrc = &ndrc_; | |
109 | #endif | |
110 | ||
111 | // stubs | |
112 | enum stub_type { | |
113 | CC_STUB = 1, | |
114 | FP_STUB = 2, | |
115 | LOADB_STUB = 3, | |
116 | LOADH_STUB = 4, | |
117 | LOADW_STUB = 5, | |
118 | LOADD_STUB = 6, | |
119 | LOADBU_STUB = 7, | |
120 | LOADHU_STUB = 8, | |
121 | STOREB_STUB = 9, | |
122 | STOREH_STUB = 10, | |
123 | STOREW_STUB = 11, | |
124 | STORED_STUB = 12, | |
125 | STORELR_STUB = 13, | |
126 | INVCODE_STUB = 14, | |
127 | }; | |
128 | ||
b15d122e | 129 | // regmap_pre[i] - regs before [i] insn starts; dirty things here that |
130 | // don't match .regmap will be written back | |
131 | // [i].regmap_entry - regs that must be set up if someone jumps here | |
132 | // [i].regmap - regs [i] insn will read/(over)write | |
fdf33825 | 133 | // branch_regs[i].* - same as above but for branches, takes delay slot into account |
57871462 | 134 | struct regstat |
135 | { | |
b15d122e | 136 | signed char regmap_entry[HOST_REGS]; |
57871462 | 137 | signed char regmap[HOST_REGS]; |
57871462 | 138 | uint64_t wasdirty; |
139 | uint64_t dirty; | |
140 | uint64_t u; | |
630b122b | 141 | u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true |
142 | u_int isconst; // ... but isconst is false when r2 is known | |
8575a877 | 143 | u_int loadedconst; // host regs that have constants loaded |
144 | u_int waswritten; // MIPS regs that were used as store base before | |
57871462 | 145 | }; |
146 | ||
630b122b | 147 | struct ht_entry |
148 | { | |
149 | u_int vaddr[2]; | |
150 | void *tcaddr[2]; | |
151 | }; | |
152 | ||
153 | struct code_stub | |
154 | { | |
155 | enum stub_type type; | |
156 | void *addr; | |
157 | void *retaddr; | |
158 | u_int a; | |
159 | uintptr_t b; | |
160 | uintptr_t c; | |
161 | u_int d; | |
162 | u_int e; | |
163 | }; | |
164 | ||
165 | struct link_entry | |
166 | { | |
167 | void *addr; | |
168 | u_int target; | |
048fcced | 169 | u_int internal; |
170 | }; | |
171 | ||
172 | struct block_info | |
173 | { | |
174 | struct block_info *next; | |
175 | const void *source; | |
176 | const void *copy; | |
177 | u_int start; // vaddr of the block start | |
178 | u_int len; // of the whole block source | |
179 | u_int tc_offs; | |
180 | //u_int tc_len; | |
181 | u_int reg_sv_flags; | |
182 | u_short is_dirty; | |
183 | u_short jump_in_cnt; | |
184 | struct { | |
185 | u_int vaddr; | |
186 | void *addr; | |
187 | } jump_in[0]; | |
630b122b | 188 | }; |
189 | ||
366d1d2b | 190 | struct jump_info |
191 | { | |
192 | int alloc; | |
193 | int count; | |
194 | struct { | |
195 | u_int target_vaddr; | |
196 | void *stub; | |
197 | } e[0]; | |
198 | }; | |
199 | ||
630b122b | 200 | static struct decoded_insn |
201 | { | |
202 | u_char itype; | |
203 | u_char opcode; | |
204 | u_char opcode2; | |
205 | u_char rs1; | |
206 | u_char rs2; | |
207 | u_char rt1; | |
208 | u_char rt2; | |
ed14d777 | 209 | u_char use_lt1:1; |
630b122b | 210 | u_char bt:1; |
211 | u_char ooo:1; | |
212 | u_char is_ds:1; | |
213 | u_char is_jump:1; | |
214 | u_char is_ujump:1; | |
215 | u_char is_load:1; | |
216 | u_char is_store:1; | |
217 | } dops[MAXBLOCK]; | |
218 | ||
bfdecce3 | 219 | static u_char *out; |
048fcced | 220 | static struct ht_entry hash_table[65536]; |
432435ea | 221 | static struct block_info *blocks[PAGE_COUNT]; |
366d1d2b | 222 | static struct jump_info *jumps[PAGE_COUNT]; |
e2b5e7aa | 223 | static u_int start; |
224 | static u_int *source; | |
bedfea38 | 225 | static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs |
226 | static uint64_t gte_rt[MAXBLOCK]; | |
227 | static uint64_t gte_unneeded[MAXBLOCK]; | |
ffb0b9e0 | 228 | static u_int smrv[32]; // speculated MIPS register values |
229 | static u_int smrv_strong; // mask or regs that are likely to have correct values | |
230 | static u_int smrv_weak; // same, but somewhat less likely | |
231 | static u_int smrv_strong_next; // same, but after current insn executes | |
232 | static u_int smrv_weak_next; | |
e2b5e7aa | 233 | static int imm[MAXBLOCK]; |
234 | static u_int ba[MAXBLOCK]; | |
e2b5e7aa | 235 | static uint64_t unneeded_reg[MAXBLOCK]; |
e2b5e7aa | 236 | static uint64_t branch_unneeded_reg[MAXBLOCK]; |
b15d122e | 237 | // see 'struct regstat' for a description |
e2b5e7aa | 238 | static signed char regmap_pre[MAXBLOCK][HOST_REGS]; |
630b122b | 239 | // contains 'real' consts at [i] insn, but may differ from what's actually |
240 | // loaded in host reg as 'final' value is always loaded, see get_final_value() | |
241 | static uint32_t current_constmap[HOST_REGS]; | |
242 | static uint32_t constmap[MAXBLOCK][HOST_REGS]; | |
956f3129 | 243 | static struct regstat regs[MAXBLOCK]; |
244 | static struct regstat branch_regs[MAXBLOCK]; | |
e2b5e7aa | 245 | static signed char minimum_free_regs[MAXBLOCK]; |
e2b5e7aa | 246 | static int ccadj[MAXBLOCK]; |
247 | static int slen; | |
630b122b | 248 | static void *instr_addr[MAXBLOCK]; |
249 | static struct link_entry link_addr[MAXBLOCK]; | |
e2b5e7aa | 250 | static int linkcount; |
630b122b | 251 | static struct code_stub stubs[MAXBLOCK*3]; |
e2b5e7aa | 252 | static int stubcount; |
253 | static u_int literals[1024][2]; | |
254 | static int literalcount; | |
255 | static int is_delayslot; | |
e2b5e7aa | 256 | static char shadow[1048576] __attribute__((aligned(16))); |
257 | static void *copy; | |
432435ea | 258 | static u_int expirep; |
e2b5e7aa | 259 | static u_int stop_after_jal; |
7c8454e3 | 260 | static u_int f1_hack; |
55cadc36 | 261 | #ifdef STAT_PRINT |
262 | static int stat_bc_direct; | |
263 | static int stat_bc_pre; | |
264 | static int stat_bc_restore; | |
048fcced | 265 | static int stat_ht_lookups; |
55cadc36 | 266 | static int stat_jump_in_lookups; |
267 | static int stat_restore_tries; | |
268 | static int stat_restore_compares; | |
269 | static int stat_inv_addr_calls; | |
270 | static int stat_inv_hits; | |
048fcced | 271 | static int stat_blocks; |
272 | static int stat_links; | |
55cadc36 | 273 | #define stat_inc(s) s++ |
048fcced | 274 | #define stat_dec(s) s-- |
275 | #define stat_clear(s) s = 0 | |
55cadc36 | 276 | #else |
277 | #define stat_inc(s) | |
048fcced | 278 | #define stat_dec(s) |
279 | #define stat_clear(s) | |
55cadc36 | 280 | #endif |
e2b5e7aa | 281 | |
282 | int new_dynarec_hacks; | |
630b122b | 283 | int new_dynarec_hacks_pergame; |
284 | int new_dynarec_hacks_old; | |
e2b5e7aa | 285 | int new_dynarec_did_compile; |
630b122b | 286 | |
287 | #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x)) | |
288 | ||
289 | extern int cycle_count; // ... until end of the timeslice, counts -N -> 0 | |
290 | extern int last_count; // last absolute target, often = next_interupt | |
291 | extern int pcaddr; | |
292 | extern int pending_exception; | |
293 | extern int branch_target; | |
294 | extern uintptr_t ram_offset; | |
295 | extern uintptr_t mini_ht[32][2]; | |
57871462 | 296 | |
297 | /* registers that may be allocated */ | |
298 | /* 1-31 gpr */ | |
630b122b | 299 | #define LOREG 32 // lo |
300 | #define HIREG 33 // hi | |
301 | //#define FSREG 34 // FPU status (FCSR) | |
57871462 | 302 | #define CSREG 35 // Coprocessor status |
303 | #define CCREG 36 // Cycle count | |
304 | #define INVCP 37 // Pointer to invalid_code | |
1edfcc68 | 305 | //#define MMREG 38 // Pointer to memory_map |
619e5ded | 306 | #define ROREG 39 // ram offset (if rdram!=0x80000000) |
307 | #define TEMPREG 40 | |
308 | #define FTEMP 40 // FPU temporary register | |
309 | #define PTEMP 41 // Prefetch temporary register | |
1edfcc68 | 310 | //#define TLREG 42 // TLB mapping offset |
619e5ded | 311 | #define RHASH 43 // Return address hash |
312 | #define RHTBL 44 // Return address hash table address | |
313 | #define RTEMP 45 // JR/JALR address register | |
314 | #define MAXREG 45 | |
315 | #define AGEN1 46 // Address generation temporary register | |
1edfcc68 | 316 | //#define AGEN2 47 // Address generation temporary register |
317 | //#define MGEN1 48 // Maptable address generation temporary register | |
318 | //#define MGEN2 49 // Maptable address generation temporary register | |
619e5ded | 319 | #define BTREG 50 // Branch target temporary register |
57871462 | 320 | |
321 | /* instruction types */ | |
322 | #define NOP 0 // No operation | |
323 | #define LOAD 1 // Load | |
324 | #define STORE 2 // Store | |
325 | #define LOADLR 3 // Unaligned load | |
326 | #define STORELR 4 // Unaligned store | |
9f51b4b9 | 327 | #define MOV 5 // Move |
57871462 | 328 | #define ALU 6 // Arithmetic/logic |
329 | #define MULTDIV 7 // Multiply/divide | |
330 | #define SHIFT 8 // Shift by register | |
331 | #define SHIFTIMM 9// Shift by immediate | |
332 | #define IMM16 10 // 16-bit immediate | |
333 | #define RJUMP 11 // Unconditional jump to register | |
334 | #define UJUMP 12 // Unconditional jump | |
335 | #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ) | |
336 | #define SJUMP 14 // Conditional branch (regimm format) | |
337 | #define COP0 15 // Coprocessor 0 | |
338 | #define COP1 16 // Coprocessor 1 | |
339 | #define C1LS 17 // Coprocessor 1 load/store | |
630b122b | 340 | //#define FJUMP 18 // Conditional branch (floating point) |
341 | //#define FLOAT 19 // Floating point unit | |
342 | //#define FCONV 20 // Convert integer to float | |
343 | //#define FCOMP 21 // Floating point compare (sets FSREG) | |
467357cc | 344 | #define SYSCALL 22// SYSCALL,BREAK |
57871462 | 345 | #define OTHER 23 // Other |
f9e37973 | 346 | //#define SPAN 24 // Branch/delay slot spans 2 pages |
57871462 | 347 | #define NI 25 // Not implemented |
7139f3c8 | 348 | #define HLECALL 26// PCSX fake opcodes for HLE |
b9b61529 | 349 | #define COP2 27 // Coprocessor 2 move |
350 | #define C2LS 28 // Coprocessor 2 load/store | |
351 | #define C2OP 29 // Coprocessor 2 operation | |
1e973cb0 | 352 | #define INTCALL 30// Call interpreter to handle rare corner cases |
57871462 | 353 | |
57871462 | 354 | /* branch codes */ |
355 | #define TAKEN 1 | |
356 | #define NOTTAKEN 2 | |
357 | #define NULLDS 3 | |
358 | ||
630b122b | 359 | #define DJT_1 (void *)1l // no function, just a label in assem_debug log |
360 | #define DJT_2 (void *)2l | |
361 | ||
57871462 | 362 | // asm linkage |
57871462 | 363 | void dyna_linker(); |
57871462 | 364 | void cc_interrupt(); |
365 | void fp_exception(); | |
366 | void fp_exception_ds(); | |
467357cc | 367 | void jump_syscall (u_int u0, u_int u1, u_int pc); |
368 | void jump_syscall_ds(u_int u0, u_int u1, u_int pc); | |
369 | void jump_break (u_int u0, u_int u1, u_int pc); | |
370 | void jump_break_ds(u_int u0, u_int u1, u_int pc); | |
630b122b | 371 | void jump_to_new_pc(); |
372 | void call_gteStall(); | |
7139f3c8 | 373 | void new_dyna_leave(); |
57871462 | 374 | |
048fcced | 375 | void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile); |
376 | void *ndrc_get_addr_ht(u_int vaddr); | |
377 | void ndrc_invalidate_addr(u_int addr); | |
378 | void ndrc_add_jump_out(u_int vaddr, void *src); | |
379 | ||
380 | static int new_recompile_block(u_int addr); | |
381 | static void invalidate_block(struct block_info *block); | |
bfdecce3 | 382 | |
57871462 | 383 | // Needed by assembler |
630b122b | 384 | static void wb_register(signed char r, const signed char regmap[], uint64_t dirty); |
385 | static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty); | |
386 | static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr); | |
387 | static void load_all_regs(const signed char i_regmap[]); | |
388 | static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]); | |
e2b5e7aa | 389 | static void load_regs_entry(int t); |
630b122b | 390 | static void load_all_consts(const signed char regmap[], u_int dirty, int i); |
391 | static u_int get_host_reglist(const signed char *regmap); | |
e2b5e7aa | 392 | |
e2b5e7aa | 393 | static int get_final_value(int hr, int i, int *value); |
630b122b | 394 | static void add_stub(enum stub_type type, void *addr, void *retaddr, |
395 | u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e); | |
396 | static void add_stub_r(enum stub_type type, void *addr, void *retaddr, | |
397 | int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist); | |
398 | static void add_to_linker(void *addr, u_int target, int ext); | |
399 | static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs, | |
400 | int addr, int *offset_reg, int *addr_reg_override); | |
401 | static void *get_direct_memhandler(void *table, u_int addr, | |
402 | enum stub_type type, uintptr_t *addr_host); | |
403 | static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist); | |
404 | static void pass_args(int a0, int a1); | |
405 | static void emit_far_jump(const void *f); | |
406 | static void emit_far_call(const void *f); | |
57871462 | 407 | |
af4a16ff | 408 | #ifdef VITA |
409 | #include <psp2/kernel/sysmem.h> | |
410 | static int sceBlock; | |
411 | // note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c | |
412 | extern int getVMBlock(); | |
413 | int _newlib_vm_size_user = sizeof(*ndrc); | |
414 | #endif | |
415 | ||
d148d265 | 416 | static void mprotect_w_x(void *start, void *end, int is_x) |
417 | { | |
418 | #ifdef NO_WRITE_EXEC | |
1e212a25 | 419 | #if defined(VITA) |
420 | // *Open* enables write on all memory that was | |
421 | // allocated by sceKernelAllocMemBlockForVM()? | |
422 | if (is_x) | |
423 | sceKernelCloseVMDomain(); | |
424 | else | |
425 | sceKernelOpenVMDomain(); | |
426 | #else | |
d148d265 | 427 | u_long mstart = (u_long)start & ~4095ul; |
428 | u_long mend = (u_long)end; | |
429 | if (mprotect((void *)mstart, mend - mstart, | |
430 | PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0) | |
431 | SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno)); | |
1e212a25 | 432 | #endif |
d148d265 | 433 | #endif |
434 | } | |
435 | ||
436 | static void start_tcache_write(void *start, void *end) | |
437 | { | |
438 | mprotect_w_x(start, end, 0); | |
439 | } | |
440 | ||
441 | static void end_tcache_write(void *start, void *end) | |
442 | { | |
630b122b | 443 | #if defined(__arm__) || defined(__aarch64__) |
d148d265 | 444 | size_t len = (char *)end - (char *)start; |
445 | #if defined(__BLACKBERRY_QNX__) | |
446 | msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE); | |
447 | #elif defined(__MACH__) | |
448 | sys_cache_control(kCacheFunctionPrepareForExecution, start, len); | |
449 | #elif defined(VITA) | |
1e212a25 | 450 | sceKernelSyncVMDomain(sceBlock, start, len); |
451 | #elif defined(_3DS) | |
452 | ctr_flush_invalidate_cache(); | |
630b122b | 453 | #elif defined(__aarch64__) |
454 | // as of 2021, __clear_cache() is still broken on arm64 | |
455 | // so here is a custom one :( | |
456 | clear_cache_arm64(start, end); | |
d148d265 | 457 | #else |
458 | __clear_cache(start, end); | |
459 | #endif | |
460 | (void)len; | |
461 | #endif | |
462 | ||
463 | mprotect_w_x(start, end, 1); | |
464 | } | |
465 | ||
466 | static void *start_block(void) | |
467 | { | |
468 | u_char *end = out + MAX_OUTPUT_BLOCK_SIZE; | |
630b122b | 469 | if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache)) |
470 | end = ndrc->translation_cache + sizeof(ndrc->translation_cache); | |
d148d265 | 471 | start_tcache_write(out, end); |
472 | return out; | |
473 | } | |
474 | ||
475 | static void end_block(void *start) | |
476 | { | |
477 | end_tcache_write(start, out); | |
478 | } | |
479 | ||
630b122b | 480 | // also takes care of w^x mappings when patching code |
481 | static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)]; | |
482 | ||
483 | static void mark_clear_cache(void *target) | |
484 | { | |
485 | uintptr_t offset = (u_char *)target - ndrc->translation_cache; | |
486 | u_int mask = 1u << ((offset >> 12) & 31); | |
487 | if (!(needs_clear_cache[offset >> 17] & mask)) { | |
488 | char *start = (char *)((uintptr_t)target & ~4095l); | |
489 | start_tcache_write(start, start + 4095); | |
490 | needs_clear_cache[offset >> 17] |= mask; | |
491 | } | |
492 | } | |
493 | ||
494 | // Clearing the cache is rather slow on ARM Linux, so mark the areas | |
495 | // that need to be cleared, and then only clear these areas once. | |
496 | static void do_clear_cache(void) | |
497 | { | |
498 | int i, j; | |
499 | for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++) | |
500 | { | |
501 | u_int bitmap = needs_clear_cache[i]; | |
502 | if (!bitmap) | |
503 | continue; | |
504 | for (j = 0; j < 32; j++) | |
505 | { | |
506 | u_char *start, *end; | |
432435ea | 507 | if (!(bitmap & (1u << j))) |
630b122b | 508 | continue; |
509 | ||
510 | start = ndrc->translation_cache + i*131072 + j*4096; | |
511 | end = start + 4095; | |
512 | for (j++; j < 32; j++) { | |
432435ea | 513 | if (!(bitmap & (1u << j))) |
630b122b | 514 | break; |
515 | end += 4096; | |
516 | } | |
517 | end_tcache_write(start, end); | |
518 | } | |
519 | needs_clear_cache[i] = 0; | |
520 | } | |
521 | } | |
522 | ||
57871462 | 523 | //#define DEBUG_CYCLE_COUNT 1 |
524 | ||
b6e87b2b | 525 | #define NO_CYCLE_PENALTY_THR 12 |
526 | ||
630b122b | 527 | int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0 |
528 | int cycle_multiplier_override; | |
529 | int cycle_multiplier_old; | |
530 | static int cycle_multiplier_active; | |
4e9dcd7f | 531 | |
532 | static int CLOCK_ADJUST(int x) | |
533 | { | |
630b122b | 534 | int m = cycle_multiplier_active; |
535 | int s = (x >> 31) | 1; | |
536 | return (x * m + s * 50) / 100; | |
537 | } | |
538 | ||
539 | static int ds_writes_rjump_rs(int i) | |
540 | { | |
541 | return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2); | |
4e9dcd7f | 542 | } |
543 | ||
048fcced | 544 | // psx addr mirror masking (for invalidation) |
545 | static u_int pmmask(u_int vaddr) | |
546 | { | |
547 | vaddr &= ~0xe0000000; | |
548 | if (vaddr < 0x01000000) | |
549 | vaddr &= ~0x00e00000; // RAM mirrors | |
550 | return vaddr; | |
551 | } | |
552 | ||
94d23bb9 | 553 | static u_int get_page(u_int vaddr) |
57871462 | 554 | { |
048fcced | 555 | u_int page = pmmask(vaddr) >> 12; |
432435ea | 556 | if (page >= PAGE_COUNT / 2) |
557 | page = PAGE_COUNT / 2 + (page & (PAGE_COUNT / 2 - 1)); | |
94d23bb9 | 558 | return page; |
559 | } | |
560 | ||
048fcced | 561 | // get a page for looking for a block that has vaddr |
562 | // (needed because the block may start in previous page) | |
563 | static u_int get_page_prev(u_int vaddr) | |
d25604ca | 564 | { |
048fcced | 565 | assert(MAXBLOCK <= (1 << 12)); |
566 | u_int page = get_page(vaddr); | |
567 | if (page & 511) | |
568 | page--; | |
569 | return page; | |
d25604ca | 570 | } |
94d23bb9 | 571 | |
630b122b | 572 | static struct ht_entry *hash_table_get(u_int vaddr) |
573 | { | |
574 | return &hash_table[((vaddr>>16)^vaddr)&0xFFFF]; | |
575 | } | |
576 | ||
048fcced | 577 | static void hash_table_add(u_int vaddr, void *tcaddr) |
630b122b | 578 | { |
048fcced | 579 | struct ht_entry *ht_bin = hash_table_get(vaddr); |
580 | assert(tcaddr); | |
630b122b | 581 | ht_bin->vaddr[1] = ht_bin->vaddr[0]; |
582 | ht_bin->tcaddr[1] = ht_bin->tcaddr[0]; | |
583 | ht_bin->vaddr[0] = vaddr; | |
584 | ht_bin->tcaddr[0] = tcaddr; | |
585 | } | |
586 | ||
048fcced | 587 | static void hash_table_remove(int vaddr) |
588 | { | |
589 | //printf("remove hash: %x\n",vaddr); | |
590 | struct ht_entry *ht_bin = hash_table_get(vaddr); | |
591 | if (ht_bin->vaddr[1] == vaddr) { | |
592 | ht_bin->vaddr[1] = -1; | |
593 | ht_bin->tcaddr[1] = NULL; | |
594 | } | |
595 | if (ht_bin->vaddr[0] == vaddr) { | |
596 | ht_bin->vaddr[0] = ht_bin->vaddr[1]; | |
597 | ht_bin->tcaddr[0] = ht_bin->tcaddr[1]; | |
598 | ht_bin->vaddr[1] = -1; | |
599 | ht_bin->tcaddr[1] = NULL; | |
600 | } | |
601 | } | |
602 | ||
603 | static void mark_invalid_code(u_int vaddr, u_int len, char invalid) | |
bfdecce3 | 604 | { |
605 | u_int i, j; | |
606 | vaddr &= 0x1fffffff; | |
607 | for (i = vaddr & ~0xfff; i < vaddr + len; i += 0x1000) { | |
608 | // ram mirrors, but should not hurt bios | |
609 | for (j = 0; j < 0x800000; j += 0x200000) { | |
610 | invalid_code[(i|j) >> 12] = | |
611 | invalid_code[(i|j|0x80000000u) >> 12] = | |
048fcced | 612 | invalid_code[(i|j|0xa0000000u) >> 12] = invalid; |
bfdecce3 | 613 | } |
614 | } | |
b9e27215 | 615 | if (!invalid && vaddr + len > inv_code_start && vaddr <= inv_code_end) |
048fcced | 616 | inv_code_start = inv_code_end = ~0; |
bfdecce3 | 617 | } |
618 | ||
432435ea | 619 | static int doesnt_expire_soon(u_char *tcaddr) |
630b122b | 620 | { |
432435ea | 621 | u_int diff = (u_int)(tcaddr - out) & ((1u << TARGET_SIZE_2) - 1u); |
622 | return diff > EXPIRITY_OFFSET + MAX_OUTPUT_BLOCK_SIZE; | |
630b122b | 623 | } |
624 | ||
048fcced | 625 | static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page) |
bfdecce3 | 626 | { |
048fcced | 627 | void *found_clean = NULL; |
628 | u_int i, page; | |
bfdecce3 | 629 | |
55cadc36 | 630 | stat_inc(stat_restore_tries); |
048fcced | 631 | for (page = start_page; page <= end_page; page++) { |
632 | struct block_info *block; | |
633 | for (block = blocks[page]; block != NULL; block = block->next) { | |
634 | if (vaddr < block->start) | |
635 | break; | |
636 | if (!block->is_dirty || vaddr >= block->start + block->len) | |
637 | continue; | |
638 | for (i = 0; i < block->jump_in_cnt; i++) | |
639 | if (block->jump_in[i].vaddr == vaddr) | |
640 | break; | |
641 | if (i == block->jump_in_cnt) | |
642 | continue; | |
643 | assert(block->source && block->copy); | |
644 | stat_inc(stat_restore_compares); | |
645 | if (memcmp(block->source, block->copy, block->len)) | |
646 | continue; | |
bfdecce3 | 647 | |
048fcced | 648 | block->is_dirty = 0; |
649 | found_clean = block->jump_in[i].addr; | |
650 | hash_table_add(vaddr, found_clean); | |
651 | mark_invalid_code(block->start, block->len, 0); | |
652 | stat_inc(stat_bc_restore); | |
653 | inv_debug("INV: restored %08x %p (%d)\n", vaddr, found_clean, block->jump_in_cnt); | |
654 | return found_clean; | |
bfdecce3 | 655 | } |
bfdecce3 | 656 | } |
048fcced | 657 | return NULL; |
bfdecce3 | 658 | } |
659 | ||
94d23bb9 | 660 | // Get address from virtual address |
661 | // This is called from the recompiled JR/JALR instructions | |
048fcced | 662 | static void noinline *get_addr(u_int vaddr, int can_compile) |
94d23bb9 | 663 | { |
048fcced | 664 | u_int start_page = get_page_prev(vaddr); |
665 | u_int i, page, end_page = get_page(vaddr); | |
666 | void *found_clean = NULL; | |
bfdecce3 | 667 | |
55cadc36 | 668 | stat_inc(stat_jump_in_lookups); |
048fcced | 669 | for (page = start_page; page <= end_page; page++) { |
670 | const struct block_info *block; | |
671 | for (block = blocks[page]; block != NULL; block = block->next) { | |
672 | if (vaddr < block->start) | |
673 | break; | |
674 | if (block->is_dirty || vaddr >= block->start + block->len) | |
675 | continue; | |
676 | for (i = 0; i < block->jump_in_cnt; i++) | |
677 | if (block->jump_in[i].vaddr == vaddr) | |
678 | break; | |
679 | if (i == block->jump_in_cnt) | |
680 | continue; | |
681 | found_clean = block->jump_in[i].addr; | |
682 | hash_table_add(vaddr, found_clean); | |
683 | return found_clean; | |
57871462 | 684 | } |
57871462 | 685 | } |
048fcced | 686 | found_clean = try_restore_block(vaddr, start_page, end_page); |
687 | if (found_clean) | |
688 | return found_clean; | |
689 | ||
690 | if (!can_compile) | |
691 | return NULL; | |
bfdecce3 | 692 | |
693 | int r = new_recompile_block(vaddr); | |
694 | if (r == 0) | |
048fcced | 695 | return ndrc_get_addr_ht(vaddr); |
0bfdd1aa | 696 | |
b0163e04 | 697 | // generate an address error |
57871462 | 698 | Status|=2; |
b0163e04 | 699 | Cause=(vaddr<<31)|(4<<2); |
57871462 | 700 | EPC=(vaddr&1)?vaddr-5:vaddr; |
701 | BadVAddr=(vaddr&~1); | |
048fcced | 702 | return ndrc_get_addr_ht(0x80000080); |
57871462 | 703 | } |
048fcced | 704 | |
57871462 | 705 | // Look up address in hash table first |
048fcced | 706 | void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile) |
57871462 | 707 | { |
630b122b | 708 | const struct ht_entry *ht_bin = hash_table_get(vaddr); |
048fcced | 709 | stat_inc(stat_ht_lookups); |
630b122b | 710 | if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0]; |
711 | if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1]; | |
048fcced | 712 | return get_addr(vaddr, can_compile); |
713 | } | |
714 | ||
715 | void *ndrc_get_addr_ht(u_int vaddr) | |
716 | { | |
717 | return ndrc_get_addr_ht_param(vaddr, 1); | |
57871462 | 718 | } |
719 | ||
b15d122e | 720 | static void clear_all_regs(signed char regmap[]) |
57871462 | 721 | { |
b15d122e | 722 | memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS); |
57871462 | 723 | } |
724 | ||
e912c27d | 725 | // get_reg: get allocated host reg from mips reg |
726 | // returns -1 if no such mips reg was allocated | |
9a6c6e37 | 727 | #if defined(__arm__) && defined(HAVE_ARMV6) && HOST_REGS == 13 && EXCLUDE_REG == 11 |
728 | ||
729 | extern signed char get_reg(const signed char regmap[], signed char r); | |
730 | ||
731 | #else | |
732 | ||
91af94f0 | 733 | static signed char get_reg(const signed char regmap[], signed char r) |
57871462 | 734 | { |
735 | int hr; | |
91af94f0 | 736 | for (hr = 0; hr < HOST_REGS; hr++) { |
737 | if (hr == EXCLUDE_REG) | |
738 | continue; | |
739 | if (regmap[hr] == r) | |
740 | return hr; | |
741 | } | |
742 | return -1; | |
743 | } | |
744 | ||
9a6c6e37 | 745 | #endif |
746 | ||
e912c27d | 747 | // get reg as mask bit (1 << hr) |
748 | static u_int get_regm(const signed char regmap[], signed char r) | |
749 | { | |
750 | return (1u << (get_reg(regmap, r) & 31)) & ~(1u << 31); | |
751 | } | |
752 | ||
91af94f0 | 753 | static signed char get_reg_temp(const signed char regmap[]) |
754 | { | |
755 | int hr; | |
756 | for (hr = 0; hr < HOST_REGS; hr++) { | |
757 | if (hr == EXCLUDE_REG) | |
758 | continue; | |
759 | if (regmap[hr] == (signed char)-1) | |
760 | return hr; | |
761 | } | |
57871462 | 762 | return -1; |
763 | } | |
764 | ||
765 | // Find a register that is available for two consecutive cycles | |
630b122b | 766 | static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r) |
57871462 | 767 | { |
768 | int hr; | |
769 | for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr; | |
770 | return -1; | |
771 | } | |
772 | ||
ed14d777 | 773 | // reverse reg map: mips -> host |
774 | #define RRMAP_SIZE 64 | |
775 | static void make_rregs(const signed char regmap[], signed char rrmap[RRMAP_SIZE], | |
776 | u_int *regs_can_change) | |
777 | { | |
778 | u_int r, hr, hr_can_change = 0; | |
779 | memset(rrmap, -1, RRMAP_SIZE); | |
780 | for (hr = 0; hr < HOST_REGS; ) | |
781 | { | |
782 | r = regmap[hr]; | |
783 | rrmap[r & (RRMAP_SIZE - 1)] = hr; | |
784 | // only add mips $1-$31+$lo, others shifted out | |
785 | hr_can_change |= (uint64_t)1 << (hr + ((r - 1) & 32)); | |
786 | hr++; | |
787 | if (hr == EXCLUDE_REG) | |
788 | hr++; | |
789 | } | |
790 | hr_can_change |= 1u << (rrmap[33] & 31); | |
791 | hr_can_change |= 1u << (rrmap[CCREG] & 31); | |
792 | hr_can_change &= ~(1u << 31); | |
793 | *regs_can_change = hr_can_change; | |
794 | } | |
795 | ||
796 | // same as get_reg, but takes rrmap | |
797 | static signed char get_rreg(signed char rrmap[RRMAP_SIZE], signed char r) | |
798 | { | |
799 | assert(0 <= r && r < RRMAP_SIZE); | |
800 | return rrmap[r]; | |
801 | } | |
802 | ||
91af94f0 | 803 | static int count_free_regs(const signed char regmap[]) |
57871462 | 804 | { |
805 | int count=0; | |
806 | int hr; | |
807 | for(hr=0;hr<HOST_REGS;hr++) | |
808 | { | |
809 | if(hr!=EXCLUDE_REG) { | |
810 | if(regmap[hr]<0) count++; | |
811 | } | |
812 | } | |
813 | return count; | |
814 | } | |
815 | ||
91af94f0 | 816 | static void dirty_reg(struct regstat *cur, signed char reg) |
57871462 | 817 | { |
818 | int hr; | |
91af94f0 | 819 | if (!reg) return; |
820 | hr = get_reg(cur->regmap, reg); | |
821 | if (hr >= 0) | |
822 | cur->dirty |= 1<<hr; | |
57871462 | 823 | } |
824 | ||
630b122b | 825 | static void set_const(struct regstat *cur, signed char reg, uint32_t value) |
57871462 | 826 | { |
827 | int hr; | |
91af94f0 | 828 | if (!reg) return; |
829 | hr = get_reg(cur->regmap, reg); | |
830 | if (hr >= 0) { | |
831 | cur->isconst |= 1<<hr; | |
832 | current_constmap[hr] = value; | |
57871462 | 833 | } |
834 | } | |
835 | ||
630b122b | 836 | static void clear_const(struct regstat *cur, signed char reg) |
57871462 | 837 | { |
838 | int hr; | |
91af94f0 | 839 | if (!reg) return; |
840 | hr = get_reg(cur->regmap, reg); | |
841 | if (hr >= 0) | |
842 | cur->isconst &= ~(1<<hr); | |
57871462 | 843 | } |
844 | ||
91af94f0 | 845 | static int is_const(const struct regstat *cur, signed char reg) |
57871462 | 846 | { |
847 | int hr; | |
91af94f0 | 848 | if (reg < 0) return 0; |
849 | if (!reg) return 1; | |
850 | hr = get_reg(cur->regmap, reg); | |
851 | if (hr >= 0) | |
852 | return (cur->isconst>>hr)&1; | |
57871462 | 853 | return 0; |
854 | } | |
630b122b | 855 | |
91af94f0 | 856 | static uint32_t get_const(const struct regstat *cur, signed char reg) |
57871462 | 857 | { |
858 | int hr; | |
91af94f0 | 859 | if (!reg) return 0; |
860 | hr = get_reg(cur->regmap, reg); | |
861 | if (hr >= 0) | |
862 | return current_constmap[hr]; | |
863 | ||
864 | SysPrintf("Unknown constant in r%d\n", reg); | |
630b122b | 865 | abort(); |
57871462 | 866 | } |
867 | ||
868 | // Least soon needed registers | |
869 | // Look at the next ten instructions and see which registers | |
870 | // will be used. Try not to reallocate these. | |
94061aa5 | 871 | static void lsn(u_char hsn[], int i, int *preferred_reg) |
57871462 | 872 | { |
873 | int j; | |
874 | int b=-1; | |
875 | for(j=0;j<9;j++) | |
876 | { | |
877 | if(i+j>=slen) { | |
878 | j=slen-i-1; | |
879 | break; | |
880 | } | |
630b122b | 881 | if (dops[i+j].is_ujump) |
57871462 | 882 | { |
883 | // Don't go past an unconditonal jump | |
884 | j++; | |
885 | break; | |
886 | } | |
887 | } | |
888 | for(;j>=0;j--) | |
889 | { | |
630b122b | 890 | if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j; |
891 | if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j; | |
892 | if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j; | |
893 | if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j; | |
894 | if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) { | |
57871462 | 895 | // Stores can allocate zero |
630b122b | 896 | hsn[dops[i+j].rs1]=j; |
897 | hsn[dops[i+j].rs2]=j; | |
57871462 | 898 | } |
630b122b | 899 | if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store)) |
900 | hsn[ROREG] = j; | |
57871462 | 901 | // On some architectures stores need invc_ptr |
902 | #if defined(HOST_IMM8) | |
630b122b | 903 | if (dops[i+j].is_store) |
904 | hsn[INVCP] = j; | |
57871462 | 905 | #endif |
630b122b | 906 | if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP)) |
57871462 | 907 | { |
908 | hsn[CCREG]=j; | |
909 | b=j; | |
910 | } | |
911 | } | |
912 | if(b>=0) | |
913 | { | |
914 | if(ba[i+b]>=start && ba[i+b]<(start+slen*4)) | |
915 | { | |
916 | // Follow first branch | |
917 | int t=(ba[i+b]-start)>>2; | |
918 | j=7-b;if(t+j>=slen) j=slen-t-1; | |
919 | for(;j>=0;j--) | |
920 | { | |
630b122b | 921 | if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2; |
922 | if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2; | |
923 | //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2; | |
924 | //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2; | |
57871462 | 925 | } |
926 | } | |
927 | // TODO: preferred register based on backward branch | |
928 | } | |
929 | // Delay slot should preferably not overwrite branch conditions or cycle count | |
630b122b | 930 | if (i > 0 && dops[i-1].is_jump) { |
931 | if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1; | |
932 | if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1; | |
57871462 | 933 | hsn[CCREG]=1; |
934 | // ...or hash tables | |
935 | hsn[RHASH]=1; | |
936 | hsn[RHTBL]=1; | |
937 | } | |
938 | // Coprocessor load/store needs FTEMP, even if not declared | |
630b122b | 939 | if(dops[i].itype==C2LS) { |
57871462 | 940 | hsn[FTEMP]=0; |
941 | } | |
942 | // Load L/R also uses FTEMP as a temporary register | |
630b122b | 943 | if(dops[i].itype==LOADLR) { |
57871462 | 944 | hsn[FTEMP]=0; |
945 | } | |
b7918751 | 946 | // Also SWL/SWR/SDL/SDR |
630b122b | 947 | if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { |
57871462 | 948 | hsn[FTEMP]=0; |
949 | } | |
57871462 | 950 | // Don't remove the miniht registers |
630b122b | 951 | if(dops[i].itype==UJUMP||dops[i].itype==RJUMP) |
57871462 | 952 | { |
953 | hsn[RHASH]=0; | |
954 | hsn[RHTBL]=0; | |
955 | } | |
956 | } | |
957 | ||
958 | // We only want to allocate registers if we're going to use them again soon | |
94061aa5 | 959 | static int needed_again(int r, int i) |
57871462 | 960 | { |
961 | int j; | |
962 | int b=-1; | |
963 | int rn=10; | |
9f51b4b9 | 964 | |
630b122b | 965 | if (i > 0 && dops[i-1].is_ujump) |
57871462 | 966 | { |
967 | if(ba[i-1]<start || ba[i-1]>start+slen*4-4) | |
968 | return 0; // Don't need any registers if exiting the block | |
969 | } | |
970 | for(j=0;j<9;j++) | |
971 | { | |
972 | if(i+j>=slen) { | |
973 | j=slen-i-1; | |
974 | break; | |
975 | } | |
630b122b | 976 | if (dops[i+j].is_ujump) |
57871462 | 977 | { |
978 | // Don't go past an unconditonal jump | |
979 | j++; | |
980 | break; | |
981 | } | |
630b122b | 982 | if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d)) |
57871462 | 983 | { |
984 | break; | |
985 | } | |
986 | } | |
987 | for(;j>=1;j--) | |
988 | { | |
630b122b | 989 | if(dops[i+j].rs1==r) rn=j; |
990 | if(dops[i+j].rs2==r) rn=j; | |
57871462 | 991 | if((unneeded_reg[i+j]>>r)&1) rn=10; |
630b122b | 992 | if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP)) |
57871462 | 993 | { |
994 | b=j; | |
995 | } | |
996 | } | |
b7217e13 | 997 | if(rn<10) return 1; |
581335b0 | 998 | (void)b; |
57871462 | 999 | return 0; |
1000 | } | |
1001 | ||
1002 | // Try to match register allocations at the end of a loop with those | |
1003 | // at the beginning | |
94061aa5 | 1004 | static int loop_reg(int i, int r, int hr) |
57871462 | 1005 | { |
1006 | int j,k; | |
1007 | for(j=0;j<9;j++) | |
1008 | { | |
1009 | if(i+j>=slen) { | |
1010 | j=slen-i-1; | |
1011 | break; | |
1012 | } | |
630b122b | 1013 | if (dops[i+j].is_ujump) |
57871462 | 1014 | { |
1015 | // Don't go past an unconditonal jump | |
1016 | j++; | |
1017 | break; | |
1018 | } | |
1019 | } | |
1020 | k=0; | |
1021 | if(i>0){ | |
630b122b | 1022 | if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP) |
57871462 | 1023 | k--; |
1024 | } | |
1025 | for(;k<j;k++) | |
1026 | { | |
630b122b | 1027 | assert(r < 64); |
1028 | if((unneeded_reg[i+k]>>r)&1) return hr; | |
1029 | if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP)) | |
57871462 | 1030 | { |
1031 | if(ba[i+k]>=start && ba[i+k]<(start+i*4)) | |
1032 | { | |
1033 | int t=(ba[i+k]-start)>>2; | |
1034 | int reg=get_reg(regs[t].regmap_entry,r); | |
1035 | if(reg>=0) return reg; | |
1036 | //reg=get_reg(regs[t+1].regmap_entry,r); | |
1037 | //if(reg>=0) return reg; | |
1038 | } | |
1039 | } | |
1040 | } | |
1041 | return hr; | |
1042 | } | |
1043 | ||
1044 | ||
1045 | // Allocate every register, preserving source/target regs | |
94061aa5 | 1046 | static void alloc_all(struct regstat *cur,int i) |
57871462 | 1047 | { |
1048 | int hr; | |
9f51b4b9 | 1049 | |
57871462 | 1050 | for(hr=0;hr<HOST_REGS;hr++) { |
1051 | if(hr!=EXCLUDE_REG) { | |
91af94f0 | 1052 | if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&& |
1053 | (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2)) | |
57871462 | 1054 | { |
1055 | cur->regmap[hr]=-1; | |
1056 | cur->dirty&=~(1<<hr); | |
1057 | } | |
1058 | // Don't need zeros | |
91af94f0 | 1059 | if(cur->regmap[hr]==0) |
57871462 | 1060 | { |
1061 | cur->regmap[hr]=-1; | |
1062 | cur->dirty&=~(1<<hr); | |
1063 | } | |
1064 | } | |
1065 | } | |
1066 | } | |
1067 | ||
630b122b | 1068 | #ifndef NDEBUG |
1069 | static int host_tempreg_in_use; | |
1070 | ||
1071 | static void host_tempreg_acquire(void) | |
1072 | { | |
1073 | assert(!host_tempreg_in_use); | |
1074 | host_tempreg_in_use = 1; | |
1075 | } | |
1076 | ||
1077 | static void host_tempreg_release(void) | |
1078 | { | |
1079 | host_tempreg_in_use = 0; | |
1080 | } | |
1081 | #else | |
1082 | static void host_tempreg_acquire(void) {} | |
1083 | static void host_tempreg_release(void) {} | |
1084 | #endif | |
1085 | ||
1086 | #ifdef ASSEM_PRINT | |
1087 | extern void gen_interupt(); | |
1088 | extern void do_insn_cmp(); | |
1089 | #define FUNCNAME(f) { f, " " #f } | |
1090 | static const struct { | |
1091 | void *addr; | |
1092 | const char *name; | |
1093 | } function_names[] = { | |
1094 | FUNCNAME(cc_interrupt), | |
1095 | FUNCNAME(gen_interupt), | |
048fcced | 1096 | FUNCNAME(ndrc_get_addr_ht), |
630b122b | 1097 | FUNCNAME(jump_handler_read8), |
1098 | FUNCNAME(jump_handler_read16), | |
1099 | FUNCNAME(jump_handler_read32), | |
1100 | FUNCNAME(jump_handler_write8), | |
1101 | FUNCNAME(jump_handler_write16), | |
1102 | FUNCNAME(jump_handler_write32), | |
048fcced | 1103 | FUNCNAME(ndrc_invalidate_addr), |
630b122b | 1104 | FUNCNAME(jump_to_new_pc), |
467357cc | 1105 | FUNCNAME(jump_break), |
1106 | FUNCNAME(jump_break_ds), | |
1107 | FUNCNAME(jump_syscall), | |
1108 | FUNCNAME(jump_syscall_ds), | |
630b122b | 1109 | FUNCNAME(call_gteStall), |
1110 | FUNCNAME(new_dyna_leave), | |
1111 | FUNCNAME(pcsx_mtc0), | |
1112 | FUNCNAME(pcsx_mtc0_ds), | |
1113 | #ifdef DRC_DBG | |
1114 | FUNCNAME(do_insn_cmp), | |
1115 | #endif | |
630b122b | 1116 | }; |
1117 | ||
1118 | static const char *func_name(const void *a) | |
1119 | { | |
1120 | int i; | |
1121 | for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++) | |
1122 | if (function_names[i].addr == a) | |
1123 | return function_names[i].name; | |
1124 | return ""; | |
1125 | } | |
1126 | #else | |
1127 | #define func_name(x) "" | |
1128 | #endif | |
1129 | ||
57871462 | 1130 | #ifdef __i386__ |
630b122b | 1131 | #include "assem_x86.c" |
57871462 | 1132 | #endif |
1133 | #ifdef __x86_64__ | |
630b122b | 1134 | #include "assem_x64.c" |
57871462 | 1135 | #endif |
1136 | #ifdef __arm__ | |
630b122b | 1137 | #include "assem_arm.c" |
1138 | #endif | |
1139 | #ifdef __aarch64__ | |
1140 | #include "assem_arm64.c" | |
57871462 | 1141 | #endif |
1142 | ||
630b122b | 1143 | static void *get_trampoline(const void *f) |
1144 | { | |
1145 | size_t i; | |
1146 | ||
1147 | for (i = 0; i < ARRAY_SIZE(ndrc->tramp.f); i++) { | |
1148 | if (ndrc->tramp.f[i] == f || ndrc->tramp.f[i] == NULL) | |
1149 | break; | |
1150 | } | |
1151 | if (i == ARRAY_SIZE(ndrc->tramp.f)) { | |
1152 | SysPrintf("trampoline table is full, last func %p\n", f); | |
1153 | abort(); | |
1154 | } | |
1155 | if (ndrc->tramp.f[i] == NULL) { | |
1156 | start_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]); | |
1157 | ndrc->tramp.f[i] = f; | |
1158 | end_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]); | |
1159 | } | |
1160 | return &ndrc->tramp.ops[i]; | |
1161 | } | |
1162 | ||
1163 | static void emit_far_jump(const void *f) | |
1164 | { | |
1165 | if (can_jump_or_call(f)) { | |
1166 | emit_jmp(f); | |
1167 | return; | |
1168 | } | |
1169 | ||
1170 | f = get_trampoline(f); | |
1171 | emit_jmp(f); | |
1172 | } | |
1173 | ||
1174 | static void emit_far_call(const void *f) | |
1175 | { | |
1176 | if (can_jump_or_call(f)) { | |
1177 | emit_call(f); | |
1178 | return; | |
1179 | } | |
1180 | ||
1181 | f = get_trampoline(f); | |
1182 | emit_call(f); | |
1183 | } | |
1184 | ||
57871462 | 1185 | // Check if an address is already compiled |
1186 | // but don't return addresses which are about to expire from the cache | |
94061aa5 | 1187 | static void *check_addr(u_int vaddr) |
57871462 | 1188 | { |
630b122b | 1189 | struct ht_entry *ht_bin = hash_table_get(vaddr); |
1190 | size_t i; | |
1191 | for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) { | |
1192 | if (ht_bin->vaddr[i] == vaddr) | |
432435ea | 1193 | if (doesnt_expire_soon(ht_bin->tcaddr[i])) |
048fcced | 1194 | return ht_bin->tcaddr[i]; |
57871462 | 1195 | } |
048fcced | 1196 | |
1197 | // refactor to get_addr_nocompile? | |
1198 | u_int start_page = get_page_prev(vaddr); | |
1199 | u_int page, end_page = get_page(vaddr); | |
1200 | ||
1201 | stat_inc(stat_jump_in_lookups); | |
1202 | for (page = start_page; page <= end_page; page++) { | |
1203 | const struct block_info *block; | |
1204 | for (block = blocks[page]; block != NULL; block = block->next) { | |
1205 | if (vaddr < block->start) | |
1206 | break; | |
1207 | if (block->is_dirty || vaddr >= block->start + block->len) | |
1208 | continue; | |
1209 | if (!doesnt_expire_soon(ndrc->translation_cache + block->tc_offs)) | |
1210 | continue; | |
1211 | for (i = 0; i < block->jump_in_cnt; i++) | |
1212 | if (block->jump_in[i].vaddr == vaddr) | |
1213 | break; | |
1214 | if (i == block->jump_in_cnt) | |
1215 | continue; | |
1216 | ||
1217 | // Update existing entry with current address | |
1218 | void *addr = block->jump_in[i].addr; | |
1219 | if (ht_bin->vaddr[0] == vaddr) { | |
1220 | ht_bin->tcaddr[0] = addr; | |
1221 | return addr; | |
1222 | } | |
1223 | if (ht_bin->vaddr[1] == vaddr) { | |
1224 | ht_bin->tcaddr[1] = addr; | |
1225 | return addr; | |
1226 | } | |
1227 | // Insert into hash table with low priority. | |
1228 | // Don't evict existing entries, as they are probably | |
1229 | // addresses that are being accessed frequently. | |
1230 | if (ht_bin->vaddr[0] == -1) { | |
1231 | ht_bin->vaddr[0] = vaddr; | |
1232 | ht_bin->tcaddr[0] = addr; | |
57871462 | 1233 | } |
048fcced | 1234 | else if (ht_bin->vaddr[1] == -1) { |
1235 | ht_bin->vaddr[1] = vaddr; | |
1236 | ht_bin->tcaddr[1] = addr; | |
1237 | } | |
1238 | return addr; | |
57871462 | 1239 | } |
57871462 | 1240 | } |
048fcced | 1241 | return NULL; |
57871462 | 1242 | } |
1243 | ||
048fcced | 1244 | static void blocks_clear(struct block_info **head) |
1245 | { | |
1246 | struct block_info *cur, *next; | |
1247 | ||
1248 | if ((cur = *head)) { | |
1249 | *head = NULL; | |
1250 | while (cur) { | |
1251 | next = cur->next; | |
1252 | free(cur); | |
1253 | cur = next; | |
1254 | } | |
1255 | } | |
1256 | } | |
1257 | ||
432435ea | 1258 | static int blocks_remove_matching_addrs(struct block_info **head, |
1259 | u_int base_offs, int shift) | |
048fcced | 1260 | { |
1261 | struct block_info *next; | |
432435ea | 1262 | int hit = 0; |
048fcced | 1263 | while (*head) { |
432435ea | 1264 | if ((((*head)->tc_offs ^ base_offs) >> shift) == 0) { |
1265 | inv_debug("EXP: rm block %08x (tc_offs %zx)\n", (*head)->start, (*head)->tc_offs); | |
048fcced | 1266 | invalidate_block(*head); |
1267 | next = (*head)->next; | |
1268 | free(*head); | |
1269 | *head = next; | |
1270 | stat_dec(stat_blocks); | |
432435ea | 1271 | hit = 1; |
048fcced | 1272 | } |
1273 | else | |
1274 | { | |
1275 | head = &((*head)->next); | |
1276 | } | |
1277 | } | |
432435ea | 1278 | return hit; |
048fcced | 1279 | } |
57871462 | 1280 | |
1281 | // This is called when we write to a compiled block (see do_invstub) | |
366d1d2b | 1282 | static void unlink_jumps_vaddr_range(u_int start, u_int end) |
57871462 | 1283 | { |
048fcced | 1284 | u_int page, start_page = get_page(start), end_page = get_page(end - 1); |
366d1d2b | 1285 | int i; |
048fcced | 1286 | |
1287 | for (page = start_page; page <= end_page; page++) { | |
366d1d2b | 1288 | struct jump_info *ji = jumps[page]; |
1289 | if (ji == NULL) | |
1290 | continue; | |
1291 | for (i = 0; i < ji->count; ) { | |
1292 | if (ji->e[i].target_vaddr < start || ji->e[i].target_vaddr >= end) { | |
1293 | i++; | |
048fcced | 1294 | continue; |
1295 | } | |
366d1d2b | 1296 | |
1297 | inv_debug("INV: rm link to %08x (tc_offs %zx)\n", ji->e[i].target_vaddr, | |
1298 | (u_char *)ji->e[i].stub - ndrc->translation_cache); | |
1299 | void *host_addr = find_extjump_insn(ji->e[i].stub); | |
048fcced | 1300 | mark_clear_cache(host_addr); |
366d1d2b | 1301 | set_jump_target(host_addr, ji->e[i].stub); // point back to dyna_linker stub |
048fcced | 1302 | |
048fcced | 1303 | stat_dec(stat_links); |
366d1d2b | 1304 | ji->count--; |
1305 | if (i < ji->count) { | |
1306 | ji->e[i] = ji->e[ji->count]; | |
1307 | continue; | |
1308 | } | |
1309 | i++; | |
1310 | } | |
1311 | } | |
1312 | } | |
1313 | ||
1314 | static void unlink_jumps_tc_range(struct jump_info *ji, u_int base_offs, int shift) | |
1315 | { | |
1316 | int i; | |
1317 | if (ji == NULL) | |
1318 | return; | |
1319 | for (i = 0; i < ji->count; ) { | |
1320 | u_int tc_offs = (u_char *)ji->e[i].stub - ndrc->translation_cache; | |
1321 | if (((tc_offs ^ base_offs) >> shift) != 0) { | |
1322 | i++; | |
1323 | continue; | |
1324 | } | |
1325 | ||
1326 | inv_debug("EXP: rm link to %08x (tc_offs %zx)\n", ji->e[i].target_vaddr, tc_offs); | |
1327 | stat_dec(stat_links); | |
1328 | ji->count--; | |
1329 | if (i < ji->count) { | |
1330 | ji->e[i] = ji->e[ji->count]; | |
1331 | continue; | |
048fcced | 1332 | } |
366d1d2b | 1333 | i++; |
57871462 | 1334 | } |
048fcced | 1335 | } |
9f51b4b9 | 1336 | |
048fcced | 1337 | static void invalidate_block(struct block_info *block) |
1338 | { | |
1339 | u_int i; | |
f76eeef9 | 1340 | |
048fcced | 1341 | block->is_dirty = 1; |
366d1d2b | 1342 | unlink_jumps_vaddr_range(block->start, block->start + block->len); |
048fcced | 1343 | for (i = 0; i < block->jump_in_cnt; i++) |
1344 | hash_table_remove(block->jump_in[i].vaddr); | |
57871462 | 1345 | } |
9be4ba64 | 1346 | |
048fcced | 1347 | static int invalidate_range(u_int start, u_int end, |
1348 | u32 *inv_start_ret, u32 *inv_end_ret) | |
9be4ba64 | 1349 | { |
048fcced | 1350 | u_int start_page = get_page_prev(start); |
1351 | u_int end_page = get_page(end - 1); | |
1352 | u_int start_m = pmmask(start); | |
1353 | u_int end_m = pmmask(end); | |
1354 | u_int inv_start, inv_end; | |
1355 | u_int blk_start_m, blk_end_m; | |
1356 | u_int page; | |
1357 | int hit = 0; | |
1358 | ||
1359 | // additional area without code (to supplement invalid_code[]), [start, end) | |
1360 | // avoids excessive ndrc_invalidate_addr() calls | |
1361 | inv_start = start_m & ~0xfff; | |
1362 | inv_end = end_m | 0xfff; | |
1363 | ||
1364 | for (page = start_page; page <= end_page; page++) { | |
1365 | struct block_info *block; | |
1366 | for (block = blocks[page]; block != NULL; block = block->next) { | |
1367 | if (block->is_dirty) | |
1368 | continue; | |
1369 | blk_end_m = pmmask(block->start + block->len); | |
1370 | if (blk_end_m <= start_m) { | |
1371 | inv_start = max(inv_start, blk_end_m); | |
1372 | continue; | |
1373 | } | |
1374 | blk_start_m = pmmask(block->start); | |
1375 | if (end_m <= blk_start_m) { | |
1376 | inv_end = min(inv_end, blk_start_m - 1); | |
1377 | continue; | |
9be4ba64 | 1378 | } |
048fcced | 1379 | if (!block->source) // "hack" block - leave it alone |
1380 | continue; | |
1381 | ||
1382 | hit++; | |
1383 | invalidate_block(block); | |
1384 | stat_inc(stat_inv_hits); | |
9be4ba64 | 1385 | } |
9be4ba64 | 1386 | } |
048fcced | 1387 | |
1388 | if (hit) { | |
1389 | do_clear_cache(); | |
1390 | #ifdef USE_MINI_HT | |
1391 | memset(mini_ht, -1, sizeof(mini_ht)); | |
1392 | #endif | |
1393 | } | |
1394 | if (inv_start <= (start_m & ~0xfff) && inv_end >= (start_m | 0xfff)) | |
1395 | // the whole page is empty now | |
1396 | mark_invalid_code(start, 1, 1); | |
1397 | ||
1398 | if (inv_start_ret) *inv_start_ret = inv_start | (start & 0xe0000000); | |
1399 | if (inv_end_ret) *inv_end_ret = inv_end | (end & 0xe0000000); | |
1400 | return hit; | |
9be4ba64 | 1401 | } |
1402 | ||
048fcced | 1403 | void new_dynarec_invalidate_range(unsigned int start, unsigned int end) |
1404 | { | |
1405 | invalidate_range(start, end, NULL, NULL); | |
1406 | } | |
1407 | ||
1408 | void ndrc_invalidate_addr(u_int addr) | |
57871462 | 1409 | { |
9be4ba64 | 1410 | // this check is done by the caller |
1411 | //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; } | |
048fcced | 1412 | int ret = invalidate_range(addr, addr + 4, &inv_code_start, &inv_code_end); |
1413 | if (ret) | |
1414 | inv_debug("INV ADDR: %08x hit %d blocks\n", addr, ret); | |
1415 | else | |
1416 | inv_debug("INV ADDR: %08x miss, inv %08x-%08x\n", addr, inv_code_start, inv_code_end); | |
55cadc36 | 1417 | stat_inc(stat_inv_addr_calls); |
57871462 | 1418 | } |
9be4ba64 | 1419 | |
dd3a91a1 | 1420 | // This is called when loading a save state. |
1421 | // Anything could have changed, so invalidate everything. | |
048fcced | 1422 | void new_dynarec_invalidate_all_pages(void) |
57871462 | 1423 | { |
048fcced | 1424 | struct block_info *block; |
581335b0 | 1425 | u_int page; |
048fcced | 1426 | for (page = 0; page < ARRAY_SIZE(blocks); page++) { |
1427 | for (block = blocks[page]; block != NULL; block = block->next) { | |
1428 | if (block->is_dirty) | |
1429 | continue; | |
1430 | if (!block->source) // hack block? | |
1431 | continue; | |
1432 | invalidate_block(block); | |
1433 | } | |
1434 | } | |
1435 | ||
630b122b | 1436 | #ifdef USE_MINI_HT |
432435ea | 1437 | memset(mini_ht, -1, sizeof(mini_ht)); |
630b122b | 1438 | #endif |
1439 | do_clear_cache(); | |
1440 | } | |
1441 | ||
1442 | static void do_invstub(int n) | |
1443 | { | |
1444 | literal_pool(20); | |
b9e27215 | 1445 | u_int reglist = stubs[n].a; |
630b122b | 1446 | set_jump_target(stubs[n].addr, out); |
1447 | save_regs(reglist); | |
b9e27215 | 1448 | if (stubs[n].b != 0) |
1449 | emit_mov(stubs[n].b, 0); | |
1450 | emit_readword(&inv_code_start, 1); | |
1451 | emit_readword(&inv_code_end, 2); | |
1452 | emit_cmp(0, 1); | |
1453 | emit_cmpcs(2, 0); | |
1454 | void *jaddr = out; | |
1455 | emit_jc(0); | |
048fcced | 1456 | emit_far_call(ndrc_invalidate_addr); |
b9e27215 | 1457 | set_jump_target(jaddr, out); |
630b122b | 1458 | restore_regs(reglist); |
1459 | emit_jmp(stubs[n].retaddr); // return address | |
57871462 | 1460 | } |
1461 | ||
1462 | // Add an entry to jump_out after making a link | |
048fcced | 1463 | // src should point to code by emit_extjump() |
366d1d2b | 1464 | void ndrc_add_jump_out(u_int vaddr, void *src) |
57871462 | 1465 | { |
366d1d2b | 1466 | inv_debug("ndrc_add_jump_out: %p -> %x\n", src, vaddr); |
1467 | u_int page = get_page(vaddr); | |
1468 | struct jump_info *ji; | |
1469 | ||
048fcced | 1470 | stat_inc(stat_links); |
366d1d2b | 1471 | check_extjump2(src); |
1472 | ji = jumps[page]; | |
1473 | if (ji == NULL) { | |
1474 | ji = malloc(sizeof(*ji) + sizeof(ji->e[0]) * 16); | |
1475 | ji->alloc = 16; | |
1476 | ji->count = 0; | |
1477 | } | |
1478 | else if (ji->count >= ji->alloc) { | |
1479 | ji->alloc += 16; | |
1480 | ji = realloc(ji, sizeof(*ji) + sizeof(ji->e[0]) * ji->alloc); | |
1481 | } | |
1482 | jumps[page] = ji; | |
1483 | ji->e[ji->count].target_vaddr = vaddr; | |
1484 | ji->e[ji->count].stub = src; | |
1485 | ji->count++; | |
57871462 | 1486 | } |
1487 | ||
630b122b | 1488 | /* Register allocation */ |
1489 | ||
1490 | // Note: registers are allocated clean (unmodified state) | |
1491 | // if you intend to modify the register, you must call dirty_reg(). | |
1492 | static void alloc_reg(struct regstat *cur,int i,signed char reg) | |
57871462 | 1493 | { |
630b122b | 1494 | int r,hr; |
1495 | int preferred_reg = PREFERRED_REG_FIRST | |
1496 | + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1); | |
1497 | if (reg == CCREG) preferred_reg = HOST_CCREG; | |
1498 | if (reg == PTEMP || reg == FTEMP) preferred_reg = 12; | |
1499 | assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS); | |
e912c27d | 1500 | assert(reg >= 0); |
630b122b | 1501 | |
1502 | // Don't allocate unused registers | |
1503 | if((cur->u>>reg)&1) return; | |
1504 | ||
1505 | // see if it's already allocated | |
e912c27d | 1506 | if (get_reg(cur->regmap, reg) >= 0) |
1507 | return; | |
630b122b | 1508 | |
1509 | // Keep the same mapping if the register was already allocated in a loop | |
1510 | preferred_reg = loop_reg(i,reg,preferred_reg); | |
1511 | ||
1512 | // Try to allocate the preferred register | |
1513 | if(cur->regmap[preferred_reg]==-1) { | |
1514 | cur->regmap[preferred_reg]=reg; | |
1515 | cur->dirty&=~(1<<preferred_reg); | |
1516 | cur->isconst&=~(1<<preferred_reg); | |
1517 | return; | |
1518 | } | |
1519 | r=cur->regmap[preferred_reg]; | |
1520 | assert(r < 64); | |
1521 | if((cur->u>>r)&1) { | |
1522 | cur->regmap[preferred_reg]=reg; | |
1523 | cur->dirty&=~(1<<preferred_reg); | |
1524 | cur->isconst&=~(1<<preferred_reg); | |
1525 | return; | |
1526 | } | |
1527 | ||
1528 | // Clear any unneeded registers | |
1529 | // We try to keep the mapping consistent, if possible, because it | |
1530 | // makes branches easier (especially loops). So we try to allocate | |
1531 | // first (see above) before removing old mappings. If this is not | |
1532 | // possible then go ahead and clear out the registers that are no | |
1533 | // longer needed. | |
1534 | for(hr=0;hr<HOST_REGS;hr++) | |
0bfdd1aa | 1535 | { |
630b122b | 1536 | r=cur->regmap[hr]; |
1537 | if(r>=0) { | |
1538 | assert(r < 64); | |
1539 | if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;} | |
1540 | } | |
57871462 | 1541 | } |
57871462 | 1542 | |
630b122b | 1543 | // Try to allocate any available register, but prefer |
1544 | // registers that have not been used recently. | |
1545 | if (i > 0) { | |
1546 | for (hr = PREFERRED_REG_FIRST; ; ) { | |
1547 | if (cur->regmap[hr] < 0) { | |
1548 | int oldreg = regs[i-1].regmap[hr]; | |
1549 | if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2 | |
1550 | && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2)) | |
1551 | { | |
1552 | cur->regmap[hr]=reg; | |
1553 | cur->dirty&=~(1<<hr); | |
1554 | cur->isconst&=~(1<<hr); | |
1555 | return; | |
1556 | } | |
dc49e339 | 1557 | } |
630b122b | 1558 | hr++; |
1559 | if (hr == EXCLUDE_REG) | |
1560 | hr++; | |
1561 | if (hr == HOST_REGS) | |
1562 | hr = 0; | |
1563 | if (hr == PREFERRED_REG_FIRST) | |
1564 | break; | |
57871462 | 1565 | } |
1566 | } | |
dc49e339 | 1567 | |
630b122b | 1568 | // Try to allocate any available register |
1569 | for (hr = PREFERRED_REG_FIRST; ; ) { | |
1570 | if (cur->regmap[hr] < 0) { | |
1571 | cur->regmap[hr]=reg; | |
1572 | cur->dirty&=~(1<<hr); | |
1573 | cur->isconst&=~(1<<hr); | |
1574 | return; | |
57871462 | 1575 | } |
630b122b | 1576 | hr++; |
1577 | if (hr == EXCLUDE_REG) | |
1578 | hr++; | |
1579 | if (hr == HOST_REGS) | |
1580 | hr = 0; | |
1581 | if (hr == PREFERRED_REG_FIRST) | |
1582 | break; | |
57871462 | 1583 | } |
630b122b | 1584 | |
1585 | // Ok, now we have to evict someone | |
1586 | // Pick a register we hopefully won't need soon | |
1587 | u_char hsn[MAXREG+1]; | |
1588 | memset(hsn,10,sizeof(hsn)); | |
1589 | int j; | |
1590 | lsn(hsn,i,&preferred_reg); | |
1591 | //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]); | |
1592 | //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]); | |
1593 | if(i>0) { | |
1594 | // Don't evict the cycle count at entry points, otherwise the entry | |
1595 | // stub will have to write it. | |
1596 | if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2; | |
1597 | if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2; | |
1598 | for(j=10;j>=3;j--) | |
1599 | { | |
1600 | // Alloc preferred register if available | |
1601 | if(hsn[r=cur->regmap[preferred_reg]&63]==j) { | |
1602 | for(hr=0;hr<HOST_REGS;hr++) { | |
1603 | // Evict both parts of a 64-bit register | |
91af94f0 | 1604 | if(cur->regmap[hr]==r) { |
630b122b | 1605 | cur->regmap[hr]=-1; |
1606 | cur->dirty&=~(1<<hr); | |
1607 | cur->isconst&=~(1<<hr); | |
1608 | } | |
1609 | } | |
1610 | cur->regmap[preferred_reg]=reg; | |
1611 | return; | |
1612 | } | |
1613 | for(r=1;r<=MAXREG;r++) | |
1614 | { | |
1615 | if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) { | |
1616 | for(hr=0;hr<HOST_REGS;hr++) { | |
1617 | if(hr!=HOST_CCREG||j<hsn[CCREG]) { | |
1618 | if(cur->regmap[hr]==r) { | |
1619 | cur->regmap[hr]=reg; | |
1620 | cur->dirty&=~(1<<hr); | |
1621 | cur->isconst&=~(1<<hr); | |
1622 | return; | |
1623 | } | |
1624 | } | |
1625 | } | |
1626 | } | |
1627 | } | |
57871462 | 1628 | } |
1629 | } | |
630b122b | 1630 | for(j=10;j>=0;j--) |
57871462 | 1631 | { |
630b122b | 1632 | for(r=1;r<=MAXREG;r++) |
1633 | { | |
1634 | if(hsn[r]==j) { | |
1635 | for(hr=0;hr<HOST_REGS;hr++) { | |
1636 | if(cur->regmap[hr]==r) { | |
1637 | cur->regmap[hr]=reg; | |
1638 | cur->dirty&=~(1<<hr); | |
1639 | cur->isconst&=~(1<<hr); | |
1640 | return; | |
1641 | } | |
1642 | } | |
57871462 | 1643 | } |
57871462 | 1644 | } |
1645 | } | |
630b122b | 1646 | SysPrintf("This shouldn't happen (alloc_reg)");abort(); |
1647 | } | |
1648 | ||
1649 | // Allocate a temporary register. This is done without regard to | |
1650 | // dirty status or whether the register we request is on the unneeded list | |
1651 | // Note: This will only allocate one register, even if called multiple times | |
1652 | static void alloc_reg_temp(struct regstat *cur,int i,signed char reg) | |
1653 | { | |
1654 | int r,hr; | |
1655 | int preferred_reg = -1; | |
1656 | ||
1657 | // see if it's already allocated | |
1658 | for(hr=0;hr<HOST_REGS;hr++) | |
1659 | { | |
1660 | if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return; | |
1661 | } | |
1662 | ||
1663 | // Try to allocate any available register | |
1664 | for(hr=HOST_REGS-1;hr>=0;hr--) { | |
1665 | if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) { | |
1666 | cur->regmap[hr]=reg; | |
1667 | cur->dirty&=~(1<<hr); | |
1668 | cur->isconst&=~(1<<hr); | |
1669 | return; | |
1670 | } | |
1671 | } | |
1672 | ||
1673 | // Find an unneeded register | |
1674 | for(hr=HOST_REGS-1;hr>=0;hr--) | |
1675 | { | |
1676 | r=cur->regmap[hr]; | |
1677 | if(r>=0) { | |
1678 | assert(r < 64); | |
1679 | if((cur->u>>r)&1) { | |
1680 | if(i==0||((unneeded_reg[i-1]>>r)&1)) { | |
1681 | cur->regmap[hr]=reg; | |
1682 | cur->dirty&=~(1<<hr); | |
1683 | cur->isconst&=~(1<<hr); | |
1684 | return; | |
1685 | } | |
1686 | } | |
1687 | } | |
1688 | } | |
1689 | ||
1690 | // Ok, now we have to evict someone | |
1691 | // Pick a register we hopefully won't need soon | |
1692 | // TODO: we might want to follow unconditional jumps here | |
1693 | // TODO: get rid of dupe code and make this into a function | |
1694 | u_char hsn[MAXREG+1]; | |
1695 | memset(hsn,10,sizeof(hsn)); | |
1696 | int j; | |
1697 | lsn(hsn,i,&preferred_reg); | |
1698 | //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]); | |
1699 | if(i>0) { | |
1700 | // Don't evict the cycle count at entry points, otherwise the entry | |
1701 | // stub will have to write it. | |
1702 | if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2; | |
1703 | if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2; | |
1704 | for(j=10;j>=3;j--) | |
1705 | { | |
1706 | for(r=1;r<=MAXREG;r++) | |
1707 | { | |
1708 | if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) { | |
1709 | for(hr=0;hr<HOST_REGS;hr++) { | |
1710 | if(hr!=HOST_CCREG||hsn[CCREG]>2) { | |
1711 | if(cur->regmap[hr]==r) { | |
1712 | cur->regmap[hr]=reg; | |
1713 | cur->dirty&=~(1<<hr); | |
1714 | cur->isconst&=~(1<<hr); | |
1715 | return; | |
1716 | } | |
1717 | } | |
1718 | } | |
1719 | } | |
1720 | } | |
1721 | } | |
1722 | } | |
1723 | for(j=10;j>=0;j--) | |
1724 | { | |
1725 | for(r=1;r<=MAXREG;r++) | |
1726 | { | |
1727 | if(hsn[r]==j) { | |
1728 | for(hr=0;hr<HOST_REGS;hr++) { | |
1729 | if(cur->regmap[hr]==r) { | |
1730 | cur->regmap[hr]=reg; | |
1731 | cur->dirty&=~(1<<hr); | |
1732 | cur->isconst&=~(1<<hr); | |
1733 | return; | |
1734 | } | |
1735 | } | |
1736 | } | |
1737 | } | |
1738 | } | |
1739 | SysPrintf("This shouldn't happen");abort(); | |
1740 | } | |
1741 | ||
1742 | static void mov_alloc(struct regstat *current,int i) | |
1743 | { | |
1744 | if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) { | |
1745 | alloc_cc(current,i); // for stalls | |
1746 | dirty_reg(current,CCREG); | |
1747 | } | |
1748 | ||
1749 | // Note: Don't need to actually alloc the source registers | |
1750 | //alloc_reg(current,i,dops[i].rs1); | |
1751 | alloc_reg(current,i,dops[i].rt1); | |
1752 | ||
1753 | clear_const(current,dops[i].rs1); | |
1754 | clear_const(current,dops[i].rt1); | |
1755 | dirty_reg(current,dops[i].rt1); | |
1756 | } | |
1757 | ||
1758 | static void shiftimm_alloc(struct regstat *current,int i) | |
1759 | { | |
1760 | if(dops[i].opcode2<=0x3) // SLL/SRL/SRA | |
1761 | { | |
1762 | if(dops[i].rt1) { | |
1763 | if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); | |
ed14d777 | 1764 | else dops[i].use_lt1=!!dops[i].rs1; |
630b122b | 1765 | alloc_reg(current,i,dops[i].rt1); |
1766 | dirty_reg(current,dops[i].rt1); | |
1767 | if(is_const(current,dops[i].rs1)) { | |
1768 | int v=get_const(current,dops[i].rs1); | |
1769 | if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]); | |
1770 | if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]); | |
1771 | if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]); | |
1772 | } | |
1773 | else clear_const(current,dops[i].rt1); | |
1774 | } | |
1775 | } | |
1776 | else | |
1777 | { | |
1778 | clear_const(current,dops[i].rs1); | |
1779 | clear_const(current,dops[i].rt1); | |
1780 | } | |
1781 | ||
1782 | if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA | |
1783 | { | |
1784 | assert(0); | |
1785 | } | |
1786 | if(dops[i].opcode2==0x3c) // DSLL32 | |
1787 | { | |
1788 | assert(0); | |
1789 | } | |
1790 | if(dops[i].opcode2==0x3e) // DSRL32 | |
1791 | { | |
1792 | assert(0); | |
1793 | } | |
1794 | if(dops[i].opcode2==0x3f) // DSRA32 | |
1795 | { | |
1796 | assert(0); | |
57871462 | 1797 | } |
1798 | } | |
1799 | ||
630b122b | 1800 | static void shift_alloc(struct regstat *current,int i) |
57871462 | 1801 | { |
630b122b | 1802 | if(dops[i].rt1) { |
1803 | if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV | |
57871462 | 1804 | { |
630b122b | 1805 | if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1); |
1806 | if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2); | |
1807 | alloc_reg(current,i,dops[i].rt1); | |
1808 | if(dops[i].rt1==dops[i].rs2) { | |
e1190b87 | 1809 | alloc_reg_temp(current,i,-1); |
1810 | minimum_free_regs[i]=1; | |
1811 | } | |
57871462 | 1812 | } else { // DSLLV/DSRLV/DSRAV |
630b122b | 1813 | assert(0); |
57871462 | 1814 | } |
630b122b | 1815 | clear_const(current,dops[i].rs1); |
1816 | clear_const(current,dops[i].rs2); | |
1817 | clear_const(current,dops[i].rt1); | |
1818 | dirty_reg(current,dops[i].rt1); | |
57871462 | 1819 | } |
1820 | } | |
1821 | ||
630b122b | 1822 | static void alu_alloc(struct regstat *current,int i) |
57871462 | 1823 | { |
630b122b | 1824 | if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU |
1825 | if(dops[i].rt1) { | |
1826 | if(dops[i].rs1&&dops[i].rs2) { | |
1827 | alloc_reg(current,i,dops[i].rs1); | |
1828 | alloc_reg(current,i,dops[i].rs2); | |
57871462 | 1829 | } |
1830 | else { | |
630b122b | 1831 | if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); |
1832 | if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2); | |
57871462 | 1833 | } |
630b122b | 1834 | alloc_reg(current,i,dops[i].rt1); |
57871462 | 1835 | } |
57871462 | 1836 | } |
630b122b | 1837 | if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU |
1838 | if(dops[i].rt1) { | |
1839 | alloc_reg(current,i,dops[i].rs1); | |
1840 | alloc_reg(current,i,dops[i].rs2); | |
1841 | alloc_reg(current,i,dops[i].rt1); | |
57871462 | 1842 | } |
57871462 | 1843 | } |
630b122b | 1844 | if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR |
1845 | if(dops[i].rt1) { | |
1846 | if(dops[i].rs1&&dops[i].rs2) { | |
1847 | alloc_reg(current,i,dops[i].rs1); | |
1848 | alloc_reg(current,i,dops[i].rs2); | |
57871462 | 1849 | } |
1850 | else | |
1851 | { | |
630b122b | 1852 | if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); |
1853 | if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2); | |
57871462 | 1854 | } |
630b122b | 1855 | alloc_reg(current,i,dops[i].rt1); |
57871462 | 1856 | } |
1857 | } | |
630b122b | 1858 | if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU |
1859 | assert(0); | |
57871462 | 1860 | } |
630b122b | 1861 | clear_const(current,dops[i].rs1); |
1862 | clear_const(current,dops[i].rs2); | |
1863 | clear_const(current,dops[i].rt1); | |
1864 | dirty_reg(current,dops[i].rt1); | |
57871462 | 1865 | } |
1866 | ||
630b122b | 1867 | static void imm16_alloc(struct regstat *current,int i) |
57871462 | 1868 | { |
630b122b | 1869 | if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); |
ed14d777 | 1870 | else dops[i].use_lt1=!!dops[i].rs1; |
630b122b | 1871 | if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1); |
1872 | if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU | |
1873 | assert(0); | |
57871462 | 1874 | } |
630b122b | 1875 | else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU |
1876 | clear_const(current,dops[i].rs1); | |
1877 | clear_const(current,dops[i].rt1); | |
57871462 | 1878 | } |
630b122b | 1879 | else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI |
1880 | if(is_const(current,dops[i].rs1)) { | |
1881 | int v=get_const(current,dops[i].rs1); | |
1882 | if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]); | |
1883 | if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]); | |
1884 | if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]); | |
57871462 | 1885 | } |
630b122b | 1886 | else clear_const(current,dops[i].rt1); |
57871462 | 1887 | } |
630b122b | 1888 | else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU |
1889 | if(is_const(current,dops[i].rs1)) { | |
1890 | int v=get_const(current,dops[i].rs1); | |
1891 | set_const(current,dops[i].rt1,v+imm[i]); | |
57871462 | 1892 | } |
630b122b | 1893 | else clear_const(current,dops[i].rt1); |
57871462 | 1894 | } |
1895 | else { | |
630b122b | 1896 | set_const(current,dops[i].rt1,imm[i]<<16); // LUI |
57871462 | 1897 | } |
630b122b | 1898 | dirty_reg(current,dops[i].rt1); |
57871462 | 1899 | } |
1900 | ||
630b122b | 1901 | static void load_alloc(struct regstat *current,int i) |
57871462 | 1902 | { |
630b122b | 1903 | clear_const(current,dops[i].rt1); |
1904 | //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt? | |
1905 | if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register | |
1906 | if (needed_again(dops[i].rs1, i)) | |
1907 | alloc_reg(current, i, dops[i].rs1); | |
1908 | if (ram_offset) | |
1909 | alloc_reg(current, i, ROREG); | |
1910 | if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) { | |
1911 | alloc_reg(current,i,dops[i].rt1); | |
1912 | assert(get_reg(current->regmap,dops[i].rt1)>=0); | |
1913 | if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD | |
57871462 | 1914 | { |
630b122b | 1915 | assert(0); |
57871462 | 1916 | } |
630b122b | 1917 | else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR |
57871462 | 1918 | { |
630b122b | 1919 | assert(0); |
57871462 | 1920 | } |
630b122b | 1921 | dirty_reg(current,dops[i].rt1); |
57871462 | 1922 | // LWL/LWR need a temporary register for the old value |
630b122b | 1923 | if(dops[i].opcode==0x22||dops[i].opcode==0x26) |
57871462 | 1924 | { |
1925 | alloc_reg(current,i,FTEMP); | |
1926 | alloc_reg_temp(current,i,-1); | |
e1190b87 | 1927 | minimum_free_regs[i]=1; |
57871462 | 1928 | } |
1929 | } | |
1930 | else | |
1931 | { | |
373d1d07 | 1932 | // Load to r0 or unneeded register (dummy load) |
57871462 | 1933 | // but we still need a register to calculate the address |
630b122b | 1934 | if(dops[i].opcode==0x22||dops[i].opcode==0x26) |
535d208a | 1935 | { |
1936 | alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary | |
1937 | } | |
57871462 | 1938 | alloc_reg_temp(current,i,-1); |
e1190b87 | 1939 | minimum_free_regs[i]=1; |
630b122b | 1940 | if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR |
535d208a | 1941 | { |
630b122b | 1942 | assert(0); |
535d208a | 1943 | } |
57871462 | 1944 | } |
1945 | } | |
1946 | ||
94061aa5 | 1947 | static void store_alloc(struct regstat *current,int i) |
57871462 | 1948 | { |
630b122b | 1949 | clear_const(current,dops[i].rs2); |
1950 | if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary | |
1951 | if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); | |
1952 | alloc_reg(current,i,dops[i].rs2); | |
1953 | if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD | |
1954 | assert(0); | |
1955 | } | |
1956 | if (ram_offset) | |
1957 | alloc_reg(current, i, ROREG); | |
57871462 | 1958 | #if defined(HOST_IMM8) |
1959 | // On CPUs without 32-bit immediates we need a pointer to invalid_code | |
630b122b | 1960 | alloc_reg(current, i, INVCP); |
57871462 | 1961 | #endif |
630b122b | 1962 | if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR |
57871462 | 1963 | alloc_reg(current,i,FTEMP); |
1964 | } | |
1965 | // We need a temporary register for address generation | |
1966 | alloc_reg_temp(current,i,-1); | |
e1190b87 | 1967 | minimum_free_regs[i]=1; |
57871462 | 1968 | } |
1969 | ||
94061aa5 | 1970 | static void c1ls_alloc(struct regstat *current,int i) |
57871462 | 1971 | { |
630b122b | 1972 | clear_const(current,dops[i].rt1); |
57871462 | 1973 | alloc_reg(current,i,CSREG); // Status |
57871462 | 1974 | } |
1975 | ||
94061aa5 | 1976 | static void c2ls_alloc(struct regstat *current,int i) |
b9b61529 | 1977 | { |
630b122b | 1978 | clear_const(current,dops[i].rt1); |
1979 | if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); | |
b9b61529 | 1980 | alloc_reg(current,i,FTEMP); |
630b122b | 1981 | if (ram_offset) |
1982 | alloc_reg(current, i, ROREG); | |
b9b61529 | 1983 | #if defined(HOST_IMM8) |
1984 | // On CPUs without 32-bit immediates we need a pointer to invalid_code | |
630b122b | 1985 | if (dops[i].opcode == 0x3a) // SWC2 |
b9b61529 | 1986 | alloc_reg(current,i,INVCP); |
1987 | #endif | |
1988 | // We need a temporary register for address generation | |
1989 | alloc_reg_temp(current,i,-1); | |
e1190b87 | 1990 | minimum_free_regs[i]=1; |
b9b61529 | 1991 | } |
1992 | ||
57871462 | 1993 | #ifndef multdiv_alloc |
94061aa5 | 1994 | static void multdiv_alloc(struct regstat *current,int i) |
57871462 | 1995 | { |
1996 | // case 0x18: MULT | |
1997 | // case 0x19: MULTU | |
1998 | // case 0x1A: DIV | |
1999 | // case 0x1B: DIVU | |
2000 | // case 0x1C: DMULT | |
2001 | // case 0x1D: DMULTU | |
2002 | // case 0x1E: DDIV | |
2003 | // case 0x1F: DDIVU | |
630b122b | 2004 | clear_const(current,dops[i].rs1); |
2005 | clear_const(current,dops[i].rs2); | |
2006 | alloc_cc(current,i); // for stalls | |
2007 | if(dops[i].rs1&&dops[i].rs2) | |
57871462 | 2008 | { |
630b122b | 2009 | if((dops[i].opcode2&4)==0) // 32-bit |
57871462 | 2010 | { |
2011 | current->u&=~(1LL<<HIREG); | |
2012 | current->u&=~(1LL<<LOREG); | |
2013 | alloc_reg(current,i,HIREG); | |
2014 | alloc_reg(current,i,LOREG); | |
630b122b | 2015 | alloc_reg(current,i,dops[i].rs1); |
2016 | alloc_reg(current,i,dops[i].rs2); | |
57871462 | 2017 | dirty_reg(current,HIREG); |
2018 | dirty_reg(current,LOREG); | |
2019 | } | |
2020 | else // 64-bit | |
2021 | { | |
630b122b | 2022 | assert(0); |
57871462 | 2023 | } |
2024 | } | |
2025 | else | |
2026 | { | |
2027 | // Multiply by zero is zero. | |
2028 | // MIPS does not have a divide by zero exception. | |
2029 | // The result is undefined, we return zero. | |
2030 | alloc_reg(current,i,HIREG); | |
2031 | alloc_reg(current,i,LOREG); | |
57871462 | 2032 | dirty_reg(current,HIREG); |
2033 | dirty_reg(current,LOREG); | |
2034 | } | |
2035 | } | |
2036 | #endif | |
2037 | ||
94061aa5 | 2038 | static void cop0_alloc(struct regstat *current,int i) |
57871462 | 2039 | { |
630b122b | 2040 | if(dops[i].opcode2==0) // MFC0 |
57871462 | 2041 | { |
630b122b | 2042 | if(dops[i].rt1) { |
2043 | clear_const(current,dops[i].rt1); | |
57871462 | 2044 | alloc_all(current,i); |
630b122b | 2045 | alloc_reg(current,i,dops[i].rt1); |
2046 | dirty_reg(current,dops[i].rt1); | |
57871462 | 2047 | } |
2048 | } | |
630b122b | 2049 | else if(dops[i].opcode2==4) // MTC0 |
57871462 | 2050 | { |
630b122b | 2051 | if(dops[i].rs1){ |
2052 | clear_const(current,dops[i].rs1); | |
2053 | alloc_reg(current,i,dops[i].rs1); | |
57871462 | 2054 | alloc_all(current,i); |
2055 | } | |
2056 | else { | |
2057 | alloc_all(current,i); // FIXME: Keep r0 | |
2058 | current->u&=~1LL; | |
2059 | alloc_reg(current,i,0); | |
2060 | } | |
2061 | } | |
2062 | else | |
2063 | { | |
2064 | // TLBR/TLBWI/TLBWR/TLBP/ERET | |
630b122b | 2065 | assert(dops[i].opcode2==0x10); |
57871462 | 2066 | alloc_all(current,i); |
2067 | } | |
e1190b87 | 2068 | minimum_free_regs[i]=HOST_REGS; |
57871462 | 2069 | } |
2070 | ||
630b122b | 2071 | static void cop2_alloc(struct regstat *current,int i) |
57871462 | 2072 | { |
630b122b | 2073 | if (dops[i].opcode2 < 3) // MFC2/CFC2 |
57871462 | 2074 | { |
630b122b | 2075 | alloc_cc(current,i); // for stalls |
2076 | dirty_reg(current,CCREG); | |
2077 | if(dops[i].rt1){ | |
2078 | clear_const(current,dops[i].rt1); | |
2079 | alloc_reg(current,i,dops[i].rt1); | |
2080 | dirty_reg(current,dops[i].rt1); | |
57871462 | 2081 | } |
57871462 | 2082 | } |
630b122b | 2083 | else if (dops[i].opcode2 > 3) // MTC2/CTC2 |
57871462 | 2084 | { |
630b122b | 2085 | if(dops[i].rs1){ |
2086 | clear_const(current,dops[i].rs1); | |
2087 | alloc_reg(current,i,dops[i].rs1); | |
57871462 | 2088 | } |
2089 | else { | |
2090 | current->u&=~1LL; | |
2091 | alloc_reg(current,i,0); | |
57871462 | 2092 | } |
2093 | } | |
57871462 | 2094 | alloc_reg_temp(current,i,-1); |
e1190b87 | 2095 | minimum_free_regs[i]=1; |
57871462 | 2096 | } |
630b122b | 2097 | |
94061aa5 | 2098 | static void c2op_alloc(struct regstat *current,int i) |
b9b61529 | 2099 | { |
630b122b | 2100 | alloc_cc(current,i); // for stalls |
2101 | dirty_reg(current,CCREG); | |
b9b61529 | 2102 | alloc_reg_temp(current,i,-1); |
2103 | } | |
57871462 | 2104 | |
94061aa5 | 2105 | static void syscall_alloc(struct regstat *current,int i) |
57871462 | 2106 | { |
2107 | alloc_cc(current,i); | |
2108 | dirty_reg(current,CCREG); | |
2109 | alloc_all(current,i); | |
e1190b87 | 2110 | minimum_free_regs[i]=HOST_REGS; |
57871462 | 2111 | current->isconst=0; |
2112 | } | |
2113 | ||
94061aa5 | 2114 | static void delayslot_alloc(struct regstat *current,int i) |
57871462 | 2115 | { |
630b122b | 2116 | switch(dops[i].itype) { |
57871462 | 2117 | case UJUMP: |
2118 | case CJUMP: | |
2119 | case SJUMP: | |
2120 | case RJUMP: | |
57871462 | 2121 | case SYSCALL: |
7139f3c8 | 2122 | case HLECALL: |
57871462 | 2123 | case IMM16: |
2124 | imm16_alloc(current,i); | |
2125 | break; | |
2126 | case LOAD: | |
2127 | case LOADLR: | |
2128 | load_alloc(current,i); | |
2129 | break; | |
2130 | case STORE: | |
2131 | case STORELR: | |
2132 | store_alloc(current,i); | |
2133 | break; | |
2134 | case ALU: | |
2135 | alu_alloc(current,i); | |
2136 | break; | |
2137 | case SHIFT: | |
2138 | shift_alloc(current,i); | |
2139 | break; | |
2140 | case MULTDIV: | |
2141 | multdiv_alloc(current,i); | |
2142 | break; | |
2143 | case SHIFTIMM: | |
2144 | shiftimm_alloc(current,i); | |
2145 | break; | |
2146 | case MOV: | |
2147 | mov_alloc(current,i); | |
2148 | break; | |
2149 | case COP0: | |
2150 | cop0_alloc(current,i); | |
2151 | break; | |
2152 | case COP1: | |
630b122b | 2153 | break; |
b9b61529 | 2154 | case COP2: |
630b122b | 2155 | cop2_alloc(current,i); |
57871462 | 2156 | break; |
2157 | case C1LS: | |
2158 | c1ls_alloc(current,i); | |
2159 | break; | |
b9b61529 | 2160 | case C2LS: |
2161 | c2ls_alloc(current,i); | |
2162 | break; | |
b9b61529 | 2163 | case C2OP: |
2164 | c2op_alloc(current,i); | |
2165 | break; | |
57871462 | 2166 | } |
2167 | } | |
2168 | ||
630b122b | 2169 | static void add_stub(enum stub_type type, void *addr, void *retaddr, |
2170 | u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e) | |
57871462 | 2171 | { |
630b122b | 2172 | assert(stubcount < ARRAY_SIZE(stubs)); |
2173 | stubs[stubcount].type = type; | |
2174 | stubs[stubcount].addr = addr; | |
2175 | stubs[stubcount].retaddr = retaddr; | |
2176 | stubs[stubcount].a = a; | |
2177 | stubs[stubcount].b = b; | |
2178 | stubs[stubcount].c = c; | |
2179 | stubs[stubcount].d = d; | |
2180 | stubs[stubcount].e = e; | |
57871462 | 2181 | stubcount++; |
2182 | } | |
2183 | ||
630b122b | 2184 | static void add_stub_r(enum stub_type type, void *addr, void *retaddr, |
2185 | int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist) | |
2186 | { | |
2187 | add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist); | |
2188 | } | |
2189 | ||
57871462 | 2190 | // Write out a single register |
630b122b | 2191 | static void wb_register(signed char r, const signed char regmap[], uint64_t dirty) |
57871462 | 2192 | { |
2193 | int hr; | |
2194 | for(hr=0;hr<HOST_REGS;hr++) { | |
2195 | if(hr!=EXCLUDE_REG) { | |
91af94f0 | 2196 | if(regmap[hr]==r) { |
57871462 | 2197 | if((dirty>>hr)&1) { |
630b122b | 2198 | assert(regmap[hr]<64); |
2199 | emit_storereg(r,hr); | |
57871462 | 2200 | } |
2201 | } | |
2202 | } | |
2203 | } | |
2204 | } | |
2205 | ||
630b122b | 2206 | static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u) |
57871462 | 2207 | { |
630b122b | 2208 | //if(dirty_pre==dirty) return; |
e912c27d | 2209 | int hr, r; |
2210 | for (hr = 0; hr < HOST_REGS; hr++) { | |
2211 | r = pre[hr]; | |
2212 | if (r < 1 || r > 33 || ((u >> r) & 1)) | |
2213 | continue; | |
2214 | if (((dirty_pre & ~dirty) >> hr) & 1) | |
2215 | emit_storereg(r, hr); | |
57871462 | 2216 | } |
57871462 | 2217 | } |
2218 | ||
630b122b | 2219 | // trashes r2 |
2220 | static void pass_args(int a0, int a1) | |
57871462 | 2221 | { |
630b122b | 2222 | if(a0==1&&a1==0) { |
2223 | // must swap | |
2224 | emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0); | |
2225 | } | |
2226 | else if(a0!=0&&a1==0) { | |
2227 | emit_mov(a1,1); | |
2228 | if (a0>=0) emit_mov(a0,0); | |
2229 | } | |
2230 | else { | |
2231 | if(a0>=0&&a0!=0) emit_mov(a0,0); | |
2232 | if(a1>=0&&a1!=1) emit_mov(a1,1); | |
57871462 | 2233 | } |
57871462 | 2234 | } |
2235 | ||
630b122b | 2236 | static void alu_assemble(int i, const struct regstat *i_regs) |
57871462 | 2237 | { |
630b122b | 2238 | if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU |
2239 | if(dops[i].rt1) { | |
57871462 | 2240 | signed char s1,s2,t; |
630b122b | 2241 | t=get_reg(i_regs->regmap,dops[i].rt1); |
57871462 | 2242 | if(t>=0) { |
630b122b | 2243 | s1=get_reg(i_regs->regmap,dops[i].rs1); |
2244 | s2=get_reg(i_regs->regmap,dops[i].rs2); | |
2245 | if(dops[i].rs1&&dops[i].rs2) { | |
57871462 | 2246 | assert(s1>=0); |
2247 | assert(s2>=0); | |
630b122b | 2248 | if(dops[i].opcode2&2) emit_sub(s1,s2,t); |
57871462 | 2249 | else emit_add(s1,s2,t); |
2250 | } | |
630b122b | 2251 | else if(dops[i].rs1) { |
57871462 | 2252 | if(s1>=0) emit_mov(s1,t); |
630b122b | 2253 | else emit_loadreg(dops[i].rs1,t); |
57871462 | 2254 | } |
630b122b | 2255 | else if(dops[i].rs2) { |
57871462 | 2256 | if(s2>=0) { |
630b122b | 2257 | if(dops[i].opcode2&2) emit_neg(s2,t); |
57871462 | 2258 | else emit_mov(s2,t); |
2259 | } | |
2260 | else { | |
630b122b | 2261 | emit_loadreg(dops[i].rs2,t); |
2262 | if(dops[i].opcode2&2) emit_neg(t,t); | |
57871462 | 2263 | } |
2264 | } | |
2265 | else emit_zeroreg(t); | |
2266 | } | |
2267 | } | |
2268 | } | |
630b122b | 2269 | if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU |
2270 | assert(0); | |
57871462 | 2271 | } |
630b122b | 2272 | if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU |
2273 | if(dops[i].rt1) { | |
2274 | signed char s1l,s2l,t; | |
57871462 | 2275 | { |
630b122b | 2276 | t=get_reg(i_regs->regmap,dops[i].rt1); |
57871462 | 2277 | //assert(t>=0); |
2278 | if(t>=0) { | |
630b122b | 2279 | s1l=get_reg(i_regs->regmap,dops[i].rs1); |
2280 | s2l=get_reg(i_regs->regmap,dops[i].rs2); | |
2281 | if(dops[i].rs2==0) // rx<r0 | |
57871462 | 2282 | { |
630b122b | 2283 | if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT |
2284 | assert(s1l>=0); | |
57871462 | 2285 | emit_shrimm(s1l,31,t); |
630b122b | 2286 | } |
2287 | else // SLTU (unsigned can not be less than zero, 0<0) | |
57871462 | 2288 | emit_zeroreg(t); |
2289 | } | |
630b122b | 2290 | else if(dops[i].rs1==0) // r0<rx |
57871462 | 2291 | { |
2292 | assert(s2l>=0); | |
630b122b | 2293 | if(dops[i].opcode2==0x2a) // SLT |
57871462 | 2294 | emit_set_gz32(s2l,t); |
2295 | else // SLTU (set if not zero) | |
2296 | emit_set_nz32(s2l,t); | |
2297 | } | |
2298 | else{ | |
2299 | assert(s1l>=0);assert(s2l>=0); | |
630b122b | 2300 | if(dops[i].opcode2==0x2a) // SLT |
57871462 | 2301 | emit_set_if_less32(s1l,s2l,t); |
2302 | else // SLTU | |
2303 | emit_set_if_carry32(s1l,s2l,t); | |
2304 | } | |
2305 | } | |
2306 | } | |
2307 | } | |
2308 | } | |
630b122b | 2309 | if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR |
2310 | if(dops[i].rt1) { | |
2311 | signed char s1l,s2l,tl; | |
2312 | tl=get_reg(i_regs->regmap,dops[i].rt1); | |
57871462 | 2313 | { |
57871462 | 2314 | if(tl>=0) { |
630b122b | 2315 | s1l=get_reg(i_regs->regmap,dops[i].rs1); |
2316 | s2l=get_reg(i_regs->regmap,dops[i].rs2); | |
2317 | if(dops[i].rs1&&dops[i].rs2) { | |
57871462 | 2318 | assert(s1l>=0); |
2319 | assert(s2l>=0); | |
630b122b | 2320 | if(dops[i].opcode2==0x24) { // AND |
57871462 | 2321 | emit_and(s1l,s2l,tl); |
2322 | } else | |
630b122b | 2323 | if(dops[i].opcode2==0x25) { // OR |
57871462 | 2324 | emit_or(s1l,s2l,tl); |
2325 | } else | |
630b122b | 2326 | if(dops[i].opcode2==0x26) { // XOR |
57871462 | 2327 | emit_xor(s1l,s2l,tl); |
2328 | } else | |
630b122b | 2329 | if(dops[i].opcode2==0x27) { // NOR |
57871462 | 2330 | emit_or(s1l,s2l,tl); |
2331 | emit_not(tl,tl); | |
2332 | } | |
2333 | } | |
2334 | else | |
2335 | { | |
630b122b | 2336 | if(dops[i].opcode2==0x24) { // AND |
57871462 | 2337 | emit_zeroreg(tl); |
2338 | } else | |
630b122b | 2339 | if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR |
2340 | if(dops[i].rs1){ | |
57871462 | 2341 | if(s1l>=0) emit_mov(s1l,tl); |
630b122b | 2342 | else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry? |
57871462 | 2343 | } |
2344 | else | |
630b122b | 2345 | if(dops[i].rs2){ |
57871462 | 2346 | if(s2l>=0) emit_mov(s2l,tl); |
630b122b | 2347 | else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry? |
57871462 | 2348 | } |
2349 | else emit_zeroreg(tl); | |
2350 | } else | |
630b122b | 2351 | if(dops[i].opcode2==0x27) { // NOR |
2352 | if(dops[i].rs1){ | |
57871462 | 2353 | if(s1l>=0) emit_not(s1l,tl); |
2354 | else { | |
630b122b | 2355 | emit_loadreg(dops[i].rs1,tl); |
57871462 | 2356 | emit_not(tl,tl); |
2357 | } | |
2358 | } | |
2359 | else | |
630b122b | 2360 | if(dops[i].rs2){ |
57871462 | 2361 | if(s2l>=0) emit_not(s2l,tl); |
2362 | else { | |
630b122b | 2363 | emit_loadreg(dops[i].rs2,tl); |
57871462 | 2364 | emit_not(tl,tl); |
2365 | } | |
2366 | } | |
2367 | else emit_movimm(-1,tl); | |
2368 | } | |
2369 | } | |
2370 | } | |
2371 | } | |
2372 | } | |
2373 | } | |
2374 | } | |
2375 | ||
630b122b | 2376 | static void imm16_assemble(int i, const struct regstat *i_regs) |
57871462 | 2377 | { |
630b122b | 2378 | if (dops[i].opcode==0x0f) { // LUI |
2379 | if(dops[i].rt1) { | |
57871462 | 2380 | signed char t; |
630b122b | 2381 | t=get_reg(i_regs->regmap,dops[i].rt1); |
57871462 | 2382 | //assert(t>=0); |
2383 | if(t>=0) { | |
2384 | if(!((i_regs->isconst>>t)&1)) | |
2385 | emit_movimm(imm[i]<<16,t); | |
2386 | } | |
2387 | } | |
2388 | } | |
630b122b | 2389 | if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU |
2390 | if(dops[i].rt1) { | |
57871462 | 2391 | signed char s,t; |
630b122b | 2392 | t=get_reg(i_regs->regmap,dops[i].rt1); |
2393 | s=get_reg(i_regs->regmap,dops[i].rs1); | |
2394 | if(dops[i].rs1) { | |
57871462 | 2395 | //assert(t>=0); |
2396 | //assert(s>=0); | |
2397 | if(t>=0) { | |
2398 | if(!((i_regs->isconst>>t)&1)) { | |
2399 | if(s<0) { | |
630b122b | 2400 | if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); |
57871462 | 2401 | emit_addimm(t,imm[i],t); |
2402 | }else{ | |
2403 | if(!((i_regs->wasconst>>s)&1)) | |
2404 | emit_addimm(s,imm[i],t); | |
2405 | else | |
2406 | emit_movimm(constmap[i][s]+imm[i],t); | |
2407 | } | |
2408 | } | |
2409 | } | |
2410 | } else { | |
2411 | if(t>=0) { | |
2412 | if(!((i_regs->isconst>>t)&1)) | |
2413 | emit_movimm(imm[i],t); | |
2414 | } | |
2415 | } | |
2416 | } | |
2417 | } | |
630b122b | 2418 | if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU |
2419 | if(dops[i].rt1) { | |
2420 | signed char sl,tl; | |
2421 | tl=get_reg(i_regs->regmap,dops[i].rt1); | |
2422 | sl=get_reg(i_regs->regmap,dops[i].rs1); | |
57871462 | 2423 | if(tl>=0) { |
630b122b | 2424 | if(dops[i].rs1) { |
57871462 | 2425 | assert(sl>=0); |
630b122b | 2426 | emit_addimm(sl,imm[i],tl); |
57871462 | 2427 | } else { |
2428 | emit_movimm(imm[i],tl); | |
57871462 | 2429 | } |
2430 | } | |
2431 | } | |
2432 | } | |
630b122b | 2433 | else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU |
2434 | if(dops[i].rt1) { | |
2435 | //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug | |
2436 | signed char sl,t; | |
2437 | t=get_reg(i_regs->regmap,dops[i].rt1); | |
2438 | sl=get_reg(i_regs->regmap,dops[i].rs1); | |
57871462 | 2439 | //assert(t>=0); |
2440 | if(t>=0) { | |
630b122b | 2441 | if(dops[i].rs1>0) { |
2442 | if(dops[i].opcode==0x0a) { // SLTI | |
57871462 | 2443 | if(sl<0) { |
630b122b | 2444 | if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); |
57871462 | 2445 | emit_slti32(t,imm[i],t); |
2446 | }else{ | |
2447 | emit_slti32(sl,imm[i],t); | |
2448 | } | |
2449 | } | |
2450 | else { // SLTIU | |
2451 | if(sl<0) { | |
630b122b | 2452 | if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); |
57871462 | 2453 | emit_sltiu32(t,imm[i],t); |
2454 | }else{ | |
2455 | emit_sltiu32(sl,imm[i],t); | |
2456 | } | |
2457 | } | |
57871462 | 2458 | }else{ |
2459 | // SLTI(U) with r0 is just stupid, | |
2460 | // nonetheless examples can be found | |
630b122b | 2461 | if(dops[i].opcode==0x0a) // SLTI |
57871462 | 2462 | if(0<imm[i]) emit_movimm(1,t); |
2463 | else emit_zeroreg(t); | |
2464 | else // SLTIU | |
2465 | { | |
2466 | if(imm[i]) emit_movimm(1,t); | |
2467 | else emit_zeroreg(t); | |
2468 | } | |
2469 | } | |
2470 | } | |
2471 | } | |
2472 | } | |
630b122b | 2473 | else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI |
2474 | if(dops[i].rt1) { | |
2475 | signed char sl,tl; | |
2476 | tl=get_reg(i_regs->regmap,dops[i].rt1); | |
2477 | sl=get_reg(i_regs->regmap,dops[i].rs1); | |
57871462 | 2478 | if(tl>=0 && !((i_regs->isconst>>tl)&1)) { |
630b122b | 2479 | if(dops[i].opcode==0x0c) //ANDI |
57871462 | 2480 | { |
630b122b | 2481 | if(dops[i].rs1) { |
57871462 | 2482 | if(sl<0) { |
630b122b | 2483 | if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl); |
57871462 | 2484 | emit_andimm(tl,imm[i],tl); |
2485 | }else{ | |
2486 | if(!((i_regs->wasconst>>sl)&1)) | |
2487 | emit_andimm(sl,imm[i],tl); | |
2488 | else | |
2489 | emit_movimm(constmap[i][sl]&imm[i],tl); | |
2490 | } | |
2491 | } | |
2492 | else | |
2493 | emit_zeroreg(tl); | |
57871462 | 2494 | } |
2495 | else | |
2496 | { | |
630b122b | 2497 | if(dops[i].rs1) { |
57871462 | 2498 | if(sl<0) { |
630b122b | 2499 | if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl); |
57871462 | 2500 | } |
630b122b | 2501 | if(dops[i].opcode==0x0d) { // ORI |
581335b0 | 2502 | if(sl<0) { |
2503 | emit_orimm(tl,imm[i],tl); | |
2504 | }else{ | |
2505 | if(!((i_regs->wasconst>>sl)&1)) | |
2506 | emit_orimm(sl,imm[i],tl); | |
2507 | else | |
2508 | emit_movimm(constmap[i][sl]|imm[i],tl); | |
2509 | } | |
57871462 | 2510 | } |
630b122b | 2511 | if(dops[i].opcode==0x0e) { // XORI |
581335b0 | 2512 | if(sl<0) { |
2513 | emit_xorimm(tl,imm[i],tl); | |
2514 | }else{ | |
2515 | if(!((i_regs->wasconst>>sl)&1)) | |
2516 | emit_xorimm(sl,imm[i],tl); | |
2517 | else | |
2518 | emit_movimm(constmap[i][sl]^imm[i],tl); | |
2519 | } | |
57871462 | 2520 | } |
2521 | } | |
2522 | else { | |
2523 | emit_movimm(imm[i],tl); | |
57871462 | 2524 | } |
2525 | } | |
2526 | } | |
2527 | } | |
2528 | } | |
2529 | } | |
2530 | ||
630b122b | 2531 | static void shiftimm_assemble(int i, const struct regstat *i_regs) |
57871462 | 2532 | { |
630b122b | 2533 | if(dops[i].opcode2<=0x3) // SLL/SRL/SRA |
57871462 | 2534 | { |
630b122b | 2535 | if(dops[i].rt1) { |
57871462 | 2536 | signed char s,t; |
630b122b | 2537 | t=get_reg(i_regs->regmap,dops[i].rt1); |
2538 | s=get_reg(i_regs->regmap,dops[i].rs1); | |
57871462 | 2539 | //assert(t>=0); |
dc49e339 | 2540 | if(t>=0&&!((i_regs->isconst>>t)&1)){ |
630b122b | 2541 | if(dops[i].rs1==0) |
57871462 | 2542 | { |
2543 | emit_zeroreg(t); | |
2544 | } | |
2545 | else | |
2546 | { | |
630b122b | 2547 | if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t); |
57871462 | 2548 | if(imm[i]) { |
630b122b | 2549 | if(dops[i].opcode2==0) // SLL |
57871462 | 2550 | { |
2551 | emit_shlimm(s<0?t:s,imm[i],t); | |
2552 | } | |
630b122b | 2553 | if(dops[i].opcode2==2) // SRL |
57871462 | 2554 | { |
2555 | emit_shrimm(s<0?t:s,imm[i],t); | |
2556 | } | |
630b122b | 2557 | if(dops[i].opcode2==3) // SRA |
57871462 | 2558 | { |
2559 | emit_sarimm(s<0?t:s,imm[i],t); | |
2560 | } | |
2561 | }else{ | |
2562 | // Shift by zero | |
2563 | if(s>=0 && s!=t) emit_mov(s,t); | |
2564 | } | |
2565 | } | |
2566 | } | |
630b122b | 2567 | //emit_storereg(dops[i].rt1,t); //DEBUG |
57871462 | 2568 | } |
2569 | } | |
630b122b | 2570 | if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA |
57871462 | 2571 | { |
630b122b | 2572 | assert(0); |
57871462 | 2573 | } |
630b122b | 2574 | if(dops[i].opcode2==0x3c) // DSLL32 |
57871462 | 2575 | { |
630b122b | 2576 | assert(0); |
57871462 | 2577 | } |
630b122b | 2578 | if(dops[i].opcode2==0x3e) // DSRL32 |
57871462 | 2579 | { |
630b122b | 2580 | assert(0); |
57871462 | 2581 | } |
630b122b | 2582 | if(dops[i].opcode2==0x3f) // DSRA32 |
57871462 | 2583 | { |
630b122b | 2584 | assert(0); |
57871462 | 2585 | } |
2586 | } | |
2587 | ||
2588 | #ifndef shift_assemble | |
630b122b | 2589 | static void shift_assemble(int i, const struct regstat *i_regs) |
57871462 | 2590 | { |
630b122b | 2591 | signed char s,t,shift; |
2592 | if (dops[i].rt1 == 0) | |
2593 | return; | |
2594 | assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV | |
2595 | t = get_reg(i_regs->regmap, dops[i].rt1); | |
2596 | s = get_reg(i_regs->regmap, dops[i].rs1); | |
2597 | shift = get_reg(i_regs->regmap, dops[i].rs2); | |
2598 | if (t < 0) | |
2599 | return; | |
2600 | ||
2601 | if(dops[i].rs1==0) | |
2602 | emit_zeroreg(t); | |
2603 | else if(dops[i].rs2==0) { | |
2604 | assert(s>=0); | |
2605 | if(s!=t) emit_mov(s,t); | |
2606 | } | |
2607 | else { | |
2608 | host_tempreg_acquire(); | |
2609 | emit_andimm(shift,31,HOST_TEMPREG); | |
2610 | switch(dops[i].opcode2) { | |
2611 | case 4: // SLLV | |
2612 | emit_shl(s,HOST_TEMPREG,t); | |
2613 | break; | |
2614 | case 6: // SRLV | |
2615 | emit_shr(s,HOST_TEMPREG,t); | |
2616 | break; | |
2617 | case 7: // SRAV | |
2618 | emit_sar(s,HOST_TEMPREG,t); | |
2619 | break; | |
2620 | default: | |
2621 | assert(0); | |
2622 | } | |
2623 | host_tempreg_release(); | |
2624 | } | |
57871462 | 2625 | } |
630b122b | 2626 | |
57871462 | 2627 | #endif |
2628 | ||
630b122b | 2629 | enum { |
2630 | MTYPE_8000 = 0, | |
2631 | MTYPE_8020, | |
2632 | MTYPE_0000, | |
2633 | MTYPE_A000, | |
2634 | MTYPE_1F80, | |
2635 | }; | |
2636 | ||
2637 | static int get_ptr_mem_type(u_int a) | |
2638 | { | |
2639 | if(a < 0x00200000) { | |
2640 | if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0)) | |
2641 | // return wrong, must use memhandler for BIOS self-test to pass | |
2642 | // 007 does similar stuff from a00 mirror, weird stuff | |
2643 | return MTYPE_8000; | |
2644 | return MTYPE_0000; | |
2645 | } | |
2646 | if(0x1f800000 <= a && a < 0x1f801000) | |
2647 | return MTYPE_1F80; | |
2648 | if(0x80200000 <= a && a < 0x80800000) | |
2649 | return MTYPE_8020; | |
2650 | if(0xa0000000 <= a && a < 0xa0200000) | |
2651 | return MTYPE_A000; | |
2652 | return MTYPE_8000; | |
2653 | } | |
2654 | ||
2655 | static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free) | |
2656 | { | |
2657 | int r = get_reg(i_regs->regmap, ROREG); | |
2658 | if (r < 0 && host_tempreg_free) { | |
2659 | host_tempreg_acquire(); | |
2660 | emit_loadreg(ROREG, r = HOST_TEMPREG); | |
2661 | } | |
2662 | if (r < 0) | |
2663 | abort(); | |
2664 | return r; | |
2665 | } | |
2666 | ||
2667 | static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs, | |
2668 | int addr, int *offset_reg, int *addr_reg_override) | |
2669 | { | |
2670 | void *jaddr = NULL; | |
2671 | int type = 0; | |
2672 | int mr = dops[i].rs1; | |
2673 | *offset_reg = -1; | |
2674 | if(((smrv_strong|smrv_weak)>>mr)&1) { | |
2675 | type=get_ptr_mem_type(smrv[mr]); | |
2676 | //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type); | |
2677 | } | |
2678 | else { | |
2679 | // use the mirror we are running on | |
2680 | type=get_ptr_mem_type(start); | |
2681 | //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type); | |
2682 | } | |
2683 | ||
2684 | if(type==MTYPE_8020) { // RAM 80200000+ mirror | |
2685 | host_tempreg_acquire(); | |
2686 | emit_andimm(addr,~0x00e00000,HOST_TEMPREG); | |
2687 | addr=*addr_reg_override=HOST_TEMPREG; | |
2688 | type=0; | |
2689 | } | |
2690 | else if(type==MTYPE_0000) { // RAM 0 mirror | |
2691 | host_tempreg_acquire(); | |
2692 | emit_orimm(addr,0x80000000,HOST_TEMPREG); | |
2693 | addr=*addr_reg_override=HOST_TEMPREG; | |
2694 | type=0; | |
2695 | } | |
2696 | else if(type==MTYPE_A000) { // RAM A mirror | |
2697 | host_tempreg_acquire(); | |
2698 | emit_andimm(addr,~0x20000000,HOST_TEMPREG); | |
2699 | addr=*addr_reg_override=HOST_TEMPREG; | |
2700 | type=0; | |
2701 | } | |
2702 | else if(type==MTYPE_1F80) { // scratchpad | |
2703 | if (psxH == (void *)0x1f800000) { | |
2704 | host_tempreg_acquire(); | |
2705 | emit_xorimm(addr,0x1f800000,HOST_TEMPREG); | |
2706 | emit_cmpimm(HOST_TEMPREG,0x1000); | |
2707 | host_tempreg_release(); | |
2708 | jaddr=out; | |
2709 | emit_jc(0); | |
2710 | } | |
2711 | else { | |
2712 | // do the usual RAM check, jump will go to the right handler | |
2713 | type=0; | |
2714 | } | |
2715 | } | |
2716 | ||
2717 | if (type == 0) // need ram check | |
2718 | { | |
2719 | emit_cmpimm(addr,RAM_SIZE); | |
2720 | jaddr = out; | |
2721 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
2722 | // Hint to branch predictor that the branch is unlikely to be taken | |
2723 | if (dops[i].rs1 >= 28) | |
2724 | emit_jno_unlikely(0); | |
2725 | else | |
2726 | #endif | |
2727 | emit_jno(0); | |
2728 | if (ram_offset != 0) | |
2729 | *offset_reg = get_ro_reg(i_regs, 0); | |
2730 | } | |
2731 | ||
2732 | return jaddr; | |
2733 | } | |
2734 | ||
2735 | // return memhandler, or get directly accessable address and return 0 | |
2736 | static void *get_direct_memhandler(void *table, u_int addr, | |
2737 | enum stub_type type, uintptr_t *addr_host) | |
2738 | { | |
2739 | uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1); | |
2740 | uintptr_t l1, l2 = 0; | |
2741 | l1 = ((uintptr_t *)table)[addr>>12]; | |
2742 | if (!(l1 & msb)) { | |
2743 | uintptr_t v = l1 << 1; | |
2744 | *addr_host = v + addr; | |
2745 | return NULL; | |
2746 | } | |
2747 | else { | |
2748 | l1 <<= 1; | |
2749 | if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB) | |
2750 | l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)]; | |
2751 | else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB) | |
2752 | l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2]; | |
2753 | else | |
2754 | l2 = ((uintptr_t *)l1)[(addr&0xfff)/4]; | |
2755 | if (!(l2 & msb)) { | |
2756 | uintptr_t v = l2 << 1; | |
2757 | *addr_host = v + (addr&0xfff); | |
2758 | return NULL; | |
2759 | } | |
2760 | return (void *)(l2 << 1); | |
2761 | } | |
2762 | } | |
2763 | ||
2764 | static u_int get_host_reglist(const signed char *regmap) | |
2765 | { | |
2766 | u_int reglist = 0, hr; | |
2767 | for (hr = 0; hr < HOST_REGS; hr++) { | |
2768 | if (hr != EXCLUDE_REG && regmap[hr] >= 0) | |
2769 | reglist |= 1 << hr; | |
2770 | } | |
2771 | return reglist; | |
2772 | } | |
2773 | ||
2774 | static u_int reglist_exclude(u_int reglist, int r1, int r2) | |
2775 | { | |
2776 | if (r1 >= 0) | |
2777 | reglist &= ~(1u << r1); | |
2778 | if (r2 >= 0) | |
2779 | reglist &= ~(1u << r2); | |
2780 | return reglist; | |
2781 | } | |
2782 | ||
2783 | // find a temp caller-saved register not in reglist (so assumed to be free) | |
2784 | static int reglist_find_free(u_int reglist) | |
2785 | { | |
2786 | u_int free_regs = ~reglist & CALLER_SAVE_REGS; | |
2787 | if (free_regs == 0) | |
2788 | return -1; | |
2789 | return __builtin_ctz(free_regs); | |
2790 | } | |
2791 | ||
2792 | static void do_load_word(int a, int rt, int offset_reg) | |
2793 | { | |
2794 | if (offset_reg >= 0) | |
2795 | emit_ldr_dualindexed(offset_reg, a, rt); | |
2796 | else | |
2797 | emit_readword_indexed(0, a, rt); | |
2798 | } | |
2799 | ||
2800 | static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a) | |
2801 | { | |
2802 | if (offset_reg < 0) { | |
2803 | emit_writeword_indexed(rt, ofs, a); | |
2804 | return; | |
2805 | } | |
2806 | if (ofs != 0) | |
2807 | emit_addimm(a, ofs, a); | |
2808 | emit_str_dualindexed(offset_reg, a, rt); | |
2809 | if (ofs != 0 && preseve_a) | |
2810 | emit_addimm(a, -ofs, a); | |
2811 | } | |
2812 | ||
2813 | static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a) | |
2814 | { | |
2815 | if (offset_reg < 0) { | |
2816 | emit_writehword_indexed(rt, ofs, a); | |
2817 | return; | |
2818 | } | |
2819 | if (ofs != 0) | |
2820 | emit_addimm(a, ofs, a); | |
2821 | emit_strh_dualindexed(offset_reg, a, rt); | |
2822 | if (ofs != 0 && preseve_a) | |
2823 | emit_addimm(a, -ofs, a); | |
2824 | } | |
2825 | ||
2826 | static void do_store_byte(int a, int rt, int offset_reg) | |
2827 | { | |
2828 | if (offset_reg >= 0) | |
2829 | emit_strb_dualindexed(offset_reg, a, rt); | |
2830 | else | |
2831 | emit_writebyte_indexed(rt, 0, a); | |
2832 | } | |
2833 | ||
2834 | static void load_assemble(int i, const struct regstat *i_regs, int ccadj_) | |
57871462 | 2835 | { |
630b122b | 2836 | int s,tl,addr; |
57871462 | 2837 | int offset; |
630b122b | 2838 | void *jaddr=0; |
5bf843dc | 2839 | int memtarget=0,c=0; |
630b122b | 2840 | int offset_reg = -1; |
2841 | int fastio_reg_override = -1; | |
2842 | u_int reglist=get_host_reglist(i_regs->regmap); | |
2843 | tl=get_reg(i_regs->regmap,dops[i].rt1); | |
2844 | s=get_reg(i_regs->regmap,dops[i].rs1); | |
57871462 | 2845 | offset=imm[i]; |
57871462 | 2846 | if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG); |
2847 | if(s>=0) { | |
2848 | c=(i_regs->wasconst>>s)&1; | |
af4ee1fe | 2849 | if (c) { |
2850 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; | |
af4ee1fe | 2851 | } |
57871462 | 2852 | } |
57871462 | 2853 | //printf("load_assemble: c=%d\n",c); |
630b122b | 2854 | //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset); |
57871462 | 2855 | // FIXME: Even if the load is a NOP, we should check for pagefaults... |
581335b0 | 2856 | if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)) |
630b122b | 2857 | ||dops[i].rt1==0) { |
5bf843dc | 2858 | // could be FIFO, must perform the read |
f18c0f46 | 2859 | // ||dummy read |
5bf843dc | 2860 | assem_debug("(forced read)\n"); |
91af94f0 | 2861 | tl=get_reg_temp(i_regs->regmap); |
5bf843dc | 2862 | assert(tl>=0); |
5bf843dc | 2863 | } |
2864 | if(offset||s<0||c) addr=tl; | |
2865 | else addr=s; | |
91af94f0 | 2866 | //if(tl<0) tl=get_reg_temp(i_regs->regmap); |
535d208a | 2867 | if(tl>=0) { |
2868 | //printf("load_assemble: c=%d\n",c); | |
630b122b | 2869 | //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset); |
535d208a | 2870 | assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O |
2871 | reglist&=~(1<<tl); | |
1edfcc68 | 2872 | if(!c) { |
1edfcc68 | 2873 | #ifdef R29_HACK |
2874 | // Strmnnrmn's speed hack | |
630b122b | 2875 | if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE) |
1edfcc68 | 2876 | #endif |
2877 | { | |
630b122b | 2878 | jaddr = emit_fastpath_cmp_jump(i, i_regs, addr, |
2879 | &offset_reg, &fastio_reg_override); | |
535d208a | 2880 | } |
1edfcc68 | 2881 | } |
630b122b | 2882 | else if (ram_offset && memtarget) { |
2883 | offset_reg = get_ro_reg(i_regs, 0); | |
535d208a | 2884 | } |
630b122b | 2885 | int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg |
2886 | switch (dops[i].opcode) { | |
2887 | case 0x20: // LB | |
535d208a | 2888 | if(!c||memtarget) { |
2889 | if(!dummy) { | |
630b122b | 2890 | int a = tl; |
2891 | if (!c) a = addr; | |
2892 | if (fastio_reg_override >= 0) | |
2893 | a = fastio_reg_override; | |
b1570849 | 2894 | |
630b122b | 2895 | if (offset_reg >= 0) |
2896 | emit_ldrsb_dualindexed(offset_reg, a, tl); | |
2897 | else | |
2898 | emit_movsbl_indexed(0, a, tl); | |
57871462 | 2899 | } |
535d208a | 2900 | if(jaddr) |
630b122b | 2901 | add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 | 2902 | } |
535d208a | 2903 | else |
630b122b | 2904 | inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
2905 | break; | |
2906 | case 0x21: // LH | |
535d208a | 2907 | if(!c||memtarget) { |
2908 | if(!dummy) { | |
630b122b | 2909 | int a = tl; |
2910 | if (!c) a = addr; | |
2911 | if (fastio_reg_override >= 0) | |
2912 | a = fastio_reg_override; | |
2913 | if (offset_reg >= 0) | |
2914 | emit_ldrsh_dualindexed(offset_reg, a, tl); | |
57871462 | 2915 | else |
630b122b | 2916 | emit_movswl_indexed(0, a, tl); |
57871462 | 2917 | } |
535d208a | 2918 | if(jaddr) |
630b122b | 2919 | add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 | 2920 | } |
535d208a | 2921 | else |
630b122b | 2922 | inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
2923 | break; | |
2924 | case 0x23: // LW | |
535d208a | 2925 | if(!c||memtarget) { |
2926 | if(!dummy) { | |
630b122b | 2927 | int a = addr; |
2928 | if (fastio_reg_override >= 0) | |
2929 | a = fastio_reg_override; | |
2930 | do_load_word(a, tl, offset_reg); | |
57871462 | 2931 | } |
535d208a | 2932 | if(jaddr) |
630b122b | 2933 | add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 | 2934 | } |
535d208a | 2935 | else |
630b122b | 2936 | inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
2937 | break; | |
2938 | case 0x24: // LBU | |
535d208a | 2939 | if(!c||memtarget) { |
2940 | if(!dummy) { | |
630b122b | 2941 | int a = tl; |
2942 | if (!c) a = addr; | |
2943 | if (fastio_reg_override >= 0) | |
2944 | a = fastio_reg_override; | |
b1570849 | 2945 | |
630b122b | 2946 | if (offset_reg >= 0) |
2947 | emit_ldrb_dualindexed(offset_reg, a, tl); | |
2948 | else | |
2949 | emit_movzbl_indexed(0, a, tl); | |
57871462 | 2950 | } |
535d208a | 2951 | if(jaddr) |
630b122b | 2952 | add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 | 2953 | } |
535d208a | 2954 | else |
630b122b | 2955 | inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
2956 | break; | |
2957 | case 0x25: // LHU | |
535d208a | 2958 | if(!c||memtarget) { |
2959 | if(!dummy) { | |
630b122b | 2960 | int a = tl; |
2961 | if(!c) a = addr; | |
2962 | if (fastio_reg_override >= 0) | |
2963 | a = fastio_reg_override; | |
2964 | if (offset_reg >= 0) | |
2965 | emit_ldrh_dualindexed(offset_reg, a, tl); | |
57871462 | 2966 | else |
630b122b | 2967 | emit_movzwl_indexed(0, a, tl); |
57871462 | 2968 | } |
535d208a | 2969 | if(jaddr) |
630b122b | 2970 | add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
57871462 | 2971 | } |
535d208a | 2972 | else |
630b122b | 2973 | inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); |
2974 | break; | |
2975 | case 0x27: // LWU | |
2976 | case 0x37: // LD | |
2977 | default: | |
2978 | assert(0); | |
535d208a | 2979 | } |
630b122b | 2980 | } |
2981 | if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) | |
2982 | host_tempreg_release(); | |
2983 | } | |
2984 | ||
2985 | #ifndef loadlr_assemble | |
2986 | static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_) | |
2987 | { | |
2988 | int s,tl,temp,temp2,addr; | |
2989 | int offset; | |
2990 | void *jaddr=0; | |
2991 | int memtarget=0,c=0; | |
2992 | int offset_reg = -1; | |
2993 | int fastio_reg_override = -1; | |
2994 | u_int reglist=get_host_reglist(i_regs->regmap); | |
2995 | tl=get_reg(i_regs->regmap,dops[i].rt1); | |
2996 | s=get_reg(i_regs->regmap,dops[i].rs1); | |
91af94f0 | 2997 | temp=get_reg_temp(i_regs->regmap); |
630b122b | 2998 | temp2=get_reg(i_regs->regmap,FTEMP); |
2999 | addr=get_reg(i_regs->regmap,AGEN1+(i&1)); | |
3000 | assert(addr<0); | |
3001 | offset=imm[i]; | |
3002 | reglist|=1<<temp; | |
3003 | if(offset||s<0||c) addr=temp2; | |
3004 | else addr=s; | |
3005 | if(s>=0) { | |
3006 | c=(i_regs->wasconst>>s)&1; | |
3007 | if(c) { | |
3008 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; | |
535d208a | 3009 | } |
630b122b | 3010 | } |
3011 | if(!c) { | |
3012 | emit_shlimm(addr,3,temp); | |
3013 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { | |
3014 | emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR | |
3015 | }else{ | |
3016 | emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR | |
3017 | } | |
3018 | jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2, | |
3019 | &offset_reg, &fastio_reg_override); | |
3020 | } | |
3021 | else { | |
3022 | if (ram_offset && memtarget) { | |
3023 | offset_reg = get_ro_reg(i_regs, 0); | |
3024 | } | |
3025 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { | |
3026 | emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR | |
3027 | }else{ | |
3028 | emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR | |
57871462 | 3029 | } |
535d208a | 3030 | } |
630b122b | 3031 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR |
535d208a | 3032 | if(!c||memtarget) { |
630b122b | 3033 | int a = temp2; |
3034 | if (fastio_reg_override >= 0) | |
3035 | a = fastio_reg_override; | |
3036 | do_load_word(a, temp2, offset_reg); | |
3037 | if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) | |
3038 | host_tempreg_release(); | |
3039 | if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist); | |
57871462 | 3040 | } |
535d208a | 3041 | else |
630b122b | 3042 | inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist); |
3043 | if(dops[i].rt1) { | |
3044 | assert(tl>=0); | |
3045 | emit_andimm(temp,24,temp); | |
3046 | if (dops[i].opcode==0x22) // LWL | |
3047 | emit_xorimm(temp,24,temp); | |
3048 | host_tempreg_acquire(); | |
3049 | emit_movimm(-1,HOST_TEMPREG); | |
3050 | if (dops[i].opcode==0x26) { | |
3051 | emit_shr(temp2,temp,temp2); | |
3052 | emit_bic_lsr(tl,HOST_TEMPREG,temp,tl); | |
3053 | }else{ | |
3054 | emit_shl(temp2,temp,temp2); | |
3055 | emit_bic_lsl(tl,HOST_TEMPREG,temp,tl); | |
3056 | } | |
3057 | host_tempreg_release(); | |
3058 | emit_or(temp2,tl,tl); | |
3059 | } | |
3060 | //emit_storereg(dops[i].rt1,tl); // DEBUG | |
3061 | } | |
3062 | if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR | |
3063 | assert(0); | |
57871462 | 3064 | } |
57871462 | 3065 | } |
3066 | #endif | |
3067 | ||
630b122b | 3068 | static void store_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 | 3069 | { |
630b122b | 3070 | int s,tl; |
57871462 | 3071 | int addr,temp; |
3072 | int offset; | |
630b122b | 3073 | void *jaddr=0; |
3074 | enum stub_type type=0; | |
666a299d | 3075 | int memtarget=0,c=0; |
57871462 | 3076 | int agr=AGEN1+(i&1); |
630b122b | 3077 | int offset_reg = -1; |
3078 | int fastio_reg_override = -1; | |
3079 | u_int reglist=get_host_reglist(i_regs->regmap); | |
3080 | tl=get_reg(i_regs->regmap,dops[i].rs2); | |
3081 | s=get_reg(i_regs->regmap,dops[i].rs1); | |
57871462 | 3082 | temp=get_reg(i_regs->regmap,agr); |
91af94f0 | 3083 | if(temp<0) temp=get_reg_temp(i_regs->regmap); |
57871462 | 3084 | offset=imm[i]; |
3085 | if(s>=0) { | |
3086 | c=(i_regs->wasconst>>s)&1; | |
af4ee1fe | 3087 | if(c) { |
3088 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; | |
af4ee1fe | 3089 | } |
57871462 | 3090 | } |
3091 | assert(tl>=0); | |
3092 | assert(temp>=0); | |
57871462 | 3093 | if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG); |
3094 | if(offset||s<0||c) addr=temp; | |
3095 | else addr=s; | |
630b122b | 3096 | if (!c) { |
3097 | jaddr = emit_fastpath_cmp_jump(i, i_regs, addr, | |
3098 | &offset_reg, &fastio_reg_override); | |
1edfcc68 | 3099 | } |
630b122b | 3100 | else if (ram_offset && memtarget) { |
3101 | offset_reg = get_ro_reg(i_regs, 0); | |
57871462 | 3102 | } |
3103 | ||
630b122b | 3104 | switch (dops[i].opcode) { |
3105 | case 0x28: // SB | |
57871462 | 3106 | if(!c||memtarget) { |
630b122b | 3107 | int a = temp; |
3108 | if (!c) a = addr; | |
3109 | if (fastio_reg_override >= 0) | |
3110 | a = fastio_reg_override; | |
3111 | do_store_byte(a, tl, offset_reg); | |
3112 | } | |
3113 | type = STOREB_STUB; | |
3114 | break; | |
3115 | case 0x29: // SH | |
dadf55f2 | 3116 | if(!c||memtarget) { |
630b122b | 3117 | int a = temp; |
3118 | if (!c) a = addr; | |
3119 | if (fastio_reg_override >= 0) | |
3120 | a = fastio_reg_override; | |
3121 | do_store_hword(a, 0, tl, offset_reg, 1); | |
3122 | } | |
3123 | type = STOREH_STUB; | |
3124 | break; | |
3125 | case 0x2B: // SW | |
57871462 | 3126 | if(!c||memtarget) { |
630b122b | 3127 | int a = addr; |
3128 | if (fastio_reg_override >= 0) | |
3129 | a = fastio_reg_override; | |
3130 | do_store_word(a, 0, tl, offset_reg, 1); | |
3131 | } | |
3132 | type = STOREW_STUB; | |
3133 | break; | |
3134 | case 0x3F: // SD | |
3135 | default: | |
3136 | assert(0); | |
3137 | } | |
3138 | if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) | |
3139 | host_tempreg_release(); | |
b96d3df7 | 3140 | if(jaddr) { |
3141 | // PCSX store handlers don't check invcode again | |
3142 | reglist|=1<<addr; | |
630b122b | 3143 | add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
b96d3df7 | 3144 | jaddr=0; |
3145 | } | |
630b122b | 3146 | if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) { |
57871462 | 3147 | if(!c||memtarget) { |
3148 | #ifdef DESTRUCTIVE_SHIFT | |
3149 | // The x86 shift operation is 'destructive'; it overwrites the | |
3150 | // source register, so we need to make a copy first and use that. | |
3151 | addr=temp; | |
3152 | #endif | |
3153 | #if defined(HOST_IMM8) | |
3154 | int ir=get_reg(i_regs->regmap,INVCP); | |
3155 | assert(ir>=0); | |
3156 | emit_cmpmem_indexedsr12_reg(ir,addr,1); | |
3157 | #else | |
630b122b | 3158 | emit_cmpmem_indexedsr12_imm(invalid_code,addr,1); |
57871462 | 3159 | #endif |
b9e27215 | 3160 | #ifdef INVALIDATE_USE_COND_CALL |
0bbd1454 | 3161 | emit_callne(invalidate_addr_reg[addr]); |
3162 | #else | |
630b122b | 3163 | void *jaddr2 = out; |
57871462 | 3164 | emit_jne(0); |
630b122b | 3165 | add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0); |
0bbd1454 | 3166 | #endif |
57871462 | 3167 | } |
3168 | } | |
7a518516 | 3169 | u_int addr_val=constmap[i][s]+offset; |
3eaa7048 | 3170 | if(jaddr) { |
630b122b | 3171 | add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist); |
3eaa7048 | 3172 | } else if(c&&!memtarget) { |
630b122b | 3173 | inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist); |
7a518516 | 3174 | } |
3175 | // basic current block modification detection.. | |
3176 | // not looking back as that should be in mips cache already | |
630b122b | 3177 | // (see Spyro2 title->attract mode) |
7a518516 | 3178 | if(c&&start+i*4<addr_val&&addr_val<start+slen*4) { |
c43b5311 | 3179 | SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4); |
7a518516 | 3180 | assert(i_regs->regmap==regs[i].regmap); // not delay slot |
3181 | if(i_regs->regmap==regs[i].regmap) { | |
630b122b | 3182 | load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i); |
3183 | wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty); | |
7a518516 | 3184 | emit_movimm(start+i*4+4,0); |
630b122b | 3185 | emit_writeword(0,&pcaddr); |
3186 | emit_addimm(HOST_CCREG,2,HOST_CCREG); | |
048fcced | 3187 | emit_far_call(ndrc_get_addr_ht); |
630b122b | 3188 | emit_jmpreg(0); |
7a518516 | 3189 | } |
3eaa7048 | 3190 | } |
57871462 | 3191 | } |
3192 | ||
630b122b | 3193 | static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 | 3194 | { |
630b122b | 3195 | int s,tl; |
57871462 | 3196 | int temp; |
57871462 | 3197 | int offset; |
630b122b | 3198 | void *jaddr=0; |
3199 | void *case1, *case23, *case3; | |
3200 | void *done0, *done1, *done2; | |
af4ee1fe | 3201 | int memtarget=0,c=0; |
fab5d06d | 3202 | int agr=AGEN1+(i&1); |
630b122b | 3203 | int offset_reg = -1; |
3204 | u_int reglist=get_host_reglist(i_regs->regmap); | |
3205 | tl=get_reg(i_regs->regmap,dops[i].rs2); | |
3206 | s=get_reg(i_regs->regmap,dops[i].rs1); | |
fab5d06d | 3207 | temp=get_reg(i_regs->regmap,agr); |
91af94f0 | 3208 | if(temp<0) temp=get_reg_temp(i_regs->regmap); |
57871462 | 3209 | offset=imm[i]; |
3210 | if(s>=0) { | |
3211 | c=(i_regs->isconst>>s)&1; | |
af4ee1fe | 3212 | if(c) { |
3213 | memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; | |
af4ee1fe | 3214 | } |
57871462 | 3215 | } |
3216 | assert(tl>=0); | |
535d208a | 3217 | assert(temp>=0); |
1edfcc68 | 3218 | if(!c) { |
3219 | emit_cmpimm(s<0||offset?temp:s,RAM_SIZE); | |
3220 | if(!offset&&s!=temp) emit_mov(s,temp); | |
630b122b | 3221 | jaddr=out; |
1edfcc68 | 3222 | emit_jno(0); |
3223 | } | |
3224 | else | |
3225 | { | |
630b122b | 3226 | if(!memtarget||!dops[i].rs1) { |
3227 | jaddr=out; | |
535d208a | 3228 | emit_jmp(0); |
57871462 | 3229 | } |
535d208a | 3230 | } |
630b122b | 3231 | if (ram_offset) |
3232 | offset_reg = get_ro_reg(i_regs, 0); | |
535d208a | 3233 | |
630b122b | 3234 | if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR |
3235 | assert(0); | |
535d208a | 3236 | } |
57871462 | 3237 | |
535d208a | 3238 | emit_testimm(temp,2); |
630b122b | 3239 | case23=out; |
535d208a | 3240 | emit_jne(0); |
3241 | emit_testimm(temp,1); | |
630b122b | 3242 | case1=out; |
535d208a | 3243 | emit_jne(0); |
3244 | // 0 | |
630b122b | 3245 | if (dops[i].opcode == 0x2A) { // SWL |
3246 | // Write msb into least significant byte | |
3247 | if (dops[i].rs2) emit_rorimm(tl, 24, tl); | |
3248 | do_store_byte(temp, tl, offset_reg); | |
3249 | if (dops[i].rs2) emit_rorimm(tl, 8, tl); | |
535d208a | 3250 | } |
630b122b | 3251 | else if (dops[i].opcode == 0x2E) { // SWR |
3252 | // Write entire word | |
3253 | do_store_word(temp, 0, tl, offset_reg, 1); | |
535d208a | 3254 | } |
630b122b | 3255 | done0 = out; |
535d208a | 3256 | emit_jmp(0); |
3257 | // 1 | |
630b122b | 3258 | set_jump_target(case1, out); |
3259 | if (dops[i].opcode == 0x2A) { // SWL | |
3260 | // Write two msb into two least significant bytes | |
3261 | if (dops[i].rs2) emit_rorimm(tl, 16, tl); | |
3262 | do_store_hword(temp, -1, tl, offset_reg, 0); | |
3263 | if (dops[i].rs2) emit_rorimm(tl, 16, tl); | |
535d208a | 3264 | } |
630b122b | 3265 | else if (dops[i].opcode == 0x2E) { // SWR |
3266 | // Write 3 lsb into three most significant bytes | |
3267 | do_store_byte(temp, tl, offset_reg); | |
3268 | if (dops[i].rs2) emit_rorimm(tl, 8, tl); | |
3269 | do_store_hword(temp, 1, tl, offset_reg, 0); | |
3270 | if (dops[i].rs2) emit_rorimm(tl, 24, tl); | |
535d208a | 3271 | } |
630b122b | 3272 | done1=out; |
535d208a | 3273 | emit_jmp(0); |
630b122b | 3274 | // 2,3 |
3275 | set_jump_target(case23, out); | |
535d208a | 3276 | emit_testimm(temp,1); |
630b122b | 3277 | case3 = out; |
535d208a | 3278 | emit_jne(0); |
630b122b | 3279 | // 2 |
3280 | if (dops[i].opcode==0x2A) { // SWL | |
3281 | // Write 3 msb into three least significant bytes | |
3282 | if (dops[i].rs2) emit_rorimm(tl, 8, tl); | |
3283 | do_store_hword(temp, -2, tl, offset_reg, 1); | |
3284 | if (dops[i].rs2) emit_rorimm(tl, 16, tl); | |
3285 | do_store_byte(temp, tl, offset_reg); | |
3286 | if (dops[i].rs2) emit_rorimm(tl, 8, tl); | |
535d208a | 3287 | } |
630b122b | 3288 | else if (dops[i].opcode == 0x2E) { // SWR |
3289 | // Write two lsb into two most significant bytes | |
3290 | do_store_hword(temp, 0, tl, offset_reg, 1); | |
535d208a | 3291 | } |
630b122b | 3292 | done2 = out; |
535d208a | 3293 | emit_jmp(0); |
3294 | // 3 | |
630b122b | 3295 | set_jump_target(case3, out); |
3296 | if (dops[i].opcode == 0x2A) { // SWL | |
3297 | do_store_word(temp, -3, tl, offset_reg, 0); | |
3298 | } | |
3299 | else if (dops[i].opcode == 0x2E) { // SWR | |
3300 | do_store_byte(temp, tl, offset_reg); | |
3301 | } | |
3302 | set_jump_target(done0, out); | |
3303 | set_jump_target(done1, out); | |
3304 | set_jump_target(done2, out); | |
3305 | if (offset_reg == HOST_TEMPREG) | |
3306 | host_tempreg_release(); | |
535d208a | 3307 | if(!c||!memtarget) |
630b122b | 3308 | add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist); |
3309 | if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) { | |
57871462 | 3310 | #if defined(HOST_IMM8) |
3311 | int ir=get_reg(i_regs->regmap,INVCP); | |
3312 | assert(ir>=0); | |
3313 | emit_cmpmem_indexedsr12_reg(ir,temp,1); | |
3314 | #else | |
630b122b | 3315 | emit_cmpmem_indexedsr12_imm(invalid_code,temp,1); |
57871462 | 3316 | #endif |
b9e27215 | 3317 | #ifdef INVALIDATE_USE_COND_CALL |
535d208a | 3318 | emit_callne(invalidate_addr_reg[temp]); |
3319 | #else | |
630b122b | 3320 | void *jaddr2 = out; |
57871462 | 3321 | emit_jne(0); |
630b122b | 3322 | add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0); |
535d208a | 3323 | #endif |
57871462 | 3324 | } |
57871462 | 3325 | } |
3326 | ||
630b122b | 3327 | static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_) |
3328 | { | |
3329 | if(dops[i].opcode2==0) // MFC0 | |
3330 | { | |
3331 | signed char t=get_reg(i_regs->regmap,dops[i].rt1); | |
3332 | u_int copr=(source[i]>>11)&0x1f; | |
3333 | //assert(t>=0); // Why does this happen? OOT is weird | |
3334 | if(t>=0&&dops[i].rt1!=0) { | |
3335 | emit_readword(®_cop0[copr],t); | |
3336 | } | |
3337 | } | |
3338 | else if(dops[i].opcode2==4) // MTC0 | |
3339 | { | |
3340 | signed char s=get_reg(i_regs->regmap,dops[i].rs1); | |
3341 | char copr=(source[i]>>11)&0x1f; | |
3342 | assert(s>=0); | |
3343 | wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty); | |
3344 | if(copr==9||copr==11||copr==12||copr==13) { | |
3345 | emit_readword(&last_count,HOST_TEMPREG); | |
3346 | emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc | |
3347 | emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG); | |
3348 | emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG); | |
3349 | emit_writeword(HOST_CCREG,&Count); | |
3350 | } | |
3351 | // What a mess. The status register (12) can enable interrupts, | |
3352 | // so needs a special case to handle a pending interrupt. | |
3353 | // The interrupt must be taken immediately, because a subsequent | |
3354 | // instruction might disable interrupts again. | |
3355 | if(copr==12||copr==13) { | |
3356 | if (is_delayslot) { | |
3357 | // burn cycles to cause cc_interrupt, which will | |
3358 | // reschedule next_interupt. Relies on CCREG from above. | |
3359 | assem_debug("MTC0 DS %d\n", copr); | |
3360 | emit_writeword(HOST_CCREG,&last_count); | |
3361 | emit_movimm(0,HOST_CCREG); | |
3362 | emit_storereg(CCREG,HOST_CCREG); | |
3363 | emit_loadreg(dops[i].rs1,1); | |
3364 | emit_movimm(copr,0); | |
3365 | emit_far_call(pcsx_mtc0_ds); | |
3366 | emit_loadreg(dops[i].rs1,s); | |
3367 | return; | |
3368 | } | |
3369 | emit_movimm(start+i*4+4,HOST_TEMPREG); | |
3370 | emit_writeword(HOST_TEMPREG,&pcaddr); | |
3371 | emit_movimm(0,HOST_TEMPREG); | |
3372 | emit_writeword(HOST_TEMPREG,&pending_exception); | |
3373 | } | |
3374 | if(s==HOST_CCREG) | |
3375 | emit_loadreg(dops[i].rs1,1); | |
3376 | else if(s!=1) | |
3377 | emit_mov(s,1); | |
3378 | emit_movimm(copr,0); | |
3379 | emit_far_call(pcsx_mtc0); | |
3380 | if(copr==9||copr==11||copr==12||copr==13) { | |
3381 | emit_readword(&Count,HOST_CCREG); | |
3382 | emit_readword(&next_interupt,HOST_TEMPREG); | |
3383 | emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG); | |
3384 | emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG); | |
3385 | emit_writeword(HOST_TEMPREG,&last_count); | |
3386 | emit_storereg(CCREG,HOST_CCREG); | |
3387 | } | |
3388 | if(copr==12||copr==13) { | |
3389 | assert(!is_delayslot); | |
3390 | emit_readword(&pending_exception,14); | |
3391 | emit_test(14,14); | |
3392 | void *jaddr = out; | |
3393 | emit_jeq(0); | |
3394 | emit_readword(&pcaddr, 0); | |
3395 | emit_addimm(HOST_CCREG,2,HOST_CCREG); | |
048fcced | 3396 | emit_far_call(ndrc_get_addr_ht); |
630b122b | 3397 | emit_jmpreg(0); |
3398 | set_jump_target(jaddr, out); | |
3399 | } | |
3400 | emit_loadreg(dops[i].rs1,s); | |
3401 | } | |
3402 | else | |
3403 | { | |
3404 | assert(dops[i].opcode2==0x10); | |
3405 | //if((source[i]&0x3f)==0x10) // RFE | |
3406 | { | |
3407 | emit_readword(&Status,0); | |
3408 | emit_andimm(0,0x3c,1); | |
3409 | emit_andimm(0,~0xf,0); | |
3410 | emit_orrshr_imm(1,2,0); | |
3411 | emit_writeword(0,&Status); | |
3412 | } | |
3413 | } | |
3414 | } | |
3415 | ||
3416 | static void cop1_unusable(int i, const struct regstat *i_regs) | |
3417 | { | |
3418 | // XXX: should just just do the exception instead | |
3419 | //if(!cop1_usable) | |
3420 | { | |
3421 | void *jaddr=out; | |
3422 | emit_jmp(0); | |
3423 | add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0); | |
3424 | } | |
3425 | } | |
3426 | ||
3427 | static void cop1_assemble(int i, const struct regstat *i_regs) | |
57871462 | 3428 | { |
3d624f89 | 3429 | cop1_unusable(i, i_regs); |
57871462 | 3430 | } |
3431 | ||
630b122b | 3432 | static void c1ls_assemble(int i, const struct regstat *i_regs) |
3433 | { | |
3434 | cop1_unusable(i, i_regs); | |
3435 | } | |
3436 | ||
3437 | // FP_STUB | |
3438 | static void do_cop1stub(int n) | |
3439 | { | |
3440 | literal_pool(256); | |
3441 | assem_debug("do_cop1stub %x\n",start+stubs[n].a*4); | |
3442 | set_jump_target(stubs[n].addr, out); | |
3443 | int i=stubs[n].a; | |
3444 | // int rs=stubs[n].b; | |
3445 | struct regstat *i_regs=(struct regstat *)stubs[n].c; | |
3446 | int ds=stubs[n].d; | |
3447 | if(!ds) { | |
3448 | load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i); | |
3449 | //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs); | |
3450 | } | |
3451 | //else {printf("fp exception in delay slot\n");} | |
3452 | wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty); | |
3453 | if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG); | |
3454 | emit_movimm(start+(i-ds)*4,EAX); // Get PC | |
3455 | emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle... | |
3456 | emit_far_jump(ds?fp_exception_ds:fp_exception); | |
3457 | } | |
3458 | ||
3459 | static int cop2_is_stalling_op(int i, int *cycles) | |
3460 | { | |
3461 | if (dops[i].opcode == 0x3a) { // SWC2 | |
3462 | *cycles = 0; | |
3463 | return 1; | |
3464 | } | |
3465 | if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2 | |
3466 | *cycles = 0; | |
3467 | return 1; | |
3468 | } | |
3469 | if (dops[i].itype == C2OP) { | |
3470 | *cycles = gte_cycletab[source[i] & 0x3f]; | |
3471 | return 1; | |
3472 | } | |
3473 | // ... what about MTC2/CTC2/LWC2? | |
3474 | return 0; | |
3475 | } | |
3476 | ||
3477 | #if 0 | |
3478 | static void log_gte_stall(int stall, u_int cycle) | |
3479 | { | |
3480 | if ((u_int)stall <= 44) | |
3481 | printf("x stall %2d %u\n", stall, cycle + last_count); | |
3482 | } | |
3483 | ||
3484 | static void emit_log_gte_stall(int i, int stall, u_int reglist) | |
3485 | { | |
3486 | save_regs(reglist); | |
3487 | if (stall > 0) | |
3488 | emit_movimm(stall, 0); | |
3489 | else | |
3490 | emit_mov(HOST_TEMPREG, 0); | |
3491 | emit_addimm(HOST_CCREG, ccadj[i], 1); | |
3492 | emit_far_call(log_gte_stall); | |
3493 | restore_regs(reglist); | |
3494 | } | |
3495 | #endif | |
3496 | ||
3497 | static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist) | |
3498 | { | |
3499 | int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed; | |
3500 | int rtmp = reglist_find_free(reglist); | |
3501 | ||
3502 | if (HACK_ENABLED(NDHACK_NO_STALLS)) | |
3503 | return; | |
3504 | if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) { | |
3505 | // happens occasionally... cc evicted? Don't bother then | |
3506 | //printf("no cc %08x\n", start + i*4); | |
3507 | return; | |
3508 | } | |
3509 | if (!dops[i].bt) { | |
3510 | for (j = i - 1; j >= 0; j--) { | |
3511 | //if (dops[j].is_ds) break; | |
3512 | if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt) | |
3513 | break; | |
3514 | if (j > 0 && ccadj[j - 1] > ccadj[j]) | |
3515 | break; | |
3516 | } | |
3517 | j = max(j, 0); | |
3518 | } | |
3519 | cycles_passed = ccadj[i] - ccadj[j]; | |
3520 | if (other_gte_op_cycles >= 0) | |
3521 | stall = other_gte_op_cycles - cycles_passed; | |
3522 | else if (cycles_passed >= 44) | |
3523 | stall = 0; // can't stall | |
3524 | if (stall == -MAXBLOCK && rtmp >= 0) { | |
3525 | // unknown stall, do the expensive runtime check | |
3526 | assem_debug("; cop2_do_stall_check\n"); | |
3527 | #if 0 // too slow | |
3528 | save_regs(reglist); | |
3529 | emit_movimm(gte_cycletab[op], 0); | |
3530 | emit_addimm(HOST_CCREG, ccadj[i], 1); | |
3531 | emit_far_call(call_gteStall); | |
3532 | restore_regs(reglist); | |
3533 | #else | |
3534 | host_tempreg_acquire(); | |
3535 | emit_readword(&psxRegs.gteBusyCycle, rtmp); | |
3536 | emit_addimm(rtmp, -ccadj[i], rtmp); | |
3537 | emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG); | |
3538 | emit_cmpimm(HOST_TEMPREG, 44); | |
3539 | emit_cmovb_reg(rtmp, HOST_CCREG); | |
3540 | //emit_log_gte_stall(i, 0, reglist); | |
3541 | host_tempreg_release(); | |
3542 | #endif | |
3543 | } | |
3544 | else if (stall > 0) { | |
3545 | //emit_log_gte_stall(i, stall, reglist); | |
3546 | emit_addimm(HOST_CCREG, stall, HOST_CCREG); | |
3547 | } | |
3548 | ||
3549 | // save gteBusyCycle, if needed | |
3550 | if (gte_cycletab[op] == 0) | |
3551 | return; | |
3552 | other_gte_op_cycles = -1; | |
3553 | for (j = i + 1; j < slen; j++) { | |
3554 | if (cop2_is_stalling_op(j, &other_gte_op_cycles)) | |
3555 | break; | |
3556 | if (dops[j].is_jump) { | |
3557 | // check ds | |
3558 | if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles)) | |
3559 | j++; | |
3560 | break; | |
3561 | } | |
3562 | } | |
3563 | if (other_gte_op_cycles >= 0) | |
3564 | // will handle stall when assembling that op | |
3565 | return; | |
3566 | cycles_passed = ccadj[min(j, slen -1)] - ccadj[i]; | |
3567 | if (cycles_passed >= 44) | |
3568 | return; | |
3569 | assem_debug("; save gteBusyCycle\n"); | |
3570 | host_tempreg_acquire(); | |
3571 | #if 0 | |
3572 | emit_readword(&last_count, HOST_TEMPREG); | |
3573 | emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG); | |
3574 | emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG); | |
3575 | emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG); | |
3576 | emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle); | |
3577 | #else | |
3578 | emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG); | |
3579 | emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle); | |
3580 | #endif | |
3581 | host_tempreg_release(); | |
3582 | } | |
3583 | ||
3584 | static int is_mflohi(int i) | |
3585 | { | |
3586 | return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG)); | |
3587 | } | |
3588 | ||
3589 | static int check_multdiv(int i, int *cycles) | |
3590 | { | |
3591 | if (dops[i].itype != MULTDIV) | |
3592 | return 0; | |
3593 | if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U) | |
3594 | *cycles = 11; // approx from 7 11 14 | |
3595 | else | |
3596 | *cycles = 37; | |
3597 | return 1; | |
3598 | } | |
3599 | ||
3600 | static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_) | |
3601 | { | |
3602 | int j, found = 0, c = 0; | |
3603 | if (HACK_ENABLED(NDHACK_NO_STALLS)) | |
3604 | return; | |
3605 | if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) { | |
3606 | // happens occasionally... cc evicted? Don't bother then | |
3607 | return; | |
3608 | } | |
3609 | for (j = i + 1; j < slen; j++) { | |
3610 | if (dops[j].bt) | |
3611 | break; | |
3612 | if ((found = is_mflohi(j))) | |
3613 | break; | |
3614 | if (dops[j].is_jump) { | |
3615 | // check ds | |
3616 | if (j + 1 < slen && (found = is_mflohi(j + 1))) | |
3617 | j++; | |
3618 | break; | |
3619 | } | |
3620 | } | |
3621 | if (found) | |
3622 | // handle all in multdiv_do_stall() | |
3623 | return; | |
3624 | check_multdiv(i, &c); | |
3625 | assert(c > 0); | |
3626 | assem_debug("; muldiv prepare stall %d\n", c); | |
3627 | host_tempreg_acquire(); | |
3628 | emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG); | |
3629 | emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle); | |
3630 | host_tempreg_release(); | |
3631 | } | |
3632 | ||
3633 | static void multdiv_do_stall(int i, const struct regstat *i_regs) | |
3634 | { | |
3635 | int j, known_cycles = 0; | |
3636 | u_int reglist = get_host_reglist(i_regs->regmap); | |
91af94f0 | 3637 | int rtmp = get_reg_temp(i_regs->regmap); |
630b122b | 3638 | if (rtmp < 0) |
3639 | rtmp = reglist_find_free(reglist); | |
3640 | if (HACK_ENABLED(NDHACK_NO_STALLS)) | |
3641 | return; | |
3642 | if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) { | |
3643 | // happens occasionally... cc evicted? Don't bother then | |
3644 | //printf("no cc/rtmp %08x\n", start + i*4); | |
3645 | return; | |
3646 | } | |
3647 | if (!dops[i].bt) { | |
3648 | for (j = i - 1; j >= 0; j--) { | |
3649 | if (dops[j].is_ds) break; | |
3650 | if (check_multdiv(j, &known_cycles)) | |
3651 | break; | |
3652 | if (is_mflohi(j)) | |
3653 | // already handled by this op | |
3654 | return; | |
3655 | if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j])) | |
3656 | break; | |
3657 | } | |
3658 | j = max(j, 0); | |
3659 | } | |
3660 | if (known_cycles > 0) { | |
3661 | known_cycles -= ccadj[i] - ccadj[j]; | |
3662 | assem_debug("; muldiv stall resolved %d\n", known_cycles); | |
3663 | if (known_cycles > 0) | |
3664 | emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG); | |
3665 | return; | |
3666 | } | |
3667 | assem_debug("; muldiv stall unresolved\n"); | |
3668 | host_tempreg_acquire(); | |
3669 | emit_readword(&psxRegs.muldivBusyCycle, rtmp); | |
3670 | emit_addimm(rtmp, -ccadj[i], rtmp); | |
3671 | emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG); | |
3672 | emit_cmpimm(HOST_TEMPREG, 37); | |
3673 | emit_cmovb_reg(rtmp, HOST_CCREG); | |
3674 | //emit_log_gte_stall(i, 0, reglist); | |
3675 | host_tempreg_release(); | |
3676 | } | |
3677 | ||
3678 | static void cop2_get_dreg(u_int copr,signed char tl,signed char temp) | |
3679 | { | |
3680 | switch (copr) { | |
3681 | case 1: | |
3682 | case 3: | |
3683 | case 5: | |
3684 | case 8: | |
3685 | case 9: | |
3686 | case 10: | |
3687 | case 11: | |
3688 | emit_readword(®_cop2d[copr],tl); | |
3689 | emit_signextend16(tl,tl); | |
3690 | emit_writeword(tl,®_cop2d[copr]); // hmh | |
3691 | break; | |
3692 | case 7: | |
3693 | case 16: | |
3694 | case 17: | |
3695 | case 18: | |
3696 | case 19: | |
3697 | emit_readword(®_cop2d[copr],tl); | |
3698 | emit_andimm(tl,0xffff,tl); | |
3699 | emit_writeword(tl,®_cop2d[copr]); | |
3700 | break; | |
3701 | case 15: | |
3702 | emit_readword(®_cop2d[14],tl); // SXY2 | |
3703 | emit_writeword(tl,®_cop2d[copr]); | |
3704 | break; | |
3705 | case 28: | |
3706 | case 29: | |
3707 | c2op_mfc2_29_assemble(tl,temp); | |
3708 | break; | |
3709 | default: | |
3710 | emit_readword(®_cop2d[copr],tl); | |
3711 | break; | |
3712 | } | |
3713 | } | |
3714 | ||
3715 | static void cop2_put_dreg(u_int copr,signed char sl,signed char temp) | |
3716 | { | |
3717 | switch (copr) { | |
3718 | case 15: | |
3719 | emit_readword(®_cop2d[13],temp); // SXY1 | |
3720 | emit_writeword(sl,®_cop2d[copr]); | |
3721 | emit_writeword(temp,®_cop2d[12]); // SXY0 | |
3722 | emit_readword(®_cop2d[14],temp); // SXY2 | |
3723 | emit_writeword(sl,®_cop2d[14]); | |
3724 | emit_writeword(temp,®_cop2d[13]); // SXY1 | |
3725 | break; | |
3726 | case 28: | |
3727 | emit_andimm(sl,0x001f,temp); | |
3728 | emit_shlimm(temp,7,temp); | |
3729 | emit_writeword(temp,®_cop2d[9]); | |
3730 | emit_andimm(sl,0x03e0,temp); | |
3731 | emit_shlimm(temp,2,temp); | |
3732 | emit_writeword(temp,®_cop2d[10]); | |
3733 | emit_andimm(sl,0x7c00,temp); | |
3734 | emit_shrimm(temp,3,temp); | |
3735 | emit_writeword(temp,®_cop2d[11]); | |
3736 | emit_writeword(sl,®_cop2d[28]); | |
3737 | break; | |
3738 | case 30: | |
3739 | emit_xorsar_imm(sl,sl,31,temp); | |
3740 | #if defined(HAVE_ARMV5) || defined(__aarch64__) | |
3741 | emit_clz(temp,temp); | |
3742 | #else | |
3743 | emit_movs(temp,HOST_TEMPREG); | |
3744 | emit_movimm(0,temp); | |
3745 | emit_jeq((int)out+4*4); | |
3746 | emit_addpl_imm(temp,1,temp); | |
3747 | emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG); | |
3748 | emit_jns((int)out-2*4); | |
3749 | #endif | |
3750 | emit_writeword(sl,®_cop2d[30]); | |
3751 | emit_writeword(temp,®_cop2d[31]); | |
3752 | break; | |
3753 | case 31: | |
3754 | break; | |
3755 | default: | |
3756 | emit_writeword(sl,®_cop2d[copr]); | |
3757 | break; | |
3758 | } | |
3759 | } | |
3760 | ||
3761 | static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_) | |
b9b61529 | 3762 | { |
3763 | int s,tl; | |
3764 | int ar; | |
3765 | int offset; | |
1fd1aceb | 3766 | int memtarget=0,c=0; |
630b122b | 3767 | void *jaddr2=NULL; |
3768 | enum stub_type type; | |
b9b61529 | 3769 | int agr=AGEN1+(i&1); |
630b122b | 3770 | int offset_reg = -1; |
3771 | int fastio_reg_override = -1; | |
3772 | u_int reglist=get_host_reglist(i_regs->regmap); | |
b9b61529 | 3773 | u_int copr=(source[i]>>16)&0x1f; |
630b122b | 3774 | s=get_reg(i_regs->regmap,dops[i].rs1); |
b9b61529 | 3775 | tl=get_reg(i_regs->regmap,FTEMP); |
3776 | offset=imm[i]; | |
630b122b | 3777 | assert(dops[i].rs1>0); |
b9b61529 | 3778 | assert(tl>=0); |
b9b61529 | 3779 | |
b9b61529 | 3780 | if(i_regs->regmap[HOST_CCREG]==CCREG) |
3781 | reglist&=~(1<<HOST_CCREG); | |
3782 | ||
3783 | // get the address | |
630b122b | 3784 | if (dops[i].opcode==0x3a) { // SWC2 |
b9b61529 | 3785 | ar=get_reg(i_regs->regmap,agr); |
91af94f0 | 3786 | if(ar<0) ar=get_reg_temp(i_regs->regmap); |
b9b61529 | 3787 | reglist|=1<<ar; |
3788 | } else { // LWC2 | |
3789 | ar=tl; | |
3790 | } | |
1fd1aceb | 3791 | if(s>=0) c=(i_regs->wasconst>>s)&1; |
3792 | memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE); | |
b9b61529 | 3793 | if (!offset&&!c&&s>=0) ar=s; |
3794 | assert(ar>=0); | |
3795 | ||
630b122b | 3796 | cop2_do_stall_check(0, i, i_regs, reglist); |
3797 | ||
3798 | if (dops[i].opcode==0x3a) { // SWC2 | |
3799 | cop2_get_dreg(copr,tl,-1); | |
1fd1aceb | 3800 | type=STOREW_STUB; |
b9b61529 | 3801 | } |
1fd1aceb | 3802 | else |
b9b61529 | 3803 | type=LOADW_STUB; |
1fd1aceb | 3804 | |
3805 | if(c&&!memtarget) { | |
630b122b | 3806 | jaddr2=out; |
1fd1aceb | 3807 | emit_jmp(0); // inline_readstub/inline_writestub? |
b9b61529 | 3808 | } |
1fd1aceb | 3809 | else { |
3810 | if(!c) { | |
630b122b | 3811 | jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar, |
3812 | &offset_reg, &fastio_reg_override); | |
3813 | } | |
3814 | else if (ram_offset && memtarget) { | |
3815 | offset_reg = get_ro_reg(i_regs, 0); | |
3816 | } | |
3817 | switch (dops[i].opcode) { | |
3818 | case 0x32: { // LWC2 | |
3819 | int a = ar; | |
3820 | if (fastio_reg_override >= 0) | |
3821 | a = fastio_reg_override; | |
3822 | do_load_word(a, tl, offset_reg); | |
3823 | break; | |
1fd1aceb | 3824 | } |
630b122b | 3825 | case 0x3a: { // SWC2 |
1fd1aceb | 3826 | #ifdef DESTRUCTIVE_SHIFT |
3827 | if(!offset&&!c&&s>=0) emit_mov(s,ar); | |
3828 | #endif | |
630b122b | 3829 | int a = ar; |
3830 | if (fastio_reg_override >= 0) | |
3831 | a = fastio_reg_override; | |
3832 | do_store_word(a, 0, tl, offset_reg, 1); | |
3833 | break; | |
3834 | } | |
3835 | default: | |
3836 | assert(0); | |
1fd1aceb | 3837 | } |
b9b61529 | 3838 | } |
630b122b | 3839 | if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) |
3840 | host_tempreg_release(); | |
b9b61529 | 3841 | if(jaddr2) |
630b122b | 3842 | add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist); |
3843 | if(dops[i].opcode==0x3a) // SWC2 | |
3844 | if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) { | |
b9b61529 | 3845 | #if defined(HOST_IMM8) |
3846 | int ir=get_reg(i_regs->regmap,INVCP); | |
3847 | assert(ir>=0); | |
3848 | emit_cmpmem_indexedsr12_reg(ir,ar,1); | |
3849 | #else | |
630b122b | 3850 | emit_cmpmem_indexedsr12_imm(invalid_code,ar,1); |
b9b61529 | 3851 | #endif |
b9e27215 | 3852 | #ifdef INVALIDATE_USE_COND_CALL |
0bbd1454 | 3853 | emit_callne(invalidate_addr_reg[ar]); |
3854 | #else | |
630b122b | 3855 | void *jaddr3 = out; |
b9b61529 | 3856 | emit_jne(0); |
630b122b | 3857 | add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0); |
0bbd1454 | 3858 | #endif |
b9b61529 | 3859 | } |
630b122b | 3860 | if (dops[i].opcode==0x32) { // LWC2 |
3861 | host_tempreg_acquire(); | |
3862 | cop2_put_dreg(copr,tl,HOST_TEMPREG); | |
3863 | host_tempreg_release(); | |
3864 | } | |
3865 | } | |
3866 | ||
3867 | static void cop2_assemble(int i, const struct regstat *i_regs) | |
3868 | { | |
3869 | u_int copr = (source[i]>>11) & 0x1f; | |
91af94f0 | 3870 | signed char temp = get_reg_temp(i_regs->regmap); |
630b122b | 3871 | |
3872 | if (!HACK_ENABLED(NDHACK_NO_STALLS)) { | |
3873 | u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1); | |
3874 | if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2 | |
3875 | signed char tl = get_reg(i_regs->regmap, dops[i].rt1); | |
3876 | reglist = reglist_exclude(reglist, tl, -1); | |
3877 | } | |
3878 | cop2_do_stall_check(0, i, i_regs, reglist); | |
3879 | } | |
3880 | if (dops[i].opcode2==0) { // MFC2 | |
3881 | signed char tl=get_reg(i_regs->regmap,dops[i].rt1); | |
3882 | if(tl>=0&&dops[i].rt1!=0) | |
3883 | cop2_get_dreg(copr,tl,temp); | |
3884 | } | |
3885 | else if (dops[i].opcode2==4) { // MTC2 | |
3886 | signed char sl=get_reg(i_regs->regmap,dops[i].rs1); | |
3887 | cop2_put_dreg(copr,sl,temp); | |
3888 | } | |
3889 | else if (dops[i].opcode2==2) // CFC2 | |
3890 | { | |
3891 | signed char tl=get_reg(i_regs->regmap,dops[i].rt1); | |
3892 | if(tl>=0&&dops[i].rt1!=0) | |
3893 | emit_readword(®_cop2c[copr],tl); | |
b9b61529 | 3894 | } |
630b122b | 3895 | else if (dops[i].opcode2==6) // CTC2 |
3896 | { | |
3897 | signed char sl=get_reg(i_regs->regmap,dops[i].rs1); | |
3898 | switch(copr) { | |
3899 | case 4: | |
3900 | case 12: | |
3901 | case 20: | |
3902 | case 26: | |
3903 | case 27: | |
3904 | case 29: | |
3905 | case 30: | |
3906 | emit_signextend16(sl,temp); | |
3907 | break; | |
3908 | case 31: | |
3909 | c2op_ctc2_31_assemble(sl,temp); | |
3910 | break; | |
3911 | default: | |
3912 | temp=sl; | |
3913 | break; | |
3914 | } | |
3915 | emit_writeword(temp,®_cop2c[copr]); | |
3916 | assert(sl>=0); | |
3917 | } | |
3918 | } | |
3919 | ||
3920 | static void do_unalignedwritestub(int n) | |
3921 | { | |
3922 | assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4); | |
3923 | literal_pool(256); | |
3924 | set_jump_target(stubs[n].addr, out); | |
3925 | ||
3926 | int i=stubs[n].a; | |
3927 | struct regstat *i_regs=(struct regstat *)stubs[n].c; | |
3928 | int addr=stubs[n].b; | |
3929 | u_int reglist=stubs[n].e; | |
3930 | signed char *i_regmap=i_regs->regmap; | |
3931 | int temp2=get_reg(i_regmap,FTEMP); | |
3932 | int rt; | |
3933 | rt=get_reg(i_regmap,dops[i].rs2); | |
3934 | assert(rt>=0); | |
3935 | assert(addr>=0); | |
3936 | assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented | |
3937 | reglist|=(1<<addr); | |
3938 | reglist&=~(1<<temp2); | |
3939 | ||
3940 | // don't bother with it and call write handler | |
3941 | save_regs(reglist); | |
3942 | pass_args(addr,rt); | |
3943 | int cc=get_reg(i_regmap,CCREG); | |
3944 | if(cc<0) | |
3945 | emit_loadreg(CCREG,2); | |
3946 | emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2); | |
3947 | emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr)); | |
3948 | emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc); | |
3949 | if(cc<0) | |
3950 | emit_storereg(CCREG,2); | |
3951 | restore_regs(reglist); | |
3952 | emit_jmp(stubs[n].retaddr); // return address | |
b9b61529 | 3953 | } |
3954 | ||
57871462 | 3955 | #ifndef multdiv_assemble |
3956 | void multdiv_assemble(int i,struct regstat *i_regs) | |
3957 | { | |
3958 | printf("Need multdiv_assemble for this architecture.\n"); | |
630b122b | 3959 | abort(); |
57871462 | 3960 | } |
3961 | #endif | |
3962 | ||
630b122b | 3963 | static void mov_assemble(int i, const struct regstat *i_regs) |
57871462 | 3964 | { |
630b122b | 3965 | //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO |
3966 | //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO | |
3967 | if(dops[i].rt1) { | |
3968 | signed char sl,tl; | |
3969 | tl=get_reg(i_regs->regmap,dops[i].rt1); | |
57871462 | 3970 | //assert(tl>=0); |
3971 | if(tl>=0) { | |
630b122b | 3972 | sl=get_reg(i_regs->regmap,dops[i].rs1); |
57871462 | 3973 | if(sl>=0) emit_mov(sl,tl); |
630b122b | 3974 | else emit_loadreg(dops[i].rs1,tl); |
57871462 | 3975 | } |
3976 | } | |
630b122b | 3977 | if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO |
3978 | multdiv_do_stall(i, i_regs); | |
57871462 | 3979 | } |
3980 | ||
630b122b | 3981 | // call interpreter, exception handler, things that change pc/regs/cycles ... |
3982 | static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func) | |
57871462 | 3983 | { |
630b122b | 3984 | signed char ccreg=get_reg(i_regs->regmap,CCREG); |
3985 | assert(ccreg==HOST_CCREG); | |
3986 | assert(!is_delayslot); | |
3987 | (void)ccreg; | |
3988 | ||
3989 | emit_movimm(pc,3); // Get PC | |
3990 | emit_readword(&last_count,2); | |
3991 | emit_writeword(3,&psxRegs.pc); | |
3992 | emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG); | |
3993 | emit_add(2,HOST_CCREG,2); | |
3994 | emit_writeword(2,&psxRegs.cycle); | |
3995 | emit_far_call(func); | |
3996 | emit_far_jump(jump_to_new_pc); | |
57871462 | 3997 | } |
57871462 | 3998 | |
630b122b | 3999 | static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 | 4000 | { |
467357cc | 4001 | // 'break' tends to be littered around to catch things like |
4002 | // division by 0 and is almost never executed, so don't emit much code here | |
4003 | void *func = (dops[i].opcode2 == 0x0C) | |
4004 | ? (is_delayslot ? jump_syscall_ds : jump_syscall) | |
4005 | : (is_delayslot ? jump_break_ds : jump_break); | |
fdf33825 | 4006 | assert(get_reg(i_regs->regmap, CCREG) == HOST_CCREG); |
467357cc | 4007 | emit_movimm(start + i*4, 2); // pc |
4008 | emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG); | |
4009 | emit_far_jump(func); | |
57871462 | 4010 | } |
57871462 | 4011 | |
630b122b | 4012 | static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_) |
57871462 | 4013 | { |
630b122b | 4014 | void *hlefunc = psxNULL; |
4015 | uint32_t hleCode = source[i] & 0x03ffffff; | |
4016 | if (hleCode < ARRAY_SIZE(psxHLEt)) | |
4017 | hlefunc = psxHLEt[hleCode]; | |
4018 | ||
4019 | call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc); | |
7139f3c8 | 4020 | } |
4021 | ||
630b122b | 4022 | static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_) |
7139f3c8 | 4023 | { |
630b122b | 4024 | call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI); |
57871462 | 4025 | } |
4026 | ||
630b122b | 4027 | static void speculate_mov(int rs,int rt) |
1e973cb0 | 4028 | { |
630b122b | 4029 | if(rt!=0) { |
4030 | smrv_strong_next|=1<<rt; | |
4031 | smrv[rt]=smrv[rs]; | |
4032 | } | |
1e973cb0 | 4033 | } |
4034 | ||
630b122b | 4035 | static void speculate_mov_weak(int rs,int rt) |
57871462 | 4036 | { |
630b122b | 4037 | if(rt!=0) { |
4038 | smrv_weak_next|=1<<rt; | |
4039 | smrv[rt]=smrv[rs]; | |
4040 | } | |
4041 | } | |
4042 | ||
4043 | static void speculate_register_values(int i) | |
4044 | { | |
4045 | if(i==0) { | |
4046 | memcpy(smrv,psxRegs.GPR.r,sizeof(smrv)); | |
4047 | // gp,sp are likely to stay the same throughout the block | |
4048 | smrv_strong_next=(1<<28)|(1<<29)|(1<<30); | |
4049 | smrv_weak_next=~smrv_strong_next; | |
4050 | //printf(" llr %08x\n", smrv[4]); | |
4051 | } | |
4052 | smrv_strong=smrv_strong_next; | |
4053 | smrv_weak=smrv_weak_next; | |
4054 | switch(dops[i].itype) { | |
4055 | case ALU: | |
4056 | if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1); | |
4057 | else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1); | |
4058 | else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1); | |
4059 | else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1); | |
4060 | else { | |
4061 | smrv_strong_next&=~(1<<dops[i].rt1); | |
4062 | smrv_weak_next&=~(1<<dops[i].rt1); | |
4063 | } | |
4064 | break; | |
4065 | case SHIFTIMM: | |
4066 | smrv_strong_next&=~(1<<dops[i].rt1); | |
4067 | smrv_weak_next&=~(1<<dops[i].rt1); | |
4068 | // fallthrough | |
4069 | case IMM16: | |
4070 | if(dops[i].rt1&&is_const(®s[i],dops[i].rt1)) { | |
4071 | int value,hr=get_reg(regs[i].regmap,dops[i].rt1); | |
4072 | if(hr>=0) { | |
4073 | if(get_final_value(hr,i,&value)) | |
4074 | smrv[dops[i].rt1]=value; | |
4075 | else smrv[dops[i].rt1]=constmap[i][hr]; | |
4076 | smrv_strong_next|=1<<dops[i].rt1; | |
4077 | } | |
4078 | } | |
4079 | else { | |
4080 | if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1); | |
4081 | else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1); | |
4082 | } | |
4083 | break; | |
4084 | case LOAD: | |
4085 | if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) { | |
4086 | // special case for BIOS | |
4087 | smrv[dops[i].rt1]=0xa0000000; | |
4088 | smrv_strong_next|=1<<dops[i].rt1; | |
4089 | break; | |
4090 | } | |
4091 | // fallthrough | |
4092 | case SHIFT: | |
4093 | case LOADLR: | |
4094 | case MOV: | |
4095 | smrv_strong_next&=~(1<<dops[i].rt1); | |
4096 | smrv_weak_next&=~(1<<dops[i].rt1); | |
4097 | break; | |
4098 | case COP0: | |
4099 | case COP2: | |
4100 | if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC | |
4101 | smrv_strong_next&=~(1<<dops[i].rt1); | |
4102 | smrv_weak_next&=~(1<<dops[i].rt1); | |
4103 | } | |
4104 | break; | |
4105 | case C2LS: | |
4106 | if (dops[i].opcode==0x32) { // LWC2 | |
4107 | smrv_strong_next&=~(1<<dops[i].rt1); | |
4108 | smrv_weak_next&=~(1<<dops[i].rt1); | |
4109 | } | |
4110 | break; | |
4111 | } | |
4112 | #if 0 | |
4113 | int r=4; | |
4114 | printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4, | |
4115 | ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst); | |
4116 | #endif | |
4117 | } | |
4118 | ||
4119 | static void ujump_assemble(int i, const struct regstat *i_regs); | |
4120 | static void rjump_assemble(int i, const struct regstat *i_regs); | |
4121 | static void cjump_assemble(int i, const struct regstat *i_regs); | |
4122 | static void sjump_assemble(int i, const struct regstat *i_regs); | |
630b122b | 4123 | |
4124 | static int assemble(int i, const struct regstat *i_regs, int ccadj_) | |
4125 | { | |
4126 | int ds = 0; | |
4127 | switch (dops[i].itype) { | |
57871462 | 4128 | case ALU: |
630b122b | 4129 | alu_assemble(i, i_regs); |
4130 | break; | |
57871462 | 4131 | case IMM16: |
630b122b | 4132 | imm16_assemble(i, i_regs); |
4133 | break; | |
57871462 | 4134 | case SHIFT: |
630b122b | 4135 | shift_assemble(i, i_regs); |
4136 | break; | |
57871462 | 4137 | case SHIFTIMM: |
630b122b | 4138 | shiftimm_assemble(i, i_regs); |
4139 | break; | |
57871462 | 4140 | case LOAD: |
630b122b | 4141 | load_assemble(i, i_regs, ccadj_); |
4142 | break; | |
57871462 | 4143 | case LOADLR: |
630b122b | 4144 | loadlr_assemble(i, i_regs, ccadj_); |
4145 | break; | |
57871462 | 4146 | case STORE: |
630b122b | 4147 | store_assemble(i, i_regs, ccadj_); |
4148 | break; | |
57871462 | 4149 | case STORELR: |
630b122b | 4150 | storelr_assemble(i, i_regs, ccadj_); |
4151 | break; | |
57871462 | 4152 | case COP0: |
630b122b | 4153 | cop0_assemble(i, i_regs, ccadj_); |
4154 | break; | |
57871462 | 4155 | case COP1: |
630b122b | 4156 | cop1_assemble(i, i_regs); |
4157 | break; | |
57871462 | 4158 | case C1LS: |
630b122b | 4159 | c1ls_assemble(i, i_regs); |
4160 | break; | |
b9b61529 | 4161 | case COP2: |
630b122b | 4162 | cop2_assemble(i, i_regs); |
4163 | break; | |
b9b61529 | 4164 | case C2LS: |
630b122b | 4165 | c2ls_assemble(i, i_regs, ccadj_); |
4166 | break; | |
b9b61529 | 4167 | case C2OP: |
630b122b | 4168 | c2op_assemble(i, i_regs); |
4169 | break; | |
57871462 | 4170 | case MULTDIV: |
630b122b | 4171 | multdiv_assemble(i, i_regs); |
4172 | multdiv_prepare_stall(i, i_regs, ccadj_); | |
4173 | break; | |
57871462 | 4174 | case MOV: |
630b122b | 4175 | mov_assemble(i, i_regs); |
4176 | break; | |
4177 | case SYSCALL: | |
4178 | syscall_assemble(i, i_regs, ccadj_); | |
4179 | break; | |
4180 | case HLECALL: | |
4181 | hlecall_assemble(i, i_regs, ccadj_); | |
4182 | break; | |
4183 | case INTCALL: | |
4184 | intcall_assemble(i, i_regs, ccadj_); | |
4185 | break; | |
4186 | case UJUMP: | |
4187 | ujump_assemble(i, i_regs); | |
4188 | ds = 1; | |
4189 | break; | |
4190 | case RJUMP: | |
4191 | rjump_assemble(i, i_regs); | |
4192 | ds = 1; | |
4193 | break; | |
4194 | case CJUMP: | |
4195 | cjump_assemble(i, i_regs); | |
4196 | ds = 1; | |
4197 | break; | |
4198 | case SJUMP: | |
4199 | sjump_assemble(i, i_regs); | |
4200 | ds = 1; | |
4201 | break; | |
630b122b | 4202 | case NOP: |
4203 | case OTHER: | |
4204 | case NI: | |
4205 | // not handled, just skip | |
4206 | break; | |
4207 | default: | |
4208 | assert(0); | |
4209 | } | |
4210 | return ds; | |
4211 | } | |
4212 | ||
4213 | static void ds_assemble(int i, const struct regstat *i_regs) | |
4214 | { | |
4215 | speculate_register_values(i); | |
4216 | is_delayslot = 1; | |
4217 | switch (dops[i].itype) { | |
57871462 | 4218 | case SYSCALL: |
7139f3c8 | 4219 | case HLECALL: |
1e973cb0 | 4220 | case INTCALL: |
57871462 | 4221 | case UJUMP: |
4222 | case RJUMP: | |
4223 | case CJUMP: | |
4224 | case SJUMP: | |
c43b5311 | 4225 | SysPrintf("Jump in the delay slot. This is probably a bug.\n"); |
630b122b | 4226 | break; |
4227 | default: | |
4228 | assemble(i, i_regs, ccadj[i]); | |
57871462 | 4229 | } |
630b122b | 4230 | is_delayslot = 0; |
57871462 | 4231 | } |
4232 | ||
4233 | // Is the branch target a valid internal jump? | |
630b122b | 4234 | static int internal_branch(int addr) |
57871462 | 4235 | { |
4236 | if(addr&1) return 0; // Indirect (register) jump | |
4237 | if(addr>=start && addr<start+slen*4-4) | |
4238 | { | |
71e490c5 | 4239 | return 1; |
57871462 | 4240 | } |
4241 | return 0; | |
4242 | } | |
4243 | ||
630b122b | 4244 | static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u) |
57871462 | 4245 | { |
4246 | int hr; | |
4247 | for(hr=0;hr<HOST_REGS;hr++) { | |
4248 | if(hr!=EXCLUDE_REG) { | |
4249 | if(pre[hr]!=entry[hr]) { | |
4250 | if(pre[hr]>=0) { | |
4251 | if((dirty>>hr)&1) { | |
4252 | if(get_reg(entry,pre[hr])<0) { | |
630b122b | 4253 | assert(pre[hr]<64); |
4254 | if(!((u>>pre[hr])&1)) | |
4255 | emit_storereg(pre[hr],hr); | |
57871462 | 4256 | } |
4257 | } | |
4258 | } | |
4259 | } | |
4260 | } | |
4261 | } | |
4262 | // Move from one register to another (no writeback) | |
4263 | for(hr=0;hr<HOST_REGS;hr++) { | |
4264 | if(hr!=EXCLUDE_REG) { | |
4265 | if(pre[hr]!=entry[hr]) { | |
91af94f0 | 4266 | if(pre[hr]>=0&&pre[hr]<TEMPREG) { |
57871462 | 4267 | int nr; |
4268 | if((nr=get_reg(entry,pre[hr]))>=0) { | |
4269 | emit_mov(hr,nr); | |
4270 | } | |
4271 | } | |
4272 | } | |
4273 | } | |
4274 | } | |
4275 | } | |
57871462 | 4276 | |
4277 | // Load the specified registers | |
4278 | // This only loads the registers given as arguments because | |
4279 | // we don't want to load things that will be overwritten | |
e912c27d | 4280 | static inline void load_reg(signed char entry[], signed char regmap[], int rs) |
57871462 | 4281 | { |
e912c27d | 4282 | int hr = get_reg(regmap, rs); |
4283 | if (hr >= 0 && entry[hr] != regmap[hr]) | |
4284 | emit_loadreg(regmap[hr], hr); | |
4285 | } | |
4286 | ||
4287 | static void load_regs(signed char entry[], signed char regmap[], int rs1, int rs2) | |
4288 | { | |
4289 | load_reg(entry, regmap, rs1); | |
4290 | if (rs1 != rs2) | |
4291 | load_reg(entry, regmap, rs2); | |
57871462 | 4292 | } |
4293 | ||
4294 | // Load registers prior to the start of a loop | |
4295 | // so that they are not loaded within the loop | |
4296 | static void loop_preload(signed char pre[],signed char entry[]) | |
4297 | { | |
4298 | int hr; | |
e912c27d | 4299 | for (hr = 0; hr < HOST_REGS; hr++) { |
4300 | int r = entry[hr]; | |
4301 | if (r >= 0 && pre[hr] != r && get_reg(pre, r) < 0) { | |
4302 | assem_debug("loop preload:\n"); | |
4303 | if (r < TEMPREG) | |
4304 | emit_loadreg(r, hr); | |
57871462 | 4305 | } |
4306 | } | |
4307 | } | |
4308 | ||
4309 | // Generate address for load/store instruction | |
b9b61529 | 4310 | // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads |
94061aa5 | 4311 | static void address_generation(int i, const struct regstat *i_regs, signed char entry[]) |
57871462 | 4312 | { |
630b122b | 4313 | if (dops[i].is_load || dops[i].is_store) { |
5194fb95 | 4314 | int ra=-1; |
57871462 | 4315 | int agr=AGEN1+(i&1); |
630b122b | 4316 | if(dops[i].itype==LOAD) { |
4317 | ra=get_reg(i_regs->regmap,dops[i].rt1); | |
91af94f0 | 4318 | if(ra<0) ra=get_reg_temp(i_regs->regmap); |
535d208a | 4319 | assert(ra>=0); |
57871462 | 4320 | } |
630b122b | 4321 | if(dops[i].itype==LOADLR) { |
57871462 | 4322 | ra=get_reg(i_regs->regmap,FTEMP); |
4323 | } | |
630b122b | 4324 | if(dops[i].itype==STORE||dops[i].itype==STORELR) { |
57871462 | 4325 | ra=get_reg(i_regs->regmap,agr); |
91af94f0 | 4326 | if(ra<0) ra=get_reg_temp(i_regs->regmap); |
57871462 | 4327 | } |
630b122b | 4328 | if(dops[i].itype==C2LS) { |
4329 | if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2 | |
57871462 | 4330 | ra=get_reg(i_regs->regmap,FTEMP); |
1fd1aceb | 4331 | else { // SWC1/SDC1/SWC2/SDC2 |
57871462 | 4332 | ra=get_reg(i_regs->regmap,agr); |
91af94f0 | 4333 | if(ra<0) ra=get_reg_temp(i_regs->regmap); |
57871462 | 4334 | } |
4335 | } | |
630b122b | 4336 | int rs=get_reg(i_regs->regmap,dops[i].rs1); |
57871462 | 4337 | if(ra>=0) { |
4338 | int offset=imm[i]; | |
4339 | int c=(i_regs->wasconst>>rs)&1; | |
630b122b | 4340 | if(dops[i].rs1==0) { |
57871462 | 4341 | // Using r0 as a base address |
57871462 | 4342 | if(!entry||entry[ra]!=agr) { |
630b122b | 4343 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { |
57871462 | 4344 | emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR |
630b122b | 4345 | }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) { |
57871462 | 4346 | emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR |
4347 | }else{ | |
4348 | emit_movimm(offset,ra); | |
4349 | } | |
4350 | } // else did it in the previous cycle | |
4351 | } | |
4352 | else if(rs<0) { | |
630b122b | 4353 | if(!entry||entry[ra]!=dops[i].rs1) |
4354 | emit_loadreg(dops[i].rs1,ra); | |
4355 | //if(!entry||entry[ra]!=dops[i].rs1) | |
57871462 | 4356 | // printf("poor load scheduling!\n"); |
4357 | } | |
4358 | else if(c) { | |
630b122b | 4359 | if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) { |
57871462 | 4360 | if(!entry||entry[ra]!=agr) { |
630b122b | 4361 | if (dops[i].opcode==0x22||dops[i].opcode==0x26) { |
57871462 | 4362 | emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR |
630b122b | 4363 | }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) { |
57871462 | 4364 | emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR |
4365 | }else{ | |
57871462 | 4366 | emit_movimm(constmap[i][rs]+offset,ra); |
8575a877 | 4367 | regs[i].loadedconst|=1<<ra; |
57871462 | 4368 | } |
4369 | } // else did it in the previous cycle | |
4370 | } // else load_consts already did it | |
4371 | } | |
630b122b | 4372 | if(offset&&!c&&dops[i].rs1) { |
57871462 | 4373 | if(rs>=0) { |
4374 | emit_addimm(rs,offset,ra); | |
4375 | }else{ | |
4376 | emit_addimm(ra,offset,ra); | |
4377 | } | |
4378 | } | |
4379 | } | |
4380 | } | |
4381 | // Preload constants for next instruction | |
630b122b | 4382 | if (dops[i+1].is_load || dops[i+1].is_store) { |
57871462 | 4383 | int agr,ra; |
57871462 | 4384 | // Actual address |
4385 | agr=AGEN1+((i+1)&1); | |
4386 | ra=get_reg(i_regs->regmap,agr); | |
4387 | if(ra>=0) { | |
630b122b | 4388 | int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1); |
57871462 | 4389 | int offset=imm[i+1]; |
4390 | int c=(regs[i+1].wasconst>>rs)&1; | |
630b122b | 4391 | if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) { |
4392 | if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) { | |
57871462 | 4393 | emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR |
630b122b | 4394 | }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) { |
57871462 | 4395 | emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR |
4396 | }else{ | |
57871462 | 4397 | emit_movimm(constmap[i+1][rs]+offset,ra); |
8575a877 | 4398 | regs[i+1].loadedconst|=1<<ra; |
57871462 | 4399 | } |
4400 | } | |
630b122b | 4401 | else if(dops[i+1].rs1==0) { |
57871462 | 4402 | // Using r0 as a base address |
630b122b | 4403 | if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) { |
57871462 | 4404 | emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR |
630b122b | 4405 | }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) { |
57871462 | 4406 | emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR |
4407 | }else{ | |
4408 | emit_movimm(offset,ra); | |
4409 | } | |
4410 | } | |
4411 | } | |
4412 | } | |
4413 | } | |
4414 | ||
e2b5e7aa | 4415 | static int get_final_value(int hr, int i, int *value) |
57871462 | 4416 | { |
4417 | int reg=regs[i].regmap[hr]; | |
4418 | while(i<slen-1) { | |
4419 | if(regs[i+1].regmap[hr]!=reg) break; | |
4420 | if(!((regs[i+1].isconst>>hr)&1)) break; | |
630b122b | 4421 | if(dops[i+1].bt) break; |
57871462 | 4422 | i++; |
4423 | } | |
4424 | if(i<slen-1) { | |
630b122b | 4425 | if (dops[i].is_jump) { |
57871462 | 4426 | *value=constmap[i][hr]; |
4427 | return 1; | |
4428 | } | |
630b122b | 4429 | if(!dops[i+1].bt) { |
4430 | if (dops[i+1].is_jump) { | |
57871462 | 4431 | // Load in delay slot, out-of-order execution |
630b122b | 4432 | if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1)) |
57871462 | 4433 | { |
57871462 | 4434 | // Precompute load address |
4435 | *value=constmap[i][hr]+imm[i+2]; | |
4436 | return 1; | |
4437 | } | |
4438 | } | |
630b122b | 4439 | if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg) |
57871462 | 4440 | { |
57871462 | 4441 | // Precompute load address |
4442 | *value=constmap[i][hr]+imm[i+1]; | |
630b122b | 4443 | //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]); |
57871462 | 4444 | return 1; |
4445 | } | |
4446 | } | |
4447 | } | |
4448 | *value=constmap[i][hr]; | |
630b122b | 4449 | //printf("c=%lx\n",(long)constmap[i][hr]); |
57871462 | 4450 | if(i==slen-1) return 1; |
630b122b | 4451 | assert(reg < 64); |
4452 | return !((unneeded_reg[i+1]>>reg)&1); | |
57871462 | 4453 | } |
4454 | ||
4455 | // Load registers with known constants | |
630b122b | 4456 | static void load_consts(signed char pre[],signed char regmap[],int i) |
57871462 | 4457 | { |
8575a877 | 4458 | int hr,hr2; |
4459 | // propagate loaded constant flags | |
630b122b | 4460 | if(i==0||dops[i].bt) |
8575a877 | 4461 | regs[i].loadedconst=0; |
4462 | else { | |
4463 | for(hr=0;hr<HOST_REGS;hr++) { | |
4464 | if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr] | |
4465 | &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1)) | |
4466 | { | |
4467 | regs[i].loadedconst|=1<<hr; | |
4468 | } | |
4469 | } | |
4470 | } | |
57871462 | 4471 | // Load 32-bit regs |
4472 | for(hr=0;hr<HOST_REGS;hr++) { | |
4473 | if(hr!=EXCLUDE_REG&®map[hr]>=0) { | |
4474 | //if(entry[hr]!=regmap[hr]) { | |
8575a877 | 4475 | if(!((regs[i].loadedconst>>hr)&1)) { |
630b122b | 4476 | assert(regmap[hr]<64); |
4477 | if(((regs[i].isconst>>hr)&1)&®map[hr]>0) { | |
8575a877 | 4478 | int value,similar=0; |
57871462 | 4479 | if(get_final_value(hr,i,&value)) { |
8575a877 | 4480 | // see if some other register has similar value |
4481 | for(hr2=0;hr2<HOST_REGS;hr2++) { | |
4482 | if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) { | |
4483 | if(is_similar_value(value,constmap[i][hr2])) { | |
4484 | similar=1; | |
4485 | break; | |
4486 | } | |
4487 | } | |
4488 | } | |
4489 | if(similar) { | |
4490 | int value2; | |
4491 | if(get_final_value(hr2,i,&value2)) // is this needed? | |
4492 | emit_movimm_from(value2,hr2,value,hr); | |
4493 | else | |
4494 | emit_movimm(value,hr); | |
4495 | } | |
4496 | else if(value==0) { | |
57871462 | 4497 | emit_zeroreg(hr); |
4498 | } | |
4499 | else { | |
4500 | emit_movimm(value,hr); | |
4501 | } | |
4502 | } | |
8575a877 | 4503 | regs[i].loadedconst|=1<<hr; |
57871462 | 4504 | } |
4505 | } | |
4506 | } | |
4507 | } | |
57871462 | 4508 | } |
630b122b | 4509 | |
4510 | static void load_all_consts(const signed char regmap[], u_int dirty, int i) | |
57871462 | 4511 | { |
4512 | int hr; | |
4513 | // Load 32-bit regs | |
4514 | for(hr=0;hr<HOST_REGS;hr++) { | |
4515 | if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) { | |
630b122b | 4516 | assert(regmap[hr] < 64); |
4517 | if(((regs[i].isconst>>hr)&1)&®map[hr]>0) { | |
57871462 | 4518 | int value=constmap[i][hr]; |
4519 | if(value==0) { | |
4520 | emit_zeroreg(hr); | |
4521 | } | |
4522 | else { | |
4523 | emit_movimm(value,hr); | |
4524 | } | |
4525 | } | |
4526 | } | |
4527 | } | |
57871462 | 4528 | } |
4529 | ||
4530 | // Write out all dirty registers (except cycle count) | |
630b122b | 4531 | static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty) |
57871462 | 4532 | { |
4533 | int hr; | |
4534 | for(hr=0;hr<HOST_REGS;hr++) { | |
4535 | if(hr!=EXCLUDE_REG) { | |
4536 | if(i_regmap[hr]>0) { | |
4537 | if(i_regmap[hr]!=CCREG) { | |
4538 | if((i_dirty>>hr)&1) { | |
630b122b | 4539 | assert(i_regmap[hr]<64); |
4540 | emit_storereg(i_regmap[hr],hr); | |
57871462 | 4541 | } |
4542 | } | |
4543 | } | |
4544 | } | |
4545 | } | |
4546 | } | |
630b122b | 4547 | |
57871462 | 4548 | // Write out dirty registers that we need to reload (pair with load_needed_regs) |
4549 | // This writes the registers not written by store_regs_bt | |
630b122b | 4550 | static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr) |
57871462 | 4551 | { |
4552 | int hr; | |
4553 | int t=(addr-start)>>2; | |
4554 | for(hr=0;hr<HOST_REGS;hr++) { | |
4555 | if(hr!=EXCLUDE_REG) { | |
4556 | if(i_regmap[hr]>0) { | |
4557 | if(i_regmap[hr]!=CCREG) { | |
630b122b | 4558 | if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) { |
57871462 | 4559 | if((i_dirty>>hr)&1) { |
630b122b | 4560 | assert(i_regmap[hr]<64); |
4561 | emit_storereg(i_regmap[hr],hr); | |
57871462 | 4562 | } |
4563 | } | |
4564 | } | |
4565 | } | |
4566 | } | |
4567 | } | |
4568 | } | |
4569 | ||
4570 | // Load all registers (except cycle count) | |
630b122b | 4571 | static void load_all_regs(const signed char i_regmap[]) |
57871462 | 4572 | { |
4573 | int hr; | |
4574 | for(hr=0;hr<HOST_REGS;hr++) { | |
4575 | if(hr!=EXCLUDE_REG) { | |
4576 | if(i_regmap[hr]==0) { | |
4577 | emit_zeroreg(hr); | |
4578 | } | |
4579 | else | |
91af94f0 | 4580 | if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG) |
57871462 | 4581 | { |
4582 | emit_loadreg(i_regmap[hr],hr); | |
4583 | } | |
4584 | } | |
4585 | } | |
4586 | } | |
4587 | ||
4588 | // Load all current registers also needed by next instruction | |
630b122b | 4589 | static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]) |
57871462 | 4590 | { |
4591 | int hr; | |
4592 | for(hr=0;hr<HOST_REGS;hr++) { | |
4593 | if(hr!=EXCLUDE_REG) { | |
4594 | if(get_reg(next_regmap,i_regmap[hr])>=0) { | |
4595 | if(i_regmap[hr]==0) { | |
4596 | emit_zeroreg(hr); | |
4597 | } | |
4598 | else | |
91af94f0 | 4599 | if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG) |
57871462 | 4600 | { |
4601 | emit_loadreg(i_regmap[hr],hr); | |
4602 | } | |
4603 | } | |
4604 | } | |
4605 | } | |
4606 | } | |
4607 | ||
4608 | // Load all regs, storing cycle count if necessary | |
630b122b | 4609 | static void load_regs_entry(int t) |
57871462 | 4610 | { |
4611 | int hr; | |
630b122b | 4612 | if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG); |
4613 | else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t],HOST_CCREG); | |
57871462 | 4614 | if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) { |
4615 | emit_storereg(CCREG,HOST_CCREG); | |
4616 | } | |
4617 | // Load 32-bit regs | |
4618 | for(hr=0;hr<HOST_REGS;hr++) { | |
ea3d2e6e | 4619 | if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) { |
57871462 | 4620 | if(regs[t].regmap_entry[hr]==0) { |
4621 | emit_zeroreg(hr); | |
4622 | } | |
4623 | else if(regs[t].regmap_entry[hr]!=CCREG) | |
4624 | { | |
4625 | emit_loadreg(regs[t].regmap_entry[hr],hr); | |
4626 | } | |
4627 | } | |
4628 | } | |
57871462 | 4629 | } |
4630 | ||
4631 | // Store dirty registers prior to branch | |
94061aa5 | 4632 | static void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr) |
57871462 | 4633 | { |
630b122b | 4634 | if(internal_branch(addr)) |
57871462 | 4635 | { |
4636 | int t=(addr-start)>>2; | |
4637 | int hr; | |
4638 | for(hr=0;hr<HOST_REGS;hr++) { | |
4639 | if(hr!=EXCLUDE_REG) { | |
4640 | if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) { | |
630b122b | 4641 | if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) { |
57871462 | 4642 | if((i_dirty>>hr)&1) { |
630b122b | 4643 | assert(i_regmap[hr]<64); |
4644 | if(!((unneeded_reg[t]>>i_regmap[hr])&1)) | |
4645 | emit_storereg(i_regmap[hr],hr); | |
57871462 | 4646 | } |
4647 | } | |
4648 | } | |
4649 | } | |
4650 | } | |
4651 | } | |
4652 | else | |
4653 | { | |
4654 | // Branch out of this block, write out all dirty regs | |
630b122b | 4655 | wb_dirtys(i_regmap,i_dirty); |
57871462 | 4656 | } |
4657 | } | |
4658 | ||
4659 | // Load all needed registers for branch target | |
630b122b | 4660 | static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr) |
57871462 | 4661 | { |
4662 | //if(addr>=start && addr<(start+slen*4)) | |
630b122b | 4663 | if(internal_branch(addr)) |
57871462 | 4664 | { |
4665 | int t=(addr-start)>>2; | |
4666 | int hr; | |
4667 | // Store the cycle count before loading something else | |
4668 | if(i_regmap[HOST_CCREG]!=CCREG) { | |
4669 | assert(i_regmap[HOST_CCREG]==-1); | |
4670 | } | |
4671 | if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) { | |
4672 | emit_storereg(CCREG,HOST_CCREG); | |
4673 | } | |
4674 | // Load 32-bit regs | |
4675 | for(hr=0;hr<HOST_REGS;hr++) { | |
ea3d2e6e | 4676 | if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) { |
630b122b | 4677 | if(i_regmap[hr]!=regs[t].regmap_entry[hr]) { |
57871462 | 4678 | if(regs[t].regmap_entry[hr]==0) { |
4679 | emit_zeroreg(hr); | |
4680 | } | |
4681 | else if(regs[t].regmap_entry[hr]!=CCREG) | |
4682 | { | |
4683 | emit_loadreg(regs[t].regmap_entry[hr],hr); | |
4684 | } | |
4685 | } | |
4686 | } | |
4687 | } | |
57871462 | 4688 | } |
4689 | } | |
4690 | ||
630b122b | 4691 | static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr) |
57871462 | 4692 | { |
4693 | if(addr>=start && addr<start+slen*4-4) | |
4694 | { | |
4695 | int t=(addr-start)>>2; | |
4696 | int hr; | |
4697 | if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0; | |
4698 | for(hr=0;hr<HOST_REGS;hr++) | |
4699 | { | |
4700 | if(hr!=EXCLUDE_REG) | |
4701 | { | |
4702 | if(i_regmap[hr]!=regs[t].regmap_entry[hr]) | |
4703 | { | |
ea3d2e6e | 4704 | if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64) |
57871462 | 4705 | { |
4706 | return 0; | |
4707 | } | |
9f51b4b9 | 4708 | else |
57871462 | 4709 | if((i_dirty>>hr)&1) |
4710 | { | |
ea3d2e6e | 4711 | if(i_regmap[hr]<TEMPREG) |
57871462 | 4712 | { |
4713 | if(!((unneeded_reg[t]>>i_regmap[hr])&1)) | |
4714 | return 0; | |
4715 | } | |
ea3d2e6e | 4716 | else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64) |
57871462 | 4717 | { |
630b122b | 4718 | assert(0); |
57871462 | 4719 | } |
4720 | } | |
4721 | } | |
4722 | else // Same register but is it 32-bit or dirty? | |
4723 | if(i_regmap[hr]>=0) | |
4724 | { | |
4725 | if(!((regs[t].dirty>>hr)&1)) | |
4726 | { | |
4727 | if((i_dirty>>hr)&1) | |
4728 | { | |
4729 | if(!((unneeded_reg[t]>>i_regmap[hr])&1)) | |
4730 | { | |
4731 | //printf("%x: dirty no match\n",addr); | |
4732 | return 0; | |
4733 | } | |
4734 | } | |
4735 | } | |
57871462 | 4736 | } |
4737 | } | |
4738 | } | |
57871462 | 4739 | // Delay slots are not valid branch targets |
630b122b | 4740 | //if(t>0&&(dops[t-1].is_jump) return 0; |
57871462 | 4741 | // Delay slots require additional processing, so do not match |
630b122b | 4742 | if(dops[t].is_ds) return 0; |
57871462 | 4743 | } |
4744 | else | |
4745 | { | |
4746 | int hr; | |
4747 | for(hr=0;hr<HOST_REGS;hr++) | |
4748 | { | |
4749 | if(hr!=EXCLUDE_REG) | |
4750 | { | |
4751 | if(i_regmap[hr]>=0) | |
4752 | { | |
4753 | if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG) | |
4754 | { | |
4755 | if((i_dirty>>hr)&1) | |
4756 | { | |
4757 | return 0; | |
4758 | } | |
4759 | } | |
4760 | } | |
4761 | } | |
4762 | } | |
4763 | } | |
4764 | return 1; | |
4765 | } | |
4766 | ||
630b122b | 4767 | #ifdef DRC_DBG |
4768 | static void drc_dbg_emit_do_cmp(int i, int ccadj_) | |
57871462 | 4769 | { |
630b122b | 4770 | extern void do_insn_cmp(); |
4771 | //extern int cycle; | |
4772 | u_int hr, reglist = get_host_reglist(regs[i].regmap); | |
4773 | ||
4774 | assem_debug("//do_insn_cmp %08x\n", start+i*4); | |
4775 | save_regs(reglist); | |
4776 | // write out changed consts to match the interpreter | |
4777 | if (i > 0 && !dops[i].bt) { | |
4778 | for (hr = 0; hr < HOST_REGS; hr++) { | |
4779 | int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr]; | |
4780 | if (hr == EXCLUDE_REG || reg < 0) | |
4781 | continue; | |
4782 | if (!((regs[i-1].isconst >> hr) & 1)) | |
4783 | continue; | |
4784 | if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr]) | |
4785 | continue; | |
4786 | emit_movimm(constmap[i-1][hr],0); | |
4787 | emit_storereg(reg, 0); | |
4788 | } | |
4789 | } | |
4790 | emit_movimm(start+i*4,0); | |
4791 | emit_writeword(0,&pcaddr); | |
4792 | int cc = get_reg(regs[i].regmap_entry, CCREG); | |
4793 | if (cc < 0) | |
4794 | emit_loadreg(CCREG, cc = 0); | |
4795 | emit_addimm(cc, ccadj_, 0); | |
4796 | emit_writeword(0, &psxRegs.cycle); | |
4797 | emit_far_call(do_insn_cmp); | |
4798 | //emit_readword(&cycle,0); | |
4799 | //emit_addimm(0,2,0); | |
4800 | //emit_writeword(0,&cycle); | |
4801 | (void)get_reg2; | |
4802 | restore_regs(reglist); | |
4803 | assem_debug("\\\\do_insn_cmp\n"); | |
4804 | } | |
4805 | #else | |
4806 | #define drc_dbg_emit_do_cmp(x,y) | |
4807 | #endif | |
4808 | ||
4809 | // Used when a branch jumps into the delay slot of another branch | |
4810 | static void ds_assemble_entry(int i) | |
4811 | { | |
4812 | int t = (ba[i] - start) >> 2; | |
4813 | int ccadj_ = -CLOCK_ADJUST(1); | |
4814 | if (!instr_addr[t]) | |
4815 | instr_addr[t] = out; | |
4816 | assem_debug("Assemble delay slot at %x\n",ba[i]); | |
4817 | assem_debug("<->\n"); | |
4818 | drc_dbg_emit_do_cmp(t, ccadj_); | |
4819 | if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG) | |
4820 | wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty); | |
4821 | load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2); | |
4822 | address_generation(t,®s[t],regs[t].regmap_entry); | |
4823 | if (ram_offset && (dops[t].is_load || dops[t].is_store)) | |
e912c27d | 4824 | load_reg(regs[t].regmap_entry,regs[t].regmap,ROREG); |
630b122b | 4825 | if (dops[t].is_store) |
e912c27d | 4826 | load_reg(regs[t].regmap_entry,regs[t].regmap,INVCP); |
630b122b | 4827 | is_delayslot=0; |
4828 | switch (dops[t].itype) { | |
57871462 | 4829 | case SYSCALL: |
7139f3c8 | 4830 | case HLECALL: |
1e973cb0 | 4831 | case INTCALL: |
57871462 | 4832 | case UJUMP: |
4833 | case RJUMP: | |
4834 | case CJUMP: | |
4835 | case SJUMP: | |
c43b5311 | 4836 | SysPrintf("Jump in the delay slot. This is probably a bug.\n"); |
630b122b | 4837 | break; |
4838 | default: | |
4839 | assemble(t, ®s[t], ccadj_); | |
57871462 | 4840 | } |
630b122b | 4841 | store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4); |
4842 | load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4); | |
4843 | if(internal_branch(ba[i]+4)) | |
57871462 | 4844 | assem_debug("branch: internal\n"); |
4845 | else | |
4846 | assem_debug("branch: external\n"); | |
630b122b | 4847 | assert(internal_branch(ba[i]+4)); |
4848 | add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4)); | |
57871462 | 4849 | emit_jmp(0); |
4850 | } | |
4851 | ||
630b122b | 4852 | // Load 2 immediates optimizing for small code size |
4853 | static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2) | |
57871462 | 4854 | { |
630b122b | 4855 | emit_movimm(imm1,rt1); |
4856 | emit_movimm_from(imm1,rt1,imm2,rt2); | |
4857 | } | |
4858 | ||
4859 | static void do_cc(int i, const signed char i_regmap[], int *adj, | |
4860 | int addr, int taken, int invert) | |
4861 | { | |
4862 | int count, count_plus2; | |
4863 | void *jaddr; | |
4864 | void *idle=NULL; | |
b6e87b2b | 4865 | int t=0; |
630b122b | 4866 | if(dops[i].itype==RJUMP) |
57871462 | 4867 | { |
4868 | *adj=0; | |
4869 | } | |
4870 | //if(ba[i]>=start && ba[i]<(start+slen*4)) | |
630b122b | 4871 | if(internal_branch(ba[i])) |
57871462 | 4872 | { |
b6e87b2b | 4873 | t=(ba[i]-start)>>2; |
630b122b | 4874 | if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle |
57871462 | 4875 | else *adj=ccadj[t]; |
4876 | } | |
4877 | else | |
4878 | { | |
4879 | *adj=0; | |
4880 | } | |
630b122b | 4881 | count = ccadj[i]; |
4882 | count_plus2 = count + CLOCK_ADJUST(2); | |
57871462 | 4883 | if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) { |
4884 | // Idle loop | |
4885 | if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG); | |
630b122b | 4886 | idle=out; |
57871462 | 4887 | //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles |
4888 | emit_andimm(HOST_CCREG,3,HOST_CCREG); | |
630b122b | 4889 | jaddr=out; |
57871462 | 4890 | emit_jmp(0); |
4891 | } | |
4892 | else if(*adj==0||invert) { | |
630b122b | 4893 | int cycles = count_plus2; |
b6e87b2b | 4894 | // faster loop HACK |
630b122b | 4895 | #if 0 |
b6e87b2b | 4896 | if (t&&*adj) { |
4897 | int rel=t-i; | |
4898 | if(-NO_CYCLE_PENALTY_THR<rel&&rel<0) | |
630b122b | 4899 | cycles=*adj+count+2-*adj; |
b6e87b2b | 4900 | } |
630b122b | 4901 | #endif |
4902 | emit_addimm_and_set_flags(cycles, HOST_CCREG); | |
4903 | jaddr = out; | |
57871462 | 4904 | emit_jns(0); |
4905 | } | |
4906 | else | |
4907 | { | |
630b122b | 4908 | emit_cmpimm(HOST_CCREG, -count_plus2); |
4909 | jaddr = out; | |
57871462 | 4910 | emit_jns(0); |
4911 | } | |
630b122b | 4912 | add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0); |
57871462 | 4913 | } |
4914 | ||
630b122b | 4915 | static void do_ccstub(int n) |
57871462 | 4916 | { |
4917 | literal_pool(256); | |
630b122b | 4918 | assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4); |
4919 | set_jump_target(stubs[n].addr, out); | |
4920 | int i=stubs[n].b; | |
4921 | if(stubs[n].d==NULLDS) { | |
57871462 | 4922 | // Delay slot instruction is nullified ("likely" branch) |
630b122b | 4923 | wb_dirtys(regs[i].regmap,regs[i].dirty); |
57871462 | 4924 | } |
630b122b | 4925 | else if(stubs[n].d!=TAKEN) { |
4926 | wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty); | |
57871462 | 4927 | } |
4928 | else { | |
630b122b | 4929 | if(internal_branch(ba[i])) |
4930 | wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
57871462 | 4931 | } |
630b122b | 4932 | if(stubs[n].c!=-1) |
57871462 | 4933 | { |
4934 | // Save PC as return address | |
630b122b | 4935 | emit_movimm(stubs[n].c,EAX); |
4936 | emit_writeword(EAX,&pcaddr); | |
57871462 | 4937 | } |
4938 | else | |
4939 | { | |
4940 | // Return address depends on which way the branch goes | |
630b122b | 4941 | if(dops[i].itype==CJUMP||dops[i].itype==SJUMP) |
57871462 | 4942 | { |
630b122b | 4943 | int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1); |
4944 | int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2); | |
4945 | if(dops[i].rs1==0) | |
57871462 | 4946 | { |
630b122b | 4947 | s1l=s2l; |
4948 | s2l=-1; | |
57871462 | 4949 | } |
630b122b | 4950 | else if(dops[i].rs2==0) |
57871462 | 4951 | { |
630b122b | 4952 | s2l=-1; |
57871462 | 4953 | } |
4954 | assert(s1l>=0); | |
4955 | #ifdef DESTRUCTIVE_WRITEBACK | |
630b122b | 4956 | if(dops[i].rs1) { |
4957 | if((branch_regs[i].dirty>>s1l)&&1) | |
4958 | emit_loadreg(dops[i].rs1,s1l); | |
9f51b4b9 | 4959 | } |
57871462 | 4960 | else { |
630b122b | 4961 | if((branch_regs[i].dirty>>s1l)&1) |
4962 | emit_loadreg(dops[i].rs2,s1l); | |
57871462 | 4963 | } |
4964 | if(s2l>=0) | |
630b122b | 4965 | if((branch_regs[i].dirty>>s2l)&1) |
4966 | emit_loadreg(dops[i].rs2,s2l); | |
57871462 | 4967 | #endif |
4968 | int hr=0; | |
5194fb95 | 4969 | int addr=-1,alt=-1,ntaddr=-1; |
57871462 | 4970 | while(hr<HOST_REGS) |
4971 | { | |
4972 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && | |
91af94f0 | 4973 | branch_regs[i].regmap[hr]!=dops[i].rs1 && |
4974 | branch_regs[i].regmap[hr]!=dops[i].rs2 ) | |
57871462 | 4975 | { |
4976 | addr=hr++;break; | |
4977 | } | |
4978 | hr++; | |
4979 | } | |
4980 | while(hr<HOST_REGS) | |
4981 | { | |
4982 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && | |
91af94f0 | 4983 | branch_regs[i].regmap[hr]!=dops[i].rs1 && |
4984 | branch_regs[i].regmap[hr]!=dops[i].rs2 ) | |
57871462 | 4985 | { |
4986 | alt=hr++;break; | |
4987 | } | |
4988 | hr++; | |
4989 | } | |
630b122b | 4990 | if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register |
57871462 | 4991 | { |
4992 | while(hr<HOST_REGS) | |
4993 | { | |
4994 | if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && | |
91af94f0 | 4995 | branch_regs[i].regmap[hr]!=dops[i].rs1 && |
4996 | branch_regs[i].regmap[hr]!=dops[i].rs2 ) | |
57871462 | 4997 | { |
4998 | ntaddr=hr;break; | |
4999 | } | |
5000 | hr++; | |
5001 | } | |
5002 | assert(hr<HOST_REGS); | |
5003 | } | |
630b122b | 5004 | if((dops[i].opcode&0x2f)==4) // BEQ |
57871462 | 5005 | { |
5006 | #ifdef HAVE_CMOV_IMM | |
630b122b | 5007 | if(s2l>=0) emit_cmp(s1l,s2l); |
5008 | else emit_test(s1l,s1l); | |
5009 | emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr); | |
5010 | #else | |
5011 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); | |
5012 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5013 | else emit_test(s1l,s1l); | |
5014 | emit_cmovne_reg(alt,addr); | |
57871462 | 5015 | #endif |
57871462 | 5016 | } |
630b122b | 5017 | if((dops[i].opcode&0x2f)==5) // BNE |
57871462 | 5018 | { |
5019 | #ifdef HAVE_CMOV_IMM | |
630b122b | 5020 | if(s2l>=0) emit_cmp(s1l,s2l); |
5021 | else emit_test(s1l,s1l); | |
5022 | emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr); | |
5023 | #else | |
5024 | emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt); | |
5025 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5026 | else emit_test(s1l,s1l); | |
5027 | emit_cmovne_reg(alt,addr); | |
57871462 | 5028 | #endif |
57871462 | 5029 | } |
630b122b | 5030 | if((dops[i].opcode&0x2f)==6) // BLEZ |
57871462 | 5031 | { |
5032 | //emit_movimm(ba[i],alt); | |
5033 | //emit_movimm(start+i*4+8,addr); | |
5034 | emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); | |
5035 | emit_cmpimm(s1l,1); | |
57871462 | 5036 | emit_cmovl_reg(alt,addr); |
57871462 | 5037 | } |
630b122b | 5038 | if((dops[i].opcode&0x2f)==7) // BGTZ |
57871462 | 5039 | { |
5040 | //emit_movimm(ba[i],addr); | |
5041 | //emit_movimm(start+i*4+8,ntaddr); | |
5042 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr); | |
5043 | emit_cmpimm(s1l,1); | |
57871462 | 5044 | emit_cmovl_reg(ntaddr,addr); |
57871462 | 5045 | } |
630b122b | 5046 | if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ |
57871462 | 5047 | { |
5048 | //emit_movimm(ba[i],alt); | |
5049 | //emit_movimm(start+i*4+8,addr); | |
5050 | emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); | |
630b122b | 5051 | emit_test(s1l,s1l); |
57871462 | 5052 | emit_cmovs_reg(alt,addr); |
5053 | } | |
630b122b | 5054 | if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ |
57871462 | 5055 | { |
5056 | //emit_movimm(ba[i],addr); | |
5057 | //emit_movimm(start+i*4+8,alt); | |
5058 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); | |
630b122b | 5059 | emit_test(s1l,s1l); |
57871462 | 5060 | emit_cmovs_reg(alt,addr); |
5061 | } | |
630b122b | 5062 | if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) { |
57871462 | 5063 | if(source[i]&0x10000) // BC1T |
5064 | { | |
5065 | //emit_movimm(ba[i],alt); | |
5066 | //emit_movimm(start+i*4+8,addr); | |
5067 | emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr); | |
5068 | emit_testimm(s1l,0x800000); | |
5069 | emit_cmovne_reg(alt,addr); | |
5070 | } | |
5071 | else // BC1F | |
5072 | { | |
5073 | //emit_movimm(ba[i],addr); | |
5074 | //emit_movimm(start+i*4+8,alt); | |
5075 | emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt); | |
5076 | emit_testimm(s1l,0x800000); | |
5077 | emit_cmovne_reg(alt,addr); | |
5078 | } | |
5079 | } | |
630b122b | 5080 | emit_writeword(addr,&pcaddr); |
57871462 | 5081 | } |
5082 | else | |
630b122b | 5083 | if(dops[i].itype==RJUMP) |
57871462 | 5084 | { |
630b122b | 5085 | int r=get_reg(branch_regs[i].regmap,dops[i].rs1); |
5086 | if (ds_writes_rjump_rs(i)) { | |
57871462 | 5087 | r=get_reg(branch_regs[i].regmap,RTEMP); |
5088 | } | |
630b122b | 5089 | emit_writeword(r,&pcaddr); |
57871462 | 5090 | } |
630b122b | 5091 | else {SysPrintf("Unknown branch type in do_ccstub\n");abort();} |
57871462 | 5092 | } |
5093 | // Update cycle count | |
5094 | assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1); | |
630b122b | 5095 | if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG); |
5096 | emit_far_call(cc_interrupt); | |
5097 | if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG); | |
5098 | if(stubs[n].d==TAKEN) { | |
5099 | if(internal_branch(ba[i])) | |
57871462 | 5100 | load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry); |
630b122b | 5101 | else if(dops[i].itype==RJUMP) { |
57871462 | 5102 | if(get_reg(branch_regs[i].regmap,RTEMP)>=0) |
630b122b | 5103 | emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP)); |
57871462 | 5104 | else |
630b122b | 5105 | emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1)); |
57871462 | 5106 | } |
630b122b | 5107 | }else if(stubs[n].d==NOTTAKEN) { |
57871462 | 5108 | if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]); |
5109 | else load_all_regs(branch_regs[i].regmap); | |
630b122b | 5110 | }else if(stubs[n].d==NULLDS) { |
57871462 | 5111 | // Delay slot instruction is nullified ("likely" branch) |
5112 | if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]); | |
5113 | else load_all_regs(regs[i].regmap); | |
5114 | }else{ | |
5115 | load_all_regs(branch_regs[i].regmap); | |
5116 | } | |
630b122b | 5117 | if (stubs[n].retaddr) |
5118 | emit_jmp(stubs[n].retaddr); | |
5119 | else | |
5120 | do_jump_vaddr(stubs[n].e); | |
5121 | } | |
5122 | ||
048fcced | 5123 | static void add_to_linker(void *addr, u_int target, int is_internal) |
630b122b | 5124 | { |
5125 | assert(linkcount < ARRAY_SIZE(link_addr)); | |
5126 | link_addr[linkcount].addr = addr; | |
5127 | link_addr[linkcount].target = target; | |
048fcced | 5128 | link_addr[linkcount].internal = is_internal; |
57871462 | 5129 | linkcount++; |
5130 | } | |
5131 | ||
eba830cd | 5132 | static void ujump_assemble_write_ra(int i) |
5133 | { | |
5134 | int rt; | |
5135 | unsigned int return_address; | |
5136 | rt=get_reg(branch_regs[i].regmap,31); | |
5137 | assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); | |
5138 | //assert(rt>=0); | |
5139 | return_address=start+i*4+8; | |
5140 | if(rt>=0) { | |
5141 | #ifdef USE_MINI_HT | |
630b122b | 5142 | if(internal_branch(return_address)&&dops[i+1].rt1!=31) { |
eba830cd | 5143 | int temp=-1; // note: must be ds-safe |
5144 | #ifdef HOST_TEMPREG | |
5145 | temp=HOST_TEMPREG; | |
5146 | #endif | |
5147 | if(temp>=0) do_miniht_insert(return_address,rt,temp); | |
5148 | else emit_movimm(return_address,rt); | |
5149 | } | |
5150 | else | |
5151 | #endif | |
5152 | { | |
5153 | #ifdef REG_PREFETCH | |
9f51b4b9 | 5154 | if(temp>=0) |
eba830cd | 5155 | { |
630b122b | 5156 | if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); |
eba830cd | 5157 | } |
5158 | #endif | |
5159 | emit_movimm(return_address,rt); // PC into link register | |
5160 | #ifdef IMM_PREFETCH | |
630b122b | 5161 | emit_prefetch(hash_table_get(return_address)); |
eba830cd | 5162 | #endif |
5163 | } | |
5164 | } | |
5165 | } | |
5166 | ||
630b122b | 5167 | static void ujump_assemble(int i, const struct regstat *i_regs) |
57871462 | 5168 | { |
eba830cd | 5169 | int ra_done=0; |
57871462 | 5170 | if(i==(ba[i]-start)>>2) assem_debug("idle loop\n"); |
5171 | address_generation(i+1,i_regs,regs[i].regmap_entry); | |
5172 | #ifdef REG_PREFETCH | |
5173 | int temp=get_reg(branch_regs[i].regmap,PTEMP); | |
630b122b | 5174 | if(dops[i].rt1==31&&temp>=0) |
57871462 | 5175 | { |
581335b0 | 5176 | signed char *i_regmap=i_regs->regmap; |
57871462 | 5177 | int return_address=start+i*4+8; |
9f51b4b9 | 5178 | if(get_reg(branch_regs[i].regmap,31)>0) |
630b122b | 5179 | if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); |
57871462 | 5180 | } |
5181 | #endif | |
630b122b | 5182 | if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) { |
eba830cd | 5183 | ujump_assemble_write_ra(i); // writeback ra for DS |
5184 | ra_done=1; | |
57871462 | 5185 | } |
4ef8f67d | 5186 | ds_assemble(i+1,i_regs); |
5187 | uint64_t bc_unneeded=branch_regs[i].u; | |
630b122b | 5188 | bc_unneeded|=1|(1LL<<dops[i].rt1); |
5189 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded); | |
e912c27d | 5190 | load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG); |
630b122b | 5191 | if(!ra_done&&dops[i].rt1==31) |
eba830cd | 5192 | ujump_assemble_write_ra(i); |
57871462 | 5193 | int cc,adj; |
5194 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
5195 | assert(cc==HOST_CCREG); | |
630b122b | 5196 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); |
57871462 | 5197 | #ifdef REG_PREFETCH |
630b122b | 5198 | if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp); |
57871462 | 5199 | #endif |
5200 | do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); | |
630b122b | 5201 | if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); |
5202 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
5203 | if(internal_branch(ba[i])) | |
57871462 | 5204 | assem_debug("branch: internal\n"); |
5205 | else | |
5206 | assem_debug("branch: external\n"); | |
630b122b | 5207 | if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) { |
57871462 | 5208 | ds_assemble_entry(i); |
5209 | } | |
5210 | else { | |
630b122b | 5211 | add_to_linker(out,ba[i],internal_branch(ba[i])); |
57871462 | 5212 | emit_jmp(0); |
5213 | } | |
5214 | } | |
5215 | ||
eba830cd | 5216 | static void rjump_assemble_write_ra(int i) |
5217 | { | |
5218 | int rt,return_address; | |
630b122b | 5219 | assert(dops[i+1].rt1!=dops[i].rt1); |
5220 | assert(dops[i+1].rt2!=dops[i].rt1); | |
5221 | rt=get_reg(branch_regs[i].regmap,dops[i].rt1); | |
eba830cd | 5222 | assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
5223 | assert(rt>=0); | |
5224 | return_address=start+i*4+8; | |
5225 | #ifdef REG_PREFETCH | |
9f51b4b9 | 5226 | if(temp>=0) |
eba830cd | 5227 | { |
630b122b | 5228 | if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); |
eba830cd | 5229 | } |
5230 | #endif | |
5231 | emit_movimm(return_address,rt); // PC into link register | |
5232 | #ifdef IMM_PREFETCH | |
630b122b | 5233 | emit_prefetch(hash_table_get(return_address)); |
eba830cd | 5234 | #endif |
5235 | } | |
5236 | ||
630b122b | 5237 | static void rjump_assemble(int i, const struct regstat *i_regs) |
57871462 | 5238 | { |
57871462 | 5239 | int temp; |
581335b0 | 5240 | int rs,cc; |
eba830cd | 5241 | int ra_done=0; |
630b122b | 5242 | rs=get_reg(branch_regs[i].regmap,dops[i].rs1); |
57871462 | 5243 | assert(rs>=0); |
630b122b | 5244 | if (ds_writes_rjump_rs(i)) { |
57871462 | 5245 | // Delay slot abuse, make a copy of the branch address register |
5246 | temp=get_reg(branch_regs[i].regmap,RTEMP); | |
5247 | assert(temp>=0); | |
5248 | assert(regs[i].regmap[temp]==RTEMP); | |
5249 | emit_mov(rs,temp); | |
5250 | rs=temp; | |
5251 | } | |
5252 | address_generation(i+1,i_regs,regs[i].regmap_entry); | |
5253 | #ifdef REG_PREFETCH | |
630b122b | 5254 | if(dops[i].rt1==31) |
57871462 | 5255 | { |
5256 | if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) { | |
581335b0 | 5257 | signed char *i_regmap=i_regs->regmap; |
57871462 | 5258 | int return_address=start+i*4+8; |
630b122b | 5259 | if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); |
57871462 | 5260 | } |
5261 | } | |
5262 | #endif | |
5263 | #ifdef USE_MINI_HT | |
630b122b | 5264 | if(dops[i].rs1==31) { |
57871462 | 5265 | int rh=get_reg(regs[i].regmap,RHASH); |
5266 | if(rh>=0) do_preload_rhash(rh); | |
5267 | } | |
5268 | #endif | |
630b122b | 5269 | if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) { |
eba830cd | 5270 | rjump_assemble_write_ra(i); |
5271 | ra_done=1; | |
57871462 | 5272 | } |
d5910d5d | 5273 | ds_assemble(i+1,i_regs); |
5274 | uint64_t bc_unneeded=branch_regs[i].u; | |
630b122b | 5275 | bc_unneeded|=1|(1LL<<dops[i].rt1); |
5276 | bc_unneeded&=~(1LL<<dops[i].rs1); | |
5277 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded); | |
5278 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG); | |
5279 | if(!ra_done&&dops[i].rt1!=0) | |
eba830cd | 5280 | rjump_assemble_write_ra(i); |
57871462 | 5281 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5282 | assert(cc==HOST_CCREG); | |
581335b0 | 5283 | (void)cc; |
57871462 | 5284 | #ifdef USE_MINI_HT |
5285 | int rh=get_reg(branch_regs[i].regmap,RHASH); | |
5286 | int ht=get_reg(branch_regs[i].regmap,RHTBL); | |
630b122b | 5287 | if(dops[i].rs1==31) { |
57871462 | 5288 | if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh); |
5289 | do_preload_rhtbl(ht); | |
5290 | do_rhash(rs,rh); | |
5291 | } | |
5292 | #endif | |
630b122b | 5293 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1); |
57871462 | 5294 | #ifdef DESTRUCTIVE_WRITEBACK |
630b122b | 5295 | if((branch_regs[i].dirty>>rs)&1) { |
5296 | if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) { | |
5297 | emit_loadreg(dops[i].rs1,rs); | |
57871462 | 5298 | } |
5299 | } | |
5300 | #endif | |
5301 | #ifdef REG_PREFETCH | |
630b122b | 5302 | if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp); |
57871462 | 5303 | #endif |
5304 | #ifdef USE_MINI_HT | |
630b122b | 5305 | if(dops[i].rs1==31) { |
57871462 | 5306 | do_miniht_load(ht,rh); |
5307 | } | |
5308 | #endif | |
5309 | //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN); | |
5310 | //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen | |
5311 | //assert(adj==0); | |
630b122b | 5312 | emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG); |
5313 | add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs); | |
5314 | if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10) | |
911f2d55 | 5315 | // special case for RFE |
5316 | emit_jmp(0); | |
5317 | else | |
71e490c5 | 5318 | emit_jns(0); |
630b122b | 5319 | //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1); |
57871462 | 5320 | #ifdef USE_MINI_HT |
630b122b | 5321 | if(dops[i].rs1==31) { |
57871462 | 5322 | do_miniht_jump(rs,rh,ht); |
5323 | } | |
5324 | else | |
5325 | #endif | |
5326 | { | |
630b122b | 5327 | do_jump_vaddr(rs); |
5328 | } | |
57871462 | 5329 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
630b122b | 5330 | if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13); |
57871462 | 5331 | #endif |
5332 | } | |
5333 | ||
630b122b | 5334 | static void cjump_assemble(int i, const struct regstat *i_regs) |
57871462 | 5335 | { |
630b122b | 5336 | const signed char *i_regmap = i_regs->regmap; |
57871462 | 5337 | int cc; |
5338 | int match; | |
630b122b | 5339 | match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); |
57871462 | 5340 | assem_debug("match=%d\n",match); |
630b122b | 5341 | int s1l,s2l; |
57871462 | 5342 | int unconditional=0,nop=0; |
57871462 | 5343 | int invert=0; |
630b122b | 5344 | int internal=internal_branch(ba[i]); |
57871462 | 5345 | if(i==(ba[i]-start)>>2) assem_debug("idle loop\n"); |
57871462 | 5346 | if(!match) invert=1; |
5347 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
5348 | if(i>(ba[i]-start)>>2) invert=1; | |
5349 | #endif | |
630b122b | 5350 | #ifdef __aarch64__ |
5351 | invert=1; // because of near cond. branches | |
5352 | #endif | |
9f51b4b9 | 5353 | |
630b122b | 5354 | if(dops[i].ooo) { |
5355 | s1l=get_reg(branch_regs[i].regmap,dops[i].rs1); | |
5356 | s2l=get_reg(branch_regs[i].regmap,dops[i].rs2); | |
57871462 | 5357 | } |
5358 | else { | |
630b122b | 5359 | s1l=get_reg(i_regmap,dops[i].rs1); |
5360 | s2l=get_reg(i_regmap,dops[i].rs2); | |
57871462 | 5361 | } |
630b122b | 5362 | if(dops[i].rs1==0&&dops[i].rs2==0) |
57871462 | 5363 | { |
630b122b | 5364 | if(dops[i].opcode&1) nop=1; |
57871462 | 5365 | else unconditional=1; |
630b122b | 5366 | //assert(dops[i].opcode!=5); |
5367 | //assert(dops[i].opcode!=7); | |
5368 | //assert(dops[i].opcode!=0x15); | |
5369 | //assert(dops[i].opcode!=0x17); | |
57871462 | 5370 | } |
630b122b | 5371 | else if(dops[i].rs1==0) |
57871462 | 5372 | { |
630b122b | 5373 | s1l=s2l; |
5374 | s2l=-1; | |
57871462 | 5375 | } |
630b122b | 5376 | else if(dops[i].rs2==0) |
57871462 | 5377 | { |
630b122b | 5378 | s2l=-1; |
57871462 | 5379 | } |
5380 | ||
630b122b | 5381 | if(dops[i].ooo) { |
57871462 | 5382 | // Out of order execution (delay slot first) |
5383 | //printf("OOOE\n"); | |
5384 | address_generation(i+1,i_regs,regs[i].regmap_entry); | |
5385 | ds_assemble(i+1,i_regs); | |
5386 | int adj; | |
5387 | uint64_t bc_unneeded=branch_regs[i].u; | |
630b122b | 5388 | bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 5389 | bc_unneeded|=1; |
630b122b | 5390 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded); |
5391 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2); | |
e912c27d | 5392 | load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG); |
57871462 | 5393 | cc=get_reg(branch_regs[i].regmap,CCREG); |
5394 | assert(cc==HOST_CCREG); | |
9f51b4b9 | 5395 | if(unconditional) |
630b122b | 5396 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); |
57871462 | 5397 | //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional); |
5398 | //assem_debug("cycle count (adj)\n"); | |
5399 | if(unconditional) { | |
5400 | do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); | |
5401 | if(i!=(ba[i]-start)>>2 || source[i+1]!=0) { | |
630b122b | 5402 | if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); |
5403 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
57871462 | 5404 | if(internal) |
5405 | assem_debug("branch: internal\n"); | |
5406 | else | |
5407 | assem_debug("branch: external\n"); | |
630b122b | 5408 | if (internal && dops[(ba[i]-start)>>2].is_ds) { |
57871462 | 5409 | ds_assemble_entry(i); |
5410 | } | |
5411 | else { | |
630b122b | 5412 | add_to_linker(out,ba[i],internal); |
57871462 | 5413 | emit_jmp(0); |
5414 | } | |
5415 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
5416 | if(((u_int)out)&7) emit_addnop(0); | |
5417 | #endif | |
5418 | } | |
5419 | } | |
5420 | else if(nop) { | |
630b122b | 5421 | emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); |
5422 | void *jaddr=out; | |
57871462 | 5423 | emit_jns(0); |
630b122b | 5424 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 | 5425 | } |
5426 | else { | |
630b122b | 5427 | void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL; |
57871462 | 5428 | do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); |
630b122b | 5429 | if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); |
9f51b4b9 | 5430 | |
57871462 | 5431 | //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
5432 | assert(s1l>=0); | |
630b122b | 5433 | if(dops[i].opcode==4) // BEQ |
57871462 | 5434 | { |
5435 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5436 | else emit_test(s1l,s1l); | |
5437 | if(invert){ | |
630b122b | 5438 | nottaken=out; |
5439 | emit_jne(DJT_1); | |
57871462 | 5440 | }else{ |
630b122b | 5441 | add_to_linker(out,ba[i],internal); |
57871462 | 5442 | emit_jeq(0); |
5443 | } | |
5444 | } | |
630b122b | 5445 | if(dops[i].opcode==5) // BNE |
57871462 | 5446 | { |
5447 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5448 | else emit_test(s1l,s1l); | |
5449 | if(invert){ | |
630b122b | 5450 | nottaken=out; |
5451 | emit_jeq(DJT_1); | |
57871462 | 5452 | }else{ |
630b122b | 5453 | add_to_linker(out,ba[i],internal); |
57871462 | 5454 | emit_jne(0); |
5455 | } | |
5456 | } | |
630b122b | 5457 | if(dops[i].opcode==6) // BLEZ |
57871462 | 5458 | { |
5459 | emit_cmpimm(s1l,1); | |
5460 | if(invert){ | |
630b122b | 5461 | nottaken=out; |
5462 | emit_jge(DJT_1); | |
57871462 | 5463 | }else{ |
630b122b | 5464 | add_to_linker(out,ba[i],internal); |
57871462 | 5465 | emit_jl(0); |
5466 | } | |
5467 | } | |
630b122b | 5468 | if(dops[i].opcode==7) // BGTZ |
57871462 | 5469 | { |
5470 | emit_cmpimm(s1l,1); | |
5471 | if(invert){ | |
630b122b | 5472 | nottaken=out; |
5473 | emit_jl(DJT_1); | |
57871462 | 5474 | }else{ |
630b122b | 5475 | add_to_linker(out,ba[i],internal); |
57871462 | 5476 | emit_jge(0); |
5477 | } | |
5478 | } | |
5479 | if(invert) { | |
630b122b | 5480 | if(taken) set_jump_target(taken, out); |
57871462 | 5481 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
630b122b | 5482 | if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) { |
57871462 | 5483 | if(adj) { |
630b122b | 5484 | emit_addimm(cc,-adj,cc); |
5485 | add_to_linker(out,ba[i],internal); | |
57871462 | 5486 | }else{ |
5487 | emit_addnop(13); | |
630b122b | 5488 | add_to_linker(out,ba[i],internal*2); |
57871462 | 5489 | } |
5490 | emit_jmp(0); | |
5491 | }else | |
5492 | #endif | |
5493 | { | |
630b122b | 5494 | if(adj) emit_addimm(cc,-adj,cc); |
5495 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
5496 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
57871462 | 5497 | if(internal) |
5498 | assem_debug("branch: internal\n"); | |
5499 | else | |
5500 | assem_debug("branch: external\n"); | |
630b122b | 5501 | if (internal && dops[(ba[i] - start) >> 2].is_ds) { |
57871462 | 5502 | ds_assemble_entry(i); |
5503 | } | |
5504 | else { | |
630b122b | 5505 | add_to_linker(out,ba[i],internal); |
57871462 | 5506 | emit_jmp(0); |
5507 | } | |
5508 | } | |
630b122b | 5509 | set_jump_target(nottaken, out); |
57871462 | 5510 | } |
5511 | ||
630b122b | 5512 | if(nottaken1) set_jump_target(nottaken1, out); |
57871462 | 5513 | if(adj) { |
630b122b | 5514 | if(!invert) emit_addimm(cc,adj,cc); |
57871462 | 5515 | } |
5516 | } // (!unconditional) | |
5517 | } // if(ooo) | |
5518 | else | |
5519 | { | |
5520 | // In-order execution (branch first) | |
630b122b | 5521 | void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL; |
57871462 | 5522 | if(!unconditional&&!nop) { |
57871462 | 5523 | //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
5524 | assert(s1l>=0); | |
630b122b | 5525 | if((dops[i].opcode&0x2f)==4) // BEQ |
57871462 | 5526 | { |
5527 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5528 | else emit_test(s1l,s1l); | |
630b122b | 5529 | nottaken=out; |
5530 | emit_jne(DJT_2); | |
57871462 | 5531 | } |
630b122b | 5532 | if((dops[i].opcode&0x2f)==5) // BNE |
57871462 | 5533 | { |
5534 | if(s2l>=0) emit_cmp(s1l,s2l); | |
5535 | else emit_test(s1l,s1l); | |
630b122b | 5536 | nottaken=out; |
5537 | emit_jeq(DJT_2); | |
57871462 | 5538 | } |
630b122b | 5539 | if((dops[i].opcode&0x2f)==6) // BLEZ |
57871462 | 5540 | { |
5541 | emit_cmpimm(s1l,1); | |
630b122b | 5542 | nottaken=out; |
5543 | emit_jge(DJT_2); | |
57871462 | 5544 | } |
630b122b | 5545 | if((dops[i].opcode&0x2f)==7) // BGTZ |
57871462 | 5546 | { |
5547 | emit_cmpimm(s1l,1); | |
630b122b | 5548 | nottaken=out; |
5549 | emit_jl(DJT_2); | |
57871462 | 5550 | } |
5551 | } // if(!unconditional) | |
5552 | int adj; | |
5553 | uint64_t ds_unneeded=branch_regs[i].u; | |
630b122b | 5554 | ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); |
57871462 | 5555 | ds_unneeded|=1; |
57871462 | 5556 | // branch taken |
5557 | if(!nop) { | |
630b122b | 5558 | if(taken) set_jump_target(taken, out); |
57871462 | 5559 | assem_debug("1:\n"); |
630b122b | 5560 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); |
57871462 | 5561 | // load regs |
630b122b | 5562 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); |
57871462 | 5563 | address_generation(i+1,&branch_regs[i],0); |
630b122b | 5564 | if (ram_offset) |
e912c27d | 5565 | load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG); |
630b122b | 5566 | load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); |
57871462 | 5567 | ds_assemble(i+1,&branch_regs[i]); |
5568 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
5569 | if(cc==-1) { | |
5570 | emit_loadreg(CCREG,cc=HOST_CCREG); | |
5571 | // CHECK: Is the following instruction (fall thru) allocated ok? | |
5572 | } | |
5573 | assert(cc==HOST_CCREG); | |
630b122b | 5574 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); |
57871462 | 5575 | do_cc(i,i_regmap,&adj,ba[i],TAKEN,0); |
5576 | assem_debug("cycle count (adj)\n"); | |
630b122b | 5577 | if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); |
5578 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
57871462 | 5579 | if(internal) |
5580 | assem_debug("branch: internal\n"); | |
5581 | else | |
5582 | assem_debug("branch: external\n"); | |
630b122b | 5583 | if (internal && dops[(ba[i] - start) >> 2].is_ds) { |
57871462 | 5584 | ds_assemble_entry(i); |
5585 | } | |
5586 | else { | |
630b122b | 5587 | add_to_linker(out,ba[i],internal); |
57871462 | 5588 | emit_jmp(0); |
5589 | } | |
5590 | } | |
5591 | // branch not taken | |
57871462 | 5592 | if(!unconditional) { |
630b122b | 5593 | if(nottaken1) set_jump_target(nottaken1, out); |
5594 | set_jump_target(nottaken, out); | |
57871462 | 5595 | assem_debug("2:\n"); |
630b122b | 5596 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); |
5597 | // load regs | |
5598 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); | |
5599 | address_generation(i+1,&branch_regs[i],0); | |
5600 | if (ram_offset) | |
e912c27d | 5601 | load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG); |
630b122b | 5602 | load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); |
5603 | ds_assemble(i+1,&branch_regs[i]); | |
57871462 | 5604 | cc=get_reg(branch_regs[i].regmap,CCREG); |
630b122b | 5605 | if (cc == -1) { |
57871462 | 5606 | // Cycle count isn't in a register, temporarily load it then write it out |
5607 | emit_loadreg(CCREG,HOST_CCREG); | |
630b122b | 5608 | emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG); |
5609 | void *jaddr=out; | |
57871462 | 5610 | emit_jns(0); |
630b122b | 5611 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 | 5612 | emit_storereg(CCREG,HOST_CCREG); |
5613 | } | |
5614 | else{ | |
5615 | cc=get_reg(i_regmap,CCREG); | |
5616 | assert(cc==HOST_CCREG); | |
630b122b | 5617 | emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); |
5618 | void *jaddr=out; | |
57871462 | 5619 | emit_jns(0); |
630b122b | 5620 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 | 5621 | } |
5622 | } | |
5623 | } | |
5624 | } | |
5625 | ||
630b122b | 5626 | static void sjump_assemble(int i, const struct regstat *i_regs) |
57871462 | 5627 | { |
630b122b | 5628 | const signed char *i_regmap = i_regs->regmap; |
57871462 | 5629 | int cc; |
5630 | int match; | |
630b122b | 5631 | match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); |
fdf33825 | 5632 | assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo); |
630b122b | 5633 | int s1l; |
57871462 | 5634 | int unconditional=0,nevertaken=0; |
57871462 | 5635 | int invert=0; |
630b122b | 5636 | int internal=internal_branch(ba[i]); |
57871462 | 5637 | if(i==(ba[i]-start)>>2) assem_debug("idle loop\n"); |
57871462 | 5638 | if(!match) invert=1; |
5639 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
5640 | if(i>(ba[i]-start)>>2) invert=1; | |
5641 | #endif | |
630b122b | 5642 | #ifdef __aarch64__ |
5643 | invert=1; // because of near cond. branches | |
5644 | #endif | |
57871462 | 5645 | |
630b122b | 5646 | //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL) |
5647 | //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL) | |
57871462 | 5648 | |
630b122b | 5649 | if(dops[i].ooo) { |
5650 | s1l=get_reg(branch_regs[i].regmap,dops[i].rs1); | |
57871462 | 5651 | } |
5652 | else { | |
630b122b | 5653 | s1l=get_reg(i_regmap,dops[i].rs1); |
57871462 | 5654 | } |
630b122b | 5655 | if(dops[i].rs1==0) |
57871462 | 5656 | { |
630b122b | 5657 | if(dops[i].opcode2&1) unconditional=1; |
57871462 | 5658 | else nevertaken=1; |
5659 | // These are never taken (r0 is never less than zero) | |
630b122b | 5660 | //assert(dops[i].opcode2!=0); |
5661 | //assert(dops[i].opcode2!=2); | |
5662 | //assert(dops[i].opcode2!=0x10); | |
5663 | //assert(dops[i].opcode2!=0x12); | |
57871462 | 5664 | } |
5665 | ||
630b122b | 5666 | if(dops[i].ooo) { |
57871462 | 5667 | // Out of order execution (delay slot first) |
5668 | //printf("OOOE\n"); | |
5669 | address_generation(i+1,i_regs,regs[i].regmap_entry); | |
5670 | ds_assemble(i+1,i_regs); | |
5671 | int adj; | |
5672 | uint64_t bc_unneeded=branch_regs[i].u; | |
630b122b | 5673 | bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 5674 | bc_unneeded|=1; |
630b122b | 5675 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded); |
5676 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1); | |
e912c27d | 5677 | load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG); |
630b122b | 5678 | if(dops[i].rt1==31) { |
57871462 | 5679 | int rt,return_address; |
57871462 | 5680 | rt=get_reg(branch_regs[i].regmap,31); |
5681 | assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); | |
5682 | if(rt>=0) { | |
5683 | // Save the PC even if the branch is not taken | |
5684 | return_address=start+i*4+8; | |
5685 | emit_movimm(return_address,rt); // PC into link register | |
5686 | #ifdef IMM_PREFETCH | |
630b122b | 5687 | if(!nevertaken) emit_prefetch(hash_table_get(return_address)); |
57871462 | 5688 | #endif |
5689 | } | |
5690 | } | |
5691 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
5692 | assert(cc==HOST_CCREG); | |
9f51b4b9 | 5693 | if(unconditional) |
630b122b | 5694 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); |
57871462 | 5695 | //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional); |
5696 | assem_debug("cycle count (adj)\n"); | |
5697 | if(unconditional) { | |
5698 | do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); | |
5699 | if(i!=(ba[i]-start)>>2 || source[i+1]!=0) { | |
630b122b | 5700 | if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); |
5701 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
57871462 | 5702 | if(internal) |
5703 | assem_debug("branch: internal\n"); | |
5704 | else | |
5705 | assem_debug("branch: external\n"); | |
630b122b | 5706 | if (internal && dops[(ba[i] - start) >> 2].is_ds) { |
57871462 | 5707 | ds_assemble_entry(i); |
5708 | } | |
5709 | else { | |
630b122b | 5710 | add_to_linker(out,ba[i],internal); |
57871462 | 5711 | emit_jmp(0); |
5712 | } | |
5713 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
5714 | if(((u_int)out)&7) emit_addnop(0); | |
5715 | #endif | |
5716 | } | |
5717 | } | |
5718 | else if(nevertaken) { | |
630b122b | 5719 | emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); |
5720 | void *jaddr=out; | |
57871462 | 5721 | emit_jns(0); |
630b122b | 5722 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 | 5723 | } |
5724 | else { | |
630b122b | 5725 | void *nottaken = NULL; |
57871462 | 5726 | do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); |
630b122b | 5727 | if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); |
57871462 | 5728 | { |
5729 | assert(s1l>=0); | |
630b122b | 5730 | if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL |
57871462 | 5731 | { |
5732 | emit_test(s1l,s1l); | |
5733 | if(invert){ | |
630b122b | 5734 | nottaken=out; |
5735 | emit_jns(DJT_1); | |
57871462 | 5736 | }else{ |
630b122b | 5737 | add_to_linker(out,ba[i],internal); |
57871462 | 5738 | emit_js(0); |
5739 | } | |
5740 | } | |
630b122b | 5741 | if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL |
57871462 | 5742 | { |
5743 | emit_test(s1l,s1l); | |
5744 | if(invert){ | |
630b122b | 5745 | nottaken=out; |
5746 | emit_js(DJT_1); | |
57871462 | 5747 | }else{ |
630b122b | 5748 | add_to_linker(out,ba[i],internal); |
57871462 | 5749 | emit_jns(0); |
5750 | } | |
5751 | } | |
57871462 | 5752 | } |
9f51b4b9 | 5753 | |
57871462 | 5754 | if(invert) { |
57871462 | 5755 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK |
630b122b | 5756 | if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) { |
5757 | if(adj) { | |
5758 | emit_addimm(cc,-adj,cc); | |
5759 | add_to_linker(out,ba[i],internal); | |
5760 | }else{ | |
5761 | emit_addnop(13); | |
5762 | add_to_linker(out,ba[i],internal*2); | |
5763 | } | |
57871462 | 5764 | emit_jmp(0); |
630b122b | 5765 | }else |
5766 | #endif | |
5767 | { | |
5768 | if(adj) emit_addimm(cc,-adj,cc); | |
5769 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
5770 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
5771 | if(internal) | |
5772 | assem_debug("branch: internal\n"); | |
5773 | else | |
5774 | assem_debug("branch: external\n"); | |
5775 | if (internal && dops[(ba[i] - start) >> 2].is_ds) { | |
5776 | ds_assemble_entry(i); | |
5777 | } | |
5778 | else { | |
5779 | add_to_linker(out,ba[i],internal); | |
5780 | emit_jmp(0); | |
5781 | } | |
57871462 | 5782 | } |
630b122b | 5783 | set_jump_target(nottaken, out); |
57871462 | 5784 | } |
5785 | ||
5786 | if(adj) { | |
630b122b | 5787 | if(!invert) emit_addimm(cc,adj,cc); |
57871462 | 5788 | } |
5789 | } // (!unconditional) | |
5790 | } // if(ooo) | |
5791 | else | |
5792 | { | |
5793 | // In-order execution (branch first) | |
5794 | //printf("IOE\n"); | |
630b122b | 5795 | void *nottaken = NULL; |
5796 | if(dops[i].rt1==31) { | |
5797 | int rt,return_address; | |
5798 | rt=get_reg(branch_regs[i].regmap,31); | |
5799 | if(rt>=0) { | |
5800 | // Save the PC even if the branch is not taken | |
5801 | return_address=start+i*4+8; | |
5802 | emit_movimm(return_address,rt); // PC into link register | |
5803 | #ifdef IMM_PREFETCH | |
5804 | emit_prefetch(hash_table_get(return_address)); | |
5805 | #endif | |
5806 | } | |
5807 | } | |
5808 | if(!unconditional) { | |
57871462 | 5809 | //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); |
630b122b | 5810 | assert(s1l>=0); |
5811 | if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL | |
57871462 | 5812 | { |
630b122b | 5813 | emit_test(s1l,s1l); |
5814 | nottaken=out; | |
5815 | emit_jns(DJT_1); | |
57871462 | 5816 | } |
630b122b | 5817 | if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL |
57871462 | 5818 | { |
630b122b | 5819 | emit_test(s1l,s1l); |
5820 | nottaken=out; | |
5821 | emit_js(DJT_1); | |
57871462 | 5822 | } |
57871462 | 5823 | } // if(!unconditional) |
5824 | int adj; | |
5825 | uint64_t ds_unneeded=branch_regs[i].u; | |
630b122b | 5826 | ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); |
57871462 | 5827 | ds_unneeded|=1; |
57871462 | 5828 | // branch taken |
630b122b | 5829 | if(!nevertaken) { |
5830 | //assem_debug("1:\n"); | |
5831 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); | |
5832 | // load regs | |
5833 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); | |
5834 | address_generation(i+1,&branch_regs[i],0); | |
5835 | if (ram_offset) | |
e912c27d | 5836 | load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG); |
630b122b | 5837 | load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); |
5838 | ds_assemble(i+1,&branch_regs[i]); | |
5839 | cc=get_reg(branch_regs[i].regmap,CCREG); | |
5840 | if(cc==-1) { | |
5841 | emit_loadreg(CCREG,cc=HOST_CCREG); | |
5842 | // CHECK: Is the following instruction (fall thru) allocated ok? | |
5843 | } | |
5844 | assert(cc==HOST_CCREG); | |
5845 | store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
5846 | do_cc(i,i_regmap,&adj,ba[i],TAKEN,0); | |
5847 | assem_debug("cycle count (adj)\n"); | |
5848 | if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); | |
5849 | load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); | |
5850 | if(internal) | |
5851 | assem_debug("branch: internal\n"); | |
5852 | else | |
5853 | assem_debug("branch: external\n"); | |
5854 | if (internal && dops[(ba[i] - start) >> 2].is_ds) { | |
5855 | ds_assemble_entry(i); | |
5856 | } | |
5857 | else { | |
5858 | add_to_linker(out,ba[i],internal); | |
5859 | emit_jmp(0); | |
5860 | } | |
57871462 | 5861 | } |
57871462 | 5862 | // branch not taken |
630b122b | 5863 | if(!unconditional) { |
5864 | set_jump_target(nottaken, out); | |
57871462 | 5865 | assem_debug("1:\n"); |
630b122b | 5866 | wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); |
5867 | load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); | |
5868 | address_generation(i+1,&branch_regs[i],0); | |
dfe6947f | 5869 | if (ram_offset) |
e912c27d | 5870 | load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG); |
dfe6947f | 5871 | load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); |
630b122b | 5872 | ds_assemble(i+1,&branch_regs[i]); |
57871462 | 5873 | cc=get_reg(branch_regs[i].regmap,CCREG); |
630b122b | 5874 | if (cc == -1) { |
57871462 | 5875 | // Cycle count isn't in a register, temporarily load it then write it out |
5876 | emit_loadreg(CCREG,HOST_CCREG); | |
630b122b | 5877 | emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG); |
5878 | void *jaddr=out; | |
57871462 | 5879 | emit_jns(0); |
630b122b | 5880 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 | 5881 | emit_storereg(CCREG,HOST_CCREG); |
5882 | } | |
5883 | else{ | |
5884 | cc=get_reg(i_regmap,CCREG); | |
5885 | assert(cc==HOST_CCREG); | |
630b122b | 5886 | emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); |
5887 | void *jaddr=out; | |
57871462 | 5888 | emit_jns(0); |
630b122b | 5889 | add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); |
57871462 | 5890 | } |
5891 | } | |
5892 | } | |
5893 | } | |
5894 | ||
648d9448 | 5895 | static void check_regmap(signed char *regmap) |
5896 | { | |
5897 | #ifndef NDEBUG | |
5898 | int i,j; | |
5899 | for (i = 0; i < HOST_REGS; i++) { | |
5900 | if (regmap[i] < 0) | |
5901 | continue; | |
5902 | for (j = i + 1; j < HOST_REGS; j++) | |
5903 | assert(regmap[i] != regmap[j]); | |
5904 | } | |
5905 | #endif | |
5906 | } | |
5907 | ||
4600ba03 | 5908 | #ifdef DISASM |
fdf33825 | 5909 | #include <inttypes.h> |
ed14d777 | 5910 | static char insn[MAXBLOCK][10]; |
5911 | ||
5912 | #define set_mnemonic(i_, n_) \ | |
5913 | strcpy(insn[i_], n_) | |
5914 | ||
fdf33825 | 5915 | void print_regmap(const char *name, const signed char *regmap) |
5916 | { | |
5917 | char buf[5]; | |
5918 | int i, l; | |
5919 | fputs(name, stdout); | |
5920 | for (i = 0; i < HOST_REGS; i++) { | |
5921 | l = 0; | |
5922 | if (regmap[i] >= 0) | |
5923 | l = snprintf(buf, sizeof(buf), "$%d", regmap[i]); | |
5924 | for (; l < 3; l++) | |
5925 | buf[l] = ' '; | |
5926 | buf[l] = 0; | |
5927 | printf(" r%d=%s", i, buf); | |
5928 | } | |
5929 | fputs("\n", stdout); | |
5930 | } | |
5931 | ||
57871462 | 5932 | /* disassembly */ |
5933 | void disassemble_inst(int i) | |
5934 | { | |
630b122b | 5935 | if (dops[i].bt) printf("*"); else printf(" "); |
5936 | switch(dops[i].itype) { | |
57871462 | 5937 | case UJUMP: |
5938 | printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break; | |
5939 | case CJUMP: | |
630b122b | 5940 | printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break; |
57871462 | 5941 | case SJUMP: |
630b122b | 5942 | printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break; |
57871462 | 5943 | case RJUMP: |
630b122b | 5944 | if (dops[i].opcode==0x9&&dops[i].rt1!=31) |
5945 | printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1); | |
5067f341 | 5946 | else |
630b122b | 5947 | printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1); |
5067f341 | 5948 | break; |
57871462 | 5949 | case IMM16: |
630b122b | 5950 | if(dops[i].opcode==0xf) //LUI |
5951 | printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff); | |
57871462 | 5952 | else |
630b122b | 5953 | printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]); |
57871462 | 5954 | break; |
5955 | case LOAD: | |
5956 | case LOADLR: | |
630b122b | 5957 | printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]); |
57871462 | 5958 | break; |
5959 | case STORE: | |
5960 | case STORELR: | |
630b122b | 5961 | printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]); |
57871462 | 5962 | break; |
5963 | case ALU: | |
5964 | case SHIFT: | |
630b122b | 5965 | printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2); |
57871462 | 5966 | break; |
5967 | case MULTDIV: | |
630b122b | 5968 | printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2); |
57871462 | 5969 | break; |
5970 | case SHIFTIMM: | |
630b122b | 5971 | printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]); |
57871462 | 5972 | break; |
5973 | case MOV: | |
630b122b | 5974 | if((dops[i].opcode2&0x1d)==0x10) |
5975 | printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1); | |
5976 | else if((dops[i].opcode2&0x1d)==0x11) | |
5977 | printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1); | |
57871462 | 5978 | else |
5979 | printf (" %x: %s\n",start+i*4,insn[i]); | |
5980 | break; | |
5981 | case COP0: | |
630b122b | 5982 | if(dops[i].opcode2==0) |
5983 | printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0 | |
5984 | else if(dops[i].opcode2==4) | |
5985 | printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0 | |
57871462 | 5986 | else printf (" %x: %s\n",start+i*4,insn[i]); |
5987 | break; | |
5988 | case COP1: | |
630b122b | 5989 | if(dops[i].opcode2<3) |
5990 | printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1 | |
5991 | else if(dops[i].opcode2>3) | |
5992 | printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1 | |
57871462 | 5993 | else printf (" %x: %s\n",start+i*4,insn[i]); |
5994 | break; | |
b9b61529 | 5995 | case COP2: |
630b122b | 5996 | if(dops[i].opcode2<3) |
5997 | printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2 | |
5998 | else if(dops[i].opcode2>3) | |
5999 | printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2 | |
b9b61529 | 6000 | else printf (" %x: %s\n",start+i*4,insn[i]); |
6001 | break; | |
57871462 | 6002 | case C1LS: |
630b122b | 6003 | printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]); |
57871462 | 6004 | break; |
b9b61529 | 6005 | case C2LS: |
630b122b | 6006 | printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]); |
b9b61529 | 6007 | break; |
1e973cb0 | 6008 | case INTCALL: |
6009 | printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]); | |
6010 | break; | |
57871462 | 6011 | default: |
6012 | //printf (" %s %8x\n",insn[i],source[i]); | |
6013 | printf (" %x: %s\n",start+i*4,insn[i]); | |
6014 | } | |
fdf33825 | 6015 | return; |
6016 | printf("D: %"PRIu64" WD: %"PRIu64" U: %"PRIu64"\n", | |
6017 | regs[i].dirty, regs[i].wasdirty, unneeded_reg[i]); | |
6018 | print_regmap("pre: ", regmap_pre[i]); | |
6019 | print_regmap("entry: ", regs[i].regmap_entry); | |
6020 | print_regmap("map: ", regs[i].regmap); | |
6021 | if (dops[i].is_jump) { | |
6022 | print_regmap("bentry:", branch_regs[i].regmap_entry); | |
6023 | print_regmap("bmap: ", branch_regs[i].regmap); | |
6024 | } | |
57871462 | 6025 | } |
4600ba03 | 6026 | #else |
ed14d777 | 6027 | #define set_mnemonic(i_, n_) |
4600ba03 | 6028 | static void disassemble_inst(int i) {} |
6029 | #endif // DISASM | |
57871462 | 6030 | |
d848b60a | 6031 | #define DRC_TEST_VAL 0x74657374 |
6032 | ||
630b122b | 6033 | static void new_dynarec_test(void) |
d848b60a | 6034 | { |
630b122b | 6035 | int (*testfunc)(void); |
d148d265 | 6036 | void *beginning; |
630b122b | 6037 | int ret[2]; |
6038 | size_t i; | |
d148d265 | 6039 | |
630b122b | 6040 | // check structure linkage |
6041 | if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs)) | |
6042 | { | |
6043 | SysPrintf("linkage_arm* miscompilation/breakage detected.\n"); | |
6044 | } | |
6045 | ||
f8a8da84 | 6046 | SysPrintf("testing if we can run recompiled code @%p...\n", out); |
630b122b | 6047 | ((volatile u_int *)out)[0]++; // make cache dirty |
6048 | ||
6049 | for (i = 0; i < ARRAY_SIZE(ret); i++) { | |
6050 | out = ndrc->translation_cache; | |
6051 | beginning = start_block(); | |
6052 | emit_movimm(DRC_TEST_VAL + i, 0); // test | |
6053 | emit_ret(); | |
6054 | literal_pool(0); | |
6055 | end_block(beginning); | |
6056 | testfunc = beginning; | |
6057 | ret[i] = testfunc(); | |
6058 | } | |
6059 | ||
6060 | if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1) | |
d848b60a | 6061 | SysPrintf("test passed.\n"); |
6062 | else | |
630b122b | 6063 | SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]); |
6064 | out = ndrc->translation_cache; | |
d848b60a | 6065 | } |
6066 | ||
dc990066 | 6067 | // clear the state completely, instead of just marking |
6068 | // things invalid like invalidate_all_pages() does | |
92d79826 | 6069 | void new_dynarec_clear_full(void) |
57871462 | 6070 | { |
57871462 | 6071 | int n; |
630b122b | 6072 | out = ndrc->translation_cache; |
35775df7 | 6073 | memset(invalid_code,1,sizeof(invalid_code)); |
6074 | memset(hash_table,0xff,sizeof(hash_table)); | |
57871462 | 6075 | memset(mini_ht,-1,sizeof(mini_ht)); |
dc990066 | 6076 | memset(shadow,0,sizeof(shadow)); |
57871462 | 6077 | copy=shadow; |
432435ea | 6078 | expirep = EXPIRITY_OFFSET; |
57871462 | 6079 | pending_exception=0; |
6080 | literalcount=0; | |
57871462 | 6081 | stop_after_jal=0; |
9be4ba64 | 6082 | inv_code_start=inv_code_end=~0; |
7c8454e3 | 6083 | hack_addr=0; |
630b122b | 6084 | f1_hack=0; |
432435ea | 6085 | for (n = 0; n < ARRAY_SIZE(blocks); n++) |
6086 | blocks_clear(&blocks[n]); | |
366d1d2b | 6087 | for (n = 0; n < ARRAY_SIZE(jumps); n++) { |
6088 | free(jumps[n]); | |
6089 | jumps[n] = NULL; | |
6090 | } | |
048fcced | 6091 | stat_clear(stat_blocks); |
6092 | stat_clear(stat_links); | |
630b122b | 6093 | |
6094 | cycle_multiplier_old = cycle_multiplier; | |
6095 | new_dynarec_hacks_old = new_dynarec_hacks; | |
dc990066 | 6096 | } |
6097 | ||
92d79826 | 6098 | void new_dynarec_init(void) |
dc990066 | 6099 | { |
ab51e9e2 | 6100 | SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc)); |
1e212a25 | 6101 | |
4666f75d | 6102 | #ifdef _3DS |
6103 | check_rosalina(); | |
6104 | #endif | |
630b122b | 6105 | #ifdef BASE_ADDR_DYNAMIC |
6106 | #ifdef VITA | |
4666f75d | 6107 | sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc)); |
ab51e9e2 | 6108 | if (sceBlock <= 0) |
6109 | SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock); | |
630b122b | 6110 | int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc); |
1e212a25 | 6111 | if (ret < 0) |
ab51e9e2 | 6112 | SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret); |
4666f75d | 6113 | sceKernelOpenVMDomain(); |
6114 | sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache); | |
6115 | #elif defined(_MSC_VER) | |
6116 | ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE, | |
6117 | PAGE_EXECUTE_READWRITE); | |
630b122b | 6118 | #else |
6119 | uintptr_t desired_addr = 0; | |
6120 | #ifdef __ELF__ | |
6121 | extern char _end; | |
6122 | desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl; | |
6123 | #endif | |
6124 | ndrc = mmap((void *)desired_addr, sizeof(*ndrc), | |
6125 | PROT_READ | PROT_WRITE | PROT_EXEC, | |
6126 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); | |
6127 | if (ndrc == MAP_FAILED) { | |
d848b60a | 6128 | SysPrintf("mmap() failed: %s\n", strerror(errno)); |
1e212a25 | 6129 | abort(); |
d848b60a | 6130 | } |
630b122b | 6131 | #endif |
1e212a25 | 6132 | #else |
630b122b | 6133 | #ifndef NO_WRITE_EXEC |
bdeade46 | 6134 | // not all systems allow execute in data segment by default |
f8a8da84 | 6135 | // size must be 4K aligned for 3DS? |
6136 | if (mprotect(ndrc, sizeof(*ndrc), | |
630b122b | 6137 | PROT_READ | PROT_WRITE | PROT_EXEC) != 0) |
d848b60a | 6138 | SysPrintf("mprotect() failed: %s\n", strerror(errno)); |
630b122b | 6139 | #endif |
dc990066 | 6140 | #endif |
630b122b | 6141 | out = ndrc->translation_cache; |
2573466a | 6142 | cycle_multiplier=200; |
dc990066 | 6143 | new_dynarec_clear_full(); |
6144 | #ifdef HOST_IMM8 | |
6145 | // Copy this into local area so we don't have to put it in every literal pool | |
6146 | invc_ptr=invalid_code; | |
6147 | #endif | |
57871462 | 6148 | arch_init(); |
d848b60a | 6149 | new_dynarec_test(); |
630b122b | 6150 | ram_offset=(uintptr_t)rdram-0x80000000; |
b105cf4f | 6151 | if (ram_offset!=0) |
c43b5311 | 6152 | SysPrintf("warning: RAM is not directly mapped, performance will suffer\n"); |
bfdecce3 | 6153 | SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n"); |
6154 | SysPrintf("%p/%p/%p/%p/%p\n", psxM, psxH, psxR, mem_rtab, out); | |
57871462 | 6155 | } |
6156 | ||
92d79826 | 6157 | void new_dynarec_cleanup(void) |
57871462 | 6158 | { |
6159 | int n; | |
630b122b | 6160 | #ifdef BASE_ADDR_DYNAMIC |
6161 | #ifdef VITA | |
ab51e9e2 | 6162 | // sceBlock is managed by retroarch's bootstrap code |
af4a16ff | 6163 | //sceKernelFreeMemBlock(sceBlock); |
6164 | //sceBlock = -1; | |
630b122b | 6165 | #else |
6166 | if (munmap(ndrc, sizeof(*ndrc)) < 0) | |
1e212a25 | 6167 | SysPrintf("munmap() failed\n"); |
630b122b | 6168 | #endif |
1e212a25 | 6169 | #endif |
432435ea | 6170 | for (n = 0; n < ARRAY_SIZE(blocks); n++) |
6171 | blocks_clear(&blocks[n]); | |
366d1d2b | 6172 | for (n = 0; n < ARRAY_SIZE(jumps); n++) { |
6173 | free(jumps[n]); | |
6174 | jumps[n] = NULL; | |
6175 | } | |
048fcced | 6176 | stat_clear(stat_blocks); |
6177 | stat_clear(stat_links); | |
630b122b | 6178 | #ifdef ROM_COPY |
c43b5311 | 6179 | if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");} |
630b122b | 6180 | #endif |
55cadc36 | 6181 | new_dynarec_print_stats(); |
57871462 | 6182 | } |
6183 | ||
03f55e6b | 6184 | static u_int *get_source_start(u_int addr, u_int *limit) |
57871462 | 6185 | { |
03f55e6b | 6186 | if (addr < 0x00200000 || |
630b122b | 6187 | (0xa0000000 <= addr && addr < 0xa0200000)) |
6188 | { | |
03f55e6b | 6189 | // used for BIOS calls mostly? |
6190 | *limit = (addr&0xa0000000)|0x00200000; | |
630b122b | 6191 | return (u_int *)(rdram + (addr&0x1fffff)); |
03f55e6b | 6192 | } |
6193 | else if (!Config.HLE && ( | |
6194 | /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/ | |
630b122b | 6195 | (0xbfc00000 <= addr && addr < 0xbfc80000))) |
6196 | { | |
6197 | // BIOS. The multiplier should be much higher as it's uncached 8bit mem, | |
6198 | // but timings in PCSX are too tied to the interpreter's BIAS | |
6199 | if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M)) | |
6200 | cycle_multiplier_active = 200; | |
6201 | ||
03f55e6b | 6202 | *limit = (addr & 0xfff00000) | 0x80000; |
630b122b | 6203 | return (u_int *)((u_char *)psxR + (addr&0x7ffff)); |
03f55e6b | 6204 | } |
6205 | else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) { | |
6206 | *limit = (addr & 0x80600000) + 0x00200000; | |
630b122b | 6207 | return (u_int *)(rdram + (addr&0x1fffff)); |
03f55e6b | 6208 | } |
581335b0 | 6209 | return NULL; |
03f55e6b | 6210 | } |
6211 | ||
6212 | static u_int scan_for_ret(u_int addr) | |
6213 | { | |
6214 | u_int limit = 0; | |
6215 | u_int *mem; | |
6216 | ||
6217 | mem = get_source_start(addr, &limit); | |
6218 | if (mem == NULL) | |
6219 | return addr; | |
6220 | ||
6221 | if (limit > addr + 0x1000) | |
6222 | limit = addr + 0x1000; | |
6223 | for (; addr < limit; addr += 4, mem++) { | |
6224 | if (*mem == 0x03e00008) // jr $ra | |
6225 | return addr + 8; | |
57871462 | 6226 | } |
581335b0 | 6227 | return addr; |
03f55e6b | 6228 | } |
6229 | ||
6230 | struct savestate_block { | |
6231 | uint32_t addr; | |
6232 | uint32_t regflags; | |
6233 | }; | |
6234 | ||
6235 | static int addr_cmp(const void *p1_, const void *p2_) | |
6236 | { | |
6237 | const struct savestate_block *p1 = p1_, *p2 = p2_; | |
6238 | return p1->addr - p2->addr; | |
6239 | } | |
6240 | ||
6241 | int new_dynarec_save_blocks(void *save, int size) | |
6242 | { | |
048fcced | 6243 | struct savestate_block *sblocks = save; |
6244 | int maxcount = size / sizeof(sblocks[0]); | |
03f55e6b | 6245 | struct savestate_block tmp_blocks[1024]; |
048fcced | 6246 | struct block_info *block; |
03f55e6b | 6247 | int p, s, d, o, bcnt; |
6248 | u_int addr; | |
6249 | ||
6250 | o = 0; | |
048fcced | 6251 | for (p = 0; p < ARRAY_SIZE(blocks); p++) { |
03f55e6b | 6252 | bcnt = 0; |
048fcced | 6253 | for (block = blocks[p]; block != NULL; block = block->next) { |
6254 | if (block->is_dirty) | |
6255 | continue; | |
6256 | tmp_blocks[bcnt].addr = block->start; | |
6257 | tmp_blocks[bcnt].regflags = block->reg_sv_flags; | |
03f55e6b | 6258 | bcnt++; |
6259 | } | |
6260 | if (bcnt < 1) | |
6261 | continue; | |
6262 | qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp); | |
6263 | ||
6264 | addr = tmp_blocks[0].addr; | |
6265 | for (s = d = 0; s < bcnt; s++) { | |
6266 | if (tmp_blocks[s].addr < addr) | |
6267 | continue; | |
6268 | if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr) | |
6269 | tmp_blocks[d++] = tmp_blocks[s]; | |
6270 | addr = scan_for_ret(tmp_blocks[s].addr); | |
6271 | } | |
6272 | ||
6273 | if (o + d > maxcount) | |
6274 | d = maxcount - o; | |
048fcced | 6275 | memcpy(&sblocks[o], tmp_blocks, d * sizeof(sblocks[0])); |
03f55e6b | 6276 | o += d; |
6277 | } | |
6278 | ||
048fcced | 6279 | return o * sizeof(sblocks[0]); |
03f55e6b | 6280 | } |
6281 | ||
6282 | void new_dynarec_load_blocks(const void *save, int size) | |
6283 | { | |
048fcced | 6284 | const struct savestate_block *sblocks = save; |
6285 | int count = size / sizeof(sblocks[0]); | |
6286 | struct block_info *block; | |
03f55e6b | 6287 | u_int regs_save[32]; |
048fcced | 6288 | u_int page; |
03f55e6b | 6289 | uint32_t f; |
6290 | int i, b; | |
6291 | ||
048fcced | 6292 | // restore clean blocks, if any |
6293 | for (page = 0, b = i = 0; page < ARRAY_SIZE(blocks); page++) { | |
6294 | for (block = blocks[page]; block != NULL; block = block->next, b++) { | |
6295 | if (!block->is_dirty) | |
6296 | continue; | |
6297 | assert(block->source && block->copy); | |
6298 | if (memcmp(block->source, block->copy, block->len)) | |
6299 | continue; | |
6300 | ||
6301 | // see try_restore_block | |
6302 | block->is_dirty = 0; | |
6303 | mark_invalid_code(block->start, block->len, 0); | |
6304 | i++; | |
6305 | } | |
6306 | } | |
6307 | inv_debug("load_blocks: %d/%d clean blocks\n", i, b); | |
03f55e6b | 6308 | |
6309 | // change GPRs for speculation to at least partially work.. | |
6310 | memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save)); | |
6311 | for (i = 1; i < 32; i++) | |
6312 | psxRegs.GPR.r[i] = 0x80000000; | |
6313 | ||
6314 | for (b = 0; b < count; b++) { | |
048fcced | 6315 | for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) { |
03f55e6b | 6316 | if (f & 1) |
6317 | psxRegs.GPR.r[i] = 0x1f800000; | |
6318 | } | |
6319 | ||
048fcced | 6320 | ndrc_get_addr_ht(sblocks[b].addr); |
03f55e6b | 6321 | |
048fcced | 6322 | for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) { |
03f55e6b | 6323 | if (f & 1) |
6324 | psxRegs.GPR.r[i] = 0x80000000; | |
6325 | } | |
6326 | } | |
6327 | ||
6328 | memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save)); | |
6329 | } | |
6330 | ||
55cadc36 | 6331 | void new_dynarec_print_stats(void) |
6332 | { | |
6333 | #ifdef STAT_PRINT | |
048fcced | 6334 | printf("cc %3d,%3d,%3d lu%6d,%3d,%3d c%3d inv%3d,%3d tc_offs %zu b %u,%u\n", |
55cadc36 | 6335 | stat_bc_pre, stat_bc_direct, stat_bc_restore, |
048fcced | 6336 | stat_ht_lookups, stat_jump_in_lookups, stat_restore_tries, |
6337 | stat_restore_compares, stat_inv_addr_calls, stat_inv_hits, | |
6338 | out - ndrc->translation_cache, stat_blocks, stat_links); | |
55cadc36 | 6339 | stat_bc_direct = stat_bc_pre = stat_bc_restore = |
048fcced | 6340 | stat_ht_lookups = stat_jump_in_lookups = stat_restore_tries = |
6341 | stat_restore_compares = stat_inv_addr_calls = stat_inv_hits = 0; | |
55cadc36 | 6342 | #endif |
6343 | } | |
6344 | ||
7c8454e3 | 6345 | static int apply_hacks(void) |
630b122b | 6346 | { |
6347 | int i; | |
6348 | if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS)) | |
7c8454e3 | 6349 | return 0; |
630b122b | 6350 | /* special hack(s) */ |
6351 | for (i = 0; i < slen - 4; i++) | |
6352 | { | |
6353 | // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224 | |
6354 | if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP | |
6355 | && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a | |
6356 | && imm[i+3] == 0x6e40 && dops[i+3].rs1 == 2) | |
6357 | { | |
6358 | SysPrintf("PE2 hack @%08x\n", start + (i+3)*4); | |
6359 | dops[i + 3].itype = NOP; | |
6360 | } | |
6361 | } | |
6362 | i = slen; | |
6363 | if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008 | |
6364 | && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809 | |
6365 | && dops[i-7].itype == STORE) | |
6366 | { | |
6367 | i = i-8; | |
6368 | if (dops[i].itype == IMM16) | |
6369 | i--; | |
6370 | // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6 | |
6371 | if (dops[i].itype == STORELR && dops[i].rs1 == 6 | |
6372 | && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6) | |
6373 | { | |
7c8454e3 | 6374 | SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr); |
6375 | f1_hack = 1; | |
6376 | return 1; | |
630b122b | 6377 | } |
6378 | } | |
7c8454e3 | 6379 | return 0; |
630b122b | 6380 | } |
6381 | ||
94061aa5 | 6382 | static noinline void pass1_disassemble(u_int pagelimit) |
03f55e6b | 6383 | { |
94061aa5 | 6384 | int i, j, done = 0, ni_count = 0; |
57871462 | 6385 | unsigned int type,op,op2; |
6386 | ||
447f5a1d | 6387 | for (i = 0; !done; i++) |
6388 | { | |
6389 | memset(&dops[i], 0, sizeof(dops[i])); | |
630b122b | 6390 | op2=0; |
e1190b87 | 6391 | minimum_free_regs[i]=0; |
630b122b | 6392 | dops[i].opcode=op=source[i]>>26; |
57871462 | 6393 | switch(op) |
6394 | { | |
ed14d777 | 6395 | case 0x00: set_mnemonic(i, "special"); type=NI; |
57871462 | 6396 | op2=source[i]&0x3f; |
6397 | switch(op2) | |
6398 | { | |
ed14d777 | 6399 | case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break; |
6400 | case 0x02: set_mnemonic(i, "SRL"); type=SHIFTIMM; break; | |
6401 | case 0x03: set_mnemonic(i, "SRA"); type=SHIFTIMM; break; | |
6402 | case 0x04: set_mnemonic(i, "SLLV"); type=SHIFT; break; | |
6403 | case 0x06: set_mnemonic(i, "SRLV"); type=SHIFT; break; | |
6404 | case 0x07: set_mnemonic(i, "SRAV"); type=SHIFT; break; | |
6405 | case 0x08: set_mnemonic(i, "JR"); type=RJUMP; break; | |
6406 | case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break; | |
6407 | case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break; | |
6408 | case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break; | |
6409 | case 0x0F: set_mnemonic(i, "SYNC"); type=OTHER; break; | |
6410 | case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break; | |
6411 | case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break; | |
6412 | case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break; | |
6413 | case 0x13: set_mnemonic(i, "MTLO"); type=MOV; break; | |
6414 | case 0x18: set_mnemonic(i, "MULT"); type=MULTDIV; break; | |
6415 | case 0x19: set_mnemonic(i, "MULTU"); type=MULTDIV; break; | |
6416 | case 0x1A: set_mnemonic(i, "DIV"); type=MULTDIV; break; | |
6417 | case 0x1B: set_mnemonic(i, "DIVU"); type=MULTDIV; break; | |
6418 | case 0x20: set_mnemonic(i, "ADD"); type=ALU; break; | |
6419 | case 0x21: set_mnemonic(i, "ADDU"); type=ALU; break; | |
6420 | case 0x22: set_mnemonic(i, "SUB"); type=ALU; break; | |
6421 | case 0x23: set_mnemonic(i, "SUBU"); type=ALU; break; | |
6422 | case 0x24: set_mnemonic(i, "AND"); type=ALU; break; | |
6423 | case 0x25: set_mnemonic(i, "OR"); type=ALU; break; | |
6424 | case 0x26: set_mnemonic(i, "XOR"); type=ALU; break; | |
6425 | case 0x27: set_mnemonic(i, "NOR"); type=ALU; break; | |
6426 | case 0x2A: set_mnemonic(i, "SLT"); type=ALU; break; | |
6427 | case 0x2B: set_mnemonic(i, "SLTU"); type=ALU; break; | |
6428 | case 0x30: set_mnemonic(i, "TGE"); type=NI; break; | |
6429 | case 0x31: set_mnemonic(i, "TGEU"); type=NI; break; | |
6430 | case 0x32: set_mnemonic(i, "TLT"); type=NI; break; | |
6431 | case 0x33: set_mnemonic(i, "TLTU"); type=NI; break; | |
6432 | case 0x34: set_mnemonic(i, "TEQ"); type=NI; break; | |
6433 | case 0x36: set_mnemonic(i, "TNE"); type=NI; break; | |
71e490c5 | 6434 | #if 0 |
ed14d777 | 6435 | case 0x14: set_mnemonic(i, "DSLLV"); type=SHIFT; break; |
6436 | case 0x16: set_mnemonic(i, "DSRLV"); type=SHIFT; break; | |
6437 | case 0x17: set_mnemonic(i, "DSRAV"); type=SHIFT; break; | |
6438 | case 0x1C: set_mnemonic(i, "DMULT"); type=MULTDIV; break; | |
6439 | case 0x1D: set_mnemonic(i, "DMULTU"); type=MULTDIV; break; | |
6440 | case 0x1E: set_mnemonic(i, "DDIV"); type=MULTDIV; break; | |
6441 | case 0x1F: set_mnemonic(i, "DDIVU"); type=MULTDIV; break; | |
6442 | case 0x2C: set_mnemonic(i, "DADD"); type=ALU; break; | |
6443 | case 0x2D: set_mnemonic(i, "DADDU"); type=ALU; break; | |
6444 | case 0x2E: set_mnemonic(i, "DSUB"); type=ALU; break; | |
6445 | case 0x2F: set_mnemonic(i, "DSUBU"); type=ALU; break; | |
6446 | case 0x38: set_mnemonic(i, "DSLL"); type=SHIFTIMM; break; | |
6447 | case 0x3A: set_mnemonic(i, "DSRL"); type=SHIFTIMM; break; | |
6448 | case 0x3B: set_mnemonic(i, "DSRA"); type=SHIFTIMM; break; | |
6449 | case 0x3C: set_mnemonic(i, "DSLL32"); type=SHIFTIMM; break; | |
6450 | case 0x3E: set_mnemonic(i, "DSRL32"); type=SHIFTIMM; break; | |
6451 | case 0x3F: set_mnemonic(i, "DSRA32"); type=SHIFTIMM; break; | |
7f2607ea | 6452 | #endif |
57871462 | 6453 | } |
6454 | break; | |
ed14d777 | 6455 | case 0x01: set_mnemonic(i, "regimm"); type=NI; |
57871462 | 6456 | op2=(source[i]>>16)&0x1f; |
6457 | switch(op2) | |
6458 | { | |
ed14d777 | 6459 | case 0x00: set_mnemonic(i, "BLTZ"); type=SJUMP; break; |
6460 | case 0x01: set_mnemonic(i, "BGEZ"); type=SJUMP; break; | |
6461 | //case 0x02: set_mnemonic(i, "BLTZL"); type=SJUMP; break; | |
6462 | //case 0x03: set_mnemonic(i, "BGEZL"); type=SJUMP; break; | |
6463 | //case 0x08: set_mnemonic(i, "TGEI"); type=NI; break; | |
6464 | //case 0x09: set_mnemonic(i, "TGEIU"); type=NI; break; | |
6465 | //case 0x0A: set_mnemonic(i, "TLTI"); type=NI; break; | |
6466 | //case 0x0B: set_mnemonic(i, "TLTIU"); type=NI; break; | |
6467 | //case 0x0C: set_mnemonic(i, "TEQI"); type=NI; break; | |
6468 | //case 0x0E: set_mnemonic(i, "TNEI"); type=NI; break; | |
6469 | case 0x10: set_mnemonic(i, "BLTZAL"); type=SJUMP; break; | |
6470 | case 0x11: set_mnemonic(i, "BGEZAL"); type=SJUMP; break; | |
6471 | //case 0x12: set_mnemonic(i, "BLTZALL"); type=SJUMP; break; | |
6472 | //case 0x13: set_mnemonic(i, "BGEZALL"); type=SJUMP; break; | |
57871462 | 6473 | } |
6474 | break; | |
ed14d777 | 6475 | case 0x02: set_mnemonic(i, "J"); type=UJUMP; break; |
6476 | case 0x03: set_mnemonic(i, "JAL"); type=UJUMP; break; | |
6477 | case 0x04: set_mnemonic(i, "BEQ"); type=CJUMP; break; | |
6478 | case 0x05: set_mnemonic(i, "BNE"); type=CJUMP; break; | |
6479 | case 0x06: set_mnemonic(i, "BLEZ"); type=CJUMP; break; | |
6480 | case 0x07: set_mnemonic(i, "BGTZ"); type=CJUMP; break; | |
6481 | case 0x08: set_mnemonic(i, "ADDI"); type=IMM16; break; | |
6482 | case 0x09: set_mnemonic(i, "ADDIU"); type=IMM16; break; | |
6483 | case 0x0A: set_mnemonic(i, "SLTI"); type=IMM16; break; | |
6484 | case 0x0B: set_mnemonic(i, "SLTIU"); type=IMM16; break; | |
6485 | case 0x0C: set_mnemonic(i, "ANDI"); type=IMM16; break; | |
6486 | case 0x0D: set_mnemonic(i, "ORI"); type=IMM16; break; | |
6487 | case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break; | |
6488 | case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break; | |
6489 | case 0x10: set_mnemonic(i, "cop0"); type=NI; | |
57871462 | 6490 | op2=(source[i]>>21)&0x1f; |
6491 | switch(op2) | |
6492 | { | |
ed14d777 | 6493 | case 0x00: set_mnemonic(i, "MFC0"); type=COP0; break; |
6494 | case 0x02: set_mnemonic(i, "CFC0"); type=COP0; break; | |
6495 | case 0x04: set_mnemonic(i, "MTC0"); type=COP0; break; | |
6496 | case 0x06: set_mnemonic(i, "CTC0"); type=COP0; break; | |
6497 | case 0x10: set_mnemonic(i, "RFE"); type=COP0; break; | |
57871462 | 6498 | } |
6499 | break; | |
ed14d777 | 6500 | case 0x11: set_mnemonic(i, "cop1"); type=COP1; |
57871462 | 6501 | op2=(source[i]>>21)&0x1f; |
57871462 | 6502 | break; |
71e490c5 | 6503 | #if 0 |
ed14d777 | 6504 | case 0x14: set_mnemonic(i, "BEQL"); type=CJUMP; break; |
6505 | case 0x15: set_mnemonic(i, "BNEL"); type=CJUMP; break; | |
6506 | case 0x16: set_mnemonic(i, "BLEZL"); type=CJUMP; break; | |
6507 | case 0x17: set_mnemonic(i, "BGTZL"); type=CJUMP; break; | |
6508 | case 0x18: set_mnemonic(i, "DADDI"); type=IMM16; break; | |
6509 | case 0x19: set_mnemonic(i, "DADDIU"); type=IMM16; break; | |
6510 | case 0x1A: set_mnemonic(i, "LDL"); type=LOADLR; break; | |
6511 | case 0x1B: set_mnemonic(i, "LDR"); type=LOADLR; break; | |
996cc15d | 6512 | #endif |
ed14d777 | 6513 | case 0x20: set_mnemonic(i, "LB"); type=LOAD; break; |
6514 | case 0x21: set_mnemonic(i, "LH"); type=LOAD; break; | |
6515 | case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; break; | |
6516 | case 0x23: set_mnemonic(i, "LW"); type=LOAD; break; | |
6517 | case 0x24: set_mnemonic(i, "LBU"); type=LOAD; break; | |
6518 | case 0x25: set_mnemonic(i, "LHU"); type=LOAD; break; | |
6519 | case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; break; | |
71e490c5 | 6520 | #if 0 |
ed14d777 | 6521 | case 0x27: set_mnemonic(i, "LWU"); type=LOAD; break; |
64bd6f82 | 6522 | #endif |
ed14d777 | 6523 | case 0x28: set_mnemonic(i, "SB"); type=STORE; break; |
6524 | case 0x29: set_mnemonic(i, "SH"); type=STORE; break; | |
6525 | case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; break; | |
6526 | case 0x2B: set_mnemonic(i, "SW"); type=STORE; break; | |
71e490c5 | 6527 | #if 0 |
ed14d777 | 6528 | case 0x2C: set_mnemonic(i, "SDL"); type=STORELR; break; |
6529 | case 0x2D: set_mnemonic(i, "SDR"); type=STORELR; break; | |
996cc15d | 6530 | #endif |
ed14d777 | 6531 | case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; break; |
6532 | case 0x2F: set_mnemonic(i, "CACHE"); type=NOP; break; | |
6533 | case 0x30: set_mnemonic(i, "LL"); type=NI; break; | |
6534 | case 0x31: set_mnemonic(i, "LWC1"); type=C1LS; break; | |
71e490c5 | 6535 | #if 0 |
ed14d777 | 6536 | case 0x34: set_mnemonic(i, "LLD"); type=NI; break; |
6537 | case 0x35: set_mnemonic(i, "LDC1"); type=C1LS; break; | |
6538 | case 0x37: set_mnemonic(i, "LD"); type=LOAD; break; | |
996cc15d | 6539 | #endif |
ed14d777 | 6540 | case 0x38: set_mnemonic(i, "SC"); type=NI; break; |
6541 | case 0x39: set_mnemonic(i, "SWC1"); type=C1LS; break; | |
71e490c5 | 6542 | #if 0 |
ed14d777 | 6543 | case 0x3C: set_mnemonic(i, "SCD"); type=NI; break; |
6544 | case 0x3D: set_mnemonic(i, "SDC1"); type=C1LS; break; | |
6545 | case 0x3F: set_mnemonic(i, "SD"); type=STORE; break; | |
996cc15d | 6546 | #endif |
ed14d777 | 6547 | case 0x12: set_mnemonic(i, "COP2"); type=NI; |
b9b61529 | 6548 | op2=(source[i]>>21)&0x1f; |
630b122b | 6549 | //if (op2 & 0x10) |
bedfea38 | 6550 | if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns |
c7abc864 | 6551 | if (gte_handlers[source[i]&0x3f]!=NULL) { |
ed14d777 | 6552 | #ifdef DISASM |
bedfea38 | 6553 | if (gte_regnames[source[i]&0x3f]!=NULL) |
6554 | strcpy(insn[i],gte_regnames[source[i]&0x3f]); | |
6555 | else | |
6556 | snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f); | |
ed14d777 | 6557 | #endif |
c7abc864 | 6558 | type=C2OP; |
6559 | } | |
6560 | } | |
6561 | else switch(op2) | |
b9b61529 | 6562 | { |
ed14d777 | 6563 | case 0x00: set_mnemonic(i, "MFC2"); type=COP2; break; |
6564 | case 0x02: set_mnemonic(i, "CFC2"); type=COP2; break; | |
6565 | case 0x04: set_mnemonic(i, "MTC2"); type=COP2; break; | |
6566 | case 0x06: set_mnemonic(i, "CTC2"); type=COP2; break; | |
b9b61529 | 6567 | } |
6568 | break; | |
ed14d777 | 6569 | case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; break; |
6570 | case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; break; | |
6571 | case 0x3B: set_mnemonic(i, "HLECALL"); type=HLECALL; break; | |
6572 | default: set_mnemonic(i, "???"); type=NI; | |
94061aa5 | 6573 | SysPrintf("NI %08x @%08x (%08x)\n", source[i], start + i*4, start); |
90ae6d4e | 6574 | break; |
57871462 | 6575 | } |
630b122b | 6576 | dops[i].itype=type; |
6577 | dops[i].opcode2=op2; | |
57871462 | 6578 | /* Get registers/immediates */ |
ed14d777 | 6579 | dops[i].use_lt1=0; |
bedfea38 | 6580 | gte_rs[i]=gte_rt[i]=0; |
57871462 | 6581 | switch(type) { |
6582 | case LOAD: | |
630b122b | 6583 | dops[i].rs1=(source[i]>>21)&0x1f; |
6584 | dops[i].rs2=0; | |
6585 | dops[i].rt1=(source[i]>>16)&0x1f; | |
6586 | dops[i].rt2=0; | |
57871462 | 6587 | imm[i]=(short)source[i]; |
6588 | break; | |
6589 | case STORE: | |
6590 | case STORELR: | |
630b122b | 6591 | dops[i].rs1=(source[i]>>21)&0x1f; |
6592 | dops[i].rs2=(source[i]>>16)&0x1f; | |
6593 | dops[i].rt1=0; | |
6594 | dops[i].rt2=0; | |
57871462 | 6595 | imm[i]=(short)source[i]; |
57871462 | 6596 | break; |
6597 | case LOADLR: | |
6598 | // LWL/LWR only load part of the register, | |
6599 | // therefore the target register must be treated as a source too | |
630b122b | 6600 | dops[i].rs1=(source[i]>>21)&0x1f; |
6601 | dops[i].rs2=(source[i]>>16)&0x1f; | |
6602 | dops[i].rt1=(source[i]>>16)&0x1f; | |
6603 | dops[i].rt2=0; | |
57871462 | 6604 | imm[i]=(short)source[i]; |
57871462 | 6605 | break; |
6606 | case IMM16: | |
630b122b | 6607 | if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register |
6608 | else dops[i].rs1=(source[i]>>21)&0x1f; | |
6609 | dops[i].rs2=0; | |
6610 | dops[i].rt1=(source[i]>>16)&0x1f; | |
6611 | dops[i].rt2=0; | |
57871462 | 6612 | if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI |
6613 | imm[i]=(unsigned short)source[i]; | |
6614 | }else{ | |
6615 | imm[i]=(short)source[i]; | |
6616 | } | |
57871462 | 6617 | break; |
6618 | case UJUMP: | |
630b122b | 6619 | dops[i].rs1=0; |
6620 | dops[i].rs2=0; | |
6621 | dops[i].rt1=0; | |
6622 | dops[i].rt2=0; | |
57871462 | 6623 | // The JAL instruction writes to r31. |
6624 | if (op&1) { | |
630b122b | 6625 | dops[i].rt1=31; |
57871462 | 6626 | } |
630b122b | 6627 | dops[i].rs2=CCREG; |
57871462 | 6628 | break; |
6629 | case RJUMP: | |
630b122b | 6630 | dops[i].rs1=(source[i]>>21)&0x1f; |
6631 | dops[i].rs2=0; | |
6632 | dops[i].rt1=0; | |
6633 | dops[i].rt2=0; | |
5067f341 | 6634 | // The JALR instruction writes to rd. |
57871462 | 6635 | if (op2&1) { |
630b122b | 6636 | dops[i].rt1=(source[i]>>11)&0x1f; |
57871462 | 6637 | } |
630b122b | 6638 | dops[i].rs2=CCREG; |
57871462 | 6639 | break; |
6640 | case CJUMP: | |
630b122b | 6641 | dops[i].rs1=(source[i]>>21)&0x1f; |
6642 | dops[i].rs2=(source[i]>>16)&0x1f; | |
6643 | dops[i].rt1=0; | |
6644 | dops[i].rt2=0; | |
57871462 | 6645 | if(op&2) { // BGTZ/BLEZ |
630b122b | 6646 | dops[i].rs2=0; |
57871462 | 6647 | } |
57871462 | 6648 | break; |
6649 | case SJUMP: | |
630b122b | 6650 | dops[i].rs1=(source[i]>>21)&0x1f; |
6651 | dops[i].rs2=CCREG; | |
6652 | dops[i].rt1=0; | |
6653 | dops[i].rt2=0; | |
57871462 | 6654 | if(op2&0x10) { // BxxAL |
630b122b | 6655 | dops[i].rt1=31; |
57871462 | 6656 | // NOTE: If the branch is not taken, r31 is still overwritten |
6657 | } | |
57871462 | 6658 | break; |
6659 | case ALU: | |
630b122b | 6660 | dops[i].rs1=(source[i]>>21)&0x1f; // source |
6661 | dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount | |
6662 | dops[i].rt1=(source[i]>>11)&0x1f; // destination | |
6663 | dops[i].rt2=0; | |
57871462 | 6664 | break; |
6665 | case MULTDIV: | |
630b122b | 6666 | dops[i].rs1=(source[i]>>21)&0x1f; // source |
6667 | dops[i].rs2=(source[i]>>16)&0x1f; // divisor | |
6668 | dops[i].rt1=HIREG; | |
6669 | dops[i].rt2=LOREG; | |
57871462 | 6670 | break; |
6671 | case MOV: | |
630b122b | 6672 | dops[i].rs1=0; |
6673 | dops[i].rs2=0; | |
6674 | dops[i].rt1=0; | |
6675 | dops[i].rt2=0; | |
6676 | if(op2==0x10) dops[i].rs1=HIREG; // MFHI | |
6677 | if(op2==0x11) dops[i].rt1=HIREG; // MTHI | |
6678 | if(op2==0x12) dops[i].rs1=LOREG; // MFLO | |
6679 | if(op2==0x13) dops[i].rt1=LOREG; // MTLO | |
6680 | if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx | |
6681 | if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx | |
57871462 | 6682 | break; |
6683 | case SHIFT: | |
630b122b | 6684 | dops[i].rs1=(source[i]>>16)&0x1f; // target of shift |
6685 | dops[i].rs2=(source[i]>>21)&0x1f; // shift amount | |
6686 | dops[i].rt1=(source[i]>>11)&0x1f; // destination | |
6687 | dops[i].rt2=0; | |
57871462 | 6688 | break; |
6689 | case SHIFTIMM: | |
630b122b | 6690 | dops[i].rs1=(source[i]>>16)&0x1f; |
6691 | dops[i].rs2=0; | |
6692 | dops[i].rt1=(source[i]>>11)&0x1f; | |
6693 | dops[i].rt2=0; | |
57871462 | 6694 | imm[i]=(source[i]>>6)&0x1f; |
6695 | // DSxx32 instructions | |
6696 | if(op2>=0x3c) imm[i]|=0x20; | |
57871462 | 6697 | break; |
6698 | case COP0: | |
630b122b | 6699 | dops[i].rs1=0; |
6700 | dops[i].rs2=0; | |
6701 | dops[i].rt1=0; | |
6702 | dops[i].rt2=0; | |
6703 | if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0 | |
6704 | if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0 | |
6705 | if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status | |
6706 | if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET | |
57871462 | 6707 | break; |
6708 | case COP1: | |
630b122b | 6709 | dops[i].rs1=0; |
6710 | dops[i].rs2=0; | |
6711 | dops[i].rt1=0; | |
6712 | dops[i].rt2=0; | |
6713 | if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1 | |
6714 | if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1 | |
6715 | dops[i].rs2=CSREG; | |
57871462 | 6716 | break; |
bedfea38 | 6717 | case COP2: |
630b122b | 6718 | dops[i].rs1=0; |
6719 | dops[i].rs2=0; | |
6720 | dops[i].rt1=0; | |
6721 | dops[i].rt2=0; | |
6722 | if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2 | |
6723 | if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2 | |
6724 | dops[i].rs2=CSREG; | |
bedfea38 | 6725 | int gr=(source[i]>>11)&0x1F; |
6726 | switch(op2) | |
6727 | { | |
6728 | case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2 | |
6729 | case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2 | |
0ff8c62c | 6730 | case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2 |
bedfea38 | 6731 | case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2 |
6732 | } | |
6733 | break; | |
57871462 | 6734 | case C1LS: |
630b122b | 6735 | dops[i].rs1=(source[i]>>21)&0x1F; |
6736 | dops[i].rs2=CSREG; | |
6737 | dops[i].rt1=0; | |
6738 | dops[i].rt2=0; | |
57871462 | 6739 | imm[i]=(short)source[i]; |
6740 | break; | |
b9b61529 | 6741 | case C2LS: |
630b122b | 6742 | dops[i].rs1=(source[i]>>21)&0x1F; |
6743 | dops[i].rs2=0; | |
6744 | dops[i].rt1=0; | |
6745 | dops[i].rt2=0; | |
b9b61529 | 6746 | imm[i]=(short)source[i]; |
bedfea38 | 6747 | if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2 |
6748 | else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2 | |
6749 | break; | |
6750 | case C2OP: | |
630b122b | 6751 | dops[i].rs1=0; |
6752 | dops[i].rs2=0; | |
6753 | dops[i].rt1=0; | |
6754 | dops[i].rt2=0; | |
2167bef6 | 6755 | gte_rs[i]=gte_reg_reads[source[i]&0x3f]; |
6756 | gte_rt[i]=gte_reg_writes[source[i]&0x3f]; | |
6757 | gte_rt[i]|=1ll<<63; // every op changes flags | |
587a5b1c | 6758 | if((source[i]&0x3f)==GTE_MVMVA) { |
6759 | int v = (source[i] >> 15) & 3; | |
6760 | gte_rs[i]&=~0xe3fll; | |
6761 | if(v==3) gte_rs[i]|=0xe00ll; | |
6762 | else gte_rs[i]|=3ll<<(v*2); | |
6763 | } | |
b9b61529 | 6764 | break; |
57871462 | 6765 | case SYSCALL: |
7139f3c8 | 6766 | case HLECALL: |
1e973cb0 | 6767 | case INTCALL: |
630b122b | 6768 | dops[i].rs1=CCREG; |
6769 | dops[i].rs2=0; | |
6770 | dops[i].rt1=0; | |
6771 | dops[i].rt2=0; | |
57871462 | 6772 | break; |
6773 | default: | |
630b122b | 6774 | dops[i].rs1=0; |
6775 | dops[i].rs2=0; | |
6776 | dops[i].rt1=0; | |
6777 | dops[i].rt2=0; | |
57871462 | 6778 | } |
6779 | /* Calculate branch target addresses */ | |
6780 | if(type==UJUMP) | |
6781 | ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4); | |
630b122b | 6782 | else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1)) |
57871462 | 6783 | ba[i]=start+i*4+8; // Ignore never taken branch |
630b122b | 6784 | else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1)) |
57871462 | 6785 | ba[i]=start+i*4+8; // Ignore never taken branch |
630b122b | 6786 | else if(type==CJUMP||type==SJUMP) |
57871462 | 6787 | ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14); |
6788 | else ba[i]=-1; | |
630b122b | 6789 | |
6790 | /* simplify always (not)taken branches */ | |
6791 | if (type == CJUMP && dops[i].rs1 == dops[i].rs2) { | |
6792 | dops[i].rs1 = dops[i].rs2 = 0; | |
6793 | if (!(op & 1)) { | |
6794 | dops[i].itype = type = UJUMP; | |
6795 | dops[i].rs2 = CCREG; | |
6796 | } | |
6797 | } | |
6798 | else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1)) | |
6799 | dops[i].itype = type = UJUMP; | |
6800 | ||
6801 | dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP); | |
6802 | dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0 | |
6803 | dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2 | |
6804 | dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2 | |
6805 | ||
6806 | /* messy cases to just pass over to the interpreter */ | |
6807 | if (i > 0 && dops[i-1].is_jump) { | |
3e535354 | 6808 | int do_in_intrp=0; |
6809 | // branch in delay slot? | |
630b122b | 6810 | if (dops[i].is_jump) { |
3e535354 | 6811 | // don't handle first branch and call interpreter if it's hit |
94061aa5 | 6812 | SysPrintf("branch in delay slot @%08x (%08x)\n", start + i*4, start); |
3e535354 | 6813 | do_in_intrp=1; |
6814 | } | |
6815 | // basic load delay detection | |
630b122b | 6816 | else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) { |
3e535354 | 6817 | int t=(ba[i-1]-start)/4; |
630b122b | 6818 | if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) { |
3e535354 | 6819 | // jump target wants DS result - potential load delay effect |
94061aa5 | 6820 | SysPrintf("load delay @%08x (%08x)\n", start + i*4, start); |
3e535354 | 6821 | do_in_intrp=1; |
630b122b | 6822 | dops[t+1].bt=1; // expected return from interpreter |
3e535354 | 6823 | } |
630b122b | 6824 | else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&& |
6825 | !(i>=3&&dops[i-3].is_jump)) { | |
3e535354 | 6826 | // v0 overwrite like this is a sign of trouble, bail out |
94061aa5 | 6827 | SysPrintf("v0 overwrite @%08x (%08x)\n", start + i*4, start); |
3e535354 | 6828 | do_in_intrp=1; |
6829 | } | |
6830 | } | |
447f5a1d | 6831 | if (do_in_intrp) { |
6832 | memset(&dops[i-1], 0, sizeof(dops[i-1])); | |
6833 | dops[i-1].itype = INTCALL; | |
6834 | dops[i-1].rs1 = CCREG; | |
6835 | ba[i-1] = -1; | |
6836 | done = 2; | |
3e535354 | 6837 | i--; // don't compile the DS |
26869094 | 6838 | } |
3e535354 | 6839 | } |
630b122b | 6840 | |
3e535354 | 6841 | /* Is this the end of the block? */ |
630b122b | 6842 | if (i > 0 && dops[i-1].is_ujump) { |
a46de547 | 6843 | if (dops[i-1].rt1 == 0) { // not jal |
6844 | int found_bbranch = 0, t = (ba[i-1] - start) / 4; | |
6845 | if ((u_int)(t - i) < 64 && start + (t+64)*4 < pagelimit) { | |
6846 | // scan for a branch back to i+1 | |
6847 | for (j = t; j < t + 64; j++) { | |
6848 | int tmpop = source[j] >> 26; | |
6849 | if (tmpop == 1 || ((tmpop & ~3) == 4)) { | |
6850 | int t2 = j + 1 + (int)(signed short)source[j]; | |
6851 | if (t2 == i + 1) { | |
6852 | //printf("blk expand %08x<-%08x\n", start + (i+1)*4, start + j*4); | |
6853 | found_bbranch = 1; | |
6854 | break; | |
6855 | } | |
6856 | } | |
6857 | } | |
6858 | } | |
6859 | if (!found_bbranch) | |
6860 | done = 2; | |
57871462 | 6861 | } |
6862 | else { | |
6863 | if(stop_after_jal) done=1; | |
6864 | // Stop on BREAK | |
6865 | if((source[i+1]&0xfc00003f)==0x0d) done=1; | |
6866 | } | |
6867 | // Don't recompile stuff that's already compiled | |
6868 | if(check_addr(start+i*4+4)) done=1; | |
6869 | // Don't get too close to the limit | |
6870 | if(i>MAXBLOCK/2) done=1; | |
6871 | } | |
467357cc | 6872 | if (dops[i].itype == SYSCALL || dops[i].itype == HLECALL || dops[i].itype == INTCALL) |
6873 | done = stop_after_jal ? 1 : 2; | |
6874 | if (done == 2) { | |
1e973cb0 | 6875 | // Does the block continue due to a branch? |
6876 | for(j=i-1;j>=0;j--) | |
6877 | { | |
2a706964 | 6878 | if(ba[j]==start+i*4) done=j=0; // Branch into delay slot |
1e973cb0 | 6879 | if(ba[j]==start+i*4+4) done=j=0; |
6880 | if(ba[j]==start+i*4+8) done=j=0; | |
6881 | } | |
6882 | } | |
75dec299 | 6883 | //assert(i<MAXBLOCK-1); |
57871462 | 6884 | if(start+i*4==pagelimit-4) done=1; |
6885 | assert(start+i*4<pagelimit); | |
6886 | if (i==MAXBLOCK-1) done=1; | |
6887 | // Stop if we're compiling junk | |
b0163e04 | 6888 | if(dops[i].itype == NI && (++ni_count > 8 || dops[i].opcode == 0x11)) { |
57871462 | 6889 | done=stop_after_jal=1; |
c43b5311 | 6890 | SysPrintf("Disabled speculative precompilation\n"); |
57871462 | 6891 | } |
6892 | } | |
f9e37973 | 6893 | while (i > 0 && dops[i-1].is_jump) |
6894 | i--; | |
6895 | assert(i > 0); | |
6896 | assert(!dops[i-1].is_jump); | |
6897 | slen = i; | |
94061aa5 | 6898 | } |
6899 | ||
6900 | // Basic liveness analysis for MIPS registers | |
6901 | static noinline void pass2_unneeded_regs(int istart,int iend,int r) | |
6902 | { | |
6903 | int i; | |
6904 | uint64_t u,gte_u,b,gte_b; | |
6905 | uint64_t temp_u,temp_gte_u=0; | |
6906 | uint64_t gte_u_unknown=0; | |
6907 | if (HACK_ENABLED(NDHACK_GTE_UNNEEDED)) | |
6908 | gte_u_unknown=~0ll; | |
6909 | if(iend==slen-1) { | |
6910 | u=1; | |
6911 | gte_u=gte_u_unknown; | |
6912 | }else{ | |
6913 | //u=unneeded_reg[iend+1]; | |
6914 | u=1; | |
6915 | gte_u=gte_unneeded[iend+1]; | |
6916 | } | |
6917 | ||
6918 | for (i=iend;i>=istart;i--) | |
6919 | { | |
6920 | //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r); | |
6921 | if(dops[i].is_jump) | |
6922 | { | |
6923 | // If subroutine call, flag return address as a possible branch target | |
6924 | if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1; | |
6925 | ||
6926 | if(ba[i]<start || ba[i]>=(start+slen*4)) | |
6927 | { | |
6928 | // Branch out of this block, flush all regs | |
6929 | u=1; | |
6930 | gte_u=gte_u_unknown; | |
6931 | branch_unneeded_reg[i]=u; | |
6932 | // Merge in delay slot | |
6933 | u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2); | |
6934 | u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); | |
6935 | u|=1; | |
6936 | gte_u|=gte_rt[i+1]; | |
6937 | gte_u&=~gte_rs[i+1]; | |
6938 | } | |
6939 | else | |
6940 | { | |
6941 | // Internal branch, flag target | |
6942 | dops[(ba[i]-start)>>2].bt=1; | |
6943 | if(ba[i]<=start+i*4) { | |
6944 | // Backward branch | |
6945 | if(dops[i].is_ujump) | |
6946 | { | |
6947 | // Unconditional branch | |
6948 | temp_u=1; | |
6949 | temp_gte_u=0; | |
6950 | } else { | |
6951 | // Conditional branch (not taken case) | |
6952 | temp_u=unneeded_reg[i+2]; | |
6953 | temp_gte_u&=gte_unneeded[i+2]; | |
6954 | } | |
6955 | // Merge in delay slot | |
6956 | temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2); | |
6957 | temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); | |
6958 | temp_u|=1; | |
6959 | temp_gte_u|=gte_rt[i+1]; | |
6960 | temp_gte_u&=~gte_rs[i+1]; | |
6961 | temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2); | |
6962 | temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); | |
6963 | temp_u|=1; | |
6964 | temp_gte_u|=gte_rt[i]; | |
6965 | temp_gte_u&=~gte_rs[i]; | |
6966 | unneeded_reg[i]=temp_u; | |
6967 | gte_unneeded[i]=temp_gte_u; | |
6968 | // Only go three levels deep. This recursion can take an | |
6969 | // excessive amount of time if there are a lot of nested loops. | |
6970 | if(r<2) { | |
6971 | pass2_unneeded_regs((ba[i]-start)>>2,i-1,r+1); | |
6972 | }else{ | |
6973 | unneeded_reg[(ba[i]-start)>>2]=1; | |
6974 | gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown; | |
6975 | } | |
6976 | } /*else*/ if(1) { | |
6977 | if (dops[i].is_ujump) | |
6978 | { | |
6979 | // Unconditional branch | |
6980 | u=unneeded_reg[(ba[i]-start)>>2]; | |
6981 | gte_u=gte_unneeded[(ba[i]-start)>>2]; | |
6982 | branch_unneeded_reg[i]=u; | |
6983 | // Merge in delay slot | |
6984 | u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2); | |
6985 | u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); | |
6986 | u|=1; | |
6987 | gte_u|=gte_rt[i+1]; | |
6988 | gte_u&=~gte_rs[i+1]; | |
6989 | } else { | |
6990 | // Conditional branch | |
6991 | b=unneeded_reg[(ba[i]-start)>>2]; | |
6992 | gte_b=gte_unneeded[(ba[i]-start)>>2]; | |
6993 | branch_unneeded_reg[i]=b; | |
6994 | // Branch delay slot | |
6995 | b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2); | |
6996 | b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); | |
6997 | b|=1; | |
6998 | gte_b|=gte_rt[i+1]; | |
6999 | gte_b&=~gte_rs[i+1]; | |
7000 | u&=b; | |
7001 | gte_u&=gte_b; | |
7002 | if(i<slen-1) { | |
7003 | branch_unneeded_reg[i]&=unneeded_reg[i+2]; | |
7004 | } else { | |
7005 | branch_unneeded_reg[i]=1; | |
7006 | } | |
7007 | } | |
7008 | } | |
7009 | } | |
7010 | } | |
7011 | else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL) | |
7012 | { | |
7013 | // SYSCALL instruction (software interrupt) | |
7014 | u=1; | |
7015 | } | |
7016 | else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18) | |
7017 | { | |
7018 | // ERET instruction (return from interrupt) | |
7019 | u=1; | |
7020 | } | |
7021 | //u=1; // DEBUG | |
7022 | // Written registers are unneeded | |
7023 | u|=1LL<<dops[i].rt1; | |
7024 | u|=1LL<<dops[i].rt2; | |
7025 | gte_u|=gte_rt[i]; | |
7026 | // Accessed registers are needed | |
7027 | u&=~(1LL<<dops[i].rs1); | |
7028 | u&=~(1LL<<dops[i].rs2); | |
7029 | gte_u&=~gte_rs[i]; | |
7030 | if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1))) | |
7031 | gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded | |
7032 | // Source-target dependencies | |
7033 | // R0 is always unneeded | |
7034 | u|=1; | |
7035 | // Save it | |
7036 | unneeded_reg[i]=u; | |
7037 | gte_unneeded[i]=gte_u; | |
7038 | /* | |
7039 | printf("ur (%d,%d) %x: ",istart,iend,start+i*4); | |
7040 | printf("U:"); | |
7041 | int r; | |
7042 | for(r=1;r<=CCREG;r++) { | |
7043 | if((unneeded_reg[i]>>r)&1) { | |
7044 | if(r==HIREG) printf(" HI"); | |
7045 | else if(r==LOREG) printf(" LO"); | |
7046 | else printf(" r%d",r); | |
7047 | } | |
7048 | } | |
7049 | printf("\n"); | |
7050 | */ | |
7051 | } | |
7052 | } | |
57871462 | 7053 | |
94061aa5 | 7054 | static noinline void pass3_register_alloc(u_int addr) |
7055 | { | |
57871462 | 7056 | struct regstat current; // Current register allocations/status |
b15d122e | 7057 | clear_all_regs(current.regmap_entry); |
57871462 | 7058 | clear_all_regs(current.regmap); |
b15d122e | 7059 | current.wasdirty = current.dirty = 0; |
7060 | current.u = unneeded_reg[0]; | |
7061 | alloc_reg(¤t, 0, CCREG); | |
7062 | dirty_reg(¤t, CCREG); | |
7063 | current.wasconst = 0; | |
7064 | current.isconst = 0; | |
7065 | current.loadedconst = 0; | |
7066 | current.waswritten = 0; | |
57871462 | 7067 | int ds=0; |
7068 | int cc=0; | |
94061aa5 | 7069 | int hr; |
7070 | int i, j; | |
6ebf4adf | 7071 | |
94061aa5 | 7072 | if (addr & 1) { |
57871462 | 7073 | // First instruction is delay slot |
7074 | cc=-1; | |
630b122b | 7075 | dops[1].bt=1; |
57871462 | 7076 | ds=1; |
7077 | unneeded_reg[0]=1; | |
57871462 | 7078 | current.regmap[HOST_BTREG]=BTREG; |
7079 | } | |
9f51b4b9 | 7080 | |
57871462 | 7081 | for(i=0;i<slen;i++) |
7082 | { | |
630b122b | 7083 | if(dops[i].bt) |
57871462 | 7084 | { |
57871462 | 7085 | for(hr=0;hr<HOST_REGS;hr++) |
7086 | { | |
7087 | // Is this really necessary? | |
7088 | if(current.regmap[hr]==0) current.regmap[hr]=-1; | |
7089 | } | |
7090 | current.isconst=0; | |
27727b63 | 7091 | current.waswritten=0; |
57871462 | 7092 | } |
24385cae | 7093 | |
57871462 | 7094 | memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap)); |
7095 | regs[i].wasconst=current.isconst; | |
57871462 | 7096 | regs[i].wasdirty=current.dirty; |
b15d122e | 7097 | regs[i].dirty=0; |
7098 | regs[i].u=0; | |
7099 | regs[i].isconst=0; | |
8575a877 | 7100 | regs[i].loadedconst=0; |
630b122b | 7101 | if (!dops[i].is_jump) { |
57871462 | 7102 | if(i+1<slen) { |
630b122b | 7103 | current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 7104 | current.u|=1; |
57871462 | 7105 | } else { |
7106 | current.u=1; | |
57871462 | 7107 | } |
7108 | } else { | |
7109 | if(i+1<slen) { | |
630b122b | 7110 | current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2)); |
7111 | current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); | |
57871462 | 7112 | current.u|=1; |
447f5a1d | 7113 | } else { |
7114 | SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4); | |
7115 | abort(); | |
7116 | } | |
57871462 | 7117 | } |
630b122b | 7118 | dops[i].is_ds=ds; |
57871462 | 7119 | if(ds) { |
7120 | ds=0; // Skip delay slot, already allocated as part of branch | |
7121 | // ...but we need to alloc it in case something jumps here | |
7122 | if(i+1<slen) { | |
7123 | current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1]; | |
57871462 | 7124 | }else{ |
7125 | current.u=branch_unneeded_reg[i-1]; | |
57871462 | 7126 | } |
630b122b | 7127 | current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 7128 | current.u|=1; |
57871462 | 7129 | struct regstat temp; |
7130 | memcpy(&temp,¤t,sizeof(current)); | |
7131 | temp.wasdirty=temp.dirty; | |
57871462 | 7132 | // TODO: Take into account unconditional branches, as below |
7133 | delayslot_alloc(&temp,i); | |
7134 | memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap)); | |
7135 | regs[i].wasdirty=temp.wasdirty; | |
57871462 | 7136 | regs[i].dirty=temp.dirty; |
57871462 | 7137 | regs[i].isconst=0; |
7138 | regs[i].wasconst=0; | |
7139 | current.isconst=0; | |
7140 | // Create entry (branch target) regmap | |
7141 | for(hr=0;hr<HOST_REGS;hr++) | |
7142 | { | |
7143 | int r=temp.regmap[hr]; | |
7144 | if(r>=0) { | |
7145 | if(r!=regmap_pre[i][hr]) { | |
7146 | regs[i].regmap_entry[hr]=-1; | |
7147 | } | |
7148 | else | |
7149 | { | |
630b122b | 7150 | assert(r < 64); |
57871462 | 7151 | if((current.u>>r)&1) { |
7152 | regs[i].regmap_entry[hr]=-1; | |
7153 | regs[i].regmap[hr]=-1; | |
7154 | //Don't clear regs in the delay slot as the branch might need them | |
7155 | //current.regmap[hr]=-1; | |
7156 | }else | |
7157 | regs[i].regmap_entry[hr]=r; | |
57871462 | 7158 | } |
7159 | } else { | |
7160 | // First instruction expects CCREG to be allocated | |
9f51b4b9 | 7161 | if(i==0&&hr==HOST_CCREG) |
57871462 | 7162 | regs[i].regmap_entry[hr]=CCREG; |
7163 | else | |
7164 | regs[i].regmap_entry[hr]=-1; | |
7165 | } | |
7166 | } | |
7167 | } | |
7168 | else { // Not delay slot | |
630b122b | 7169 | switch(dops[i].itype) { |
57871462 | 7170 | case UJUMP: |
7171 | //current.isconst=0; // DEBUG | |
7172 | //current.wasconst=0; // DEBUG | |
7173 | //regs[i].wasconst=0; // DEBUG | |
630b122b | 7174 | clear_const(¤t,dops[i].rt1); |
57871462 | 7175 | alloc_cc(¤t,i); |
7176 | dirty_reg(¤t,CCREG); | |
630b122b | 7177 | if (dops[i].rt1==31) { |
57871462 | 7178 | alloc_reg(¤t,i,31); |
7179 | dirty_reg(¤t,31); | |
630b122b | 7180 | //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31); |
7181 | //assert(dops[i+1].rt1!=dops[i].rt1); | |
57871462 | 7182 | #ifdef REG_PREFETCH |
7183 | alloc_reg(¤t,i,PTEMP); | |
7184 | #endif | |
57871462 | 7185 | } |
630b122b | 7186 | dops[i].ooo=1; |
269bb29a | 7187 | delayslot_alloc(¤t,i+1); |
57871462 | 7188 | //current.isconst=0; // DEBUG |
7189 | ds=1; | |
7190 | //printf("i=%d, isconst=%x\n",i,current.isconst); | |
7191 | break; | |
7192 | case RJUMP: | |
7193 | //current.isconst=0; | |
7194 | //current.wasconst=0; | |
7195 | //regs[i].wasconst=0; | |
630b122b | 7196 | clear_const(¤t,dops[i].rs1); |
7197 | clear_const(¤t,dops[i].rt1); | |
57871462 | 7198 | alloc_cc(¤t,i); |
7199 | dirty_reg(¤t,CCREG); | |
630b122b | 7200 | if (!ds_writes_rjump_rs(i)) { |
7201 | alloc_reg(¤t,i,dops[i].rs1); | |
7202 | if (dops[i].rt1!=0) { | |
7203 | alloc_reg(¤t,i,dops[i].rt1); | |
7204 | dirty_reg(¤t,dops[i].rt1); | |
7205 | assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1); | |
7206 | assert(dops[i+1].rt1!=dops[i].rt1); | |
57871462 | 7207 | #ifdef REG_PREFETCH |
7208 | alloc_reg(¤t,i,PTEMP); | |
7209 | #endif | |
7210 | } | |
7211 | #ifdef USE_MINI_HT | |
630b122b | 7212 | if(dops[i].rs1==31) { // JALR |
57871462 | 7213 | alloc_reg(¤t,i,RHASH); |
57871462 | 7214 | alloc_reg(¤t,i,RHTBL); |
57871462 | 7215 | } |
7216 | #endif | |
7217 | delayslot_alloc(¤t,i+1); | |
7218 | } else { | |
7219 | // The delay slot overwrites our source register, | |
7220 | // allocate a temporary register to hold the old value. | |
7221 | current.isconst=0; | |
7222 | current.wasconst=0; | |
7223 | regs[i].wasconst=0; | |
7224 | delayslot_alloc(¤t,i+1); | |
7225 | current.isconst=0; | |
7226 | alloc_reg(¤t,i,RTEMP); | |
7227 | } | |
7228 | //current.isconst=0; // DEBUG | |
630b122b | 7229 | dops[i].ooo=1; |
57871462 | 7230 | ds=1; |
7231 | break; | |
7232 | case CJUMP: | |
7233 | //current.isconst=0; | |
7234 | //current.wasconst=0; | |
7235 | //regs[i].wasconst=0; | |
630b122b | 7236 | clear_const(¤t,dops[i].rs1); |
7237 | clear_const(¤t,dops[i].rs2); | |
7238 | if((dops[i].opcode&0x3E)==4) // BEQ/BNE | |
57871462 | 7239 | { |
7240 | alloc_cc(¤t,i); | |
7241 | dirty_reg(¤t,CCREG); | |
630b122b | 7242 | if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1); |
7243 | if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2); | |
7244 | if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))|| | |
7245 | (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) { | |
57871462 | 7246 | // The delay slot overwrites one of our conditions. |
7247 | // Allocate the branch condition registers instead. | |
57871462 | 7248 | current.isconst=0; |
7249 | current.wasconst=0; | |
7250 | regs[i].wasconst=0; | |
630b122b | 7251 | if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1); |
7252 | if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2); | |
57871462 | 7253 | } |
e1190b87 | 7254 | else |
7255 | { | |
630b122b | 7256 | dops[i].ooo=1; |
e1190b87 | 7257 | delayslot_alloc(¤t,i+1); |
7258 | } | |
57871462 | 7259 | } |
7260 | else | |
630b122b | 7261 | if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ |
57871462 | 7262 | { |
7263 | alloc_cc(¤t,i); | |
7264 | dirty_reg(¤t,CCREG); | |
630b122b | 7265 | alloc_reg(¤t,i,dops[i].rs1); |
7266 | if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) { | |
57871462 | 7267 | // The delay slot overwrites one of our conditions. |
7268 | // Allocate the branch condition registers instead. | |
57871462 | 7269 | current.isconst=0; |
7270 | current.wasconst=0; | |
7271 | regs[i].wasconst=0; | |
630b122b | 7272 | if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1); |
57871462 | 7273 | } |
e1190b87 | 7274 | else |
7275 | { | |
630b122b | 7276 | dops[i].ooo=1; |
e1190b87 | 7277 | delayslot_alloc(¤t,i+1); |
7278 | } | |
57871462 | 7279 | } |
7280 | else | |
7281 | // Don't alloc the delay slot yet because we might not execute it | |
630b122b | 7282 | if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL |
57871462 | 7283 | { |
7284 | current.isconst=0; | |
7285 | current.wasconst=0; | |
7286 | regs[i].wasconst=0; | |
7287 | alloc_cc(¤t,i); | |
7288 | dirty_reg(¤t,CCREG); | |
630b122b | 7289 | alloc_reg(¤t,i,dops[i].rs1); |
7290 | alloc_reg(¤t,i,dops[i].rs2); | |
57871462 | 7291 | } |
7292 | else | |
630b122b | 7293 | if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL |
57871462 | 7294 | { |
7295 | current.isconst=0; | |
7296 | current.wasconst=0; | |
7297 | regs[i].wasconst=0; | |
7298 | alloc_cc(¤t,i); | |
7299 | dirty_reg(¤t,CCREG); | |
630b122b | 7300 | alloc_reg(¤t,i,dops[i].rs1); |
57871462 | 7301 | } |
7302 | ds=1; | |
7303 | //current.isconst=0; | |
7304 | break; | |
7305 | case SJUMP: | |
7306 | //current.isconst=0; | |
7307 | //current.wasconst=0; | |
7308 | //regs[i].wasconst=0; | |
630b122b | 7309 | clear_const(¤t,dops[i].rs1); |
7310 | clear_const(¤t,dops[i].rt1); | |
7311 | //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ | |
7312 | if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ | |
57871462 | 7313 | { |
7314 | alloc_cc(¤t,i); | |
7315 | dirty_reg(¤t,CCREG); | |
630b122b | 7316 | alloc_reg(¤t,i,dops[i].rs1); |
7317 | if (dops[i].rt1==31) { // BLTZAL/BGEZAL | |
57871462 | 7318 | alloc_reg(¤t,i,31); |
7319 | dirty_reg(¤t,31); | |
57871462 | 7320 | //#ifdef REG_PREFETCH |
7321 | //alloc_reg(¤t,i,PTEMP); | |
7322 | //#endif | |
57871462 | 7323 | } |
630b122b | 7324 | if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition. |
7325 | ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra | |
57871462 | 7326 | // Allocate the branch condition registers instead. |
57871462 | 7327 | current.isconst=0; |
7328 | current.wasconst=0; | |
7329 | regs[i].wasconst=0; | |
630b122b | 7330 | if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1); |
57871462 | 7331 | } |
e1190b87 | 7332 | else |
7333 | { | |
630b122b | 7334 | dops[i].ooo=1; |
e1190b87 | 7335 | delayslot_alloc(¤t,i+1); |
7336 | } | |
57871462 | 7337 | } |
7338 | else | |
7339 | // Don't alloc the delay slot yet because we might not execute it | |
630b122b | 7340 | if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL |
57871462 | 7341 | { |
7342 | current.isconst=0; | |
7343 | current.wasconst=0; | |
7344 | regs[i].wasconst=0; | |
7345 | alloc_cc(¤t,i); | |
7346 | dirty_reg(¤t,CCREG); | |
630b122b | 7347 | alloc_reg(¤t,i,dops[i].rs1); |
57871462 | 7348 | } |
7349 | ds=1; | |
7350 | //current.isconst=0; | |
7351 | break; | |
57871462 | 7352 | case IMM16: |
7353 | imm16_alloc(¤t,i); | |
7354 | break; | |
7355 | case LOAD: | |
7356 | case LOADLR: | |
7357 | load_alloc(¤t,i); | |
7358 | break; | |
7359 | case STORE: | |
7360 | case STORELR: | |
7361 | store_alloc(¤t,i); | |
7362 | break; | |
7363 | case ALU: | |
7364 | alu_alloc(¤t,i); | |
7365 | break; | |
7366 | case SHIFT: | |
7367 | shift_alloc(¤t,i); | |
7368 | break; | |
7369 | case MULTDIV: | |
7370 | multdiv_alloc(¤t,i); | |
7371 | break; | |
7372 | case SHIFTIMM: | |
7373 | shiftimm_alloc(¤t,i); | |
7374 | break; | |
7375 | case MOV: | |
7376 | mov_alloc(¤t,i); | |
7377 | break; | |
7378 | case COP0: | |
7379 | cop0_alloc(¤t,i); | |
7380 | break; | |
7381 | case COP1: | |
630b122b | 7382 | break; |
b9b61529 | 7383 | case COP2: |
630b122b | 7384 | cop2_alloc(¤t,i); |
57871462 | 7385 | break; |
7386 | case C1LS: | |
7387 | c1ls_alloc(¤t,i); | |
7388 | break; | |
b9b61529 | 7389 | case C2LS: |
7390 | c2ls_alloc(¤t,i); | |
7391 | break; | |
7392 | case C2OP: | |
7393 | c2op_alloc(¤t,i); | |
7394 | break; | |
57871462 | 7395 | case SYSCALL: |
7139f3c8 | 7396 | case HLECALL: |
1e973cb0 | 7397 | case INTCALL: |
57871462 | 7398 | syscall_alloc(¤t,i); |
7399 | break; | |
57871462 | 7400 | } |
9f51b4b9 | 7401 | |
57871462 | 7402 | // Create entry (branch target) regmap |
7403 | for(hr=0;hr<HOST_REGS;hr++) | |
7404 | { | |
581335b0 | 7405 | int r,or; |
57871462 | 7406 | r=current.regmap[hr]; |
7407 | if(r>=0) { | |
7408 | if(r!=regmap_pre[i][hr]) { | |
7409 | // TODO: delay slot (?) | |
7410 | or=get_reg(regmap_pre[i],r); // Get old mapping for this register | |
91af94f0 | 7411 | if(or<0||r>=TEMPREG){ |
57871462 | 7412 | regs[i].regmap_entry[hr]=-1; |
7413 | } | |
7414 | else | |
7415 | { | |
7416 | // Just move it to a different register | |
7417 | regs[i].regmap_entry[hr]=r; | |
7418 | // If it was dirty before, it's still dirty | |
91af94f0 | 7419 | if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r); |
57871462 | 7420 | } |
7421 | } | |
7422 | else | |
7423 | { | |
7424 | // Unneeded | |
7425 | if(r==0){ | |
7426 | regs[i].regmap_entry[hr]=0; | |
7427 | } | |
7428 | else | |
630b122b | 7429 | { |
7430 | assert(r<64); | |
57871462 | 7431 | if((current.u>>r)&1) { |
7432 | regs[i].regmap_entry[hr]=-1; | |
7433 | //regs[i].regmap[hr]=-1; | |
7434 | current.regmap[hr]=-1; | |
7435 | }else | |
7436 | regs[i].regmap_entry[hr]=r; | |
7437 | } | |
57871462 | 7438 | } |
7439 | } else { | |
7440 | // Branches expect CCREG to be allocated at the target | |
9f51b4b9 | 7441 | if(regmap_pre[i][hr]==CCREG) |
57871462 | 7442 | regs[i].regmap_entry[hr]=CCREG; |
7443 | else | |
7444 | regs[i].regmap_entry[hr]=-1; | |
7445 | } | |
7446 | } | |
7447 | memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap)); | |
7448 | } | |
27727b63 | 7449 | |
630b122b | 7450 | if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800) |
7451 | current.waswritten|=1<<dops[i-1].rs1; | |
7452 | current.waswritten&=~(1<<dops[i].rt1); | |
7453 | current.waswritten&=~(1<<dops[i].rt2); | |
7454 | if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800) | |
7455 | current.waswritten&=~(1<<dops[i].rs1); | |
27727b63 | 7456 | |
57871462 | 7457 | /* Branch post-alloc */ |
7458 | if(i>0) | |
7459 | { | |
57871462 | 7460 | current.wasdirty=current.dirty; |
630b122b | 7461 | switch(dops[i-1].itype) { |
57871462 | 7462 | case UJUMP: |
7463 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
7464 | branch_regs[i-1].isconst=0; | |
7465 | branch_regs[i-1].wasconst=0; | |
630b122b | 7466 | branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2)); |
57871462 | 7467 | alloc_cc(&branch_regs[i-1],i-1); |
7468 | dirty_reg(&branch_regs[i-1],CCREG); | |
630b122b | 7469 | if(dops[i-1].rt1==31) { // JAL |
57871462 | 7470 | alloc_reg(&branch_regs[i-1],i-1,31); |
7471 | dirty_reg(&branch_regs[i-1],31); | |
57871462 | 7472 | } |
7473 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); | |
630b122b | 7474 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 | 7475 | break; |
7476 | case RJUMP: | |
7477 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
7478 | branch_regs[i-1].isconst=0; | |
7479 | branch_regs[i-1].wasconst=0; | |
630b122b | 7480 | branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2)); |
57871462 | 7481 | alloc_cc(&branch_regs[i-1],i-1); |
7482 | dirty_reg(&branch_regs[i-1],CCREG); | |
630b122b | 7483 | alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1); |
7484 | if(dops[i-1].rt1!=0) { // JALR | |
7485 | alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1); | |
7486 | dirty_reg(&branch_regs[i-1],dops[i-1].rt1); | |
57871462 | 7487 | } |
7488 | #ifdef USE_MINI_HT | |
630b122b | 7489 | if(dops[i-1].rs1==31) { // JALR |
57871462 | 7490 | alloc_reg(&branch_regs[i-1],i-1,RHASH); |
57871462 | 7491 | alloc_reg(&branch_regs[i-1],i-1,RHTBL); |
57871462 | 7492 | } |
7493 | #endif | |
7494 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); | |
630b122b | 7495 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 | 7496 | break; |
7497 | case CJUMP: | |
630b122b | 7498 | if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE |
57871462 | 7499 | { |
7500 | alloc_cc(¤t,i-1); | |
7501 | dirty_reg(¤t,CCREG); | |
630b122b | 7502 | if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))|| |
7503 | (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) { | |
57871462 | 7504 | // The delay slot overwrote one of our conditions |
7505 | // Delay slot goes after the test (in order) | |
630b122b | 7506 | current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 7507 | current.u|=1; |
57871462 | 7508 | delayslot_alloc(¤t,i); |
7509 | current.isconst=0; | |
7510 | } | |
7511 | else | |
7512 | { | |
630b122b | 7513 | current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2)); |
57871462 | 7514 | // Alloc the branch condition registers |
630b122b | 7515 | if(dops[i-1].rs1) alloc_reg(¤t,i-1,dops[i-1].rs1); |
7516 | if(dops[i-1].rs2) alloc_reg(¤t,i-1,dops[i-1].rs2); | |
57871462 | 7517 | } |
7518 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
7519 | branch_regs[i-1].isconst=0; | |
7520 | branch_regs[i-1].wasconst=0; | |
7521 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); | |
630b122b | 7522 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 | 7523 | } |
7524 | else | |
630b122b | 7525 | if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ |
57871462 | 7526 | { |
7527 | alloc_cc(¤t,i-1); | |
7528 | dirty_reg(¤t,CCREG); | |
630b122b | 7529 | if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) { |
57871462 | 7530 | // The delay slot overwrote the branch condition |
7531 | // Delay slot goes after the test (in order) | |
630b122b | 7532 | current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 7533 | current.u|=1; |
57871462 | 7534 | delayslot_alloc(¤t,i); |
7535 | current.isconst=0; | |
7536 | } | |
7537 | else | |
7538 | { | |
630b122b | 7539 | current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1); |
57871462 | 7540 | // Alloc the branch condition register |
630b122b | 7541 | alloc_reg(¤t,i-1,dops[i-1].rs1); |
57871462 | 7542 | } |
7543 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
7544 | branch_regs[i-1].isconst=0; | |
7545 | branch_regs[i-1].wasconst=0; | |
7546 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); | |
630b122b | 7547 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 | 7548 | } |
7549 | else | |
7550 | // Alloc the delay slot in case the branch is taken | |
630b122b | 7551 | if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL |
57871462 | 7552 | { |
7553 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
630b122b | 7554 | branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1; |
57871462 | 7555 | alloc_cc(&branch_regs[i-1],i); |
7556 | dirty_reg(&branch_regs[i-1],CCREG); | |
7557 | delayslot_alloc(&branch_regs[i-1],i); | |
7558 | branch_regs[i-1].isconst=0; | |
7559 | alloc_reg(¤t,i,CCREG); // Not taken path | |
7560 | dirty_reg(¤t,CCREG); | |
7561 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); | |
7562 | } | |
7563 | else | |
630b122b | 7564 | if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL |
57871462 | 7565 | { |
7566 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
630b122b | 7567 | branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1; |
57871462 | 7568 | alloc_cc(&branch_regs[i-1],i); |
7569 | dirty_reg(&branch_regs[i-1],CCREG); | |
7570 | delayslot_alloc(&branch_regs[i-1],i); | |
7571 | branch_regs[i-1].isconst=0; | |
7572 | alloc_reg(¤t,i,CCREG); // Not taken path | |
7573 | dirty_reg(¤t,CCREG); | |
7574 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); | |
7575 | } | |
7576 | break; | |
7577 | case SJUMP: | |
630b122b | 7578 | //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ |
7579 | if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ | |
57871462 | 7580 | { |
7581 | alloc_cc(¤t,i-1); | |
7582 | dirty_reg(¤t,CCREG); | |
630b122b | 7583 | if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) { |
57871462 | 7584 | // The delay slot overwrote the branch condition |
7585 | // Delay slot goes after the test (in order) | |
630b122b | 7586 | current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)); |
57871462 | 7587 | current.u|=1; |
57871462 | 7588 | delayslot_alloc(¤t,i); |
7589 | current.isconst=0; | |
7590 | } | |
7591 | else | |
7592 | { | |
630b122b | 7593 | current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1); |
57871462 | 7594 | // Alloc the branch condition register |
630b122b | 7595 | alloc_reg(¤t,i-1,dops[i-1].rs1); |
57871462 | 7596 | } |
7597 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
7598 | branch_regs[i-1].isconst=0; | |
7599 | branch_regs[i-1].wasconst=0; | |
7600 | memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap)); | |
630b122b | 7601 | memcpy(constmap[i],constmap[i-1],sizeof(constmap[i])); |
57871462 | 7602 | } |
7603 | else | |
7604 | // Alloc the delay slot in case the branch is taken | |
630b122b | 7605 | if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL |
57871462 | 7606 | { |
7607 | memcpy(&branch_regs[i-1],¤t,sizeof(current)); | |
630b122b | 7608 | branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1; |
57871462 | 7609 | alloc_cc(&branch_regs[i-1],i); |
7610 | dirty_reg(&branch_regs[i-1],CCREG); | |
7611 | delayslot_alloc(&branch_regs[i-1],i); | |
7612 | branch_regs[i-1].isconst=0; | |
7613 | alloc_reg(¤t,i,CCREG); // Not taken path | |
7614 | dirty_reg(¤t,CCREG); | |
7615 | memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap)); | |
7616 | } | |
7617 | // FIXME: BLTZAL/BGEZAL | |
630b122b | 7618 | if(dops[i-1].opcode2&0x10) { // BxxZAL |
57871462 | 7619 | alloc_reg(&branch_regs[i-1],i-1,31); |
7620 | dirty_reg(&branch_regs[i-1],31); | |
57871462 | 7621 | } |
7622 | break; | |
7623 | } | |
7624 | ||
630b122b | 7625 | if (dops[i-1].is_ujump) |
57871462 | 7626 | { |
630b122b | 7627 | if(dops[i-1].rt1==31) // JAL/JALR |
57871462 | 7628 | { |
7629 | // Subroutine call will return here, don't alloc any registers | |
57871462 | 7630 | current.dirty=0; |
7631 | clear_all_regs(current.regmap); | |
7632 | alloc_reg(¤t,i,CCREG); | |
7633 | dirty_reg(¤t,CCREG); | |
7634 | } | |
7635 | else if(i+1<slen) | |
7636 | { | |
7637 | // Internal branch will jump here, match registers to caller | |
57871462 | 7638 | current.dirty=0; |
7639 | clear_all_regs(current.regmap); | |
7640 | alloc_reg(¤t,i,CCREG); | |
7641 | dirty_reg(¤t,CCREG); | |
7642 | for(j=i-1;j>=0;j--) | |
7643 | { | |
7644 | if(ba[j]==start+i*4+4) { | |
7645 | memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap)); | |
57871462 | 7646 | current.dirty=branch_regs[j].dirty; |
7647 | break; | |
7648 | } | |
7649 | } | |
7650 | while(j>=0) { | |
7651 | if(ba[j]==start+i*4+4) { | |
7652 | for(hr=0;hr<HOST_REGS;hr++) { | |
7653 | if(current.regmap[hr]!=branch_regs[j].regmap[hr]) { | |
7654 | current.regmap[hr]=-1; | |
7655 | } | |
57871462 | 7656 | current.dirty&=branch_regs[j].dirty; |
7657 | } | |
7658 | } | |
7659 | j--; | |
7660 | } | |
7661 | } | |
7662 | } | |
7663 | } | |
7664 | ||
7665 | // Count cycles in between branches | |
630b122b | 7666 | ccadj[i] = CLOCK_ADJUST(cc); |
7667 | if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL)) | |
57871462 | 7668 | { |
7669 | cc=0; | |
7670 | } | |
71e490c5 | 7671 | #if !defined(DRC_DBG) |
630b122b | 7672 | else if(dops[i].itype==C2OP&>e_cycletab[source[i]&0x3f]>2) |
fb407447 | 7673 | { |
630b122b | 7674 | // this should really be removed since the real stalls have been implemented, |
7675 | // but doing so causes sizeable perf regression against the older version | |
7676 | u_int gtec = gte_cycletab[source[i] & 0x3f]; | |
7677 | cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2; | |
fb407447 | 7678 | } |
630b122b | 7679 | else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt) |
5fdcbb5a | 7680 | { |
7681 | cc+=4; | |
7682 | } | |
630b122b | 7683 | else if(dops[i].itype==C2LS) |
fb407447 | 7684 | { |
630b122b | 7685 | // same as with C2OP |
7686 | cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2; | |
fb407447 | 7687 | } |
7688 | #endif | |
57871462 | 7689 | else |
7690 | { | |
7691 | cc++; | |
7692 | } | |
7693 | ||
630b122b | 7694 | if(!dops[i].is_ds) { |
57871462 | 7695 | regs[i].dirty=current.dirty; |
7696 | regs[i].isconst=current.isconst; | |
630b122b | 7697 | memcpy(constmap[i],current_constmap,sizeof(constmap[i])); |
57871462 | 7698 | } |
7699 | for(hr=0;hr<HOST_REGS;hr++) { | |
7700 | if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) { | |
7701 | if(regmap_pre[i][hr]!=regs[i].regmap[hr]) { | |
7702 | regs[i].wasconst&=~(1<<hr); | |
7703 | } | |
7704 | } | |
7705 | } | |
7706 | if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1; | |
27727b63 | 7707 | regs[i].waswritten=current.waswritten; |
57871462 | 7708 | } |
94061aa5 | 7709 | } |
9f51b4b9 | 7710 | |
94061aa5 | 7711 | static noinline void pass4_cull_unused_regs(void) |
7712 | { | |
e912c27d | 7713 | u_int last_needed_regs[4] = {0,0,0,0}; |
94061aa5 | 7714 | u_int nr=0; |
7715 | int i; | |
9f51b4b9 | 7716 | |
57871462 | 7717 | for (i=slen-1;i>=0;i--) |
7718 | { | |
7719 | int hr; | |
e912c27d | 7720 | __builtin_prefetch(regs[i-2].regmap); |
630b122b | 7721 | if(dops[i].is_jump) |
57871462 | 7722 | { |
7723 | if(ba[i]<start || ba[i]>=(start+slen*4)) | |
7724 | { | |
7725 | // Branch out of this block, don't need anything | |
7726 | nr=0; | |
7727 | } | |
7728 | else | |
7729 | { | |
7730 | // Internal branch | |
7731 | // Need whatever matches the target | |
7732 | nr=0; | |
7733 | int t=(ba[i]-start)>>2; | |
7734 | for(hr=0;hr<HOST_REGS;hr++) | |
7735 | { | |
7736 | if(regs[i].regmap_entry[hr]>=0) { | |
7737 | if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr; | |
7738 | } | |
7739 | } | |
7740 | } | |
7741 | // Conditional branch may need registers for following instructions | |
630b122b | 7742 | if (!dops[i].is_ujump) |
57871462 | 7743 | { |
7744 | if(i<slen-2) { | |
e912c27d | 7745 | nr |= last_needed_regs[(i+2) & 3]; |
57871462 | 7746 | for(hr=0;hr<HOST_REGS;hr++) |
7747 | { | |
7748 | if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr); | |
7749 | //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]); | |
7750 | } | |
7751 | } | |
7752 | } | |
7753 | // Don't need stuff which is overwritten | |
f5955059 | 7754 | //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr); |
7755 | //if(regs[i].regmap[hr]<0) nr&=~(1<<hr); | |
57871462 | 7756 | // Merge in delay slot |
e912c27d | 7757 | if (dops[i+1].rt1) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt1); |
7758 | if (dops[i+1].rt2) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt2); | |
7759 | nr |= get_regm(regmap_pre[i], dops[i+1].rs1); | |
7760 | nr |= get_regm(regmap_pre[i], dops[i+1].rs2); | |
7761 | nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs1); | |
7762 | nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs2); | |
7763 | if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) { | |
7764 | nr |= get_regm(regmap_pre[i], ROREG); | |
7765 | nr |= get_regm(regs[i].regmap_entry, ROREG); | |
7766 | } | |
7767 | if (dops[i+1].is_store) { | |
7768 | nr |= get_regm(regmap_pre[i], INVCP); | |
7769 | nr |= get_regm(regs[i].regmap_entry, INVCP); | |
57871462 | 7770 | } |
7771 | } | |
630b122b | 7772 | else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL) |
57871462 | 7773 | { |
7774 | // SYSCALL instruction (software interrupt) | |
7775 | nr=0; | |
7776 | } | |
630b122b | 7777 | else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18) |
57871462 | 7778 | { |
7779 | // ERET instruction (return from interrupt) | |
7780 | nr=0; | |
7781 | } | |
7782 | else // Non-branch | |
7783 | { | |
7784 | if(i<slen-1) { | |
7785 | for(hr=0;hr<HOST_REGS;hr++) { | |
7786 | if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr); | |
7787 | if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr); | |
7788 | if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr); | |
7789 | if(regs[i].regmap[hr]<0) nr&=~(1<<hr); | |
7790 | } | |
7791 | } | |
7792 | } | |
e912c27d | 7793 | // Overwritten registers are not needed |
7794 | if (dops[i].rt1) nr &= ~get_regm(regs[i].regmap, dops[i].rt1); | |
7795 | if (dops[i].rt2) nr &= ~get_regm(regs[i].regmap, dops[i].rt2); | |
7796 | nr &= ~get_regm(regs[i].regmap, FTEMP); | |
7797 | // Source registers are needed | |
7798 | nr |= get_regm(regmap_pre[i], dops[i].rs1); | |
7799 | nr |= get_regm(regmap_pre[i], dops[i].rs2); | |
7800 | nr |= get_regm(regs[i].regmap_entry, dops[i].rs1); | |
7801 | nr |= get_regm(regs[i].regmap_entry, dops[i].rs2); | |
7802 | if (ram_offset && (dops[i].is_load || dops[i].is_store)) { | |
7803 | nr |= get_regm(regmap_pre[i], ROREG); | |
7804 | nr |= get_regm(regs[i].regmap_entry, ROREG); | |
7805 | } | |
7806 | if (dops[i].is_store) { | |
7807 | nr |= get_regm(regmap_pre[i], INVCP); | |
7808 | nr |= get_regm(regs[i].regmap_entry, INVCP); | |
7809 | } | |
7810 | ||
7811 | if (i > 0 && !dops[i].bt && regs[i].wasdirty) | |
57871462 | 7812 | for(hr=0;hr<HOST_REGS;hr++) |
7813 | { | |
57871462 | 7814 | // Don't store a register immediately after writing it, |
7815 | // may prevent dual-issue. | |
7816 | // But do so if this is a branch target, otherwise we | |
7817 | // might have to load the register before the branch. | |
e912c27d | 7818 | if((regs[i].wasdirty>>hr)&1) { |
630b122b | 7819 | if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) { |
91af94f0 | 7820 | if(dops[i-1].rt1==regmap_pre[i][hr]) nr|=1<<hr; |
7821 | if(dops[i-1].rt2==regmap_pre[i][hr]) nr|=1<<hr; | |
57871462 | 7822 | } |
630b122b | 7823 | if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) { |
91af94f0 | 7824 | if(dops[i-1].rt1==regs[i].regmap_entry[hr]) nr|=1<<hr; |
7825 | if(dops[i-1].rt2==regs[i].regmap_entry[hr]) nr|=1<<hr; | |
57871462 | 7826 | } |
7827 | } | |
7828 | } | |
7829 | // Cycle count is needed at branches. Assume it is needed at the target too. | |
f9e37973 | 7830 | if(i==0||dops[i].bt||dops[i].itype==CJUMP) { |
57871462 | 7831 | if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG; |
7832 | if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG; | |
7833 | } | |
7834 | // Save it | |
e912c27d | 7835 | last_needed_regs[i & 3] = nr; |
9f51b4b9 | 7836 | |
57871462 | 7837 | // Deallocate unneeded registers |
7838 | for(hr=0;hr<HOST_REGS;hr++) | |
7839 | { | |
7840 | if(!((nr>>hr)&1)) { | |
7841 | if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1; | |
630b122b | 7842 | if(dops[i].is_jump) |
57871462 | 7843 | { |
630b122b | 7844 | int map1 = 0, map2 = 0, temp = 0; // or -1 ?? |
7845 | if (dops[i+1].is_load || dops[i+1].is_store) | |
7846 | map1 = ROREG; | |
7847 | if (dops[i+1].is_store) | |
7848 | map2 = INVCP; | |
7849 | if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS) | |
7850 | temp = FTEMP; | |
91af94f0 | 7851 | if(regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 && |
7852 | regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 && | |
7853 | regs[i].regmap[hr]!=dops[i+1].rt1 && regs[i].regmap[hr]!=dops[i+1].rt2 && | |
630b122b | 7854 | regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 && |
91af94f0 | 7855 | regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=PTEMP && |
57871462 | 7856 | regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL && |
7857 | regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG && | |
630b122b | 7858 | regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2) |
57871462 | 7859 | { |
7860 | regs[i].regmap[hr]=-1; | |
7861 | regs[i].isconst&=~(1<<hr); | |
214f6f35 | 7862 | regs[i].dirty&=~(1<<hr); |
7863 | regs[i+1].wasdirty&=~(1<<hr); | |
91af94f0 | 7864 | if(branch_regs[i].regmap[hr]!=dops[i].rs1 && branch_regs[i].regmap[hr]!=dops[i].rs2 && |
7865 | branch_regs[i].regmap[hr]!=dops[i].rt1 && branch_regs[i].regmap[hr]!=dops[i].rt2 && | |
7866 | branch_regs[i].regmap[hr]!=dops[i+1].rt1 && branch_regs[i].regmap[hr]!=dops[i+1].rt2 && | |
630b122b | 7867 | branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 && |
91af94f0 | 7868 | branch_regs[i].regmap[hr]!=temp && branch_regs[i].regmap[hr]!=PTEMP && |
57871462 | 7869 | branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL && |
7870 | branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG && | |
630b122b | 7871 | branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2) |
57871462 | 7872 | { |
7873 | branch_regs[i].regmap[hr]=-1; | |
7874 | branch_regs[i].regmap_entry[hr]=-1; | |
630b122b | 7875 | if (!dops[i].is_ujump) |
57871462 | 7876 | { |
630b122b | 7877 | if (i < slen-2) { |
57871462 | 7878 | regmap_pre[i+2][hr]=-1; |
79c75f1b | 7879 | regs[i+2].wasconst&=~(1<<hr); |
57871462 | 7880 | } |
7881 | } | |
7882 | } | |
7883 | } | |
7884 | } | |
7885 | else | |
7886 | { | |
7887 | // Non-branch | |
7888 | if(i>0) | |
7889 | { | |
630b122b | 7890 | int map1 = -1, map2 = -1, temp=-1; |
7891 | if (dops[i].is_load || dops[i].is_store) | |
7892 | map1 = ROREG; | |
7893 | if (dops[i].is_store) | |
7894 | map2 = INVCP; | |
7895 | if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS) | |
7896 | temp = FTEMP; | |
91af94f0 | 7897 | if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 && |
630b122b | 7898 | regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 && |
91af94f0 | 7899 | regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 && |
630b122b | 7900 | //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG) |
7901 | regs[i].regmap[hr] != CCREG) | |
57871462 | 7902 | { |
630b122b | 7903 | if(i<slen-1&&!dops[i].is_ds) { |
7904 | assert(regs[i].regmap[hr]<64); | |
7905 | if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0) | |
57871462 | 7906 | if(regmap_pre[i+1][hr]!=regs[i].regmap[hr]) |
57871462 | 7907 | { |
c43b5311 | 7908 | SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]); |
57871462 | 7909 | assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]); |
7910 | } | |
7911 | regmap_pre[i+1][hr]=-1; | |
7912 | if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1; | |
79c75f1b | 7913 | regs[i+1].wasconst&=~(1<<hr); |
57871462 | 7914 | } |
7915 | regs[i].regmap[hr]=-1; | |
7916 | regs[i].isconst&=~(1<<hr); | |
214f6f35 | 7917 | regs[i].dirty&=~(1<<hr); |
7918 | regs[i+1].wasdirty&=~(1<<hr); | |
57871462 | 7919 | } |
7920 | } | |
7921 | } | |
630b122b | 7922 | } // if needed |
7923 | } // for hr | |
57871462 | 7924 | } |
94061aa5 | 7925 | } |
9f51b4b9 | 7926 | |
94061aa5 | 7927 | // If a register is allocated during a loop, try to allocate it for the |
7928 | // entire loop, if possible. This avoids loading/storing registers | |
7929 | // inside of the loop. | |
7930 | static noinline void pass5a_preallocate1(void) | |
7931 | { | |
7932 | int i, j, hr; | |
57871462 | 7933 | signed char f_regmap[HOST_REGS]; |
7934 | clear_all_regs(f_regmap); | |
7935 | for(i=0;i<slen-1;i++) | |
7936 | { | |
630b122b | 7937 | if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP) |
57871462 | 7938 | { |
9f51b4b9 | 7939 | if(ba[i]>=start && ba[i]<(start+i*4)) |
630b122b | 7940 | if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU |
7941 | ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD | |
7942 | ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS | |
7943 | ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1 | |
7944 | ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP) | |
57871462 | 7945 | { |
7946 | int t=(ba[i]-start)>>2; | |
630b122b | 7947 | if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots |
7948 | if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated | |
57871462 | 7949 | for(hr=0;hr<HOST_REGS;hr++) |
7950 | { | |
630b122b | 7951 | if(regs[i].regmap[hr]>=0) { |
b372a952 | 7952 | if(f_regmap[hr]!=regs[i].regmap[hr]) { |
7953 | // dealloc old register | |
7954 | int n; | |
7955 | for(n=0;n<HOST_REGS;n++) | |
7956 | { | |
7957 | if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;} | |
7958 | } | |
7959 | // and alloc new one | |
7960 | f_regmap[hr]=regs[i].regmap[hr]; | |
7961 | } | |
7962 | } | |
630b122b | 7963 | if(branch_regs[i].regmap[hr]>=0) { |
b372a952 | 7964 | if(f_regmap[hr]!=branch_regs[i].regmap[hr]) { |
7965 | // dealloc old register | |
7966 | int n; | |
7967 | for(n=0;n<HOST_REGS;n++) | |
7968 | { | |
7969 | if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;} | |
7970 | } | |
7971 | // and alloc new one | |
7972 | f_regmap[hr]=branch_regs[i].regmap[hr]; | |
7973 | } | |
7974 | } | |
630b122b | 7975 | if(dops[i].ooo) { |
9f51b4b9 | 7976 | if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) |
e1190b87 | 7977 | f_regmap[hr]=branch_regs[i].regmap[hr]; |
7978 | }else{ | |
9f51b4b9 | 7979 | if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) |
57871462 | 7980 | f_regmap[hr]=branch_regs[i].regmap[hr]; |
7981 | } | |
7982 | // Avoid dirty->clean transition | |
e1190b87 | 7983 | #ifdef DESTRUCTIVE_WRITEBACK |
57871462 | 7984 | if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1; |
e1190b87 | 7985 | #endif |
7986 | // This check is only strictly required in the DESTRUCTIVE_WRITEBACK | |
7987 | // case above, however it's always a good idea. We can't hoist the | |
7988 | // load if the register was already allocated, so there's no point | |
7989 | // wasting time analyzing most of these cases. It only "succeeds" | |
7990 | // when the mapping was different and the load can be replaced with | |
7991 | // a mov, which is of negligible benefit. So such cases are | |
7992 | // skipped below. | |
57871462 | 7993 | if(f_regmap[hr]>0) { |
198df76f | 7994 | if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) { |
57871462 | 7995 | int r=f_regmap[hr]; |
7996 | for(j=t;j<=i;j++) | |
7997 | { | |
7998 | //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r); | |
7999 | if(r<34&&((unneeded_reg[j]>>r)&1)) break; | |
630b122b | 8000 | assert(r < 64); |
91af94f0 | 8001 | if(regs[j].regmap[hr]==f_regmap[hr]&&f_regmap[hr]<TEMPREG) { |
57871462 | 8002 | //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r); |
8003 | int k; | |
8004 | if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) { | |
648d9448 | 8005 | if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break; |
57871462 | 8006 | if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break; |
57871462 | 8007 | k=i; |
8008 | while(k>1&®s[k-1].regmap[hr]==-1) { | |
e1190b87 | 8009 | if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) { |
8010 | //printf("no free regs for store %x\n",start+(k-1)*4); | |
8011 | break; | |
57871462 | 8012 | } |
57871462 | 8013 | if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) { |
8014 | //printf("no-match due to different register\n"); | |
8015 | break; | |
8016 | } | |
630b122b | 8017 | if (dops[k-2].is_jump) { |
57871462 | 8018 | //printf("no-match due to branch\n"); |
8019 | break; | |
8020 | } | |
8021 | // call/ret fast path assumes no registers allocated | |
630b122b | 8022 | if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) { |
57871462 | 8023 | break; |
8024 | } | |
57871462 | 8025 | k--; |
8026 | } | |
57871462 | 8027 | if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) { |
8028 | //printf("Extend r%d, %x ->\n",hr,start+k*4); | |
8029 | while(k<i) { | |
8030 | regs[k].regmap_entry[hr]=f_regmap[hr]; | |
8031 | regs[k].regmap[hr]=f_regmap[hr]; | |
8032 | regmap_pre[k+1][hr]=f_regmap[hr]; | |
8033 | regs[k].wasdirty&=~(1<<hr); | |
8034 | regs[k].dirty&=~(1<<hr); | |
8035 | regs[k].wasdirty|=(1<<hr)®s[k-1].dirty; | |
8036 | regs[k].dirty|=(1<<hr)®s[k].wasdirty; | |
8037 | regs[k].wasconst&=~(1<<hr); | |
8038 | regs[k].isconst&=~(1<<hr); | |
8039 | k++; | |
8040 | } | |
8041 | } | |
8042 | else { | |
8043 | //printf("Fail Extend r%d, %x ->\n",hr,start+k*4); | |
8044 | break; | |
8045 | } | |
8046 | assert(regs[i-1].regmap[hr]==f_regmap[hr]); | |
8047 | if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) { | |
8048 | //printf("OK fill %x (r%d)\n",start+i*4,hr); | |
8049 | regs[i].regmap_entry[hr]=f_regmap[hr]; | |
8050 | regs[i].regmap[hr]=f_regmap[hr]; | |
8051 | regs[i].wasdirty&=~(1<<hr); | |
8052 | regs[i].dirty&=~(1<<hr); | |
8053 | regs[i].wasdirty|=(1<<hr)®s[i-1].dirty; | |
8054 | regs[i].dirty|=(1<<hr)®s[i-1].dirty; | |
8055 | regs[i].wasconst&=~(1<<hr); | |
8056 | regs[i].isconst&=~(1<<hr); | |
8057 | branch_regs[i].regmap_entry[hr]=f_regmap[hr]; | |
8058 | branch_regs[i].wasdirty&=~(1<<hr); | |
8059 | branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty; | |
8060 | branch_regs[i].regmap[hr]=f_regmap[hr]; | |
8061 | branch_regs[i].dirty&=~(1<<hr); | |
8062 | branch_regs[i].dirty|=(1<<hr)®s[i].dirty; | |
8063 | branch_regs[i].wasconst&=~(1<<hr); | |
8064 | branch_regs[i].isconst&=~(1<<hr); | |
630b122b | 8065 | if (!dops[i].is_ujump) { |
57871462 | 8066 | regmap_pre[i+2][hr]=f_regmap[hr]; |
8067 | regs[i+2].wasdirty&=~(1<<hr); | |
8068 | regs[i+2].wasdirty|=(1<<hr)®s[i].dirty; | |
57871462 | 8069 | } |
8070 | } | |
8071 | } | |
8072 | for(k=t;k<j;k++) { | |
e1190b87 | 8073 | // Alloc register clean at beginning of loop, |
8074 | // but may dirty it in pass 6 | |
57871462 | 8075 | regs[k].regmap_entry[hr]=f_regmap[hr]; |
8076 | regs[k].regmap[hr]=f_regmap[hr]; | |
57871462 | 8077 | regs[k].dirty&=~(1<<hr); |
8078 | regs[k].wasconst&=~(1<<hr); | |
8079 | regs[k].isconst&=~(1<<hr); | |
630b122b | 8080 | if (dops[k].is_jump) { |
e1190b87 | 8081 | branch_regs[k].regmap_entry[hr]=f_regmap[hr]; |
8082 | branch_regs[k].regmap[hr]=f_regmap[hr]; | |
8083 | branch_regs[k].dirty&=~(1<<hr); | |
8084 | branch_regs[k].wasconst&=~(1<<hr); | |
8085 | branch_regs[k].isconst&=~(1<<hr); | |
630b122b | 8086 | if (!dops[k].is_ujump) { |
e1190b87 | 8087 | regmap_pre[k+2][hr]=f_regmap[hr]; |
8088 | regs[k+2].wasdirty&=~(1<<hr); | |
e1190b87 | 8089 | } |
8090 | } | |
8091 | else | |
8092 | { | |
8093 | regmap_pre[k+1][hr]=f_regmap[hr]; | |
8094 | regs[k+1].wasdirty&=~(1<<hr); | |
8095 | } | |
57871462 | 8096 | } |
8097 | if(regs[j].regmap[hr]==f_regmap[hr]) | |
8098 | regs[j].regmap_entry[hr]=f_regmap[hr]; | |
8099 | break; | |
8100 | } | |
8101 | if(j==i) break; | |
8102 | if(regs[j].regmap[hr]>=0) | |
8103 | break; | |
8104 | if(get_reg(regs[j].regmap,f_regmap[hr])>=0) { | |
8105 | //printf("no-match due to different register\n"); | |
8106 | break; | |
8107 | } | |
630b122b | 8108 | if (dops[j].is_ujump) |
e1190b87 | 8109 | { |
8110 | // Stop on unconditional branch | |
8111 | break; | |
8112 | } | |
630b122b | 8113 | if(dops[j].itype==CJUMP||dops[j].itype==SJUMP) |
e1190b87 | 8114 | { |
630b122b | 8115 | if(dops[j].ooo) { |
9f51b4b9 | 8116 | if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) |
e1190b87 | 8117 | break; |
8118 | }else{ | |
9f51b4b9 | 8119 | if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) |
e1190b87 | 8120 | break; |
8121 | } | |
8122 | if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) { | |
8123 | //printf("no-match due to different register (branch)\n"); | |
57871462 | 8124 | break; |
8125 | } | |
8126 | } | |
e1190b87 | 8127 | if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) { |
8128 | //printf("No free regs for store %x\n",start+j*4); | |
8129 | break; | |
8130 | } | |
630b122b | 8131 | assert(f_regmap[hr]<64); |
57871462 | 8132 | } |
8133 | } | |
8134 | } | |
8135 | } | |
8136 | } | |
8137 | }else{ | |
198df76f | 8138 | // Non branch or undetermined branch target |
57871462 | 8139 | for(hr=0;hr<HOST_REGS;hr++) |
8140 | { | |
8141 | if(hr!=EXCLUDE_REG) { | |
630b122b | 8142 | if(regs[i].regmap[hr]>=0) { |
b372a952 | 8143 | if(f_regmap[hr]!=regs[i].regmap[hr]) { |
8144 | // dealloc old register | |
8145 | int n; | |
8146 | for(n=0;n<HOST_REGS;n++) | |
8147 | { | |
8148 | if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;} | |
8149 | } | |
94061aa5 | 8150 | // and alloc new one |
8151 | f_regmap[hr]=regs[i].regmap[hr]; | |
8152 | } | |
8153 | } | |
8154 | } | |
8155 | } | |
8156 | // Try to restore cycle count at branch targets | |
8157 | if(dops[i].bt) { | |
8158 | for(j=i;j<slen-1;j++) { | |
8159 | if(regs[j].regmap[HOST_CCREG]!=-1) break; | |
8160 | if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) { | |
8161 | //printf("no free regs for store %x\n",start+j*4); | |
8162 | break; | |
8163 | } | |
8164 | } | |
8165 | if(regs[j].regmap[HOST_CCREG]==CCREG) { | |
8166 | int k=i; | |
8167 | //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4); | |
8168 | while(k<j) { | |
8169 | regs[k].regmap_entry[HOST_CCREG]=CCREG; | |
8170 | regs[k].regmap[HOST_CCREG]=CCREG; | |
8171 | regmap_pre[k+1][HOST_CCREG]=CCREG; | |
8172 | regs[k+1].wasdirty|=1<<HOST_CCREG; | |
8173 | regs[k].dirty|=1<<HOST_CCREG; | |
8174 | regs[k].wasconst&=~(1<<HOST_CCREG); | |
8175 | regs[k].isconst&=~(1<<HOST_CCREG); | |
8176 | k++; | |
8177 | } | |
8178 | regs[j].regmap_entry[HOST_CCREG]=CCREG; | |
8179 | } | |
8180 | // Work backwards from the branch target | |
8181 | if(j>i&&f_regmap[HOST_CCREG]==CCREG) | |
8182 | { | |
8183 | //printf("Extend backwards\n"); | |
8184 | int k; | |
8185 | k=i; | |
8186 | while(regs[k-1].regmap[HOST_CCREG]==-1) { | |
8187 | if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) { | |
8188 | //printf("no free regs for store %x\n",start+(k-1)*4); | |
8189 | break; | |
8190 | } | |
8191 | k--; | |
8192 | } | |
8193 | if(regs[k-1].regmap[HOST_CCREG]==CCREG) { | |
8194 | //printf("Extend CC, %x ->\n",start+k*4); | |
8195 | while(k<=i) { | |
8196 | regs[k].regmap_entry[HOST_CCREG]=CCREG; | |
8197 | regs[k].regmap[HOST_CCREG]=CCREG; | |
8198 | regmap_pre[k+1][HOST_CCREG]=CCREG; | |
8199 | regs[k+1].wasdirty|=1<<HOST_CCREG; | |
8200 | regs[k].dirty|=1<<HOST_CCREG; | |
8201 | regs[k].wasconst&=~(1<<HOST_CCREG); | |
8202 | regs[k].isconst&=~(1<<HOST_CCREG); | |
8203 | k++; | |
8204 | } | |
8205 | } | |
8206 | else { | |
8207 | //printf("Fail Extend CC, %x ->\n",start+k*4); | |
8208 | } | |
8209 | } | |
8210 | } | |
8211 | if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&& | |
8212 | dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&& | |
8213 | dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1) | |
8214 | { | |
8215 | memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap)); | |
8216 | } | |
8217 | } | |
8218 | } | |
8219 | } | |
8220 | ||
8221 | // This allocates registers (if possible) one instruction prior | |
8222 | // to use, which can avoid a load-use penalty on certain CPUs. | |
8223 | static noinline void pass5b_preallocate2(void) | |
8224 | { | |
8225 | int i, hr; | |
8226 | for(i=0;i<slen-1;i++) | |
8227 | { | |
8228 | if (!i || !dops[i-1].is_jump) | |
8229 | { | |
8230 | if(!dops[i+1].bt) | |
8231 | { | |
8232 | if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16 | |
8233 | ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3)) | |
8234 | { | |
8235 | if(dops[i+1].rs1) { | |
8236 | if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0) | |
8237 | { | |
8238 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
8239 | { | |
8240 | regs[i].regmap[hr]=regs[i+1].regmap[hr]; | |
8241 | regmap_pre[i+1][hr]=regs[i+1].regmap[hr]; | |
8242 | regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr]; | |
8243 | regs[i].isconst&=~(1<<hr); | |
8244 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
8245 | constmap[i][hr]=constmap[i+1][hr]; | |
8246 | regs[i+1].wasdirty&=~(1<<hr); | |
8247 | regs[i].dirty&=~(1<<hr); | |
8248 | } | |
8249 | } | |
8250 | } | |
8251 | if(dops[i+1].rs2) { | |
8252 | if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0) | |
8253 | { | |
8254 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
8255 | { | |
8256 | regs[i].regmap[hr]=regs[i+1].regmap[hr]; | |
8257 | regmap_pre[i+1][hr]=regs[i+1].regmap[hr]; | |
8258 | regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr]; | |
8259 | regs[i].isconst&=~(1<<hr); | |
8260 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
8261 | constmap[i][hr]=constmap[i+1][hr]; | |
8262 | regs[i+1].wasdirty&=~(1<<hr); | |
8263 | regs[i].dirty&=~(1<<hr); | |
8264 | } | |
8265 | } | |
8266 | } | |
8267 | // Preload target address for load instruction (non-constant) | |
8268 | if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { | |
8269 | if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0) | |
8270 | { | |
8271 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
8272 | { | |
8273 | regs[i].regmap[hr]=dops[i+1].rs1; | |
8274 | regmap_pre[i+1][hr]=dops[i+1].rs1; | |
8275 | regs[i+1].regmap_entry[hr]=dops[i+1].rs1; | |
8276 | regs[i].isconst&=~(1<<hr); | |
8277 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
8278 | constmap[i][hr]=constmap[i+1][hr]; | |
8279 | regs[i+1].wasdirty&=~(1<<hr); | |
8280 | regs[i].dirty&=~(1<<hr); | |
8281 | } | |
8282 | } | |
8283 | } | |
8284 | // Load source into target register | |
8285 | if(dops[i+1].use_lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { | |
8286 | if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0) | |
8287 | { | |
8288 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
8289 | { | |
8290 | regs[i].regmap[hr]=dops[i+1].rs1; | |
8291 | regmap_pre[i+1][hr]=dops[i+1].rs1; | |
8292 | regs[i+1].regmap_entry[hr]=dops[i+1].rs1; | |
8293 | regs[i].isconst&=~(1<<hr); | |
8294 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
8295 | constmap[i][hr]=constmap[i+1][hr]; | |
8296 | regs[i+1].wasdirty&=~(1<<hr); | |
8297 | regs[i].dirty&=~(1<<hr); | |
8298 | } | |
8299 | } | |
8300 | } | |
8301 | // Address for store instruction (non-constant) | |
8302 | if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR | |
8303 | ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2 | |
8304 | if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { | |
8305 | hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1); | |
8306 | if(hr<0) hr=get_reg_temp(regs[i+1].regmap); | |
8307 | else { | |
8308 | regs[i+1].regmap[hr]=AGEN1+((i+1)&1); | |
8309 | regs[i+1].isconst&=~(1<<hr); | |
8310 | } | |
8311 | assert(hr>=0); | |
8312 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
8313 | { | |
8314 | regs[i].regmap[hr]=dops[i+1].rs1; | |
8315 | regmap_pre[i+1][hr]=dops[i+1].rs1; | |
8316 | regs[i+1].regmap_entry[hr]=dops[i+1].rs1; | |
8317 | regs[i].isconst&=~(1<<hr); | |
8318 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
8319 | constmap[i][hr]=constmap[i+1][hr]; | |
8320 | regs[i+1].wasdirty&=~(1<<hr); | |
8321 | regs[i].dirty&=~(1<<hr); | |
8322 | } | |
8323 | } | |
8324 | } | |
8325 | if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2 | |
8326 | if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { | |
8327 | int nr; | |
8328 | hr=get_reg(regs[i+1].regmap,FTEMP); | |
8329 | assert(hr>=0); | |
8330 | if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) | |
8331 | { | |
8332 | regs[i].regmap[hr]=dops[i+1].rs1; | |
8333 | regmap_pre[i+1][hr]=dops[i+1].rs1; | |
8334 | regs[i+1].regmap_entry[hr]=dops[i+1].rs1; | |
8335 | regs[i].isconst&=~(1<<hr); | |
8336 | regs[i].isconst|=regs[i+1].isconst&(1<<hr); | |
8337 | constmap[i][hr]=constmap[i+1][hr]; | |
8338 | regs[i+1].wasdirty&=~(1<<hr); | |
8339 | regs[i].dirty&=~(1<<hr); | |
8340 | } | |
8341 | else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0) | |
8342 | { | |
8343 | // move it to another register | |
8344 | regs[i+1].regmap[hr]=-1; | |
8345 | regmap_pre[i+2][hr]=-1; | |
8346 | regs[i+1].regmap[nr]=FTEMP; | |
8347 | regmap_pre[i+2][nr]=FTEMP; | |
8348 | regs[i].regmap[nr]=dops[i+1].rs1; | |
8349 | regmap_pre[i+1][nr]=dops[i+1].rs1; | |
8350 | regs[i+1].regmap_entry[nr]=dops[i+1].rs1; | |
8351 | regs[i].isconst&=~(1<<nr); | |
8352 | regs[i+1].isconst&=~(1<<nr); | |
8353 | regs[i].dirty&=~(1<<nr); | |
8354 | regs[i+1].wasdirty&=~(1<<nr); | |
8355 | regs[i+1].dirty&=~(1<<nr); | |
8356 | regs[i+2].wasdirty&=~(1<<nr); | |
8357 | } | |
8358 | } | |
8359 | } | |
8360 | if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) { | |
8361 | hr = -1; | |
8362 | if(dops[i+1].itype==LOAD) | |
8363 | hr=get_reg(regs[i+1].regmap,dops[i+1].rt1); | |
8364 | if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2 | |
8365 | hr=get_reg(regs[i+1].regmap,FTEMP); | |
8366 | if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2 | |
8367 | hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1)); | |
8368 | if(hr<0) hr=get_reg_temp(regs[i+1].regmap); | |
8369 | } | |
8370 | if(hr>=0&®s[i].regmap[hr]<0) { | |
8371 | int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1); | |
8372 | if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) { | |
8373 | regs[i].regmap[hr]=AGEN1+((i+1)&1); | |
8374 | regmap_pre[i+1][hr]=AGEN1+((i+1)&1); | |
8375 | regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1); | |
8376 | regs[i].isconst&=~(1<<hr); | |
8377 | regs[i+1].wasdirty&=~(1<<hr); | |
8378 | regs[i].dirty&=~(1<<hr); | |
8379 | } | |
b372a952 | 8380 | } |
8381 | } | |
57871462 | 8382 | } |
8383 | } | |
94061aa5 | 8384 | } |
8385 | } | |
8386 | } | |
8387 | ||
8388 | // Write back dirty registers as soon as we will no longer modify them, | |
8389 | // so that we don't end up with lots of writes at the branches. | |
8390 | static noinline void pass6_clean_registers(int istart, int iend, int wr) | |
8391 | { | |
e912c27d | 8392 | static u_int wont_dirty[MAXBLOCK]; |
8393 | static u_int will_dirty[MAXBLOCK]; | |
94061aa5 | 8394 | int i; |
8395 | int r; | |
8396 | u_int will_dirty_i,will_dirty_next,temp_will_dirty; | |
8397 | u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty; | |
8398 | if(iend==slen-1) { | |
8399 | will_dirty_i=will_dirty_next=0; | |
8400 | wont_dirty_i=wont_dirty_next=0; | |
8401 | }else{ | |
8402 | will_dirty_i=will_dirty_next=will_dirty[iend+1]; | |
8403 | wont_dirty_i=wont_dirty_next=wont_dirty[iend+1]; | |
8404 | } | |
8405 | for (i=iend;i>=istart;i--) | |
8406 | { | |
8407 | signed char rregmap_i[RRMAP_SIZE]; | |
8408 | u_int hr_candirty = 0; | |
8409 | assert(HOST_REGS < 32); | |
8410 | make_rregs(regs[i].regmap, rregmap_i, &hr_candirty); | |
8411 | __builtin_prefetch(regs[i-1].regmap); | |
8412 | if(dops[i].is_jump) | |
8413 | { | |
8414 | signed char branch_rregmap_i[RRMAP_SIZE]; | |
8415 | u_int branch_hr_candirty = 0; | |
8416 | make_rregs(branch_regs[i].regmap, branch_rregmap_i, &branch_hr_candirty); | |
8417 | if(ba[i]<start || ba[i]>=(start+slen*4)) | |
8418 | { | |
8419 | // Branch out of this block, flush all regs | |
8420 | will_dirty_i = 0; | |
8421 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); | |
8422 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); | |
8423 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); | |
8424 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); | |
8425 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); | |
8426 | will_dirty_i &= branch_hr_candirty; | |
8427 | if (dops[i].is_ujump) | |
8428 | { | |
8429 | // Unconditional branch | |
8430 | wont_dirty_i = 0; | |
8431 | // Merge in delay slot (will dirty) | |
8432 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8433 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8434 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); | |
8435 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); | |
8436 | will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8437 | will_dirty_i &= hr_candirty; | |
57871462 | 8438 | } |
94061aa5 | 8439 | else |
8440 | { | |
8441 | // Conditional branch | |
8442 | wont_dirty_i = wont_dirty_next; | |
8443 | // Merge in delay slot (will dirty) | |
8444 | // (the original code had no explanation why these 2 are commented out) | |
8445 | //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8446 | //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8447 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); | |
8448 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); | |
8449 | will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8450 | will_dirty_i &= hr_candirty; | |
8451 | } | |
8452 | // Merge in delay slot (wont dirty) | |
8453 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8454 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8455 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); | |
8456 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); | |
8457 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8458 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); | |
8459 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); | |
8460 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); | |
8461 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); | |
8462 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); | |
8463 | wont_dirty_i &= ~(1u << 31); | |
8464 | if(wr) { | |
8465 | #ifndef DESTRUCTIVE_WRITEBACK | |
8466 | branch_regs[i].dirty&=wont_dirty_i; | |
8467 | #endif | |
8468 | branch_regs[i].dirty|=will_dirty_i; | |
8469 | } | |
8470 | } | |
8471 | else | |
8472 | { | |
8473 | // Internal branch | |
8474 | if(ba[i]<=start+i*4) { | |
8475 | // Backward branch | |
8476 | if (dops[i].is_ujump) | |
8477 | { | |
8478 | // Unconditional branch | |
8479 | temp_will_dirty=0; | |
8480 | temp_wont_dirty=0; | |
8481 | // Merge in delay slot (will dirty) | |
8482 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); | |
8483 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); | |
8484 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); | |
8485 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); | |
8486 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); | |
8487 | temp_will_dirty &= branch_hr_candirty; | |
8488 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8489 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8490 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); | |
8491 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); | |
8492 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8493 | temp_will_dirty &= hr_candirty; | |
8494 | } else { | |
8495 | // Conditional branch (not taken case) | |
8496 | temp_will_dirty=will_dirty_next; | |
8497 | temp_wont_dirty=wont_dirty_next; | |
8498 | // Merge in delay slot (will dirty) | |
8499 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); | |
8500 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); | |
8501 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); | |
8502 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); | |
8503 | temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); | |
8504 | temp_will_dirty &= branch_hr_candirty; | |
8505 | //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8506 | //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8507 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); | |
8508 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); | |
8509 | temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8510 | temp_will_dirty &= hr_candirty; | |
8511 | } | |
8512 | // Merge in delay slot (wont dirty) | |
8513 | temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8514 | temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8515 | temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); | |
8516 | temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); | |
8517 | temp_wont_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8518 | temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); | |
8519 | temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); | |
8520 | temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); | |
8521 | temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); | |
8522 | temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); | |
8523 | temp_wont_dirty &= ~(1u << 31); | |
8524 | // Deal with changed mappings | |
8525 | if(i<iend) { | |
8526 | for(r=0;r<HOST_REGS;r++) { | |
8527 | if(r!=EXCLUDE_REG) { | |
8528 | if(regs[i].regmap[r]!=regmap_pre[i][r]) { | |
8529 | temp_will_dirty&=~(1<<r); | |
8530 | temp_wont_dirty&=~(1<<r); | |
8531 | if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) { | |
8532 | temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r; | |
8533 | temp_wont_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r; | |
8534 | } else { | |
8535 | temp_will_dirty|=1<<r; | |
8536 | temp_wont_dirty|=1<<r; | |
8537 | } | |
8538 | } | |
8539 | } | |
8540 | } | |
8541 | } | |
8542 | if(wr) { | |
8543 | will_dirty[i]=temp_will_dirty; | |
8544 | wont_dirty[i]=temp_wont_dirty; | |
8545 | pass6_clean_registers((ba[i]-start)>>2,i-1,0); | |
8546 | }else{ | |
8547 | // Limit recursion. It can take an excessive amount | |
8548 | // of time if there are a lot of nested loops. | |
8549 | will_dirty[(ba[i]-start)>>2]=0; | |
8550 | wont_dirty[(ba[i]-start)>>2]=-1; | |
57871462 | 8551 | } |
57871462 | 8552 | } |
94061aa5 | 8553 | /*else*/ if(1) |
57871462 | 8554 | { |
94061aa5 | 8555 | if (dops[i].is_ujump) |
8556 | { | |
8557 | // Unconditional branch | |
8558 | will_dirty_i=0; | |
8559 | wont_dirty_i=0; | |
8560 | //if(ba[i]>start+i*4) { // Disable recursion (for debugging) | |
8561 | for(r=0;r<HOST_REGS;r++) { | |
8562 | if(r!=EXCLUDE_REG) { | |
8563 | if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) { | |
8564 | will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r); | |
8565 | wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r); | |
8566 | } | |
8567 | if(branch_regs[i].regmap[r]>=0) { | |
8568 | will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>branch_regs[i].regmap[r])&1)<<r; | |
8569 | wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>branch_regs[i].regmap[r])&1)<<r; | |
8570 | } | |
8571 | } | |
57871462 | 8572 | } |
94061aa5 | 8573 | //} |
8574 | // Merge in delay slot | |
8575 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); | |
8576 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); | |
8577 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); | |
8578 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); | |
8579 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); | |
8580 | will_dirty_i &= branch_hr_candirty; | |
8581 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8582 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8583 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); | |
8584 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); | |
8585 | will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8586 | will_dirty_i &= hr_candirty; | |
8587 | } else { | |
8588 | // Conditional branch | |
8589 | will_dirty_i=will_dirty_next; | |
8590 | wont_dirty_i=wont_dirty_next; | |
8591 | //if(ba[i]>start+i*4) // Disable recursion (for debugging) | |
8592 | for(r=0;r<HOST_REGS;r++) { | |
8593 | if(r!=EXCLUDE_REG) { | |
8594 | signed char target_reg=branch_regs[i].regmap[r]; | |
8595 | if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) { | |
8596 | will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r); | |
8597 | wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r); | |
8598 | } | |
8599 | else if(target_reg>=0) { | |
8600 | will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>target_reg)&1)<<r; | |
8601 | wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>target_reg)&1)<<r; | |
8602 | } | |
8603 | } | |
57871462 | 8604 | } |
94061aa5 | 8605 | // Merge in delay slot |
8606 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); | |
8607 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); | |
8608 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); | |
8609 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); | |
8610 | will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); | |
8611 | will_dirty_i &= branch_hr_candirty; | |
8612 | //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8613 | //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8614 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); | |
8615 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); | |
8616 | will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8617 | will_dirty_i &= hr_candirty; | |
57871462 | 8618 | } |
94061aa5 | 8619 | // Merge in delay slot (won't dirty) |
8620 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8621 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8622 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); | |
8623 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); | |
8624 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8625 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); | |
8626 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); | |
8627 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); | |
8628 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); | |
8629 | wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); | |
8630 | wont_dirty_i &= ~(1u << 31); | |
8631 | if(wr) { | |
8632 | #ifndef DESTRUCTIVE_WRITEBACK | |
8633 | branch_regs[i].dirty&=wont_dirty_i; | |
8634 | #endif | |
8635 | branch_regs[i].dirty|=will_dirty_i; | |
57871462 | 8636 | } |
8637 | } | |
8638 | } | |
57871462 | 8639 | } |
94061aa5 | 8640 | else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL) |
57871462 | 8641 | { |
94061aa5 | 8642 | // SYSCALL instruction (software interrupt) |
8643 | will_dirty_i=0; | |
8644 | wont_dirty_i=0; | |
8645 | } | |
8646 | else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18) | |
8647 | { | |
8648 | // ERET instruction (return from interrupt) | |
8649 | will_dirty_i=0; | |
8650 | wont_dirty_i=0; | |
8651 | } | |
8652 | will_dirty_next=will_dirty_i; | |
8653 | wont_dirty_next=wont_dirty_i; | |
8654 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8655 | will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8656 | will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8657 | will_dirty_i &= hr_candirty; | |
8658 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); | |
8659 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); | |
8660 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); | |
8661 | wont_dirty_i &= ~(1u << 31); | |
8662 | if (i > istart && !dops[i].is_jump) { | |
8663 | // Don't store a register immediately after writing it, | |
8664 | // may prevent dual-issue. | |
8665 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt1) & 31); | |
8666 | wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt2) & 31); | |
8667 | } | |
8668 | // Save it | |
8669 | will_dirty[i]=will_dirty_i; | |
8670 | wont_dirty[i]=wont_dirty_i; | |
8671 | // Mark registers that won't be dirtied as not dirty | |
8672 | if(wr) { | |
8673 | regs[i].dirty|=will_dirty_i; | |
8674 | #ifndef DESTRUCTIVE_WRITEBACK | |
8675 | regs[i].dirty&=wont_dirty_i; | |
8676 | if(dops[i].is_jump) | |
57871462 | 8677 | { |
94061aa5 | 8678 | if (i < iend-1 && !dops[i].is_ujump) { |
8679 | for(r=0;r<HOST_REGS;r++) { | |
8680 | if(r!=EXCLUDE_REG) { | |
8681 | if(regs[i].regmap[r]==regmap_pre[i+2][r]) { | |
8682 | regs[i+2].wasdirty&=wont_dirty_i|~(1<<r); | |
8683 | }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/} | |
57871462 | 8684 | } |
8685 | } | |
8686 | } | |
94061aa5 | 8687 | } |
8688 | else | |
8689 | { | |
8690 | if(i<iend) { | |
8691 | for(r=0;r<HOST_REGS;r++) { | |
8692 | if(r!=EXCLUDE_REG) { | |
8693 | if(regs[i].regmap[r]==regmap_pre[i+1][r]) { | |
8694 | regs[i+1].wasdirty&=wont_dirty_i|~(1<<r); | |
8695 | }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/} | |
57871462 | 8696 | } |
8697 | } | |
8698 | } | |
94061aa5 | 8699 | } |
8700 | #endif | |
8701 | } | |
8702 | // Deal with changed mappings | |
8703 | temp_will_dirty=will_dirty_i; | |
8704 | temp_wont_dirty=wont_dirty_i; | |
8705 | for(r=0;r<HOST_REGS;r++) { | |
8706 | if(r!=EXCLUDE_REG) { | |
8707 | int nr; | |
8708 | if(regs[i].regmap[r]==regmap_pre[i][r]) { | |
8709 | if(wr) { | |
8710 | #ifndef DESTRUCTIVE_WRITEBACK | |
8711 | regs[i].wasdirty&=wont_dirty_i|~(1<<r); | |
8712 | #endif | |
8713 | regs[i].wasdirty|=will_dirty_i&(1<<r); | |
57871462 | 8714 | } |
94061aa5 | 8715 | } |
8716 | else if(regmap_pre[i][r]>=0&&(nr=get_rreg(rregmap_i,regmap_pre[i][r]))>=0) { | |
8717 | // Register moved to a different register | |
8718 | will_dirty_i&=~(1<<r); | |
8719 | wont_dirty_i&=~(1<<r); | |
8720 | will_dirty_i|=((temp_will_dirty>>nr)&1)<<r; | |
8721 | wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r; | |
8722 | if(wr) { | |
8723 | #ifndef DESTRUCTIVE_WRITEBACK | |
8724 | regs[i].wasdirty&=wont_dirty_i|~(1<<r); | |
8725 | #endif | |
8726 | regs[i].wasdirty|=will_dirty_i&(1<<r); | |
8727 | } | |
8728 | } | |
8729 | else { | |
8730 | will_dirty_i&=~(1<<r); | |
8731 | wont_dirty_i&=~(1<<r); | |
8732 | if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) { | |
8733 | will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r; | |
8734 | wont_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r; | |
8735 | } else { | |
8736 | wont_dirty_i|=1<<r; | |
8737 | /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/ | |
57871462 | 8738 | } |
8739 | } | |
8740 | } | |
8741 | } | |
8742 | } | |
94061aa5 | 8743 | } |
8744 | ||
8745 | static noinline void pass10_expire_blocks(void) | |
8746 | { | |
432435ea | 8747 | u_int step = MAX_OUTPUT_BLOCK_SIZE / PAGE_COUNT / 2; |
8748 | // not sizeof(ndrc->translation_cache) due to vita hack | |
8749 | u_int step_mask = ((1u << TARGET_SIZE_2) - 1u) & ~(step - 1u); | |
8750 | u_int end = (out - ndrc->translation_cache + EXPIRITY_OFFSET) & step_mask; | |
8751 | u_int base_shift = __builtin_ctz(MAX_OUTPUT_BLOCK_SIZE); | |
8752 | int hit; | |
8753 | ||
8754 | for (; expirep != end; expirep = ((expirep + step) & step_mask)) | |
94061aa5 | 8755 | { |
432435ea | 8756 | u_int base_offs = expirep & ~(MAX_OUTPUT_BLOCK_SIZE - 1); |
8757 | u_int block_i = expirep / step & (PAGE_COUNT - 1); | |
8758 | u_int phase = (expirep >> (base_shift - 1)) & 1u; | |
8759 | if (!(expirep & (MAX_OUTPUT_BLOCK_SIZE / 2 - 1))) { | |
8760 | inv_debug("EXP: base_offs %x/%x phase %u\n", base_offs, | |
8761 | out - ndrc->translation_cache phase); | |
8762 | } | |
8763 | ||
8764 | if (!phase) { | |
8765 | hit = blocks_remove_matching_addrs(&blocks[block_i], base_offs, base_shift); | |
8766 | if (hit) { | |
8767 | do_clear_cache(); | |
8768 | #ifdef USE_MINI_HT | |
8769 | memset(mini_ht, -1, sizeof(mini_ht)); | |
8770 | #endif | |
8771 | } | |
94061aa5 | 8772 | } |
432435ea | 8773 | else |
366d1d2b | 8774 | unlink_jumps_tc_range(jumps[block_i], base_offs, base_shift); |
94061aa5 | 8775 | } |
8776 | } | |
8777 | ||
048fcced | 8778 | static struct block_info *new_block_info(u_int start, u_int len, |
8779 | const void *source, const void *copy, u_char *beginning, u_short jump_in_count) | |
8780 | { | |
8781 | struct block_info **b_pptr; | |
8782 | struct block_info *block; | |
8783 | u_int page = get_page(start); | |
8784 | ||
8785 | block = malloc(sizeof(*block) + jump_in_count * sizeof(block->jump_in[0])); | |
8786 | assert(block); | |
8787 | assert(jump_in_count > 0); | |
8788 | block->source = source; | |
8789 | block->copy = copy; | |
8790 | block->start = start; | |
8791 | block->len = len; | |
8792 | block->reg_sv_flags = 0; | |
8793 | block->tc_offs = beginning - ndrc->translation_cache; | |
8794 | //block->tc_len = out - beginning; | |
8795 | block->is_dirty = 0; | |
8796 | block->jump_in_cnt = jump_in_count; | |
8797 | ||
432435ea | 8798 | // insert sorted by start mirror-unmasked vaddr |
048fcced | 8799 | for (b_pptr = &blocks[page]; ; b_pptr = &((*b_pptr)->next)) { |
8800 | if (*b_pptr == NULL || (*b_pptr)->start >= start) { | |
8801 | block->next = *b_pptr; | |
8802 | *b_pptr = block; | |
8803 | break; | |
8804 | } | |
8805 | } | |
8806 | stat_inc(stat_blocks); | |
8807 | return block; | |
8808 | } | |
8809 | ||
8810 | static int new_recompile_block(u_int addr) | |
94061aa5 | 8811 | { |
8812 | u_int pagelimit = 0; | |
8813 | u_int state_rflags = 0; | |
8814 | int i; | |
8815 | ||
8816 | assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out); | |
8817 | ||
8818 | // this is just for speculation | |
8819 | for (i = 1; i < 32; i++) { | |
8820 | if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000) | |
8821 | state_rflags |= 1 << i; | |
8822 | } | |
8823 | ||
f9e37973 | 8824 | assert(!(addr & 3)); |
8825 | start = addr & ~3; | |
94061aa5 | 8826 | new_dynarec_did_compile=1; |
8827 | if (Config.HLE && start == 0x80001000) // hlecall | |
8828 | { | |
8829 | // XXX: is this enough? Maybe check hleSoftCall? | |
048fcced | 8830 | void *beginning = start_block(); |
94061aa5 | 8831 | |
94061aa5 | 8832 | emit_movimm(start,0); |
8833 | emit_writeword(0,&pcaddr); | |
8834 | emit_far_jump(new_dyna_leave); | |
8835 | literal_pool(0); | |
8836 | end_block(beginning); | |
048fcced | 8837 | struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1); |
8838 | block->jump_in[0].vaddr = start; | |
8839 | block->jump_in[0].addr = beginning; | |
94061aa5 | 8840 | return 0; |
8841 | } | |
8842 | else if (f1_hack && hack_addr == 0) { | |
8843 | void *beginning = start_block(); | |
94061aa5 | 8844 | emit_movimm(start, 0); |
8845 | emit_writeword(0, &hack_addr); | |
8846 | emit_readword(&psxRegs.GPR.n.sp, 0); | |
8847 | emit_readptr(&mem_rtab, 1); | |
8848 | emit_shrimm(0, 12, 2); | |
8849 | emit_readptr_dualindexedx_ptrlen(1, 2, 1); | |
8850 | emit_addimm(0, 0x18, 0); | |
8851 | emit_adds_ptr(1, 1, 1); | |
8852 | emit_ldr_dualindexed(1, 0, 0); | |
8853 | emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp) | |
048fcced | 8854 | emit_far_call(ndrc_get_addr_ht); |
94061aa5 | 8855 | emit_jmpreg(0); // jr k0 |
8856 | literal_pool(0); | |
8857 | end_block(beginning); | |
8858 | ||
048fcced | 8859 | struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1); |
8860 | block->jump_in[0].vaddr = start; | |
8861 | block->jump_in[0].addr = beginning; | |
94061aa5 | 8862 | SysPrintf("F1 hack to %08x\n", start); |
8863 | return 0; | |
8864 | } | |
8865 | ||
8866 | cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT | |
8867 | ? cycle_multiplier_override : cycle_multiplier; | |
8868 | ||
8869 | source = get_source_start(start, &pagelimit); | |
8870 | if (source == NULL) { | |
8871 | if (addr != hack_addr) { | |
8872 | SysPrintf("Compile at bogus memory address: %08x\n", addr); | |
8873 | hack_addr = addr; | |
8874 | } | |
8875 | //abort(); | |
8876 | return -1; | |
8877 | } | |
8878 | ||
8879 | /* Pass 1: disassemble */ | |
8880 | /* Pass 2: register dependencies, branch targets */ | |
8881 | /* Pass 3: register allocation */ | |
8882 | /* Pass 4: branch dependencies */ | |
8883 | /* Pass 5: pre-alloc */ | |
8884 | /* Pass 6: optimize clean/dirty state */ | |
8885 | /* Pass 7: flag 32-bit registers */ | |
8886 | /* Pass 8: assembly */ | |
8887 | /* Pass 9: linker */ | |
8888 | /* Pass 10: garbage collection / free memory */ | |
8889 | ||
8890 | /* Pass 1 disassembly */ | |
8891 | ||
8892 | pass1_disassemble(pagelimit); | |
8893 | ||
8894 | int clear_hack_addr = apply_hacks(); | |
8895 | ||
8896 | /* Pass 2 - Register dependencies and branch targets */ | |
8897 | ||
8898 | pass2_unneeded_regs(0,slen-1,0); | |
8899 | ||
8900 | /* Pass 3 - Register allocation */ | |
8901 | ||
8902 | pass3_register_alloc(addr); | |
8903 | ||
8904 | /* Pass 4 - Cull unused host registers */ | |
8905 | ||
8906 | pass4_cull_unused_regs(); | |
8907 | ||
8908 | /* Pass 5 - Pre-allocate registers */ | |
8909 | ||
8910 | pass5a_preallocate1(); | |
8911 | pass5b_preallocate2(); | |
9f51b4b9 | 8912 | |
57871462 | 8913 | /* Pass 6 - Optimize clean/dirty state */ |
94061aa5 | 8914 | pass6_clean_registers(0, slen-1, 1); |
9f51b4b9 | 8915 | |
57871462 | 8916 | /* Pass 7 - Identify 32-bit registers */ |
04fd948a | 8917 | for (i=slen-1;i>=0;i--) |
8918 | { | |
630b122b | 8919 | if(dops[i].itype==CJUMP||dops[i].itype==SJUMP) |
04fd948a | 8920 | { |
8921 | // Conditional branch | |
8922 | if((source[i]>>16)!=0x1000&&i<slen-2) { | |
8923 | // Mark this address as a branch target since it may be called | |
8924 | // upon return from interrupt | |
630b122b | 8925 | dops[i+2].bt=1; |
04fd948a | 8926 | } |
8927 | } | |
8928 | } | |
57871462 | 8929 | |
57871462 | 8930 | /* Pass 8 - Assembly */ |
8931 | linkcount=0;stubcount=0; | |
94061aa5 | 8932 | is_delayslot=0; |
57871462 | 8933 | u_int dirty_pre=0; |
d148d265 | 8934 | void *beginning=start_block(); |
630b122b | 8935 | void *instr_addr0_override = NULL; |
f9e37973 | 8936 | int ds = 0; |
9ad4d757 | 8937 | |
9ad4d757 | 8938 | if (start == 0x80030000) { |
630b122b | 8939 | // nasty hack for the fastbios thing |
96186eba | 8940 | // override block entry to this code |
630b122b | 8941 | instr_addr0_override = out; |
9ad4d757 | 8942 | emit_movimm(start,0); |
96186eba | 8943 | // abuse io address var as a flag that we |
8944 | // have already returned here once | |
630b122b | 8945 | emit_readword(&address,1); |
8946 | emit_writeword(0,&pcaddr); | |
8947 | emit_writeword(0,&address); | |
9ad4d757 | 8948 | emit_cmp(0,1); |
630b122b | 8949 | #ifdef __aarch64__ |
8950 | emit_jeq(out + 4*2); | |
8951 | emit_far_jump(new_dyna_leave); | |
8952 | #else | |
8953 | emit_jne(new_dyna_leave); | |
8954 | #endif | |
9ad4d757 | 8955 | } |
57871462 | 8956 | for(i=0;i<slen;i++) |
8957 | { | |
91af94f0 | 8958 | __builtin_prefetch(regs[i+1].regmap); |
648d9448 | 8959 | check_regmap(regmap_pre[i]); |
8960 | check_regmap(regs[i].regmap_entry); | |
8961 | check_regmap(regs[i].regmap); | |
57871462 | 8962 | //if(ds) printf("ds: "); |
4600ba03 | 8963 | disassemble_inst(i); |
57871462 | 8964 | if(ds) { |
8965 | ds=0; // Skip delay slot | |
630b122b | 8966 | if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n"); |
8967 | instr_addr[i] = NULL; | |
57871462 | 8968 | } else { |
ffb0b9e0 | 8969 | speculate_register_values(i); |
57871462 | 8970 | #ifndef DESTRUCTIVE_WRITEBACK |
630b122b | 8971 | if (i < 2 || !dops[i-2].is_ujump) |
57871462 | 8972 | { |
630b122b | 8973 | wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]); |
57871462 | 8974 | } |
630b122b | 8975 | if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) { |
f776eb14 | 8976 | dirty_pre=branch_regs[i].dirty; |
8977 | }else{ | |
f776eb14 | 8978 | dirty_pre=regs[i].dirty; |
8979 | } | |
57871462 | 8980 | #endif |
8981 | // write back | |
630b122b | 8982 | if (i < 2 || !dops[i-2].is_ujump) |
57871462 | 8983 | { |
630b122b | 8984 | wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]); |
57871462 | 8985 | loop_preload(regmap_pre[i],regs[i].regmap_entry); |
8986 | } | |
8987 | // branch target entry point | |
630b122b | 8988 | instr_addr[i] = out; |
57871462 | 8989 | assem_debug("<->\n"); |
630b122b | 8990 | drc_dbg_emit_do_cmp(i, ccadj[i]); |
7c8454e3 | 8991 | if (clear_hack_addr) { |
8992 | emit_movimm(0, 0); | |
8993 | emit_writeword(0, &hack_addr); | |
8994 | clear_hack_addr = 0; | |
8995 | } | |
630b122b | 8996 | |
57871462 | 8997 | // load regs |
8998 | if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG) | |
630b122b | 8999 | wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty); |
9000 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2); | |
57871462 | 9001 | address_generation(i,®s[i],regs[i].regmap_entry); |
630b122b | 9002 | load_consts(regmap_pre[i],regs[i].regmap,i); |
9003 | if(dops[i].is_jump) | |
57871462 | 9004 | { |
9005 | // Load the delay slot registers if necessary | |
630b122b | 9006 | if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0)) |
9007 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1); | |
9008 | if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0)) | |
9009 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2); | |
9010 | if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) | |
e912c27d | 9011 | load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG); |
630b122b | 9012 | if (dops[i+1].is_store) |
e912c27d | 9013 | load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP); |
57871462 | 9014 | } |
9015 | else if(i+1<slen) | |
9016 | { | |
9017 | // Preload registers for following instruction | |
630b122b | 9018 | if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2) |
9019 | if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2) | |
9020 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1); | |
9021 | if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2) | |
9022 | if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2) | |
9023 | load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2); | |
57871462 | 9024 | } |
9025 | // TODO: if(is_ooo(i)) address_generation(i+1); | |
630b122b | 9026 | if (!dops[i].is_jump || dops[i].itype == CJUMP) |
e912c27d | 9027 | load_reg(regs[i].regmap_entry,regs[i].regmap,CCREG); |
630b122b | 9028 | if (ram_offset && (dops[i].is_load || dops[i].is_store)) |
e912c27d | 9029 | load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG); |
630b122b | 9030 | if (dops[i].is_store) |
e912c27d | 9031 | load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP); |
630b122b | 9032 | |
9033 | ds = assemble(i, ®s[i], ccadj[i]); | |
9034 | ||
9035 | if (dops[i].is_ujump) | |
57871462 | 9036 | literal_pool(1024); |
9037 | else | |
9038 | literal_pool_jumpover(256); | |
9039 | } | |
9040 | } | |
630b122b | 9041 | |
9042 | assert(slen > 0); | |
9043 | if (slen > 0 && dops[slen-1].itype == INTCALL) { | |
9044 | // no ending needed for this block since INTCALL never returns | |
9045 | } | |
57871462 | 9046 | // If the block did not end with an unconditional branch, |
9047 | // add a jump to the next instruction. | |
630b122b | 9048 | else if (i > 1) { |
f9e37973 | 9049 | if (!dops[i-2].is_ujump) { |
630b122b | 9050 | assert(!dops[i-1].is_jump); |
57871462 | 9051 | assert(i==slen); |
630b122b | 9052 | if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) { |
9053 | store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4); | |
57871462 | 9054 | if(regs[i-1].regmap[HOST_CCREG]!=CCREG) |
9055 | emit_loadreg(CCREG,HOST_CCREG); | |
630b122b | 9056 | emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG); |
57871462 | 9057 | } |
9058 | else | |
9059 | { | |
630b122b | 9060 | store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4); |
9061 | assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG); | |
57871462 | 9062 | } |
630b122b | 9063 | add_to_linker(out,start+i*4,0); |
57871462 | 9064 | emit_jmp(0); |
9065 | } | |
9066 | } | |
9067 | else | |
9068 | { | |
9069 | assert(i>0); | |
630b122b | 9070 | assert(!dops[i-1].is_jump); |
9071 | store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4); | |
57871462 | 9072 | if(regs[i-1].regmap[HOST_CCREG]!=CCREG) |
9073 | emit_loadreg(CCREG,HOST_CCREG); | |
630b122b | 9074 | emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG); |
9075 | add_to_linker(out,start+i*4,0); | |
57871462 | 9076 | emit_jmp(0); |
9077 | } | |
9078 | ||
9079 | // TODO: delay slot stubs? | |
9080 | // Stubs | |
9081 | for(i=0;i<stubcount;i++) | |
9082 | { | |
630b122b | 9083 | switch(stubs[i].type) |
57871462 | 9084 | { |
9085 | case LOADB_STUB: | |
9086 | case LOADH_STUB: | |
9087 | case LOADW_STUB: | |
9088 | case LOADD_STUB: | |
9089 | case LOADBU_STUB: | |
9090 | case LOADHU_STUB: | |
9091 | do_readstub(i);break; | |
9092 | case STOREB_STUB: | |
9093 | case STOREH_STUB: | |
9094 | case STOREW_STUB: | |
9095 | case STORED_STUB: | |
9096 | do_writestub(i);break; | |
9097 | case CC_STUB: | |
9098 | do_ccstub(i);break; | |
9099 | case INVCODE_STUB: | |
9100 | do_invstub(i);break; | |
9101 | case FP_STUB: | |
9102 | do_cop1stub(i);break; | |
9103 | case STORELR_STUB: | |
9104 | do_unalignedwritestub(i);break; | |
9105 | } | |
9106 | } | |
9107 | ||
9ad4d757 | 9108 | if (instr_addr0_override) |
9109 | instr_addr[0] = instr_addr0_override; | |
9110 | ||
432435ea | 9111 | #if 0 |
9112 | /* check for improper expiration */ | |
9113 | for (i = 0; i < ARRAY_SIZE(jumps); i++) { | |
9114 | int j; | |
9115 | if (!jumps[i]) | |
9116 | continue; | |
9117 | for (j = 0; j < jumps[i]->count; j++) | |
9118 | assert(jumps[i]->e[j].stub < beginning || (u_char *)jumps[i]->e[j].stub > out); | |
9119 | } | |
9120 | #endif | |
9121 | ||
57871462 | 9122 | /* Pass 9 - Linker */ |
9123 | for(i=0;i<linkcount;i++) | |
9124 | { | |
630b122b | 9125 | assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target); |
57871462 | 9126 | literal_pool(64); |
048fcced | 9127 | if (!link_addr[i].internal) |
57871462 | 9128 | { |
630b122b | 9129 | void *stub = out; |
9130 | void *addr = check_addr(link_addr[i].target); | |
9131 | emit_extjump(link_addr[i].addr, link_addr[i].target); | |
9132 | if (addr) { | |
9133 | set_jump_target(link_addr[i].addr, addr); | |
048fcced | 9134 | ndrc_add_jump_out(link_addr[i].target,stub); |
57871462 | 9135 | } |
630b122b | 9136 | else |
9137 | set_jump_target(link_addr[i].addr, stub); | |
57871462 | 9138 | } |
9139 | else | |
9140 | { | |
9141 | // Internal branch | |
630b122b | 9142 | int target=(link_addr[i].target-start)>>2; |
57871462 | 9143 | assert(target>=0&&target<slen); |
9144 | assert(instr_addr[target]); | |
9145 | //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
630b122b | 9146 | //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1); |
57871462 | 9147 | //#else |
630b122b | 9148 | set_jump_target(link_addr[i].addr, instr_addr[target]); |
57871462 | 9149 | //#endif |
9150 | } | |
9151 | } | |
630b122b | 9152 | |
9153 | u_int source_len = slen*4; | |
9154 | if (dops[slen-1].itype == INTCALL && source_len > 4) | |
9155 | // no need to treat the last instruction as compiled | |
9156 | // as interpreter fully handles it | |
9157 | source_len -= 4; | |
9158 | ||
9159 | if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow)) | |
9160 | copy = shadow; | |
9161 | ||
57871462 | 9162 | // External Branch Targets (jump_in) |
048fcced | 9163 | int jump_in_count = 1; |
9164 | assert(instr_addr[0]); | |
9165 | for (i = 1; i < slen; i++) | |
9166 | { | |
9167 | if (dops[i].bt && instr_addr[i]) | |
9168 | jump_in_count++; | |
9169 | } | |
9170 | ||
9171 | struct block_info *block = | |
9172 | new_block_info(start, slen * 4, source, copy, beginning, jump_in_count); | |
9173 | block->reg_sv_flags = state_rflags; | |
9174 | ||
9175 | int jump_in_i = 0; | |
9176 | for (i = 0; i < slen; i++) | |
57871462 | 9177 | { |
048fcced | 9178 | if ((i == 0 || dops[i].bt) && instr_addr[i]) |
57871462 | 9179 | { |
048fcced | 9180 | assem_debug("%p (%d) <- %8x\n", instr_addr[i], i, start + i*4); |
9181 | u_int vaddr = start + i*4; | |
9182 | ||
9183 | literal_pool(256); | |
9184 | void *entry = out; | |
9185 | load_regs_entry(i); | |
9186 | if (entry == out) | |
9187 | entry = instr_addr[i]; | |
9188 | else | |
9189 | emit_jmp(instr_addr[i]); | |
9190 | ||
9191 | block->jump_in[jump_in_i].vaddr = vaddr; | |
9192 | block->jump_in[jump_in_i].addr = entry; | |
9193 | jump_in_i++; | |
57871462 | 9194 | } |
9195 | } | |
048fcced | 9196 | assert(jump_in_i == jump_in_count); |
9197 | hash_table_add(block->jump_in[0].vaddr, block->jump_in[0].addr); | |
57871462 | 9198 | // Write out the literal pool if necessary |
9199 | literal_pool(0); | |
9200 | #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK | |
9201 | // Align code | |
9202 | if(((u_int)out)&7) emit_addnop(13); | |
9203 | #endif | |
630b122b | 9204 | assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE); |
9205 | //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4); | |
9206 | memcpy(copy, source, source_len); | |
9207 | copy += source_len; | |
9f51b4b9 | 9208 | |
d148d265 | 9209 | end_block(beginning); |
9f51b4b9 | 9210 | |
57871462 | 9211 | // If we're within 256K of the end of the buffer, |
9212 | // start over from the beginning. (Is 256K enough?) | |
630b122b | 9213 | if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE) |
9214 | out = ndrc->translation_cache; | |
9f51b4b9 | 9215 | |
57871462 | 9216 | // Trap writes to any of the pages we compiled |
048fcced | 9217 | mark_invalid_code(start, slen*4, 0); |
9f51b4b9 | 9218 | |
57871462 | 9219 | /* Pass 10 - Free memory by expiring oldest blocks */ |
9f51b4b9 | 9220 | |
94061aa5 | 9221 | pass10_expire_blocks(); |
9222 | ||
630b122b | 9223 | #ifdef ASSEM_PRINT |
9224 | fflush(stdout); | |
9225 | #endif | |
55cadc36 | 9226 | stat_inc(stat_bc_direct); |
57871462 | 9227 | return 0; |
9228 | } | |
b9b61529 | 9229 | |
9230 | // vim:shiftwidth=2:expandtab |