7e605697 |
1 | /* |
274c4243 |
2 | * (C) GraÅžvydas "notaz" Ignotas, 2010-2011 |
7e605697 |
3 | * |
4 | * This work is licensed under the terms of GNU GPL version 2 or later. |
5 | * See the COPYING file in the top-level directory. |
6 | */ |
7 | |
8 | #include <stdio.h> |
9 | #include "../psxhw.h" |
10 | #include "../cdrom.h" |
11 | #include "../mdec.h" |
ddbaf678 |
12 | #include "../gpu.h" |
87e5b45f |
13 | #include "../psxmem_map.h" |
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14 | #include "emu_if.h" |
15 | #include "pcsxmem.h" |
16 | |
5905989e |
17 | #ifdef __thumb__ |
9f704290 |
18 | #error the dynarec is incompatible with Thumb functions, |
19 | #error please add -marm to compile flags |
5905989e |
20 | #endif |
21 | |
7e605697 |
22 | //#define memprintf printf |
23 | #define memprintf(...) |
24 | |
b1be1eee |
25 | static u32 *mem_readtab; |
26 | static u32 *mem_writetab; |
27 | static u32 mem_iortab[(1+2+4) * 0x1000 / 4]; |
28 | static u32 mem_iowtab[(1+2+4) * 0x1000 / 4]; |
29 | static u32 mem_ffwtab[(1+2+4) * 0x1000 / 4]; |
30 | //static u32 mem_unmrtab[(1+2+4) * 0x1000 / 4]; |
31 | static u32 mem_unmwtab[(1+2+4) * 0x1000 / 4]; |
32 | |
33 | static void map_item(u32 *out, const void *h, u32 flag) |
34 | { |
35 | u32 hv = (u32)h; |
5905989e |
36 | if (hv & 1) { |
f29fbd53 |
37 | SysPrintf("FATAL: %p has LSB set\n", h); |
5905989e |
38 | abort(); |
39 | } |
b1be1eee |
40 | *out = (hv >> 1) | (flag << 31); |
41 | } |
42 | |
43 | // size must be power of 2, at least 4k |
44 | #define map_l1_mem(tab, i, addr, size, base) \ |
45 | map_item(&tab[((addr)>>12) + i], (u8 *)(base) - (u32)(addr) - ((i << 12) & ~(size - 1)), 0) |
46 | |
47 | #define IOMEM32(a) (((a) & 0xfff) / 4) |
48 | #define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2)) |
49 | #define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff)) |
50 | |
054175e9 |
51 | u8 zero_mem[0x1000]; |
7a481d40 |
52 | |
63cb0298 |
53 | u32 read_mem_dummy() |
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54 | { |
63cb0298 |
55 | return 0; |
7e605697 |
56 | } |
57 | |
b96d3df7 |
58 | static void write_mem_dummy(u32 data) |
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59 | { |
b96d3df7 |
60 | memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle); |
7e605697 |
61 | } |
62 | |
7e605697 |
63 | /* IO handlers */ |
64 | static u32 io_read_sio16() |
65 | { |
66 | return sioRead8() | (sioRead8() << 8); |
67 | } |
68 | |
69 | static u32 io_read_sio32() |
70 | { |
71 | return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24); |
72 | } |
73 | |
74 | static void io_write_sio16(u32 value) |
75 | { |
76 | sioWrite8((unsigned char)value); |
77 | sioWrite8((unsigned char)(value>>8)); |
78 | } |
79 | |
80 | static void io_write_sio32(u32 value) |
81 | { |
82 | sioWrite8((unsigned char)value); |
b96d3df7 |
83 | sioWrite8((unsigned char)(value >> 8)); |
84 | sioWrite8((unsigned char)(value >> 16)); |
85 | sioWrite8((unsigned char)(value >> 24)); |
7e605697 |
86 | } |
87 | |
19776aef |
88 | #ifndef DRC_DBG |
89 | |
b1be1eee |
90 | static void map_rcnt_rcount0(u32 mode) |
91 | { |
59fb0bb4 |
92 | if (mode & 0x100) { // pixel clock |
b1be1eee |
93 | map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1); |
94 | map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1); |
95 | } |
96 | else { |
97 | map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1); |
98 | map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1); |
99 | } |
100 | } |
101 | |
102 | static void map_rcnt_rcount1(u32 mode) |
103 | { |
59fb0bb4 |
104 | if (mode & 0x100) { // hcnt |
b1be1eee |
105 | map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1); |
106 | map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1); |
107 | } |
108 | else { |
109 | map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1); |
110 | map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1); |
111 | } |
112 | } |
113 | |
114 | static void map_rcnt_rcount2(u32 mode) |
115 | { |
116 | if (mode & 0x01) { // gate |
117 | map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0); |
118 | map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0); |
119 | } |
120 | else if (mode & 0x200) { // clk/8 |
121 | map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1); |
122 | map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1); |
123 | } |
124 | else { |
125 | map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1); |
126 | map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1); |
127 | } |
128 | } |
129 | |
19776aef |
130 | #else |
131 | #define map_rcnt_rcount0(mode) |
132 | #define map_rcnt_rcount1(mode) |
133 | #define map_rcnt_rcount2(mode) |
134 | #endif |
135 | |
7e605697 |
136 | #define make_rcnt_funcs(i) \ |
137 | static u32 io_rcnt_read_count##i() { return psxRcntRcount(i); } \ |
138 | static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \ |
139 | static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \ |
140 | static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \ |
b1be1eee |
141 | static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \ |
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142 | static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); } |
143 | |
144 | make_rcnt_funcs(0) |
145 | make_rcnt_funcs(1) |
146 | make_rcnt_funcs(2) |
147 | |
148 | static void io_write_ireg16(u32 value) |
149 | { |
9705788a |
150 | //if (Config.Sio) psxHu16ref(0x1070) |= 0x80; |
7e605697 |
151 | if (Config.SpuIrq) psxHu16ref(0x1070) |= 0x200; |
9705788a |
152 | psxHu16ref(0x1070) &= value; |
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153 | } |
154 | |
155 | static void io_write_imask16(u32 value) |
156 | { |
157 | psxHu16ref(0x1074) = value; |
158 | if (psxHu16ref(0x1070) & value) |
d28b54b1 |
159 | new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1); |
7e605697 |
160 | } |
161 | |
162 | static void io_write_ireg32(u32 value) |
163 | { |
9705788a |
164 | //if (Config.Sio) psxHu32ref(0x1070) |= 0x80; |
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165 | if (Config.SpuIrq) psxHu32ref(0x1070) |= 0x200; |
9705788a |
166 | psxHu32ref(0x1070) &= value; |
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167 | } |
168 | |
169 | static void io_write_imask32(u32 value) |
170 | { |
171 | psxHu32ref(0x1074) = value; |
172 | if (psxHu32ref(0x1070) & value) |
d28b54b1 |
173 | new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1); |
7e605697 |
174 | } |
175 | |
176 | static void io_write_dma_icr32(u32 value) |
177 | { |
1f77c863 |
178 | u32 tmp = value & 0x00ff803f; |
179 | tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000; |
180 | if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000) |
181 | || tmp & HW_DMA_ICR_BUS_ERROR) { |
182 | if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT)) |
183 | psxHu32ref(0x1070) |= SWAP32(8); |
184 | tmp |= HW_DMA_ICR_IRQ_SENT; |
185 | } |
186 | HW_DMA_ICR = SWAPu32(tmp); |
7e605697 |
187 | } |
188 | |
189 | #define make_dma_func(n) \ |
190 | static void io_write_chcr##n(u32 value) \ |
191 | { \ |
192 | HW_DMA##n##_CHCR = value; \ |
193 | if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \ |
194 | psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \ |
195 | } \ |
196 | } |
197 | |
198 | make_dma_func(0) |
199 | make_dma_func(1) |
200 | make_dma_func(2) |
201 | make_dma_func(3) |
202 | make_dma_func(4) |
203 | make_dma_func(6) |
204 | |
b96d3df7 |
205 | static void io_spu_write16(u32 value) |
206 | { |
207 | // meh |
208 | SPU_writeRegister(address, value); |
209 | } |
210 | |
211 | static void io_spu_write32(u32 value) |
212 | { |
213 | SPUwriteRegister wfunc = SPU_writeRegister; |
214 | u32 a = address; |
215 | |
216 | wfunc(a, value & 0xffff); |
217 | wfunc(a + 2, value >> 16); |
218 | } |
219 | |
ddbaf678 |
220 | static u32 io_gpu_read_status(void) |
221 | { |
0486fdc9 |
222 | u32 v; |
223 | |
ddbaf678 |
224 | // meh2, syncing for img bit, might want to avoid it.. |
225 | gpuSyncPluginSR(); |
0486fdc9 |
226 | v = HW_GPU_STATUS; |
227 | |
228 | // XXX: because of large timeslices can't use hSyncCount, using rough |
229 | // approximization instead. Perhaps better use hcounter code here or something. |
230 | if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS) |
231 | v |= PSXGPU_LCF & (psxRegs.cycle << 20); |
232 | return v; |
ddbaf678 |
233 | } |
234 | |
235 | static void io_gpu_write_status(u32 value) |
236 | { |
237 | GPU_writeStatus(value); |
238 | gpuSyncPluginSR(); |
239 | } |
240 | |
b96d3df7 |
241 | static void map_ram_write(void) |
242 | { |
243 | int i; |
244 | |
245 | for (i = 0; i < (0x800000 >> 12); i++) { |
246 | map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM); |
247 | map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM); |
248 | map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM); |
249 | } |
250 | } |
251 | |
252 | static void unmap_ram_write(void) |
253 | { |
254 | int i; |
255 | |
256 | for (i = 0; i < (0x800000 >> 12); i++) { |
257 | map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1); |
258 | map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1); |
259 | map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1); |
260 | } |
261 | } |
262 | |
263 | static void write_biu(u32 value) |
264 | { |
265 | memprintf("write_biu %08x, %08x @%08x %u\n", address, value, psxRegs.pc, psxRegs.cycle); |
266 | |
267 | if (address != 0xfffe0130) |
268 | return; |
269 | |
270 | switch (value) { |
271 | case 0x800: case 0x804: |
272 | unmap_ram_write(); |
273 | break; |
274 | case 0: case 0x1e988: |
275 | map_ram_write(); |
276 | break; |
277 | default: |
278 | printf("write_biu: unexpected val: %08x\n", value); |
279 | break; |
280 | } |
281 | } |
282 | |
b1be1eee |
283 | void new_dyna_pcsx_mem_load_state(void) |
284 | { |
285 | map_rcnt_rcount0(rcnts[0].mode); |
286 | map_rcnt_rcount1(rcnts[1].mode); |
287 | map_rcnt_rcount2(rcnts[2].mode); |
288 | } |
289 | |
290 | int pcsxmem_is_handler_dynamic(u_int addr) |
291 | { |
292 | if ((addr & 0xfffff000) != 0x1f801000) |
293 | return 0; |
294 | |
295 | addr &= 0xffff; |
296 | return addr == 0x1100 || addr == 0x1110 || addr == 0x1120; |
297 | } |
298 | |
7e605697 |
299 | void new_dyna_pcsx_mem_init(void) |
300 | { |
301 | int i; |
63cb0298 |
302 | |
c6c3b1b3 |
303 | // have to map these further to keep tcache close to .text |
87e5b45f |
304 | mem_readtab = psxMap(0x08000000, 0x200000 * 4, 0, MAP_TAG_LUTS); |
305 | if (mem_readtab == NULL) { |
f29fbd53 |
306 | SysPrintf("failed to map mem tables\n"); |
c6c3b1b3 |
307 | exit(1); |
308 | } |
309 | mem_writetab = mem_readtab + 0x100000; |
310 | |
311 | // 1st level lookup: |
312 | // 0: direct mem |
313 | // 1: use 2nd lookup |
314 | // 2nd level lookup: |
315 | // 0: direct mem variable |
316 | // 1: memhandler |
317 | |
318 | // default/unmapped memhandlers |
319 | for (i = 0; i < 0x100000; i++) { |
320 | //map_item(&mem_readtab[i], mem_unmrtab, 1); |
054175e9 |
321 | map_l1_mem(mem_readtab, i, 0, 0x1000, zero_mem); |
c6c3b1b3 |
322 | map_item(&mem_writetab[i], mem_unmwtab, 1); |
323 | } |
324 | |
325 | // RAM and it's mirrors |
326 | for (i = 0; i < (0x800000 >> 12); i++) { |
327 | map_l1_mem(mem_readtab, i, 0x80000000, 0x200000, psxM); |
c6c3b1b3 |
328 | map_l1_mem(mem_readtab, i, 0x00000000, 0x200000, psxM); |
c6c3b1b3 |
329 | map_l1_mem(mem_readtab, i, 0xa0000000, 0x200000, psxM); |
c6c3b1b3 |
330 | } |
b96d3df7 |
331 | map_ram_write(); |
c6c3b1b3 |
332 | |
333 | // BIOS and it's mirrors |
334 | for (i = 0; i < (0x80000 >> 12); i++) { |
335 | map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR); |
336 | map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR); |
337 | } |
338 | |
339 | // scratchpad |
340 | map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH); |
9dd7d179 |
341 | map_l1_mem(mem_readtab, 0, 0x9f800000, 0x1000, psxH); |
c6c3b1b3 |
342 | map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH); |
9dd7d179 |
343 | map_l1_mem(mem_writetab, 0, 0x9f800000, 0x1000, psxH); |
c6c3b1b3 |
344 | |
345 | // I/O |
346 | map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1); |
9dd7d179 |
347 | map_item(&mem_readtab[0x9f801000 >> 12], mem_iortab, 1); |
348 | map_item(&mem_readtab[0xbf801000 >> 12], mem_iortab, 1); |
c6c3b1b3 |
349 | map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1); |
9dd7d179 |
350 | map_item(&mem_writetab[0x9f801000 >> 12], mem_iowtab, 1); |
351 | map_item(&mem_writetab[0xbf801000 >> 12], mem_iowtab, 1); |
7e605697 |
352 | |
c6c3b1b3 |
353 | // L2 |
354 | // unmapped tables |
b96d3df7 |
355 | for (i = 0; i < (1+2+4) * 0x1000 / 4; i++) |
c6c3b1b3 |
356 | map_item(&mem_unmwtab[i], write_mem_dummy, 1); |
357 | |
358 | // fill IO tables |
359 | for (i = 0; i < 0x1000/4; i++) { |
360 | map_item(&mem_iortab[i], &psxH[0x1000], 0); |
361 | map_item(&mem_iowtab[i], &psxH[0x1000], 0); |
362 | } |
363 | for (; i < 0x1000/4 + 0x1000/2; i++) { |
364 | map_item(&mem_iortab[i], &psxH[0x1000], 0); |
365 | map_item(&mem_iowtab[i], &psxH[0x1000], 0); |
366 | } |
367 | for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) { |
368 | map_item(&mem_iortab[i], &psxH[0x1000], 0); |
369 | map_item(&mem_iowtab[i], &psxH[0x1000], 0); |
370 | } |
371 | |
372 | map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1); |
373 | map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1); |
374 | map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1); |
375 | map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1); |
376 | map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1); |
377 | map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1); |
378 | map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1); |
379 | map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1); |
380 | map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1); |
381 | map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1); |
382 | // map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1); |
ddbaf678 |
383 | map_item(&mem_iortab[IOMEM32(0x1814)], io_gpu_read_status, 1); |
c6c3b1b3 |
384 | map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1); |
385 | map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1); |
386 | |
387 | map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1); |
388 | map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1); |
389 | map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1); |
390 | map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1); |
391 | map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1); |
392 | map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1); |
393 | map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1); |
394 | map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1); |
395 | map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1); |
396 | map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1); |
397 | map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1); |
398 | map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1); |
399 | map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1); |
400 | map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1); |
401 | |
402 | map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1); |
403 | map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1); |
404 | map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1); |
405 | map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1); |
406 | map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1); |
407 | |
b96d3df7 |
408 | // write(u32 data) |
409 | map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1); |
410 | map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1); |
411 | map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1); |
412 | map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1); |
413 | map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1); |
414 | map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1); |
415 | map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1); |
416 | map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1); |
417 | map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1); |
418 | map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1); |
419 | map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1); |
420 | map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1); |
421 | map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1); |
422 | map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1); |
423 | map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1); |
424 | map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1); |
425 | map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1); |
426 | map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1); |
427 | map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1); |
428 | // map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1); |
ddbaf678 |
429 | map_item(&mem_iowtab[IOMEM32(0x1814)], io_gpu_write_status, 1); |
b96d3df7 |
430 | map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1); |
431 | map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1); |
432 | |
433 | map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1); |
434 | map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1); |
435 | map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1); |
436 | map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1); |
437 | map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1); |
438 | map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1); |
439 | map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1); |
440 | map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1); |
441 | map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1); |
442 | map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1); |
443 | map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1); |
444 | map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1); |
445 | map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1); |
446 | map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1); |
447 | map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1); |
448 | map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1); |
449 | |
450 | map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1); |
451 | map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1); |
452 | map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1); |
453 | map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1); |
454 | map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1); |
455 | |
456 | for (i = 0x1c00; i < 0x1e00; i += 2) { |
457 | map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1); |
458 | map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1); |
459 | } |
460 | |
461 | // misc |
462 | map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1); |
463 | for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) |
464 | map_item(&mem_ffwtab[i], write_biu, 1); |
465 | |
c6c3b1b3 |
466 | mem_rtab = mem_readtab; |
467 | mem_wtab = mem_writetab; |
b1be1eee |
468 | |
469 | new_dyna_pcsx_mem_load_state(); |
7e605697 |
470 | } |
471 | |
472 | void new_dyna_pcsx_mem_reset(void) |
473 | { |
c6c3b1b3 |
474 | int i; |
475 | |
7e605697 |
476 | // plugins might change so update the pointers |
c6c3b1b3 |
477 | map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1); |
c6c3b1b3 |
478 | |
479 | for (i = 0x1c00; i < 0x1e00; i += 2) |
480 | map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1); |
481 | |
b96d3df7 |
482 | map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1); |
7e605697 |
483 | } |
92879b62 |
484 | |
485 | void new_dyna_pcsx_mem_shutdown(void) |
486 | { |
487 | psxUnmap(mem_readtab, 0x200000 * 4, MAP_TAG_LUTS); |
488 | mem_writetab = mem_readtab = NULL; |
489 | } |