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ef79bbde P |
1 | /*************************************************************************** |
2 | * Copyright (C) 2010 by Blade_Arma * | |
3 | * * | |
4 | * This program is free software; you can redistribute it and/or modify * | |
5 | * it under the terms of the GNU General Public License as published by * | |
6 | * the Free Software Foundation; either version 2 of the License, or * | |
7 | * (at your option) any later version. * | |
8 | * * | |
9 | * This program is distributed in the hope that it will be useful, * | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
12 | * GNU General Public License for more details. * | |
13 | * * | |
14 | * You should have received a copy of the GNU General Public License * | |
15 | * along with this program; if not, write to the * | |
16 | * Free Software Foundation, Inc., * | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * | |
18 | ***************************************************************************/ | |
19 | ||
20 | /* | |
21 | * Internal PSX counters. | |
22 | */ | |
23 | ||
24 | #include "psxcounters.h" | |
c6a249e3 | 25 | #include "psxevents.h" |
ddbaf678 | 26 | #include "gpu.h" |
5b568098 | 27 | //#include "debug.h" |
28 | #define DebugVSync() | |
ef79bbde P |
29 | |
30 | /******************************************************************************/ | |
31 | ||
ef79bbde P |
32 | enum |
33 | { | |
d3d41455 | 34 | RcSyncModeEnable = 0x0001, // 0 |
35 | Rc01BlankPause = 0 << 1, // 1,2 | |
36 | Rc01UnblankReset = 1 << 1, // 1,2 | |
37 | Rc01UnblankReset2 = 2 << 1, // 1,2 | |
38 | Rc2Stop = 0 << 1, // 1,2 | |
39 | Rc2Stop2 = 3 << 1, // 1,2 | |
ef79bbde P |
40 | RcCountToTarget = 0x0008, // 3 |
41 | RcIrqOnTarget = 0x0010, // 4 | |
42 | RcIrqOnOverflow = 0x0020, // 5 | |
43 | RcIrqRegenerate = 0x0040, // 6 | |
44 | RcUnknown7 = 0x0080, // 7 ? | |
45 | Rc0PixelClock = 0x0100, // 8 fake implementation | |
46 | Rc1HSyncClock = 0x0100, // 8 | |
47 | Rc2Unknown8 = 0x0100, // 8 ? | |
48 | Rc0Unknown9 = 0x0200, // 9 ? | |
49 | Rc1Unknown9 = 0x0200, // 9 ? | |
50 | Rc2OneEighthClock = 0x0200, // 9 | |
51 | RcUnknown10 = 0x0400, // 10 ? | |
52 | RcCountEqTarget = 0x0800, // 11 | |
53 | RcOverflow = 0x1000, // 12 | |
54 | RcUnknown13 = 0x2000, // 13 ? (always zero) | |
55 | RcUnknown14 = 0x4000, // 14 ? (always zero) | |
56 | RcUnknown15 = 0x8000, // 15 ? (always zero) | |
57 | }; | |
58 | ||
59 | #define CounterQuantity ( 4 ) | |
60 | //static const u32 CounterQuantity = 4; | |
61 | ||
62 | static const u32 CountToOverflow = 0; | |
63 | static const u32 CountToTarget = 1; | |
64 | ||
d6b2a130 | 65 | static const u32 HSyncTotal[] = { 263, 314 }; |
66 | #define VBlankStart 240 // todo: depend on the actual GPU setting | |
ef79bbde | 67 | |
9f7ee52e | 68 | #define VERBOSE_LEVEL 0 |
ef79bbde P |
69 | |
70 | /******************************************************************************/ | |
630b122b | 71 | #ifdef DRC_DISABLE |
93c9e42a | 72 | Rcnt rcnts[ CounterQuantity ]; |
1a32b0f8 | 73 | #endif |
24de2dd4 | 74 | u32 hSyncCount = 0; |
75 | u32 frame_counter = 0; | |
61ef5cf4 | 76 | static u32 hsync_steps = 0; |
ef79bbde P |
77 | |
78 | u32 psxNextCounter = 0, psxNextsCounter = 0; | |
79 | ||
80 | /******************************************************************************/ | |
81 | ||
2f326fa1 | 82 | #define FPS_FRACTIONAL_PAL (53203425/314./3406) // ~49.75 |
83 | #define FPS_FRACTIONAL_NTSC (53693175/263./3413) // ~59.81 | |
84 | ||
85 | static inline | |
86 | u32 frameCycles(void) | |
87 | { | |
88 | int ff = Config.FractionalFramerate >= 0 | |
89 | ? Config.FractionalFramerate : Config.hacks.fractional_Framerate; | |
90 | if (ff) | |
91 | { | |
92 | if (Config.PsxType) | |
93 | return (u32)(PSXCLK / FPS_FRACTIONAL_PAL); | |
94 | else | |
95 | return (u32)(PSXCLK / FPS_FRACTIONAL_NTSC); | |
96 | } | |
97 | return Config.PsxType ? (PSXCLK / 50) : (PSXCLK / 60); | |
98 | } | |
99 | ||
100 | // used to inform the frontend about the exact framerate | |
101 | double psxGetFps() | |
102 | { | |
103 | int ff = Config.FractionalFramerate >= 0 | |
104 | ? Config.FractionalFramerate : Config.hacks.fractional_Framerate; | |
105 | if (ff) | |
106 | return Config.PsxType ? FPS_FRACTIONAL_PAL : FPS_FRACTIONAL_NTSC; | |
107 | else | |
108 | return Config.PsxType ? 50.0 : 60.0; | |
109 | } | |
110 | ||
111 | // to inform the frontend about the exact famerate | |
d6b2a130 | 112 | static inline |
113 | u32 lineCycles(void) | |
114 | { | |
2f326fa1 | 115 | // should be more like above, but our timing is already poor anyway |
d6b2a130 | 116 | if (Config.PsxType) |
117 | return PSXCLK / 50 / HSyncTotal[1]; | |
118 | else | |
119 | return PSXCLK / 60 / HSyncTotal[0]; | |
120 | } | |
121 | ||
ef79bbde P |
122 | static inline |
123 | void setIrq( u32 irq ) | |
124 | { | |
125 | psxHu32ref(0x1070) |= SWAPu32(irq); | |
126 | } | |
127 | ||
128 | static | |
9f7ee52e | 129 | void verboseLog( u32 level, const char *str, ... ) |
ef79bbde | 130 | { |
9f7ee52e | 131 | #if VERBOSE_LEVEL > 0 |
630b122b | 132 | if( level <= VERBOSE_LEVEL ) |
ef79bbde P |
133 | { |
134 | va_list va; | |
135 | char buf[ 4096 ]; | |
136 | ||
137 | va_start( va, str ); | |
138 | vsprintf( buf, str, va ); | |
139 | va_end( va ); | |
140 | ||
ab948f7e | 141 | printf( "%s", buf ); |
ef79bbde P |
142 | fflush( stdout ); |
143 | } | |
9f7ee52e | 144 | #endif |
ef79bbde P |
145 | } |
146 | ||
147 | /******************************************************************************/ | |
148 | ||
149 | static inline | |
150 | void _psxRcntWcount( u32 index, u32 value ) | |
151 | { | |
bb0379b7 | 152 | value &= 0xffff; |
ef79bbde P |
153 | |
154 | rcnts[index].cycleStart = psxRegs.cycle; | |
155 | rcnts[index].cycleStart -= value * rcnts[index].rate; | |
156 | ||
157 | // TODO: <=. | |
158 | if( value < rcnts[index].target ) | |
159 | { | |
160 | rcnts[index].cycle = rcnts[index].target * rcnts[index].rate; | |
161 | rcnts[index].counterState = CountToTarget; | |
162 | } | |
163 | else | |
164 | { | |
8ca6b0a6 | 165 | rcnts[index].cycle = 0x10000 * rcnts[index].rate; |
ef79bbde P |
166 | rcnts[index].counterState = CountToOverflow; |
167 | } | |
168 | } | |
169 | ||
170 | static inline | |
171 | u32 _psxRcntRcount( u32 index ) | |
172 | { | |
173 | u32 count; | |
174 | ||
175 | count = psxRegs.cycle; | |
176 | count -= rcnts[index].cycleStart; | |
61ef5cf4 | 177 | if (rcnts[index].rate > 1) |
178 | count /= rcnts[index].rate; | |
ef79bbde | 179 | |
8ca6b0a6 | 180 | if( count > 0x10000 ) |
ef79bbde | 181 | { |
8ca6b0a6 | 182 | verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count ); |
ef79bbde | 183 | } |
8ca6b0a6 | 184 | count &= 0xffff; |
ef79bbde P |
185 | |
186 | return count; | |
187 | } | |
188 | ||
a29f182f | 189 | static |
190 | void _psxRcntWmode( u32 index, u32 value ) | |
191 | { | |
192 | rcnts[index].mode = value; | |
193 | ||
194 | switch( index ) | |
195 | { | |
196 | case 0: | |
197 | if( value & Rc0PixelClock ) | |
198 | { | |
199 | rcnts[index].rate = 5; | |
200 | } | |
201 | else | |
202 | { | |
203 | rcnts[index].rate = 1; | |
204 | } | |
205 | break; | |
206 | case 1: | |
207 | if( value & Rc1HSyncClock ) | |
208 | { | |
d6b2a130 | 209 | rcnts[index].rate = lineCycles(); |
a29f182f | 210 | } |
211 | else | |
212 | { | |
213 | rcnts[index].rate = 1; | |
214 | } | |
215 | break; | |
216 | case 2: | |
217 | if( value & Rc2OneEighthClock ) | |
218 | { | |
219 | rcnts[index].rate = 8; | |
220 | } | |
221 | else | |
222 | { | |
223 | rcnts[index].rate = 1; | |
224 | } | |
225 | ||
226 | // TODO: wcount must work. | |
d3d41455 | 227 | if( (value & 7) == (RcSyncModeEnable | Rc2Stop) || |
228 | (value & 7) == (RcSyncModeEnable | Rc2Stop2) ) | |
a29f182f | 229 | { |
230 | rcnts[index].rate = 0xffffffff; | |
231 | } | |
232 | break; | |
233 | } | |
234 | } | |
235 | ||
ef79bbde P |
236 | /******************************************************************************/ |
237 | ||
238 | static | |
239 | void psxRcntSet() | |
240 | { | |
241 | s32 countToUpdate; | |
242 | u32 i; | |
243 | ||
244 | psxNextsCounter = psxRegs.cycle; | |
245 | psxNextCounter = 0x7fffffff; | |
246 | ||
247 | for( i = 0; i < CounterQuantity; ++i ) | |
248 | { | |
249 | countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart); | |
250 | ||
251 | if( countToUpdate < 0 ) | |
252 | { | |
253 | psxNextCounter = 0; | |
254 | break; | |
255 | } | |
256 | ||
257 | if( countToUpdate < (s32)psxNextCounter ) | |
258 | { | |
259 | psxNextCounter = countToUpdate; | |
260 | } | |
261 | } | |
5b8c000f | 262 | |
c6a249e3 | 263 | set_event(PSXINT_RCNT, psxNextCounter); |
ef79bbde P |
264 | } |
265 | ||
266 | /******************************************************************************/ | |
267 | ||
268 | static | |
269 | void psxRcntReset( u32 index ) | |
270 | { | |
8ca6b0a6 | 271 | u32 rcycles; |
ef79bbde | 272 | |
53c361f0 | 273 | rcnts[index].mode |= RcUnknown10; |
274 | ||
ef79bbde P |
275 | if( rcnts[index].counterState == CountToTarget ) |
276 | { | |
8ca6b0a6 | 277 | rcycles = psxRegs.cycle - rcnts[index].cycleStart; |
ef79bbde | 278 | if( rcnts[index].mode & RcCountToTarget ) |
8ca6b0a6 | 279 | { |
280 | rcycles -= rcnts[index].target * rcnts[index].rate; | |
281 | rcnts[index].cycleStart = psxRegs.cycle - rcycles; | |
282 | } | |
283 | else | |
284 | { | |
285 | rcnts[index].cycle = 0x10000 * rcnts[index].rate; | |
286 | rcnts[index].counterState = CountToOverflow; | |
287 | } | |
ef79bbde P |
288 | |
289 | if( rcnts[index].mode & RcIrqOnTarget ) | |
290 | { | |
291 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) | |
292 | { | |
8ca6b0a6 | 293 | verboseLog( 3, "[RCNT %i] irq\n", index ); |
ef79bbde P |
294 | setIrq( rcnts[index].irq ); |
295 | rcnts[index].irqState = 1; | |
296 | } | |
297 | } | |
298 | ||
299 | rcnts[index].mode |= RcCountEqTarget; | |
53c361f0 | 300 | |
8ca6b0a6 | 301 | if( rcycles < 0x10000 * rcnts[index].rate ) |
53c361f0 | 302 | return; |
ef79bbde | 303 | } |
53c361f0 | 304 | |
305 | if( rcnts[index].counterState == CountToOverflow ) | |
ef79bbde | 306 | { |
8ca6b0a6 | 307 | rcycles = psxRegs.cycle - rcnts[index].cycleStart; |
308 | rcycles -= 0x10000 * rcnts[index].rate; | |
309 | ||
310 | rcnts[index].cycleStart = psxRegs.cycle - rcycles; | |
ef79bbde | 311 | |
8ca6b0a6 | 312 | if( rcycles < rcnts[index].target * rcnts[index].rate ) |
313 | { | |
314 | rcnts[index].cycle = rcnts[index].target * rcnts[index].rate; | |
315 | rcnts[index].counterState = CountToTarget; | |
316 | } | |
ef79bbde P |
317 | |
318 | if( rcnts[index].mode & RcIrqOnOverflow ) | |
319 | { | |
320 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) | |
321 | { | |
8ca6b0a6 | 322 | verboseLog( 3, "[RCNT %i] irq\n", index ); |
ef79bbde P |
323 | setIrq( rcnts[index].irq ); |
324 | rcnts[index].irqState = 1; | |
325 | } | |
326 | } | |
327 | ||
328 | rcnts[index].mode |= RcOverflow; | |
329 | } | |
ef79bbde P |
330 | } |
331 | ||
43614ebd | 332 | static void scheduleRcntBase(void) |
333 | { | |
334 | // Schedule next call, in hsyncs | |
335 | if (hSyncCount < VBlankStart) | |
336 | hsync_steps = VBlankStart - hSyncCount; | |
337 | else | |
338 | hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount; | |
339 | ||
340 | if (hSyncCount + hsync_steps == HSyncTotal[Config.PsxType]) | |
341 | { | |
2f326fa1 | 342 | rcnts[3].cycle = frameCycles(); |
43614ebd | 343 | } |
344 | else | |
345 | { | |
346 | // clk / 50 / 314 ~= 2157.25 | |
347 | // clk / 60 / 263 ~= 2146.31 | |
348 | u32 mult = Config.PsxType ? 8836089 : 8791293; | |
349 | rcnts[3].cycle = hsync_steps * mult >> 12; | |
350 | } | |
351 | } | |
352 | ||
ef79bbde P |
353 | void psxRcntUpdate() |
354 | { | |
d3d41455 | 355 | u32 cycle, cycles_passed; |
ef79bbde P |
356 | |
357 | cycle = psxRegs.cycle; | |
358 | ||
359 | // rcnt 0. | |
d3d41455 | 360 | cycles_passed = cycle - rcnts[0].cycleStart; |
361 | while( cycles_passed >= rcnts[0].cycle ) | |
ef79bbde | 362 | { |
d3d41455 | 363 | if (((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) || |
364 | (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2)) | |
d6b2a130 | 365 | && cycles_passed > lineCycles()) |
d3d41455 | 366 | { |
d6b2a130 | 367 | u32 q = cycles_passed / (lineCycles() + 1u); |
368 | rcnts[0].cycleStart += q * lineCycles(); | |
d3d41455 | 369 | break; |
370 | } | |
371 | else | |
372 | psxRcntReset( 0 ); | |
373 | ||
374 | cycles_passed = cycle - rcnts[0].cycleStart; | |
ef79bbde P |
375 | } |
376 | ||
377 | // rcnt 1. | |
74a0bb9f | 378 | while( cycle - rcnts[1].cycleStart >= rcnts[1].cycle ) |
ef79bbde P |
379 | { |
380 | psxRcntReset( 1 ); | |
381 | } | |
382 | ||
383 | // rcnt 2. | |
74a0bb9f | 384 | while( cycle - rcnts[2].cycleStart >= rcnts[2].cycle ) |
ef79bbde P |
385 | { |
386 | psxRcntReset( 2 ); | |
387 | } | |
388 | ||
389 | // rcnt base. | |
390 | if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle ) | |
391 | { | |
61ef5cf4 | 392 | hSyncCount += hsync_steps; |
ef79bbde | 393 | |
ef79bbde | 394 | // VSync irq. |
0486fdc9 | 395 | if( hSyncCount == VBlankStart ) |
ef79bbde | 396 | { |
adb7d7ac | 397 | HW_GPU_STATUS &= SWAP32(~PSXGPU_LCF); |
72e5023f | 398 | GPU_vBlank( 1, 0 ); |
8bbbd091 | 399 | setIrq( 0x01 ); |
400 | ||
401 | EmuUpdate(); | |
402 | GPU_updateLace(); | |
d618a240 | 403 | |
404 | if( SPU_async ) | |
405 | { | |
406 | SPU_async( cycle, 1 ); | |
407 | } | |
ef79bbde P |
408 | } |
409 | ||
840639a5 | 410 | // Update lace. |
411 | if( hSyncCount >= HSyncTotal[Config.PsxType] ) | |
ef79bbde | 412 | { |
d6b2a130 | 413 | u32 status, field = 0; |
2f326fa1 | 414 | rcnts[3].cycleStart += frameCycles(); |
ef79bbde | 415 | hSyncCount = 0; |
ddbaf678 | 416 | frame_counter++; |
ef79bbde | 417 | |
0486fdc9 | 418 | gpuSyncPluginSR(); |
4db82c07 | 419 | status = SWAP32(HW_GPU_STATUS) | PSXGPU_FIELD; |
420 | if ((status & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS) { | |
421 | field = frame_counter & 1; | |
422 | status |= field << 31; | |
423 | status ^= field << 13; | |
424 | } | |
425 | HW_GPU_STATUS = SWAP32(status); | |
426 | GPU_vBlank(0, field); | |
8cba0a22 | 427 | if ((s32)(psxRegs.gpuIdleAfter - psxRegs.cycle) < 0) |
428 | psxRegs.gpuIdleAfter = psxRegs.cycle - 1; // prevent overflow | |
d3d41455 | 429 | |
d6b2a130 | 430 | if ((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) || |
431 | (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2)) | |
432 | { | |
433 | rcnts[0].cycleStart = rcnts[3].cycleStart; | |
434 | } | |
435 | ||
436 | if ((rcnts[1].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) || | |
437 | (rcnts[1].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2)) | |
438 | { | |
439 | rcnts[1].cycleStart = rcnts[3].cycleStart; | |
440 | } | |
441 | else if (rcnts[1].mode & Rc1HSyncClock) | |
d3d41455 | 442 | { |
d6b2a130 | 443 | // adjust to remove the rounding error |
444 | _psxRcntWcount(1, (psxRegs.cycle - rcnts[1].cycleStart) / rcnts[1].rate); | |
d3d41455 | 445 | } |
ef79bbde | 446 | } |
61ef5cf4 | 447 | |
43614ebd | 448 | scheduleRcntBase(); |
ef79bbde P |
449 | } |
450 | ||
95df1a04 | 451 | psxRcntSet(); |
452 | ||
ee8fd567 | 453 | #if 0 //ndef NDEBUG |
ef79bbde | 454 | DebugVSync(); |
61ef5cf4 | 455 | #endif |
ef79bbde P |
456 | } |
457 | ||
458 | /******************************************************************************/ | |
459 | ||
460 | void psxRcntWcount( u32 index, u32 value ) | |
461 | { | |
462 | verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value ); | |
463 | ||
ef79bbde P |
464 | _psxRcntWcount( index, value ); |
465 | psxRcntSet(); | |
466 | } | |
467 | ||
468 | void psxRcntWmode( u32 index, u32 value ) | |
469 | { | |
470 | verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value ); | |
471 | ||
a29f182f | 472 | _psxRcntWmode( index, value ); |
ef79bbde | 473 | _psxRcntWcount( index, 0 ); |
a29f182f | 474 | |
475 | rcnts[index].irqState = 0; | |
ef79bbde P |
476 | psxRcntSet(); |
477 | } | |
478 | ||
479 | void psxRcntWtarget( u32 index, u32 value ) | |
480 | { | |
481 | verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value ); | |
482 | ||
ef79bbde P |
483 | rcnts[index].target = value; |
484 | ||
485 | _psxRcntWcount( index, _psxRcntRcount( index ) ); | |
486 | psxRcntSet(); | |
487 | } | |
488 | ||
489 | /******************************************************************************/ | |
490 | ||
d3d41455 | 491 | u32 psxRcntRcount0() |
492 | { | |
493 | u32 index = 0; | |
494 | u32 count; | |
495 | ||
496 | if ((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) || | |
497 | (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2)) | |
498 | { | |
499 | count = psxRegs.cycle - rcnts[index].cycleStart; | |
d6b2a130 | 500 | //count = ((16u * count) % (16u * PSXCLK / 60 / 263)) / 16u; |
501 | count = count % lineCycles(); | |
d3d41455 | 502 | rcnts[index].cycleStart = psxRegs.cycle - count; |
503 | } | |
504 | else | |
505 | count = _psxRcntRcount( index ); | |
506 | ||
507 | verboseLog( 2, "[RCNT 0] rcount: %04x m: %04x\n", count, rcnts[index].mode); | |
508 | ||
509 | return count; | |
510 | } | |
511 | ||
512 | u32 psxRcntRcount1() | |
513 | { | |
514 | u32 index = 1; | |
515 | u32 count; | |
516 | ||
517 | count = _psxRcntRcount( index ); | |
518 | ||
519 | verboseLog( 2, "[RCNT 1] rcount: %04x m: %04x\n", count, rcnts[index].mode); | |
520 | ||
521 | return count; | |
522 | } | |
523 | ||
524 | u32 psxRcntRcount2() | |
ef79bbde | 525 | { |
d3d41455 | 526 | u32 index = 2; |
ef79bbde P |
527 | u32 count; |
528 | ||
ef79bbde P |
529 | count = _psxRcntRcount( index ); |
530 | ||
d3d41455 | 531 | verboseLog( 2, "[RCNT 2] rcount: %04x m: %04x\n", count, rcnts[index].mode); |
ef79bbde P |
532 | |
533 | return count; | |
534 | } | |
535 | ||
536 | u32 psxRcntRmode( u32 index ) | |
537 | { | |
538 | u16 mode; | |
539 | ||
ef79bbde P |
540 | mode = rcnts[index].mode; |
541 | rcnts[index].mode &= 0xe7ff; | |
542 | ||
543 | verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode ); | |
544 | ||
545 | return mode; | |
546 | } | |
547 | ||
548 | u32 psxRcntRtarget( u32 index ) | |
549 | { | |
550 | verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target ); | |
551 | ||
552 | return rcnts[index].target; | |
553 | } | |
554 | ||
555 | /******************************************************************************/ | |
556 | ||
557 | void psxRcntInit() | |
558 | { | |
559 | s32 i; | |
560 | ||
561 | // rcnt 0. | |
562 | rcnts[0].rate = 1; | |
563 | rcnts[0].irq = 0x10; | |
564 | ||
565 | // rcnt 1. | |
566 | rcnts[1].rate = 1; | |
567 | rcnts[1].irq = 0x20; | |
568 | ||
569 | // rcnt 2. | |
570 | rcnts[2].rate = 1; | |
571 | rcnts[2].irq = 0x40; | |
572 | ||
573 | // rcnt base. | |
574 | rcnts[3].rate = 1; | |
ef79bbde P |
575 | |
576 | for( i = 0; i < CounterQuantity; ++i ) | |
577 | { | |
578 | _psxRcntWcount( i, 0 ); | |
579 | } | |
580 | ||
c62b43c9 | 581 | hSyncCount = 0; |
61ef5cf4 | 582 | hsync_steps = 1; |
c62b43c9 | 583 | |
d6b2a130 | 584 | scheduleRcntBase(); |
ef79bbde P |
585 | psxRcntSet(); |
586 | } | |
587 | ||
588 | /******************************************************************************/ | |
589 | ||
496d88d4 | 590 | s32 psxRcntFreeze( void *f, s32 Mode ) |
ef79bbde | 591 | { |
d618a240 | 592 | u32 spuSyncCount = 0; |
6a3fa667 | 593 | u32 count; |
a29f182f | 594 | s32 i; |
595 | ||
1a32b0f8 | 596 | gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity ); |
ef79bbde P |
597 | gzfreeze( &hSyncCount, sizeof(hSyncCount) ); |
598 | gzfreeze( &spuSyncCount, sizeof(spuSyncCount) ); | |
599 | gzfreeze( &psxNextCounter, sizeof(psxNextCounter) ); | |
600 | gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) ); | |
601 | ||
61ef5cf4 | 602 | if (Mode == 0) |
a29f182f | 603 | { |
630b122b | 604 | rcnts[3].rate = 1; |
403a6290 | 605 | for( i = 0; i < CounterQuantity - 1; ++i ) |
6a3fa667 | 606 | { |
a29f182f | 607 | _psxRcntWmode( i, rcnts[i].mode ); |
6a3fa667 | 608 | count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate; |
609 | if (count > 0x1000) | |
610 | _psxRcntWcount( i, count & 0xffff ); | |
611 | } | |
43614ebd | 612 | scheduleRcntBase(); |
a29f182f | 613 | psxRcntSet(); |
a29f182f | 614 | } |
4f55097d | 615 | |
ef79bbde P |
616 | return 0; |
617 | } | |
618 | ||
619 | /******************************************************************************/ | |
43614ebd | 620 | // vim:ts=4:shiftwidth=4:expandtab |