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ef79bbde P |
1 | /*************************************************************************** |
2 | * Copyright (C) 2010 by Blade_Arma * | |
3 | * * | |
4 | * This program is free software; you can redistribute it and/or modify * | |
5 | * it under the terms of the GNU General Public License as published by * | |
6 | * the Free Software Foundation; either version 2 of the License, or * | |
7 | * (at your option) any later version. * | |
8 | * * | |
9 | * This program is distributed in the hope that it will be useful, * | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
12 | * GNU General Public License for more details. * | |
13 | * * | |
14 | * You should have received a copy of the GNU General Public License * | |
15 | * along with this program; if not, write to the * | |
16 | * Free Software Foundation, Inc., * | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * | |
18 | ***************************************************************************/ | |
19 | ||
20 | /* | |
21 | * Internal PSX counters. | |
22 | */ | |
23 | ||
24 | #include "psxcounters.h" | |
ddbaf678 | 25 | #include "gpu.h" |
fc8145b7 | 26 | #include "debug.h" |
ef79bbde P |
27 | |
28 | /******************************************************************************/ | |
29 | ||
ef79bbde P |
30 | enum |
31 | { | |
32 | Rc0Gate = 0x0001, // 0 not implemented | |
33 | Rc1Gate = 0x0001, // 0 not implemented | |
34 | Rc2Disable = 0x0001, // 0 partially implemented | |
35 | RcUnknown1 = 0x0002, // 1 ? | |
36 | RcUnknown2 = 0x0004, // 2 ? | |
37 | RcCountToTarget = 0x0008, // 3 | |
38 | RcIrqOnTarget = 0x0010, // 4 | |
39 | RcIrqOnOverflow = 0x0020, // 5 | |
40 | RcIrqRegenerate = 0x0040, // 6 | |
41 | RcUnknown7 = 0x0080, // 7 ? | |
42 | Rc0PixelClock = 0x0100, // 8 fake implementation | |
43 | Rc1HSyncClock = 0x0100, // 8 | |
44 | Rc2Unknown8 = 0x0100, // 8 ? | |
45 | Rc0Unknown9 = 0x0200, // 9 ? | |
46 | Rc1Unknown9 = 0x0200, // 9 ? | |
47 | Rc2OneEighthClock = 0x0200, // 9 | |
48 | RcUnknown10 = 0x0400, // 10 ? | |
49 | RcCountEqTarget = 0x0800, // 11 | |
50 | RcOverflow = 0x1000, // 12 | |
51 | RcUnknown13 = 0x2000, // 13 ? (always zero) | |
52 | RcUnknown14 = 0x4000, // 14 ? (always zero) | |
53 | RcUnknown15 = 0x8000, // 15 ? (always zero) | |
54 | }; | |
55 | ||
56 | #define CounterQuantity ( 4 ) | |
57 | //static const u32 CounterQuantity = 4; | |
58 | ||
59 | static const u32 CountToOverflow = 0; | |
60 | static const u32 CountToTarget = 1; | |
61 | ||
62 | static const u32 FrameRate[] = { 60, 50 }; | |
aecf98c5 | 63 | static const u32 HSyncTotal[] = { 263, 313 }; |
0486fdc9 | 64 | #define VBlankStart 240 |
ef79bbde | 65 | |
9f7ee52e | 66 | #define VERBOSE_LEVEL 0 |
4b7da20a | 67 | #if VERBOSE_LEVEL > 0 |
9f7ee52e | 68 | static const s32 VerboseLevel = VERBOSE_LEVEL; |
4b7da20a | 69 | #endif |
ef79bbde P |
70 | |
71 | /******************************************************************************/ | |
72 | ||
24de2dd4 | 73 | u32 hSyncCount = 0; |
74 | u32 frame_counter = 0; | |
61ef5cf4 | 75 | static u32 hsync_steps = 0; |
4f55097d | 76 | static u32 base_cycle = 0; |
ef79bbde P |
77 | |
78 | u32 psxNextCounter = 0, psxNextsCounter = 0; | |
79 | ||
80 | /******************************************************************************/ | |
81 | ||
82 | static inline | |
83 | void setIrq( u32 irq ) | |
84 | { | |
85 | psxHu32ref(0x1070) |= SWAPu32(irq); | |
86 | } | |
87 | ||
88 | static | |
9f7ee52e | 89 | void verboseLog( u32 level, const char *str, ... ) |
ef79bbde | 90 | { |
9f7ee52e | 91 | #if VERBOSE_LEVEL > 0 |
ef79bbde P |
92 | if( level <= VerboseLevel ) |
93 | { | |
94 | va_list va; | |
95 | char buf[ 4096 ]; | |
96 | ||
97 | va_start( va, str ); | |
98 | vsprintf( buf, str, va ); | |
99 | va_end( va ); | |
100 | ||
ab948f7e | 101 | printf( "%s", buf ); |
ef79bbde P |
102 | fflush( stdout ); |
103 | } | |
9f7ee52e | 104 | #endif |
ef79bbde P |
105 | } |
106 | ||
107 | /******************************************************************************/ | |
108 | ||
109 | static inline | |
110 | void _psxRcntWcount( u32 index, u32 value ) | |
111 | { | |
112 | if( value > 0xffff ) | |
113 | { | |
114 | verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value ); | |
115 | value &= 0xffff; | |
116 | } | |
117 | ||
118 | rcnts[index].cycleStart = psxRegs.cycle; | |
119 | rcnts[index].cycleStart -= value * rcnts[index].rate; | |
120 | ||
121 | // TODO: <=. | |
122 | if( value < rcnts[index].target ) | |
123 | { | |
124 | rcnts[index].cycle = rcnts[index].target * rcnts[index].rate; | |
125 | rcnts[index].counterState = CountToTarget; | |
126 | } | |
127 | else | |
128 | { | |
8ca6b0a6 | 129 | rcnts[index].cycle = 0x10000 * rcnts[index].rate; |
ef79bbde P |
130 | rcnts[index].counterState = CountToOverflow; |
131 | } | |
132 | } | |
133 | ||
134 | static inline | |
135 | u32 _psxRcntRcount( u32 index ) | |
136 | { | |
137 | u32 count; | |
138 | ||
139 | count = psxRegs.cycle; | |
140 | count -= rcnts[index].cycleStart; | |
61ef5cf4 | 141 | if (rcnts[index].rate > 1) |
142 | count /= rcnts[index].rate; | |
ef79bbde | 143 | |
8ca6b0a6 | 144 | if( count > 0x10000 ) |
ef79bbde | 145 | { |
8ca6b0a6 | 146 | verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count ); |
ef79bbde | 147 | } |
8ca6b0a6 | 148 | count &= 0xffff; |
ef79bbde P |
149 | |
150 | return count; | |
151 | } | |
152 | ||
a29f182f | 153 | static |
154 | void _psxRcntWmode( u32 index, u32 value ) | |
155 | { | |
156 | rcnts[index].mode = value; | |
157 | ||
158 | switch( index ) | |
159 | { | |
160 | case 0: | |
161 | if( value & Rc0PixelClock ) | |
162 | { | |
163 | rcnts[index].rate = 5; | |
164 | } | |
165 | else | |
166 | { | |
167 | rcnts[index].rate = 1; | |
168 | } | |
169 | break; | |
170 | case 1: | |
171 | if( value & Rc1HSyncClock ) | |
172 | { | |
173 | rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); | |
174 | } | |
175 | else | |
176 | { | |
177 | rcnts[index].rate = 1; | |
178 | } | |
179 | break; | |
180 | case 2: | |
181 | if( value & Rc2OneEighthClock ) | |
182 | { | |
183 | rcnts[index].rate = 8; | |
184 | } | |
185 | else | |
186 | { | |
187 | rcnts[index].rate = 1; | |
188 | } | |
189 | ||
190 | // TODO: wcount must work. | |
191 | if( value & Rc2Disable ) | |
192 | { | |
193 | rcnts[index].rate = 0xffffffff; | |
194 | } | |
195 | break; | |
196 | } | |
197 | } | |
198 | ||
ef79bbde P |
199 | /******************************************************************************/ |
200 | ||
201 | static | |
202 | void psxRcntSet() | |
203 | { | |
204 | s32 countToUpdate; | |
205 | u32 i; | |
206 | ||
207 | psxNextsCounter = psxRegs.cycle; | |
208 | psxNextCounter = 0x7fffffff; | |
209 | ||
210 | for( i = 0; i < CounterQuantity; ++i ) | |
211 | { | |
212 | countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart); | |
213 | ||
214 | if( countToUpdate < 0 ) | |
215 | { | |
216 | psxNextCounter = 0; | |
217 | break; | |
218 | } | |
219 | ||
220 | if( countToUpdate < (s32)psxNextCounter ) | |
221 | { | |
222 | psxNextCounter = countToUpdate; | |
223 | } | |
224 | } | |
5b8c000f | 225 | |
226 | psxRegs.interrupt |= (1 << PSXINT_RCNT); | |
227 | new_dyna_set_event(PSXINT_RCNT, psxNextCounter); | |
ef79bbde P |
228 | } |
229 | ||
230 | /******************************************************************************/ | |
231 | ||
232 | static | |
233 | void psxRcntReset( u32 index ) | |
234 | { | |
8ca6b0a6 | 235 | u32 rcycles; |
ef79bbde | 236 | |
53c361f0 | 237 | rcnts[index].mode |= RcUnknown10; |
238 | ||
ef79bbde P |
239 | if( rcnts[index].counterState == CountToTarget ) |
240 | { | |
8ca6b0a6 | 241 | rcycles = psxRegs.cycle - rcnts[index].cycleStart; |
ef79bbde | 242 | if( rcnts[index].mode & RcCountToTarget ) |
8ca6b0a6 | 243 | { |
244 | rcycles -= rcnts[index].target * rcnts[index].rate; | |
245 | rcnts[index].cycleStart = psxRegs.cycle - rcycles; | |
246 | } | |
247 | else | |
248 | { | |
249 | rcnts[index].cycle = 0x10000 * rcnts[index].rate; | |
250 | rcnts[index].counterState = CountToOverflow; | |
251 | } | |
ef79bbde P |
252 | |
253 | if( rcnts[index].mode & RcIrqOnTarget ) | |
254 | { | |
255 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) | |
256 | { | |
8ca6b0a6 | 257 | verboseLog( 3, "[RCNT %i] irq\n", index ); |
ef79bbde P |
258 | setIrq( rcnts[index].irq ); |
259 | rcnts[index].irqState = 1; | |
260 | } | |
261 | } | |
262 | ||
263 | rcnts[index].mode |= RcCountEqTarget; | |
53c361f0 | 264 | |
8ca6b0a6 | 265 | if( rcycles < 0x10000 * rcnts[index].rate ) |
53c361f0 | 266 | return; |
ef79bbde | 267 | } |
53c361f0 | 268 | |
269 | if( rcnts[index].counterState == CountToOverflow ) | |
ef79bbde | 270 | { |
8ca6b0a6 | 271 | rcycles = psxRegs.cycle - rcnts[index].cycleStart; |
272 | rcycles -= 0x10000 * rcnts[index].rate; | |
273 | ||
274 | rcnts[index].cycleStart = psxRegs.cycle - rcycles; | |
ef79bbde | 275 | |
8ca6b0a6 | 276 | if( rcycles < rcnts[index].target * rcnts[index].rate ) |
277 | { | |
278 | rcnts[index].cycle = rcnts[index].target * rcnts[index].rate; | |
279 | rcnts[index].counterState = CountToTarget; | |
280 | } | |
ef79bbde P |
281 | |
282 | if( rcnts[index].mode & RcIrqOnOverflow ) | |
283 | { | |
284 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) | |
285 | { | |
8ca6b0a6 | 286 | verboseLog( 3, "[RCNT %i] irq\n", index ); |
ef79bbde P |
287 | setIrq( rcnts[index].irq ); |
288 | rcnts[index].irqState = 1; | |
289 | } | |
290 | } | |
291 | ||
292 | rcnts[index].mode |= RcOverflow; | |
293 | } | |
ef79bbde P |
294 | } |
295 | ||
296 | void psxRcntUpdate() | |
297 | { | |
298 | u32 cycle; | |
299 | ||
300 | cycle = psxRegs.cycle; | |
301 | ||
302 | // rcnt 0. | |
303 | if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle ) | |
304 | { | |
305 | psxRcntReset( 0 ); | |
306 | } | |
307 | ||
308 | // rcnt 1. | |
309 | if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle ) | |
310 | { | |
311 | psxRcntReset( 1 ); | |
312 | } | |
313 | ||
314 | // rcnt 2. | |
315 | if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle ) | |
316 | { | |
317 | psxRcntReset( 2 ); | |
318 | } | |
319 | ||
320 | // rcnt base. | |
321 | if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle ) | |
322 | { | |
61ef5cf4 | 323 | u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle; |
d618a240 | 324 | u32 next_vsync; |
ef79bbde | 325 | |
61ef5cf4 | 326 | hSyncCount += hsync_steps; |
ef79bbde | 327 | |
ef79bbde | 328 | // VSync irq. |
0486fdc9 | 329 | if( hSyncCount == VBlankStart ) |
ef79bbde | 330 | { |
0486fdc9 | 331 | HW_GPU_STATUS &= ~PSXGPU_LCF; |
72e5023f | 332 | GPU_vBlank( 1, 0 ); |
8bbbd091 | 333 | setIrq( 0x01 ); |
334 | ||
335 | EmuUpdate(); | |
336 | GPU_updateLace(); | |
d618a240 | 337 | |
338 | if( SPU_async ) | |
339 | { | |
340 | SPU_async( cycle, 1 ); | |
341 | } | |
ef79bbde P |
342 | } |
343 | ||
344 | // Update lace. (with InuYasha fix) | |
345 | if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) ) | |
346 | { | |
347 | hSyncCount = 0; | |
ddbaf678 | 348 | frame_counter++; |
ef79bbde | 349 | |
0486fdc9 | 350 | gpuSyncPluginSR(); |
351 | if( (HW_GPU_STATUS & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS ) | |
ddbaf678 | 352 | HW_GPU_STATUS |= frame_counter << 31; |
72e5023f | 353 | GPU_vBlank( 0, HW_GPU_STATUS >> 31 ); |
ef79bbde | 354 | } |
61ef5cf4 | 355 | |
356 | // Schedule next call, in hsyncs | |
d618a240 | 357 | hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount; |
0486fdc9 | 358 | next_vsync = VBlankStart - hSyncCount; // ok to overflow |
61ef5cf4 | 359 | if( next_vsync && next_vsync < hsync_steps ) |
360 | hsync_steps = next_vsync; | |
61ef5cf4 | 361 | |
362 | rcnts[3].cycleStart = cycle - leftover_cycles; | |
4f55097d | 363 | if (Config.PsxType) |
364 | // 20.12 precision, clk / 50 / 313 ~= 2164.14 | |
365 | base_cycle += hsync_steps * 8864320; | |
366 | else | |
367 | // clk / 60 / 263 ~= 2146.31 | |
368 | base_cycle += hsync_steps * 8791293; | |
369 | rcnts[3].cycle = base_cycle >> 12; | |
370 | base_cycle &= 0xfff; | |
ef79bbde P |
371 | } |
372 | ||
95df1a04 | 373 | psxRcntSet(); |
374 | ||
61ef5cf4 | 375 | #ifndef NDEBUG |
ef79bbde | 376 | DebugVSync(); |
61ef5cf4 | 377 | #endif |
ef79bbde P |
378 | } |
379 | ||
380 | /******************************************************************************/ | |
381 | ||
382 | void psxRcntWcount( u32 index, u32 value ) | |
383 | { | |
384 | verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value ); | |
385 | ||
ef79bbde P |
386 | _psxRcntWcount( index, value ); |
387 | psxRcntSet(); | |
388 | } | |
389 | ||
390 | void psxRcntWmode( u32 index, u32 value ) | |
391 | { | |
392 | verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value ); | |
393 | ||
a29f182f | 394 | _psxRcntWmode( index, value ); |
ef79bbde | 395 | _psxRcntWcount( index, 0 ); |
a29f182f | 396 | |
397 | rcnts[index].irqState = 0; | |
ef79bbde P |
398 | psxRcntSet(); |
399 | } | |
400 | ||
401 | void psxRcntWtarget( u32 index, u32 value ) | |
402 | { | |
403 | verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value ); | |
404 | ||
ef79bbde P |
405 | rcnts[index].target = value; |
406 | ||
407 | _psxRcntWcount( index, _psxRcntRcount( index ) ); | |
408 | psxRcntSet(); | |
409 | } | |
410 | ||
411 | /******************************************************************************/ | |
412 | ||
413 | u32 psxRcntRcount( u32 index ) | |
414 | { | |
415 | u32 count; | |
416 | ||
ef79bbde P |
417 | count = _psxRcntRcount( index ); |
418 | ||
419 | // Parasite Eve 2 fix. | |
420 | if( Config.RCntFix ) | |
421 | { | |
422 | if( index == 2 ) | |
423 | { | |
424 | if( rcnts[index].counterState == CountToTarget ) | |
425 | { | |
426 | count /= BIAS; | |
427 | } | |
428 | } | |
429 | } | |
430 | ||
431 | verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count ); | |
432 | ||
433 | return count; | |
434 | } | |
435 | ||
436 | u32 psxRcntRmode( u32 index ) | |
437 | { | |
438 | u16 mode; | |
439 | ||
ef79bbde P |
440 | mode = rcnts[index].mode; |
441 | rcnts[index].mode &= 0xe7ff; | |
442 | ||
443 | verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode ); | |
444 | ||
445 | return mode; | |
446 | } | |
447 | ||
448 | u32 psxRcntRtarget( u32 index ) | |
449 | { | |
450 | verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target ); | |
451 | ||
452 | return rcnts[index].target; | |
453 | } | |
454 | ||
455 | /******************************************************************************/ | |
456 | ||
457 | void psxRcntInit() | |
458 | { | |
459 | s32 i; | |
460 | ||
461 | // rcnt 0. | |
462 | rcnts[0].rate = 1; | |
463 | rcnts[0].irq = 0x10; | |
464 | ||
465 | // rcnt 1. | |
466 | rcnts[1].rate = 1; | |
467 | rcnts[1].irq = 0x20; | |
468 | ||
469 | // rcnt 2. | |
470 | rcnts[2].rate = 1; | |
471 | rcnts[2].irq = 0x40; | |
472 | ||
473 | // rcnt base. | |
474 | rcnts[3].rate = 1; | |
475 | rcnts[3].mode = RcCountToTarget; | |
476 | rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); | |
477 | ||
478 | for( i = 0; i < CounterQuantity; ++i ) | |
479 | { | |
480 | _psxRcntWcount( i, 0 ); | |
481 | } | |
482 | ||
c62b43c9 | 483 | hSyncCount = 0; |
61ef5cf4 | 484 | hsync_steps = 1; |
c62b43c9 | 485 | |
ef79bbde P |
486 | psxRcntSet(); |
487 | } | |
488 | ||
489 | /******************************************************************************/ | |
490 | ||
496d88d4 | 491 | s32 psxRcntFreeze( void *f, s32 Mode ) |
ef79bbde | 492 | { |
d618a240 | 493 | u32 spuSyncCount = 0; |
a29f182f | 494 | u32 count; |
495 | s32 i; | |
496 | ||
b6b38f88 | 497 | gzfreeze( &rcnts, sizeof(*rcnts) * CounterQuantity ); |
ef79bbde P |
498 | gzfreeze( &hSyncCount, sizeof(hSyncCount) ); |
499 | gzfreeze( &spuSyncCount, sizeof(spuSyncCount) ); | |
500 | gzfreeze( &psxNextCounter, sizeof(psxNextCounter) ); | |
501 | gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) ); | |
502 | ||
61ef5cf4 | 503 | if (Mode == 0) |
a29f182f | 504 | { |
505 | // don't trust things from a savestate | |
506 | for( i = 0; i < CounterQuantity; ++i ) | |
507 | { | |
508 | _psxRcntWmode( i, rcnts[i].mode ); | |
509 | count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate; | |
510 | _psxRcntWcount( i, count ); | |
511 | } | |
61ef5cf4 | 512 | hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target; |
a29f182f | 513 | psxRcntSet(); |
61ef5cf4 | 514 | |
a29f182f | 515 | base_cycle = 0; |
516 | } | |
4f55097d | 517 | |
ef79bbde P |
518 | return 0; |
519 | } | |
520 | ||
521 | /******************************************************************************/ |