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ef79bbde P |
1 | /*************************************************************************** |
2 | * Copyright (C) 2010 by Blade_Arma * | |
3 | * * | |
4 | * This program is free software; you can redistribute it and/or modify * | |
5 | * it under the terms of the GNU General Public License as published by * | |
6 | * the Free Software Foundation; either version 2 of the License, or * | |
7 | * (at your option) any later version. * | |
8 | * * | |
9 | * This program is distributed in the hope that it will be useful, * | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
12 | * GNU General Public License for more details. * | |
13 | * * | |
14 | * You should have received a copy of the GNU General Public License * | |
15 | * along with this program; if not, write to the * | |
16 | * Free Software Foundation, Inc., * | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * | |
18 | ***************************************************************************/ | |
19 | ||
20 | /* | |
21 | * Internal PSX counters. | |
22 | */ | |
23 | ||
24 | #include "psxcounters.h" | |
ddbaf678 | 25 | #include "gpu.h" |
5b568098 | 26 | //#include "debug.h" |
27 | #define DebugVSync() | |
ef79bbde P |
28 | |
29 | /******************************************************************************/ | |
30 | ||
ef79bbde P |
31 | enum |
32 | { | |
d3d41455 | 33 | RcSyncModeEnable = 0x0001, // 0 |
34 | Rc01BlankPause = 0 << 1, // 1,2 | |
35 | Rc01UnblankReset = 1 << 1, // 1,2 | |
36 | Rc01UnblankReset2 = 2 << 1, // 1,2 | |
37 | Rc2Stop = 0 << 1, // 1,2 | |
38 | Rc2Stop2 = 3 << 1, // 1,2 | |
ef79bbde P |
39 | RcCountToTarget = 0x0008, // 3 |
40 | RcIrqOnTarget = 0x0010, // 4 | |
41 | RcIrqOnOverflow = 0x0020, // 5 | |
42 | RcIrqRegenerate = 0x0040, // 6 | |
43 | RcUnknown7 = 0x0080, // 7 ? | |
44 | Rc0PixelClock = 0x0100, // 8 fake implementation | |
45 | Rc1HSyncClock = 0x0100, // 8 | |
46 | Rc2Unknown8 = 0x0100, // 8 ? | |
47 | Rc0Unknown9 = 0x0200, // 9 ? | |
48 | Rc1Unknown9 = 0x0200, // 9 ? | |
49 | Rc2OneEighthClock = 0x0200, // 9 | |
50 | RcUnknown10 = 0x0400, // 10 ? | |
51 | RcCountEqTarget = 0x0800, // 11 | |
52 | RcOverflow = 0x1000, // 12 | |
53 | RcUnknown13 = 0x2000, // 13 ? (always zero) | |
54 | RcUnknown14 = 0x4000, // 14 ? (always zero) | |
55 | RcUnknown15 = 0x8000, // 15 ? (always zero) | |
56 | }; | |
57 | ||
58 | #define CounterQuantity ( 4 ) | |
59 | //static const u32 CounterQuantity = 4; | |
60 | ||
61 | static const u32 CountToOverflow = 0; | |
62 | static const u32 CountToTarget = 1; | |
63 | ||
64 | static const u32 FrameRate[] = { 60, 50 }; | |
630b122b | 65 | static const u32 HSyncTotal[] = { 263, 314 }; // actually one more on odd lines for PAL |
0486fdc9 | 66 | #define VBlankStart 240 |
ef79bbde | 67 | |
9f7ee52e | 68 | #define VERBOSE_LEVEL 0 |
ef79bbde P |
69 | |
70 | /******************************************************************************/ | |
630b122b | 71 | #ifdef DRC_DISABLE |
93c9e42a | 72 | Rcnt rcnts[ CounterQuantity ]; |
1a32b0f8 | 73 | #endif |
24de2dd4 | 74 | u32 hSyncCount = 0; |
75 | u32 frame_counter = 0; | |
61ef5cf4 | 76 | static u32 hsync_steps = 0; |
ef79bbde P |
77 | |
78 | u32 psxNextCounter = 0, psxNextsCounter = 0; | |
79 | ||
80 | /******************************************************************************/ | |
81 | ||
82 | static inline | |
83 | void setIrq( u32 irq ) | |
84 | { | |
85 | psxHu32ref(0x1070) |= SWAPu32(irq); | |
86 | } | |
87 | ||
88 | static | |
9f7ee52e | 89 | void verboseLog( u32 level, const char *str, ... ) |
ef79bbde | 90 | { |
9f7ee52e | 91 | #if VERBOSE_LEVEL > 0 |
630b122b | 92 | if( level <= VERBOSE_LEVEL ) |
ef79bbde P |
93 | { |
94 | va_list va; | |
95 | char buf[ 4096 ]; | |
96 | ||
97 | va_start( va, str ); | |
98 | vsprintf( buf, str, va ); | |
99 | va_end( va ); | |
100 | ||
ab948f7e | 101 | printf( "%s", buf ); |
ef79bbde P |
102 | fflush( stdout ); |
103 | } | |
9f7ee52e | 104 | #endif |
ef79bbde P |
105 | } |
106 | ||
107 | /******************************************************************************/ | |
108 | ||
109 | static inline | |
110 | void _psxRcntWcount( u32 index, u32 value ) | |
111 | { | |
112 | if( value > 0xffff ) | |
113 | { | |
114 | verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value ); | |
115 | value &= 0xffff; | |
116 | } | |
117 | ||
118 | rcnts[index].cycleStart = psxRegs.cycle; | |
119 | rcnts[index].cycleStart -= value * rcnts[index].rate; | |
120 | ||
121 | // TODO: <=. | |
122 | if( value < rcnts[index].target ) | |
123 | { | |
124 | rcnts[index].cycle = rcnts[index].target * rcnts[index].rate; | |
125 | rcnts[index].counterState = CountToTarget; | |
126 | } | |
127 | else | |
128 | { | |
8ca6b0a6 | 129 | rcnts[index].cycle = 0x10000 * rcnts[index].rate; |
ef79bbde P |
130 | rcnts[index].counterState = CountToOverflow; |
131 | } | |
132 | } | |
133 | ||
134 | static inline | |
135 | u32 _psxRcntRcount( u32 index ) | |
136 | { | |
137 | u32 count; | |
138 | ||
139 | count = psxRegs.cycle; | |
140 | count -= rcnts[index].cycleStart; | |
61ef5cf4 | 141 | if (rcnts[index].rate > 1) |
142 | count /= rcnts[index].rate; | |
ef79bbde | 143 | |
8ca6b0a6 | 144 | if( count > 0x10000 ) |
ef79bbde | 145 | { |
8ca6b0a6 | 146 | verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count ); |
ef79bbde | 147 | } |
8ca6b0a6 | 148 | count &= 0xffff; |
ef79bbde P |
149 | |
150 | return count; | |
151 | } | |
152 | ||
a29f182f | 153 | static |
154 | void _psxRcntWmode( u32 index, u32 value ) | |
155 | { | |
156 | rcnts[index].mode = value; | |
157 | ||
158 | switch( index ) | |
159 | { | |
160 | case 0: | |
161 | if( value & Rc0PixelClock ) | |
162 | { | |
163 | rcnts[index].rate = 5; | |
164 | } | |
165 | else | |
166 | { | |
167 | rcnts[index].rate = 1; | |
168 | } | |
169 | break; | |
170 | case 1: | |
171 | if( value & Rc1HSyncClock ) | |
172 | { | |
173 | rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); | |
174 | } | |
175 | else | |
176 | { | |
177 | rcnts[index].rate = 1; | |
178 | } | |
179 | break; | |
180 | case 2: | |
181 | if( value & Rc2OneEighthClock ) | |
182 | { | |
183 | rcnts[index].rate = 8; | |
184 | } | |
185 | else | |
186 | { | |
187 | rcnts[index].rate = 1; | |
188 | } | |
189 | ||
190 | // TODO: wcount must work. | |
d3d41455 | 191 | if( (value & 7) == (RcSyncModeEnable | Rc2Stop) || |
192 | (value & 7) == (RcSyncModeEnable | Rc2Stop2) ) | |
a29f182f | 193 | { |
194 | rcnts[index].rate = 0xffffffff; | |
195 | } | |
196 | break; | |
197 | } | |
198 | } | |
199 | ||
ef79bbde P |
200 | /******************************************************************************/ |
201 | ||
202 | static | |
203 | void psxRcntSet() | |
204 | { | |
205 | s32 countToUpdate; | |
206 | u32 i; | |
207 | ||
208 | psxNextsCounter = psxRegs.cycle; | |
209 | psxNextCounter = 0x7fffffff; | |
210 | ||
211 | for( i = 0; i < CounterQuantity; ++i ) | |
212 | { | |
213 | countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart); | |
214 | ||
215 | if( countToUpdate < 0 ) | |
216 | { | |
217 | psxNextCounter = 0; | |
218 | break; | |
219 | } | |
220 | ||
221 | if( countToUpdate < (s32)psxNextCounter ) | |
222 | { | |
223 | psxNextCounter = countToUpdate; | |
224 | } | |
225 | } | |
5b8c000f | 226 | |
227 | psxRegs.interrupt |= (1 << PSXINT_RCNT); | |
228 | new_dyna_set_event(PSXINT_RCNT, psxNextCounter); | |
ef79bbde P |
229 | } |
230 | ||
231 | /******************************************************************************/ | |
232 | ||
233 | static | |
234 | void psxRcntReset( u32 index ) | |
235 | { | |
8ca6b0a6 | 236 | u32 rcycles; |
ef79bbde | 237 | |
53c361f0 | 238 | rcnts[index].mode |= RcUnknown10; |
239 | ||
ef79bbde P |
240 | if( rcnts[index].counterState == CountToTarget ) |
241 | { | |
8ca6b0a6 | 242 | rcycles = psxRegs.cycle - rcnts[index].cycleStart; |
ef79bbde | 243 | if( rcnts[index].mode & RcCountToTarget ) |
8ca6b0a6 | 244 | { |
245 | rcycles -= rcnts[index].target * rcnts[index].rate; | |
246 | rcnts[index].cycleStart = psxRegs.cycle - rcycles; | |
247 | } | |
248 | else | |
249 | { | |
250 | rcnts[index].cycle = 0x10000 * rcnts[index].rate; | |
251 | rcnts[index].counterState = CountToOverflow; | |
252 | } | |
ef79bbde P |
253 | |
254 | if( rcnts[index].mode & RcIrqOnTarget ) | |
255 | { | |
256 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) | |
257 | { | |
8ca6b0a6 | 258 | verboseLog( 3, "[RCNT %i] irq\n", index ); |
ef79bbde P |
259 | setIrq( rcnts[index].irq ); |
260 | rcnts[index].irqState = 1; | |
261 | } | |
262 | } | |
263 | ||
264 | rcnts[index].mode |= RcCountEqTarget; | |
53c361f0 | 265 | |
8ca6b0a6 | 266 | if( rcycles < 0x10000 * rcnts[index].rate ) |
53c361f0 | 267 | return; |
ef79bbde | 268 | } |
53c361f0 | 269 | |
270 | if( rcnts[index].counterState == CountToOverflow ) | |
ef79bbde | 271 | { |
8ca6b0a6 | 272 | rcycles = psxRegs.cycle - rcnts[index].cycleStart; |
273 | rcycles -= 0x10000 * rcnts[index].rate; | |
274 | ||
275 | rcnts[index].cycleStart = psxRegs.cycle - rcycles; | |
ef79bbde | 276 | |
8ca6b0a6 | 277 | if( rcycles < rcnts[index].target * rcnts[index].rate ) |
278 | { | |
279 | rcnts[index].cycle = rcnts[index].target * rcnts[index].rate; | |
280 | rcnts[index].counterState = CountToTarget; | |
281 | } | |
ef79bbde P |
282 | |
283 | if( rcnts[index].mode & RcIrqOnOverflow ) | |
284 | { | |
285 | if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) | |
286 | { | |
8ca6b0a6 | 287 | verboseLog( 3, "[RCNT %i] irq\n", index ); |
ef79bbde P |
288 | setIrq( rcnts[index].irq ); |
289 | rcnts[index].irqState = 1; | |
290 | } | |
291 | } | |
292 | ||
293 | rcnts[index].mode |= RcOverflow; | |
294 | } | |
ef79bbde P |
295 | } |
296 | ||
43614ebd | 297 | static void scheduleRcntBase(void) |
298 | { | |
299 | // Schedule next call, in hsyncs | |
300 | if (hSyncCount < VBlankStart) | |
301 | hsync_steps = VBlankStart - hSyncCount; | |
302 | else | |
303 | hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount; | |
304 | ||
305 | if (hSyncCount + hsync_steps == HSyncTotal[Config.PsxType]) | |
306 | { | |
307 | rcnts[3].cycle = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60; | |
308 | } | |
309 | else | |
310 | { | |
311 | // clk / 50 / 314 ~= 2157.25 | |
312 | // clk / 60 / 263 ~= 2146.31 | |
313 | u32 mult = Config.PsxType ? 8836089 : 8791293; | |
314 | rcnts[3].cycle = hsync_steps * mult >> 12; | |
315 | } | |
316 | } | |
317 | ||
ef79bbde P |
318 | void psxRcntUpdate() |
319 | { | |
d3d41455 | 320 | u32 cycle, cycles_passed; |
ef79bbde P |
321 | |
322 | cycle = psxRegs.cycle; | |
323 | ||
324 | // rcnt 0. | |
d3d41455 | 325 | cycles_passed = cycle - rcnts[0].cycleStart; |
326 | while( cycles_passed >= rcnts[0].cycle ) | |
ef79bbde | 327 | { |
d3d41455 | 328 | if (((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) || |
329 | (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2)) | |
330 | && cycles_passed > PSXCLK / 60 / 263) | |
331 | { | |
332 | u32 q = cycles_passed / (PSXCLK / 60 / 263 + 1u); | |
333 | rcnts[0].cycleStart += q * (PSXCLK / 60) / 263u; | |
334 | break; | |
335 | } | |
336 | else | |
337 | psxRcntReset( 0 ); | |
338 | ||
339 | cycles_passed = cycle - rcnts[0].cycleStart; | |
ef79bbde P |
340 | } |
341 | ||
342 | // rcnt 1. | |
74a0bb9f | 343 | while( cycle - rcnts[1].cycleStart >= rcnts[1].cycle ) |
ef79bbde P |
344 | { |
345 | psxRcntReset( 1 ); | |
346 | } | |
347 | ||
348 | // rcnt 2. | |
74a0bb9f | 349 | while( cycle - rcnts[2].cycleStart >= rcnts[2].cycle ) |
ef79bbde P |
350 | { |
351 | psxRcntReset( 2 ); | |
352 | } | |
353 | ||
354 | // rcnt base. | |
355 | if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle ) | |
356 | { | |
61ef5cf4 | 357 | hSyncCount += hsync_steps; |
ef79bbde | 358 | |
ef79bbde | 359 | // VSync irq. |
0486fdc9 | 360 | if( hSyncCount == VBlankStart ) |
ef79bbde | 361 | { |
adb7d7ac | 362 | HW_GPU_STATUS &= SWAP32(~PSXGPU_LCF); |
72e5023f | 363 | GPU_vBlank( 1, 0 ); |
8bbbd091 | 364 | setIrq( 0x01 ); |
365 | ||
366 | EmuUpdate(); | |
367 | GPU_updateLace(); | |
d618a240 | 368 | |
369 | if( SPU_async ) | |
370 | { | |
371 | SPU_async( cycle, 1 ); | |
372 | } | |
ef79bbde P |
373 | } |
374 | ||
840639a5 | 375 | // Update lace. |
376 | if( hSyncCount >= HSyncTotal[Config.PsxType] ) | |
ef79bbde | 377 | { |
d3d41455 | 378 | u32 status, field = 0, i; |
43614ebd | 379 | rcnts[3].cycleStart += Config.PsxType ? PSXCLK / 50 : PSXCLK / 60; |
ef79bbde | 380 | hSyncCount = 0; |
ddbaf678 | 381 | frame_counter++; |
ef79bbde | 382 | |
0486fdc9 | 383 | gpuSyncPluginSR(); |
4db82c07 | 384 | status = SWAP32(HW_GPU_STATUS) | PSXGPU_FIELD; |
385 | if ((status & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS) { | |
386 | field = frame_counter & 1; | |
387 | status |= field << 31; | |
388 | status ^= field << 13; | |
389 | } | |
390 | HW_GPU_STATUS = SWAP32(status); | |
391 | GPU_vBlank(0, field); | |
d3d41455 | 392 | |
393 | for (i = 0; i < 2; i++) | |
394 | { | |
395 | if ((rcnts[i].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) || | |
396 | (rcnts[i].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2)) | |
397 | { | |
398 | rcnts[i].cycleStart = rcnts[3].cycleStart; | |
399 | } | |
400 | } | |
ef79bbde | 401 | } |
61ef5cf4 | 402 | |
43614ebd | 403 | scheduleRcntBase(); |
ef79bbde P |
404 | } |
405 | ||
95df1a04 | 406 | psxRcntSet(); |
407 | ||
ee8fd567 | 408 | #if 0 //ndef NDEBUG |
ef79bbde | 409 | DebugVSync(); |
61ef5cf4 | 410 | #endif |
ef79bbde P |
411 | } |
412 | ||
413 | /******************************************************************************/ | |
414 | ||
415 | void psxRcntWcount( u32 index, u32 value ) | |
416 | { | |
417 | verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value ); | |
418 | ||
ef79bbde P |
419 | _psxRcntWcount( index, value ); |
420 | psxRcntSet(); | |
421 | } | |
422 | ||
423 | void psxRcntWmode( u32 index, u32 value ) | |
424 | { | |
425 | verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value ); | |
426 | ||
a29f182f | 427 | _psxRcntWmode( index, value ); |
ef79bbde | 428 | _psxRcntWcount( index, 0 ); |
a29f182f | 429 | |
430 | rcnts[index].irqState = 0; | |
ef79bbde P |
431 | psxRcntSet(); |
432 | } | |
433 | ||
434 | void psxRcntWtarget( u32 index, u32 value ) | |
435 | { | |
436 | verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value ); | |
437 | ||
ef79bbde P |
438 | rcnts[index].target = value; |
439 | ||
440 | _psxRcntWcount( index, _psxRcntRcount( index ) ); | |
441 | psxRcntSet(); | |
442 | } | |
443 | ||
444 | /******************************************************************************/ | |
445 | ||
d3d41455 | 446 | u32 psxRcntRcount0() |
447 | { | |
448 | u32 index = 0; | |
449 | u32 count; | |
450 | ||
451 | if ((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) || | |
452 | (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2)) | |
453 | { | |
454 | count = psxRegs.cycle - rcnts[index].cycleStart; | |
455 | count = ((16u * count) % (16u * PSXCLK / 60 / 263)) / 16u; | |
456 | rcnts[index].cycleStart = psxRegs.cycle - count; | |
457 | } | |
458 | else | |
459 | count = _psxRcntRcount( index ); | |
460 | ||
461 | verboseLog( 2, "[RCNT 0] rcount: %04x m: %04x\n", count, rcnts[index].mode); | |
462 | ||
463 | return count; | |
464 | } | |
465 | ||
466 | u32 psxRcntRcount1() | |
467 | { | |
468 | u32 index = 1; | |
469 | u32 count; | |
470 | ||
471 | count = _psxRcntRcount( index ); | |
472 | ||
473 | verboseLog( 2, "[RCNT 1] rcount: %04x m: %04x\n", count, rcnts[index].mode); | |
474 | ||
475 | return count; | |
476 | } | |
477 | ||
478 | u32 psxRcntRcount2() | |
ef79bbde | 479 | { |
d3d41455 | 480 | u32 index = 2; |
ef79bbde P |
481 | u32 count; |
482 | ||
ef79bbde P |
483 | count = _psxRcntRcount( index ); |
484 | ||
d3d41455 | 485 | verboseLog( 2, "[RCNT 2] rcount: %04x m: %04x\n", count, rcnts[index].mode); |
ef79bbde P |
486 | |
487 | return count; | |
488 | } | |
489 | ||
490 | u32 psxRcntRmode( u32 index ) | |
491 | { | |
492 | u16 mode; | |
493 | ||
ef79bbde P |
494 | mode = rcnts[index].mode; |
495 | rcnts[index].mode &= 0xe7ff; | |
496 | ||
497 | verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode ); | |
498 | ||
499 | return mode; | |
500 | } | |
501 | ||
502 | u32 psxRcntRtarget( u32 index ) | |
503 | { | |
504 | verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target ); | |
505 | ||
506 | return rcnts[index].target; | |
507 | } | |
508 | ||
509 | /******************************************************************************/ | |
510 | ||
511 | void psxRcntInit() | |
512 | { | |
513 | s32 i; | |
514 | ||
515 | // rcnt 0. | |
516 | rcnts[0].rate = 1; | |
517 | rcnts[0].irq = 0x10; | |
518 | ||
519 | // rcnt 1. | |
520 | rcnts[1].rate = 1; | |
521 | rcnts[1].irq = 0x20; | |
522 | ||
523 | // rcnt 2. | |
524 | rcnts[2].rate = 1; | |
525 | rcnts[2].irq = 0x40; | |
526 | ||
527 | // rcnt base. | |
528 | rcnts[3].rate = 1; | |
529 | rcnts[3].mode = RcCountToTarget; | |
530 | rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); | |
531 | ||
532 | for( i = 0; i < CounterQuantity; ++i ) | |
533 | { | |
534 | _psxRcntWcount( i, 0 ); | |
535 | } | |
536 | ||
c62b43c9 | 537 | hSyncCount = 0; |
61ef5cf4 | 538 | hsync_steps = 1; |
c62b43c9 | 539 | |
ef79bbde P |
540 | psxRcntSet(); |
541 | } | |
542 | ||
543 | /******************************************************************************/ | |
544 | ||
496d88d4 | 545 | s32 psxRcntFreeze( void *f, s32 Mode ) |
ef79bbde | 546 | { |
d618a240 | 547 | u32 spuSyncCount = 0; |
a29f182f | 548 | u32 count; |
549 | s32 i; | |
550 | ||
1a32b0f8 | 551 | gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity ); |
ef79bbde P |
552 | gzfreeze( &hSyncCount, sizeof(hSyncCount) ); |
553 | gzfreeze( &spuSyncCount, sizeof(spuSyncCount) ); | |
554 | gzfreeze( &psxNextCounter, sizeof(psxNextCounter) ); | |
555 | gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) ); | |
556 | ||
61ef5cf4 | 557 | if (Mode == 0) |
a29f182f | 558 | { |
559 | // don't trust things from a savestate | |
630b122b | 560 | rcnts[3].rate = 1; |
a29f182f | 561 | for( i = 0; i < CounterQuantity; ++i ) |
562 | { | |
563 | _psxRcntWmode( i, rcnts[i].mode ); | |
564 | count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate; | |
565 | _psxRcntWcount( i, count ); | |
566 | } | |
43614ebd | 567 | scheduleRcntBase(); |
a29f182f | 568 | psxRcntSet(); |
a29f182f | 569 | } |
4f55097d | 570 | |
ef79bbde P |
571 | return 0; |
572 | } | |
573 | ||
574 | /******************************************************************************/ | |
43614ebd | 575 | // vim:ts=4:shiftwidth=4:expandtab |