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1 | /*************************************************************************** |
2 | * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team * | |
3 | * * | |
4 | * This program is free software; you can redistribute it and/or modify * | |
5 | * it under the terms of the GNU General Public License as published by * | |
6 | * the Free Software Foundation; either version 2 of the License, or * | |
7 | * (at your option) any later version. * | |
8 | * * | |
9 | * This program is distributed in the hope that it will be useful, * | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
12 | * GNU General Public License for more details. * | |
13 | * * | |
14 | * You should have received a copy of the GNU General Public License * | |
15 | * along with this program; if not, write to the * | |
16 | * Free Software Foundation, Inc., * | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * | |
18 | ***************************************************************************/ | |
19 | ||
20 | #ifndef __PSXDMA_H__ | |
21 | #define __PSXDMA_H__ | |
22 | ||
23 | #ifdef __cplusplus | |
24 | extern "C" { | |
25 | #endif | |
26 | ||
27 | #include "psxcommon.h" | |
28 | #include "r3000a.h" | |
29 | #include "psxhw.h" | |
30 | #include "psxmem.h" | |
31 | ||
32 | #define GPUDMA_INT(eCycle) { \ | |
d28b54b1 | 33 | psxRegs.interrupt |= (1 << PSXINT_GPUDMA); \ |
34 | psxRegs.intCycle[PSXINT_GPUDMA].cycle = eCycle; \ | |
35 | psxRegs.intCycle[PSXINT_GPUDMA].sCycle = psxRegs.cycle; \ | |
36 | new_dyna_set_event(PSXINT_GPUDMA, eCycle); \ | |
ef79bbde P |
37 | } |
38 | ||
39 | #define SPUDMA_INT(eCycle) { \ | |
d28b54b1 | 40 | psxRegs.interrupt |= (1 << PSXINT_SPUDMA); \ |
41 | psxRegs.intCycle[PSXINT_SPUDMA].cycle = eCycle; \ | |
42 | psxRegs.intCycle[PSXINT_SPUDMA].sCycle = psxRegs.cycle; \ | |
43 | new_dyna_set_event(PSXINT_SPUDMA, eCycle); \ | |
ef79bbde P |
44 | } |
45 | ||
46 | #define MDECOUTDMA_INT(eCycle) { \ | |
d28b54b1 | 47 | psxRegs.interrupt |= (1 << PSXINT_MDECOUTDMA); \ |
48 | psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle = eCycle; \ | |
49 | psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle = psxRegs.cycle; \ | |
50 | new_dyna_set_event(PSXINT_MDECOUTDMA, eCycle); \ | |
ef79bbde P |
51 | } |
52 | ||
528ad661 | 53 | #define MDECINDMA_INT(eCycle) { \ |
54 | psxRegs.interrupt |= (1 << PSXINT_MDECINDMA); \ | |
55 | psxRegs.intCycle[PSXINT_MDECINDMA].cycle = eCycle; \ | |
56 | psxRegs.intCycle[PSXINT_MDECINDMA].sCycle = psxRegs.cycle; \ | |
57 | new_dyna_set_event(PSXINT_MDECINDMA, eCycle); \ | |
58 | } | |
59 | ||
57a757ce | 60 | #define GPUOTCDMA_INT(eCycle) { \ |
61 | psxRegs.interrupt |= (1 << PSXINT_GPUOTCDMA); \ | |
62 | psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle = eCycle; \ | |
63 | psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle = psxRegs.cycle; \ | |
64 | new_dyna_set_event(PSXINT_GPUOTCDMA, eCycle); \ | |
65 | } | |
66 | ||
ef79bbde P |
67 | void psxDma2(u32 madr, u32 bcr, u32 chcr); |
68 | void psxDma3(u32 madr, u32 bcr, u32 chcr); | |
69 | void psxDma4(u32 madr, u32 bcr, u32 chcr); | |
70 | void psxDma6(u32 madr, u32 bcr, u32 chcr); | |
71 | void gpuInterrupt(); | |
72 | void spuInterrupt(); | |
57a757ce | 73 | void gpuotcInterrupt(); |
ef79bbde P |
74 | |
75 | #ifdef __cplusplus | |
76 | } | |
77 | #endif | |
78 | #endif |