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1 | /*************************************************************************** |
2 | * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team * | |
3 | * * | |
4 | * This program is free software; you can redistribute it and/or modify * | |
5 | * it under the terms of the GNU General Public License as published by * | |
6 | * the Free Software Foundation; either version 2 of the License, or * | |
7 | * (at your option) any later version. * | |
8 | * * | |
9 | * This program is distributed in the hope that it will be useful, * | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
12 | * GNU General Public License for more details. * | |
13 | * * | |
14 | * You should have received a copy of the GNU General Public License * | |
15 | * along with this program; if not, write to the * | |
16 | * Free Software Foundation, Inc., * | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * | |
18 | ***************************************************************************/ | |
19 | ||
20 | #ifndef __PSXHW_H__ | |
21 | #define __PSXHW_H__ | |
22 | ||
23 | #ifdef __cplusplus | |
24 | extern "C" { | |
25 | #endif | |
26 | ||
27 | #include "psxcommon.h" | |
28 | #include "r3000a.h" | |
29 | #include "psxmem.h" | |
30 | #include "sio.h" | |
31 | #include "psxcounters.h" | |
32 | ||
33 | #define HW_DMA0_MADR (psxHu32ref(0x1080)) // MDEC in DMA | |
34 | #define HW_DMA0_BCR (psxHu32ref(0x1084)) | |
35 | #define HW_DMA0_CHCR (psxHu32ref(0x1088)) | |
36 | ||
37 | #define HW_DMA1_MADR (psxHu32ref(0x1090)) // MDEC out DMA | |
38 | #define HW_DMA1_BCR (psxHu32ref(0x1094)) | |
39 | #define HW_DMA1_CHCR (psxHu32ref(0x1098)) | |
40 | ||
41 | #define HW_DMA2_MADR (psxHu32ref(0x10a0)) // GPU DMA | |
42 | #define HW_DMA2_BCR (psxHu32ref(0x10a4)) | |
43 | #define HW_DMA2_CHCR (psxHu32ref(0x10a8)) | |
44 | ||
45 | #define HW_DMA3_MADR (psxHu32ref(0x10b0)) // CDROM DMA | |
46 | #define HW_DMA3_BCR (psxHu32ref(0x10b4)) | |
47 | #define HW_DMA3_CHCR (psxHu32ref(0x10b8)) | |
48 | ||
49 | #define HW_DMA4_MADR (psxHu32ref(0x10c0)) // SPU DMA | |
50 | #define HW_DMA4_BCR (psxHu32ref(0x10c4)) | |
51 | #define HW_DMA4_CHCR (psxHu32ref(0x10c8)) | |
52 | ||
53 | #define HW_DMA6_MADR (psxHu32ref(0x10e0)) // GPU DMA (OT) | |
54 | #define HW_DMA6_BCR (psxHu32ref(0x10e4)) | |
55 | #define HW_DMA6_CHCR (psxHu32ref(0x10e8)) | |
56 | ||
57 | #define HW_DMA_PCR (psxHu32ref(0x10f0)) | |
58 | #define HW_DMA_ICR (psxHu32ref(0x10f4)) | |
59 | ||
1f77c863 | 60 | #define HW_DMA_ICR_BUS_ERROR (1<<15) |
61 | #define HW_DMA_ICR_GLOBAL_ENABLE (1<<23) | |
62 | #define HW_DMA_ICR_IRQ_SENT (1<<31) | |
63 | ||
64 | #define DMA_INTERRUPT(n) { \ | |
65 | u32 icr = SWAPu32(HW_DMA_ICR); \ | |
66 | if (icr & (1 << (16 + n))) { \ | |
67 | icr |= 1 << (24 + n); \ | |
68 | if (icr & HW_DMA_ICR_GLOBAL_ENABLE && !(icr & HW_DMA_ICR_IRQ_SENT)) { \ | |
69 | psxHu32ref(0x1070) |= SWAP32(8); \ | |
70 | icr |= HW_DMA_ICR_IRQ_SENT; \ | |
71 | } \ | |
72 | HW_DMA_ICR = SWAP32(icr); \ | |
73 | } \ | |
74 | } | |
ef79bbde P |
75 | |
76 | void psxHwReset(); | |
77 | u8 psxHwRead8(u32 add); | |
78 | u16 psxHwRead16(u32 add); | |
79 | u32 psxHwRead32(u32 add); | |
20bfbac0 | 80 | void psxHwWrite8(u32 add, u32 value); |
81 | void psxHwWrite16(u32 add, u32 value); | |
ef79bbde | 82 | void psxHwWrite32(u32 add, u32 value); |
496d88d4 | 83 | int psxHwFreeze(void *f, int Mode); |
ef79bbde | 84 | |
a01b90c3 | 85 | void psxHwWriteIstat(u32 value); |
86 | void psxHwWriteImask(u32 value); | |
20bfbac0 | 87 | void psxHwWriteChcr0(u32 value); |
88 | void psxHwWriteChcr1(u32 value); | |
89 | void psxHwWriteChcr2(u32 value); | |
90 | void psxHwWriteChcr3(u32 value); | |
91 | void psxHwWriteChcr4(u32 value); | |
92 | void psxHwWriteChcr6(u32 value); | |
a01b90c3 | 93 | void psxHwWriteDmaIcr32(u32 value); |
979b861b | 94 | void psxHwWriteGpuSR(u32 value); |
95 | u32 psxHwReadGpuSR(void); | |
96 | u32 psxHwReadGpuSRbusyHack(void); | |
a01b90c3 | 97 | |
ef79bbde P |
98 | #ifdef __cplusplus |
99 | } | |
100 | #endif | |
101 | #endif |