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ef79bbde P |
1 | /*************************************************************************** |
2 | * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team * | |
633d365e | 3 | * Copyright (C) 2023 notaz * |
ef79bbde P |
4 | * * |
5 | * This program is free software; you can redistribute it and/or modify * | |
6 | * it under the terms of the GNU General Public License as published by * | |
7 | * the Free Software Foundation; either version 2 of the License, or * | |
8 | * (at your option) any later version. * | |
9 | * * | |
10 | * This program is distributed in the hope that it will be useful, * | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
13 | * GNU General Public License for more details. * | |
14 | * * | |
15 | * You should have received a copy of the GNU General Public License * | |
16 | * along with this program; if not, write to the * | |
17 | * Free Software Foundation, Inc., * | |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * | |
19 | ***************************************************************************/ | |
20 | ||
21 | /* | |
22 | * PSX assembly interpreter. | |
23 | */ | |
24 | ||
25 | #include "psxcommon.h" | |
26 | #include "r3000a.h" | |
27 | #include "gte.h" | |
28 | #include "psxhle.h" | |
630b122b | 29 | #include "psxinterpreter.h" |
cab87bf3 | 30 | #include <stddef.h> |
630b122b | 31 | #include <assert.h> |
dec3c1d7 | 32 | #include "../include/compiler_features.h" |
33 | ||
34 | // these may cause issues: because of poor timing we may step | |
35 | // on instructions that real hardware would never reach | |
36 | #define DO_EXCEPTION_RESERVEDI | |
633d365e | 37 | #define HANDLE_LOAD_DELAY |
ef79bbde | 38 | |
6d79a06f | 39 | static int branchSeen = 0; |
ef79bbde | 40 | |
cab87bf3 | 41 | #ifdef __i386__ |
42 | #define INT_ATTR __attribute__((regparm(2))) | |
43 | #else | |
44 | #define INT_ATTR | |
45 | #endif | |
46 | #ifndef INVALID_PTR | |
47 | #define INVALID_PTR NULL | |
48 | #endif | |
49 | ||
ef79bbde | 50 | // Subsets |
cab87bf3 | 51 | static void (INT_ATTR *psxBSC[64])(psxRegisters *regs_, u32 code); |
52 | static void (INT_ATTR *psxSPC[64])(psxRegisters *regs_, u32 code); | |
53 | ||
633d365e | 54 | // load delay |
55 | static void doLoad(psxRegisters *regs, u32 r, u32 val) | |
56 | { | |
57 | #ifdef HANDLE_LOAD_DELAY | |
58 | int sel = regs->dloadSel ^ 1; | |
59 | assert(regs->dloadReg[sel] == 0); | |
60 | regs->dloadReg[sel] = r; | |
61 | regs->dloadVal[sel] = r ? val : 0; | |
62 | if (regs->dloadReg[sel ^ 1] == r) | |
63 | regs->dloadVal[sel ^ 1] = regs->dloadReg[sel ^ 1] = 0; | |
64 | #else | |
65 | regs->GPR.r[r] = r ? val : 0; | |
66 | #endif | |
67 | } | |
68 | ||
69 | static void dloadRt(psxRegisters *regs, u32 r, u32 val) | |
70 | { | |
71 | #ifdef HANDLE_LOAD_DELAY | |
72 | int sel = regs->dloadSel; | |
73 | if (unlikely(regs->dloadReg[sel] == r)) | |
74 | regs->dloadVal[sel] = regs->dloadReg[sel] = 0; | |
75 | #endif | |
76 | regs->GPR.r[r] = r ? val : 0; | |
77 | } | |
78 | ||
79 | static void dloadStep(psxRegisters *regs) | |
80 | { | |
81 | #ifdef HANDLE_LOAD_DELAY | |
82 | int sel = regs->dloadSel; | |
83 | regs->GPR.r[regs->dloadReg[sel]] = regs->dloadVal[sel]; | |
84 | regs->dloadVal[sel] = regs->dloadReg[sel] = 0; | |
85 | regs->dloadSel ^= 1; | |
86 | assert(regs->GPR.r[0] == 0); | |
87 | #endif | |
88 | } | |
89 | ||
90 | static void dloadFlush(psxRegisters *regs) | |
91 | { | |
92 | #ifdef HANDLE_LOAD_DELAY | |
93 | regs->GPR.r[regs->dloadReg[0]] = regs->dloadVal[0]; | |
94 | regs->GPR.r[regs->dloadReg[1]] = regs->dloadVal[1]; | |
95 | regs->dloadVal[0] = regs->dloadVal[1] = 0; | |
96 | regs->dloadReg[0] = regs->dloadReg[1] = 0; | |
97 | assert(regs->GPR.r[0] == 0); | |
98 | #endif | |
99 | } | |
100 | ||
101 | static void dloadClear(psxRegisters *regs) | |
102 | { | |
103 | #ifdef HANDLE_LOAD_DELAY | |
104 | regs->dloadVal[0] = regs->dloadVal[1] = 0; | |
105 | regs->dloadReg[0] = regs->dloadReg[1] = 0; | |
106 | regs->dloadSel = 0; | |
107 | #endif | |
108 | } | |
109 | ||
110 | static void intException(psxRegisters *regs, u32 pc, u32 cause) | |
111 | { | |
6d79a06f | 112 | if (cause != 0x20) { |
113 | //FILE *f = fopen("/tmp/psx_ram.bin", "wb"); | |
114 | //fwrite(psxM, 1, 0x200000, f); fclose(f); | |
9415f066 | 115 | log_unhandled("exception %08x @%08x ra=%08x\n", |
116 | cause, pc, regs->GPR.n.ra); | |
6d79a06f | 117 | } |
633d365e | 118 | dloadFlush(regs); |
119 | regs->pc = pc; | |
6d79a06f | 120 | psxException(cause, regs->branching, ®s->CP0); |
121 | regs->branching = R3000A_BRANCH_NONE_OR_EXCEPTION; | |
122 | } | |
123 | ||
124 | // exception caused by current instruction (excluding unkasking) | |
125 | static void intExceptionInsn(psxRegisters *regs, u32 cause) | |
126 | { | |
127 | cause |= (regs->code & 0x0c000000) << 2; | |
128 | intException(regs, regs->pc - 4, cause); | |
129 | } | |
130 | ||
131 | // 29 Enable for 80000000-ffffffff | |
132 | // 30 Enable for 00000000-7fffffff | |
133 | // 31 Enable exception | |
134 | #define DBR_ABIT(dc, a) ((dc) & (1u << (29+(((a)>>31)^1)))) | |
135 | #define DBR_EN_EXEC(dc, a) (((dc) & 0x01800000) == 0x01800000 && DBR_ABIT(dc, a)) | |
136 | #define DBR_EN_LD(dc, a) (((dc) & 0x06800000) == 0x06800000 && DBR_ABIT(dc, a)) | |
137 | #define DBR_EN_ST(dc, a) (((dc) & 0x0a800000) == 0x0a800000 && DBR_ABIT(dc, a)) | |
138 | static void intExceptionDebugBp(psxRegisters *regs, u32 pc) | |
139 | { | |
140 | psxCP0Regs *cp0 = ®s->CP0; | |
141 | dloadFlush(regs); | |
142 | cp0->n.Cause &= 0x300; | |
143 | cp0->n.Cause |= (regs->branching << 30) | (R3000E_Bp << 2); | |
144 | cp0->n.SR = (cp0->n.SR & ~0x3f) | ((cp0->n.SR & 0x0f) << 2); | |
145 | cp0->n.EPC = regs->branching ? pc - 4 : pc; | |
146 | psxRegs.pc = 0x80000040; | |
147 | } | |
148 | ||
149 | static int execBreakCheck(psxRegisters *regs, u32 pc) | |
150 | { | |
151 | if (unlikely(DBR_EN_EXEC(regs->CP0.n.DCIC, pc) && | |
152 | ((pc ^ regs->CP0.n.BPC) & regs->CP0.n.BPCM) == 0)) | |
153 | { | |
154 | regs->CP0.n.DCIC |= 0x03; | |
155 | if (regs->CP0.n.DCIC & (1u << 31)) { | |
156 | intExceptionDebugBp(regs, pc); | |
157 | return 1; | |
158 | } | |
159 | } | |
160 | return 0; | |
633d365e | 161 | } |
162 | ||
dec3c1d7 | 163 | // get an opcode without triggering exceptions or affecting cache |
164 | u32 intFakeFetch(u32 pc) | |
165 | { | |
166 | u8 *base = psxMemRLUT[pc >> 16]; | |
167 | u32 *code; | |
168 | if (unlikely(base == INVALID_PTR)) | |
169 | return 0; // nop | |
170 | code = (u32 *)(base + (pc & 0xfffc)); | |
171 | return SWAP32(*code); | |
172 | ||
173 | } | |
174 | ||
175 | static u32 INT_ATTR fetchNoCache(psxRegisters *regs, u8 **memRLUT, u32 pc) | |
630b122b | 176 | { |
cab87bf3 | 177 | u8 *base = memRLUT[pc >> 16]; |
dec3c1d7 | 178 | u32 *code; |
179 | if (unlikely(base == INVALID_PTR)) { | |
180 | SysPrintf("game crash @%08x, ra=%08x\n", pc, regs->GPR.n.ra); | |
633d365e | 181 | intException(regs, pc, R3000E_IBE << 2); |
dec3c1d7 | 182 | return 0; // execute as nop |
183 | } | |
184 | code = (u32 *)(base + (pc & 0xfffc)); | |
cab87bf3 | 185 | return SWAP32(*code); |
630b122b | 186 | } |
187 | ||
7a811716 | 188 | /* |
189 | Formula One 2001 : | |
190 | Use old CPU cache code when the RAM location is updated with new code (affects in-game racing) | |
191 | */ | |
630b122b | 192 | static struct cache_entry { |
193 | u32 tag; | |
194 | u32 data[4]; | |
195 | } ICache[256]; | |
7a811716 | 196 | |
dec3c1d7 | 197 | static u32 INT_ATTR fetchICache(psxRegisters *regs, u8 **memRLUT, u32 pc) |
630b122b | 198 | { |
199 | // cached? | |
200 | if (pc < 0xa0000000) | |
7a811716 | 201 | { |
630b122b | 202 | // this is not how the hardware works but whatever |
203 | struct cache_entry *entry = &ICache[(pc & 0xff0) >> 4]; | |
204 | ||
205 | if (((entry->tag ^ pc) & 0xfffffff0) != 0 || pc < entry->tag) | |
7a811716 | 206 | { |
cab87bf3 | 207 | const u8 *base = memRLUT[pc >> 16]; |
208 | const u32 *code; | |
dec3c1d7 | 209 | if (unlikely(base == INVALID_PTR)) { |
210 | SysPrintf("game crash @%08x, ra=%08x\n", pc, regs->GPR.n.ra); | |
633d365e | 211 | intException(regs, pc, R3000E_IBE << 2); |
dec3c1d7 | 212 | return 0; // execute as nop |
213 | } | |
cab87bf3 | 214 | code = (u32 *)(base + (pc & 0xfff0)); |
630b122b | 215 | |
216 | entry->tag = pc; | |
217 | // treat as 4 words, although other configurations are said to be possible | |
218 | switch (pc & 0x0c) | |
219 | { | |
220 | case 0x00: entry->data[0] = SWAP32(code[0]); | |
221 | case 0x04: entry->data[1] = SWAP32(code[1]); | |
222 | case 0x08: entry->data[2] = SWAP32(code[2]); | |
223 | case 0x0c: entry->data[3] = SWAP32(code[3]); | |
224 | } | |
7a811716 | 225 | } |
630b122b | 226 | return entry->data[(pc & 0x0f) >> 2]; |
7a811716 | 227 | } |
228 | ||
dec3c1d7 | 229 | return fetchNoCache(regs, memRLUT, pc); |
7a811716 | 230 | } |
630b122b | 231 | |
dec3c1d7 | 232 | static u32 (INT_ATTR *fetch)(psxRegisters *regs_, u8 **memRLUT, u32 pc) = fetchNoCache; |
7a811716 | 233 | |
1562ed57 | 234 | // Make the timing events trigger faster as we are currently assuming everything |
235 | // takes one cycle, which is not the case on real hardware. | |
236 | // FIXME: count cache misses, memory latencies, stalls to get rid of this | |
6d79a06f | 237 | static inline void addCycle(psxRegisters *regs) |
1562ed57 | 238 | { |
6d79a06f | 239 | assert(regs->subCycleStep >= 0x10000); |
240 | regs->subCycle += regs->subCycleStep; | |
241 | regs->cycle += regs->subCycle >> 16; | |
242 | regs->subCycle &= 0xffff; | |
1562ed57 | 243 | } |
244 | ||
cab87bf3 | 245 | /**** R3000A Instruction Macros ****/ |
246 | #define _PC_ regs_->pc // The next PC to be executed | |
247 | ||
248 | #define _fOp_(code) ((code >> 26) ) // The opcode part of the instruction register | |
249 | #define _fFunct_(code) ((code ) & 0x3F) // The funct part of the instruction register | |
250 | #define _fRd_(code) ((code >> 11) & 0x1F) // The rd part of the instruction register | |
251 | #define _fRt_(code) ((code >> 16) & 0x1F) // The rt part of the instruction register | |
252 | #define _fRs_(code) ((code >> 21) & 0x1F) // The rs part of the instruction register | |
253 | #define _fSa_(code) ((code >> 6) & 0x1F) // The sa part of the instruction register | |
254 | #define _fIm_(code) ((u16)code) // The immediate part of the instruction register | |
255 | #define _fTarget_(code) (code & 0x03ffffff) // The target part of the instruction register | |
256 | ||
257 | #define _fImm_(code) ((s16)code) // sign-extended immediate | |
258 | #define _fImmU_(code) (code&0xffff) // zero-extended immediate | |
259 | ||
260 | #define _Op_ _fOp_(code) | |
261 | #define _Funct_ _fFunct_(code) | |
262 | #define _Rd_ _fRd_(code) | |
263 | #define _Rt_ _fRt_(code) | |
264 | #define _Rs_ _fRs_(code) | |
265 | #define _Sa_ _fSa_(code) | |
266 | #define _Im_ _fIm_(code) | |
267 | #define _Target_ _fTarget_(code) | |
268 | ||
269 | #define _Imm_ _fImm_(code) | |
270 | #define _ImmU_ _fImmU_(code) | |
271 | ||
272 | #define _rRs_ regs_->GPR.r[_Rs_] // Rs register | |
273 | #define _rRt_ regs_->GPR.r[_Rt_] // Rt register | |
cab87bf3 | 274 | #define _rSa_ regs_->GPR.r[_Sa_] // Sa register |
cab87bf3 | 275 | |
276 | #define _rHi_ regs_->GPR.n.hi // The HI register | |
277 | #define _rLo_ regs_->GPR.n.lo // The LO register | |
278 | ||
279 | #define _JumpTarget_ ((_Target_ * 4) + (_PC_ & 0xf0000000)) // Calculates the target during a jump instruction | |
280 | #define _BranchTarget_ ((s16)_Im_ * 4 + _PC_) // Calculates the target during a branch instruction | |
281 | ||
633d365e | 282 | #define _SetLink(x) dloadRt(regs_, x, _PC_ + 4); // Sets the return address in the link register |
cab87bf3 | 283 | |
284 | #define OP(name) \ | |
285 | static inline INT_ATTR void name(psxRegisters *regs_, u32 code) | |
286 | ||
ef79bbde P |
287 | // this defines shall be used with the tmp |
288 | // of the next func (instead of _Funct_...) | |
289 | #define _tFunct_ ((tmp ) & 0x3F) // The funct part of the instruction register | |
290 | #define _tRd_ ((tmp >> 11) & 0x1F) // The rd part of the instruction register | |
291 | #define _tRt_ ((tmp >> 16) & 0x1F) // The rt part of the instruction register | |
292 | #define _tRs_ ((tmp >> 21) & 0x1F) // The rs part of the instruction register | |
293 | #define _tSa_ ((tmp >> 6) & 0x1F) // The sa part of the instruction register | |
294 | ||
cab87bf3 | 295 | #define _i32(x) (s32)(x) |
296 | #define _u32(x) (u32)(x) | |
297 | ||
0f15c5bc | 298 | #define isBranch(c_) \ |
299 | ((1 <= ((c_) >> 26) && ((c_) >> 26) <= 7) || ((c_) & 0xfc00003e) == 8) | |
300 | #define swap_(a_, b_) { u32 t_ = a_; a_ = b_; b_ = t_; } | |
990cb018 | 301 | |
0f15c5bc | 302 | // tar1 is main branch target, 'code' is opcode in DS |
303 | static u32 psxBranchNoDelay(psxRegisters *regs_, u32 tar1, u32 code, int *taken) { | |
304 | u32 temp, rt; | |
305 | ||
306 | assert(isBranch(code)); | |
307 | *taken = 1; | |
308 | switch (code >> 26) { | |
990cb018 | 309 | case 0x00: // SPECIAL |
310 | switch (_Funct_) { | |
311 | case 0x08: // JR | |
312 | return _u32(_rRs_); | |
313 | case 0x09: // JALR | |
314 | temp = _u32(_rRs_); | |
0f15c5bc | 315 | if (_Rd_) |
316 | regs_->GPR.r[_Rd_] = tar1 + 4; | |
990cb018 | 317 | return temp; |
318 | } | |
319 | break; | |
320 | case 0x01: // REGIMM | |
0f15c5bc | 321 | rt = _Rt_; |
322 | switch (rt) { | |
323 | case 0x10: // BLTZAL | |
324 | regs_->GPR.n.ra = tar1 + 4; | |
990cb018 | 325 | if (_i32(_rRs_) < 0) |
0f15c5bc | 326 | return tar1 + (s16)_Im_ * 4; |
990cb018 | 327 | break; |
0f15c5bc | 328 | case 0x11: // BGEZAL |
329 | regs_->GPR.n.ra = tar1 + 4; | |
990cb018 | 330 | if (_i32(_rRs_) >= 0) |
0f15c5bc | 331 | return tar1 + (s16)_Im_ * 4; |
990cb018 | 332 | break; |
0f15c5bc | 333 | default: |
334 | if (rt & 1) { // BGEZ | |
335 | if (_i32(_rRs_) >= 0) | |
336 | return tar1 + (s16)_Im_ * 4; | |
990cb018 | 337 | } |
0f15c5bc | 338 | else { // BLTZ |
339 | if (_i32(_rRs_) < 0) | |
340 | return tar1 + (s16)_Im_ * 4; | |
990cb018 | 341 | } |
342 | break; | |
343 | } | |
344 | break; | |
345 | case 0x02: // J | |
0f15c5bc | 346 | return (tar1 & 0xf0000000u) + _Target_ * 4; |
990cb018 | 347 | case 0x03: // JAL |
0f15c5bc | 348 | regs_->GPR.n.ra = tar1 + 4; |
349 | return (tar1 & 0xf0000000u) + _Target_ * 4; | |
990cb018 | 350 | case 0x04: // BEQ |
351 | if (_i32(_rRs_) == _i32(_rRt_)) | |
0f15c5bc | 352 | return tar1 + (s16)_Im_ * 4; |
990cb018 | 353 | break; |
354 | case 0x05: // BNE | |
355 | if (_i32(_rRs_) != _i32(_rRt_)) | |
0f15c5bc | 356 | return tar1 + (s16)_Im_ * 4; |
990cb018 | 357 | break; |
358 | case 0x06: // BLEZ | |
359 | if (_i32(_rRs_) <= 0) | |
0f15c5bc | 360 | return tar1 + (s16)_Im_ * 4; |
990cb018 | 361 | break; |
362 | case 0x07: // BGTZ | |
363 | if (_i32(_rRs_) > 0) | |
0f15c5bc | 364 | return tar1 + (s16)_Im_ * 4; |
990cb018 | 365 | break; |
366 | } | |
367 | ||
0f15c5bc | 368 | *taken = 0; |
369 | return tar1; | |
990cb018 | 370 | } |
371 | ||
0f15c5bc | 372 | static void psxDoDelayBranch(psxRegisters *regs, u32 tar1, u32 code1) { |
373 | u32 tar2, code; | |
374 | int taken, lim; | |
990cb018 | 375 | |
0f15c5bc | 376 | tar2 = psxBranchNoDelay(regs, tar1, code1, &taken); |
377 | regs->pc = tar1; | |
378 | if (!taken) | |
379 | return; | |
990cb018 | 380 | |
990cb018 | 381 | /* |
0f15c5bc | 382 | * taken branch in delay slot: |
990cb018 | 383 | * - execute 1 instruction at tar1 |
384 | * - jump to tar2 (target of branch in delay slot; this branch | |
385 | * has no normal delay slot, instruction at tar1 was fetched instead) | |
386 | */ | |
0f15c5bc | 387 | for (lim = 0; lim < 8; lim++) { |
388 | regs->code = code = fetch(regs, psxMemRLUT, tar1); | |
6d79a06f | 389 | addCycle(regs); |
0f15c5bc | 390 | if (likely(!isBranch(code))) { |
633d365e | 391 | dloadStep(regs); |
0f15c5bc | 392 | psxBSC[code >> 26](regs, code); |
393 | regs->pc = tar2; | |
394 | return; | |
395 | } | |
396 | tar1 = psxBranchNoDelay(regs, tar2, code, &taken); | |
397 | regs->pc = tar2; | |
398 | if (!taken) | |
399 | return; | |
400 | swap_(tar1, tar2); | |
990cb018 | 401 | } |
0f15c5bc | 402 | SysPrintf("Evil chained DS branches @ %08x %08x %08x\n", regs->pc, tar1, tar2); |
990cb018 | 403 | } |
404 | ||
6d79a06f | 405 | static void doBranch(psxRegisters *regs, u32 tar, enum R3000Abdt taken) { |
406 | u32 code, pc, pc_final; | |
ef79bbde | 407 | |
6d79a06f | 408 | branchSeen = regs->branching = taken; |
409 | pc_final = taken == R3000A_BRANCH_TAKEN ? tar : regs->pc + 4; | |
990cb018 | 410 | |
0f15c5bc | 411 | // fetch the delay slot |
412 | pc = regs->pc; | |
413 | regs->pc = pc + 4; | |
414 | regs->code = code = fetch(regs, psxMemRLUT, pc); | |
dec3c1d7 | 415 | |
6d79a06f | 416 | addCycle(regs); |
ef79bbde | 417 | |
0f15c5bc | 418 | // check for branch in delay slot |
419 | if (unlikely(isBranch(code))) { | |
6d79a06f | 420 | regs->pc = pc; |
421 | if (taken == R3000A_BRANCH_TAKEN) | |
422 | psxDoDelayBranch(regs, tar, code); | |
0f15c5bc | 423 | log_unhandled("branch in DS: %08x->%08x\n", pc, regs->pc); |
6d79a06f | 424 | regs->branching = 0; |
0f15c5bc | 425 | psxBranchTest(); |
426 | return; | |
427 | } | |
428 | ||
633d365e | 429 | dloadStep(regs); |
0f15c5bc | 430 | psxBSC[code >> 26](regs, code); |
ef79bbde | 431 | |
6d79a06f | 432 | if (likely(regs->branching != R3000A_BRANCH_NONE_OR_EXCEPTION)) |
433 | regs->pc = pc_final; | |
434 | else | |
435 | regs->CP0.n.Target = pc_final; | |
436 | regs->branching = 0; | |
ef79bbde P |
437 | |
438 | psxBranchTest(); | |
439 | } | |
440 | ||
0f15c5bc | 441 | static void doBranchReg(psxRegisters *regs, u32 tar) { |
6d79a06f | 442 | doBranch(regs, tar & ~3, R3000A_BRANCH_TAKEN); |
443 | } | |
444 | ||
445 | static void doBranchRegE(psxRegisters *regs, u32 tar) { | |
446 | if (unlikely(DBR_EN_EXEC(regs->CP0.n.DCIC, tar) && | |
447 | ((tar ^ regs->CP0.n.BPC) & regs->CP0.n.BPCM) == 0)) | |
448 | regs->CP0.n.DCIC |= 0x03; | |
dec3c1d7 | 449 | if (unlikely(tar & 3)) { |
633d365e | 450 | SysPrintf("game crash @%08x, ra=%08x\n", tar, regs->GPR.n.ra); |
6d79a06f | 451 | regs->CP0.n.BadVAddr = tar; |
633d365e | 452 | intException(regs, tar, R3000E_AdEL << 2); |
dec3c1d7 | 453 | return; |
454 | } | |
6d79a06f | 455 | doBranch(regs, tar, R3000A_BRANCH_TAKEN); |
dec3c1d7 | 456 | } |
457 | ||
dec3c1d7 | 458 | static void addExc(psxRegisters *regs, u32 rt, s32 a1, s32 a2) { |
633d365e | 459 | s32 val; |
460 | if (add_overflow(a1, a2, val)) { | |
461 | //printf("ov %08x + %08x = %08x\n", a1, a2, val); | |
6d79a06f | 462 | intExceptionInsn(regs, R3000E_Ov << 2); |
dec3c1d7 | 463 | return; |
464 | } | |
633d365e | 465 | dloadRt(regs, rt, val); |
dec3c1d7 | 466 | } |
467 | ||
468 | static void subExc(psxRegisters *regs, u32 rt, s32 a1, s32 a2) { | |
633d365e | 469 | s32 val; |
470 | if (sub_overflow(a1, a2, val)) { | |
6d79a06f | 471 | intExceptionInsn(regs, R3000E_Ov << 2); |
dec3c1d7 | 472 | return; |
473 | } | |
633d365e | 474 | dloadRt(regs, rt, val); |
dec3c1d7 | 475 | } |
476 | ||
ef79bbde P |
477 | /********************************************************* |
478 | * Arithmetic with immediate operand * | |
479 | * Format: OP rt, rs, immediate * | |
480 | *********************************************************/ | |
633d365e | 481 | OP(psxADDI) { addExc (regs_, _Rt_, _i32(_rRs_), _Imm_); } // Rt = Rs + Im (Exception on Integer Overflow) |
482 | OP(psxADDIU) { dloadRt(regs_, _Rt_, _u32(_rRs_) + _Imm_ ); } // Rt = Rs + Im | |
483 | OP(psxANDI) { dloadRt(regs_, _Rt_, _u32(_rRs_) & _ImmU_); } // Rt = Rs And Im | |
484 | OP(psxORI) { dloadRt(regs_, _Rt_, _u32(_rRs_) | _ImmU_); } // Rt = Rs Or Im | |
485 | OP(psxXORI) { dloadRt(regs_, _Rt_, _u32(_rRs_) ^ _ImmU_); } // Rt = Rs Xor Im | |
486 | OP(psxSLTI) { dloadRt(regs_, _Rt_, _i32(_rRs_) < _Imm_ ); } // Rt = Rs < Im (Signed) | |
487 | OP(psxSLTIU) { dloadRt(regs_, _Rt_, _u32(_rRs_) < ((u32)_Imm_)); } // Rt = Rs < Im (Unsigned) | |
ef79bbde P |
488 | |
489 | /********************************************************* | |
490 | * Register arithmetic * | |
491 | * Format: OP rd, rs, rt * | |
492 | *********************************************************/ | |
633d365e | 493 | OP(psxADD) { addExc (regs_, _Rd_, _i32(_rRs_), _i32(_rRt_)); } // Rd = Rs + Rt (Exception on Integer Overflow) |
494 | OP(psxSUB) { subExc (regs_, _Rd_, _i32(_rRs_), _i32(_rRt_)); } // Rd = Rs - Rt (Exception on Integer Overflow) | |
495 | OP(psxADDU) { dloadRt(regs_, _Rd_, _u32(_rRs_) + _u32(_rRt_)); } // Rd = Rs + Rt | |
496 | OP(psxSUBU) { dloadRt(regs_, _Rd_, _u32(_rRs_) - _u32(_rRt_)); } // Rd = Rs - Rt | |
497 | OP(psxAND) { dloadRt(regs_, _Rd_, _u32(_rRs_) & _u32(_rRt_)); } // Rd = Rs And Rt | |
498 | OP(psxOR) { dloadRt(regs_, _Rd_, _u32(_rRs_) | _u32(_rRt_)); } // Rd = Rs Or Rt | |
499 | OP(psxXOR) { dloadRt(regs_, _Rd_, _u32(_rRs_) ^ _u32(_rRt_)); } // Rd = Rs Xor Rt | |
500 | OP(psxNOR) { dloadRt(regs_, _Rd_, ~_u32(_rRs_ | _u32(_rRt_))); } // Rd = Rs Nor Rt | |
501 | OP(psxSLT) { dloadRt(regs_, _Rd_, _i32(_rRs_) < _i32(_rRt_)); } // Rd = Rs < Rt (Signed) | |
502 | OP(psxSLTU) { dloadRt(regs_, _Rd_, _u32(_rRs_) < _u32(_rRt_)); } // Rd = Rs < Rt (Unsigned) | |
ef79bbde P |
503 | |
504 | /********************************************************* | |
505 | * Register mult/div & Register trap logic * | |
506 | * Format: OP rs, rt * | |
507 | *********************************************************/ | |
cab87bf3 | 508 | OP(psxDIV) { |
509 | if (!_rRt_) { | |
510 | _rHi_ = _rRs_; | |
511 | if (_rRs_ & 0x80000000) { | |
512 | _rLo_ = 1; | |
513 | } else { | |
514 | _rLo_ = 0xFFFFFFFF; | |
515 | } | |
516 | } | |
630b122b | 517 | #if !defined(__arm__) && !defined(__aarch64__) |
cab87bf3 | 518 | else if (_rRs_ == 0x80000000 && _rRt_ == 0xFFFFFFFF) { |
519 | _rLo_ = 0x80000000; | |
520 | _rHi_ = 0; | |
521 | } | |
630b122b | 522 | #endif |
cab87bf3 | 523 | else { |
524 | _rLo_ = _i32(_rRs_) / _i32(_rRt_); | |
525 | _rHi_ = _i32(_rRs_) % _i32(_rRt_); | |
526 | } | |
ef79bbde P |
527 | } |
528 | ||
cab87bf3 | 529 | OP(psxDIV_stall) { |
530 | regs_->muldivBusyCycle = regs_->cycle + 37; | |
531 | psxDIV(regs_, code); | |
630b122b | 532 | } |
533 | ||
cab87bf3 | 534 | OP(psxDIVU) { |
ef79bbde P |
535 | if (_rRt_ != 0) { |
536 | _rLo_ = _rRs_ / _rRt_; | |
537 | _rHi_ = _rRs_ % _rRt_; | |
538 | } | |
c7a56f4f | 539 | else { |
cab87bf3 | 540 | _rLo_ = 0xffffffff; |
541 | _rHi_ = _rRs_; | |
c7a56f4f | 542 | } |
ef79bbde P |
543 | } |
544 | ||
cab87bf3 | 545 | OP(psxDIVU_stall) { |
546 | regs_->muldivBusyCycle = regs_->cycle + 37; | |
547 | psxDIVU(regs_, code); | |
630b122b | 548 | } |
549 | ||
cab87bf3 | 550 | OP(psxMULT) { |
551 | u64 res = (s64)_i32(_rRs_) * _i32(_rRt_); | |
ef79bbde | 552 | |
cab87bf3 | 553 | regs_->GPR.n.lo = (u32)res; |
554 | regs_->GPR.n.hi = (u32)(res >> 32); | |
ef79bbde P |
555 | } |
556 | ||
cab87bf3 | 557 | OP(psxMULT_stall) { |
630b122b | 558 | // approximate, but maybe good enough |
559 | u32 rs = _rRs_; | |
560 | u32 lz = __builtin_clz(((rs ^ ((s32)rs >> 21)) | 1)); | |
561 | u32 c = 7 + (2 - (lz / 11)) * 4; | |
cab87bf3 | 562 | regs_->muldivBusyCycle = regs_->cycle + c; |
563 | psxMULT(regs_, code); | |
630b122b | 564 | } |
565 | ||
cab87bf3 | 566 | OP(psxMULTU) { |
567 | u64 res = (u64)_u32(_rRs_) * _u32(_rRt_); | |
ef79bbde | 568 | |
cab87bf3 | 569 | regs_->GPR.n.lo = (u32)(res & 0xffffffff); |
570 | regs_->GPR.n.hi = (u32)((res >> 32) & 0xffffffff); | |
ef79bbde P |
571 | } |
572 | ||
cab87bf3 | 573 | OP(psxMULTU_stall) { |
630b122b | 574 | // approximate, but maybe good enough |
575 | u32 lz = __builtin_clz(_rRs_ | 1); | |
576 | u32 c = 7 + (2 - (lz / 11)) * 4; | |
cab87bf3 | 577 | regs_->muldivBusyCycle = regs_->cycle + c; |
578 | psxMULTU(regs_, code); | |
630b122b | 579 | } |
580 | ||
ef79bbde P |
581 | /********************************************************* |
582 | * Register branch logic * | |
583 | * Format: OP rs, offset * | |
584 | *********************************************************/ | |
6d79a06f | 585 | #define BrCond(c) (c) ? R3000A_BRANCH_TAKEN : R3000A_BRANCH_NOT_TAKEN |
424e6d52 | 586 | #define RepZBranchi32(op) \ |
6d79a06f | 587 | doBranch(regs_, _BranchTarget_, BrCond(_i32(_rRs_) op 0)); |
424e6d52 | 588 | #define RepZBranchLinki32(op) { \ |
589 | s32 temp = _i32(_rRs_); \ | |
6d79a06f | 590 | dloadFlush(regs_); \ |
424e6d52 | 591 | _SetLink(31); \ |
6d79a06f | 592 | doBranch(regs_, _BranchTarget_, BrCond(temp op 0)); \ |
424e6d52 | 593 | } |
ef79bbde | 594 | |
cab87bf3 | 595 | OP(psxBGEZ) { RepZBranchi32(>=) } // Branch if Rs >= 0 |
596 | OP(psxBGEZAL) { RepZBranchLinki32(>=) } // Branch if Rs >= 0 and link | |
597 | OP(psxBGTZ) { RepZBranchi32(>) } // Branch if Rs > 0 | |
598 | OP(psxBLEZ) { RepZBranchi32(<=) } // Branch if Rs <= 0 | |
599 | OP(psxBLTZ) { RepZBranchi32(<) } // Branch if Rs < 0 | |
600 | OP(psxBLTZAL) { RepZBranchLinki32(<) } // Branch if Rs < 0 and link | |
ef79bbde P |
601 | |
602 | /********************************************************* | |
603 | * Shift arithmetic with constant shift * | |
604 | * Format: OP rd, rt, sa * | |
605 | *********************************************************/ | |
633d365e | 606 | OP(psxSLL) { dloadRt(regs_, _Rd_, _u32(_rRt_) << _Sa_); } // Rd = Rt << sa |
607 | OP(psxSRA) { dloadRt(regs_, _Rd_, _i32(_rRt_) >> _Sa_); } // Rd = Rt >> sa (arithmetic) | |
608 | OP(psxSRL) { dloadRt(regs_, _Rd_, _u32(_rRt_) >> _Sa_); } // Rd = Rt >> sa (logical) | |
ef79bbde P |
609 | |
610 | /********************************************************* | |
611 | * Shift arithmetic with variant register shift * | |
612 | * Format: OP rd, rt, rs * | |
613 | *********************************************************/ | |
633d365e | 614 | OP(psxSLLV) { dloadRt(regs_, _Rd_, _u32(_rRt_) << (_u32(_rRs_) & 0x1F)); } // Rd = Rt << rs |
615 | OP(psxSRAV) { dloadRt(regs_, _Rd_, _i32(_rRt_) >> (_u32(_rRs_) & 0x1F)); } // Rd = Rt >> rs (arithmetic) | |
616 | OP(psxSRLV) { dloadRt(regs_, _Rd_, _u32(_rRt_) >> (_u32(_rRs_) & 0x1F)); } // Rd = Rt >> rs (logical) | |
ef79bbde P |
617 | |
618 | /********************************************************* | |
619 | * Load higher 16 bits of the first word in GPR with imm * | |
620 | * Format: OP rt, immediate * | |
621 | *********************************************************/ | |
633d365e | 622 | OP(psxLUI) { dloadRt(regs_, _Rt_, code << 16); } // Upper halfword of Rt = Im |
ef79bbde P |
623 | |
624 | /********************************************************* | |
625 | * Move from HI/LO to GPR * | |
626 | * Format: OP rd * | |
627 | *********************************************************/ | |
633d365e | 628 | OP(psxMFHI) { dloadRt(regs_, _Rd_, _rHi_); } // Rd = Hi |
629 | OP(psxMFLO) { dloadRt(regs_, _Rd_, _rLo_); } // Rd = Lo | |
ef79bbde | 630 | |
cab87bf3 | 631 | static void mflohiCheckStall(psxRegisters *regs_) |
630b122b | 632 | { |
cab87bf3 | 633 | u32 left = regs_->muldivBusyCycle - regs_->cycle; |
630b122b | 634 | if (left <= 37) { |
635 | //printf("muldiv stall %u\n", left); | |
cab87bf3 | 636 | regs_->cycle = regs_->muldivBusyCycle; |
630b122b | 637 | } |
638 | } | |
639 | ||
cab87bf3 | 640 | OP(psxMFHI_stall) { mflohiCheckStall(regs_); psxMFHI(regs_, code); } |
641 | OP(psxMFLO_stall) { mflohiCheckStall(regs_); psxMFLO(regs_, code); } | |
630b122b | 642 | |
ef79bbde P |
643 | /********************************************************* |
644 | * Move to GPR to HI/LO & Register jump * | |
645 | * Format: OP rs * | |
646 | *********************************************************/ | |
cab87bf3 | 647 | OP(psxMTHI) { _rHi_ = _rRs_; } // Hi = Rs |
648 | OP(psxMTLO) { _rLo_ = _rRs_; } // Lo = Rs | |
ef79bbde P |
649 | |
650 | /********************************************************* | |
651 | * Special purpose instructions * | |
652 | * Format: OP * | |
653 | *********************************************************/ | |
cab87bf3 | 654 | OP(psxBREAK) { |
6d79a06f | 655 | intExceptionInsn(regs_, R3000E_Bp << 2); |
ef79bbde P |
656 | } |
657 | ||
cab87bf3 | 658 | OP(psxSYSCALL) { |
6d79a06f | 659 | intExceptionInsn(regs_, R3000E_Syscall << 2); |
ef79bbde P |
660 | } |
661 | ||
dec3c1d7 | 662 | static inline void execI_(u8 **memRLUT, psxRegisters *regs_); |
663 | ||
664 | static inline void psxTestSWInts(psxRegisters *regs_, int step) { | |
6d79a06f | 665 | if ((regs_->CP0.n.Cause & regs_->CP0.n.SR & 0x0300) && |
666 | (regs_->CP0.n.SR & 0x1)) { | |
dec3c1d7 | 667 | if (step) |
668 | execI_(psxMemRLUT, regs_); | |
cab87bf3 | 669 | regs_->CP0.n.Cause &= ~0x7c; |
633d365e | 670 | intException(regs_, regs_->pc, regs_->CP0.n.Cause); |
cab87bf3 | 671 | } |
672 | } | |
673 | ||
674 | OP(psxRFE) { | |
6d79a06f | 675 | regs_->CP0.n.SR = (regs_->CP0.n.SR & ~0x0f) | ((regs_->CP0.n.SR & 0x3c) >> 2); |
dec3c1d7 | 676 | psxTestSWInts(regs_, 0); |
ef79bbde P |
677 | } |
678 | ||
679 | /********************************************************* | |
680 | * Register branch logic * | |
681 | * Format: OP rs, rt, offset * | |
682 | *********************************************************/ | |
6d79a06f | 683 | #define RepBranchi32(op) \ |
684 | doBranch(regs_, _BranchTarget_, BrCond(_i32(_rRs_) op _i32(_rRt_))); | |
ef79bbde | 685 | |
cab87bf3 | 686 | OP(psxBEQ) { RepBranchi32(==) } // Branch if Rs == Rt |
687 | OP(psxBNE) { RepBranchi32(!=) } // Branch if Rs != Rt | |
ef79bbde P |
688 | |
689 | /********************************************************* | |
690 | * Jump to target * | |
691 | * Format: OP target * | |
692 | *********************************************************/ | |
6d79a06f | 693 | OP(psxJ) { doBranch(regs_, _JumpTarget_, R3000A_BRANCH_TAKEN); } |
694 | OP(psxJAL) { | |
695 | dloadFlush(regs_); | |
696 | _SetLink(31); | |
697 | doBranch(regs_, _JumpTarget_, R3000A_BRANCH_TAKEN); | |
698 | } | |
ef79bbde P |
699 | |
700 | /********************************************************* | |
701 | * Register jump * | |
702 | * Format: OP rs, rd * | |
703 | *********************************************************/ | |
cab87bf3 | 704 | OP(psxJR) { |
0f15c5bc | 705 | doBranchReg(regs_, _rRs_); |
ef79bbde P |
706 | psxJumpTest(); |
707 | } | |
708 | ||
6d79a06f | 709 | OP(psxJRe) { |
710 | doBranchRegE(regs_, _rRs_); | |
711 | psxJumpTest(); | |
712 | } | |
713 | ||
cab87bf3 | 714 | OP(psxJALR) { |
ef79bbde | 715 | u32 temp = _u32(_rRs_); |
6d79a06f | 716 | dloadFlush(regs_); |
ef79bbde | 717 | if (_Rd_) { _SetLink(_Rd_); } |
0f15c5bc | 718 | doBranchReg(regs_, temp); |
ef79bbde P |
719 | } |
720 | ||
6d79a06f | 721 | OP(psxJALRe) { |
722 | u32 temp = _u32(_rRs_); | |
723 | dloadFlush(regs_); | |
724 | if (_Rd_) { _SetLink(_Rd_); } | |
725 | doBranchRegE(regs_, temp); | |
726 | } | |
727 | ||
ef79bbde | 728 | /********************************************************* |
ef79bbde P |
729 | *********************************************************/ |
730 | ||
6d79a06f | 731 | // revisit: incomplete |
732 | #define BUS_LOCKED_ADDR(a) \ | |
733 | ((0x1fc80000u <= (a) && (a) < 0x80000000u) || \ | |
734 | (0xc0000000u <= (a) && (a) < 0xfffe0000u)) | |
735 | ||
736 | // exception checking order is important | |
737 | static inline int checkLD(psxRegisters *regs, u32 addr, u32 m) { | |
738 | int bpException = 0; | |
739 | if (unlikely(DBR_EN_LD(regs->CP0.n.DCIC, addr) && | |
740 | ((addr ^ regs->CP0.n.BDA) & regs->CP0.n.BDAM) == 0)) { | |
741 | regs->CP0.n.DCIC |= 0x0d; | |
742 | bpException = regs->CP0.n.DCIC >> 31; | |
743 | } | |
633d365e | 744 | if (unlikely(addr & m)) { |
6d79a06f | 745 | regs->CP0.n.BadVAddr = addr; |
746 | intExceptionInsn(regs, R3000E_AdEL << 2); | |
747 | return 0; | |
748 | } | |
749 | if (unlikely(bpException)) { | |
750 | intExceptionDebugBp(regs, regs->pc - 4); | |
751 | return 0; | |
752 | } | |
753 | if (unlikely(BUS_LOCKED_ADDR(addr))) { | |
754 | intException(regs, regs->pc - 4, R3000E_DBE << 2); | |
633d365e | 755 | return 0; |
633d365e | 756 | } |
757 | return 1; | |
758 | } | |
759 | ||
6d79a06f | 760 | static inline int checkST(psxRegisters *regs, u32 addr, u32 m) { |
761 | int bpException = 0; | |
762 | if (unlikely(DBR_EN_ST(regs->CP0.n.DCIC, addr) && | |
763 | ((addr ^ regs->CP0.n.BDA) & regs->CP0.n.BDAM) == 0)) { | |
764 | regs->CP0.n.DCIC |= 0x15; | |
765 | bpException = regs->CP0.n.DCIC >> 31; | |
766 | } | |
633d365e | 767 | if (unlikely(addr & m)) { |
6d79a06f | 768 | regs->CP0.n.BadVAddr = addr; |
769 | intExceptionInsn(regs, R3000E_AdES << 2); | |
770 | return 0; | |
771 | } | |
772 | if (unlikely(bpException)) { | |
773 | intExceptionDebugBp(regs, regs->pc - 4); | |
774 | return 0; | |
775 | } | |
776 | if (unlikely(BUS_LOCKED_ADDR(addr))) { | |
777 | intException(regs, regs->pc - 4, R3000E_DBE << 2); | |
633d365e | 778 | return 0; |
633d365e | 779 | } |
780 | return 1; | |
781 | } | |
782 | ||
783 | /********************************************************* | |
784 | * Load and store for GPR * | |
785 | * Format: OP rt, offset(base) * | |
786 | *********************************************************/ | |
787 | ||
6d79a06f | 788 | /********************************************************* |
789 | * Load and store for GPR * | |
790 | * Format: OP rt, offset(base) * | |
791 | *********************************************************/ | |
792 | ||
cab87bf3 | 793 | #define _oB_ (regs_->GPR.r[_Rs_] + _Imm_) |
ef79bbde | 794 | |
6d79a06f | 795 | OP(psxLB) { doLoad(regs_, _Rt_, (s8)psxMemRead8(_oB_)); } |
796 | OP(psxLBU) { doLoad(regs_, _Rt_, psxMemRead8(_oB_)); } | |
797 | OP(psxLH) { doLoad(regs_, _Rt_, (s16)psxMemRead16(_oB_ & ~1)); } | |
798 | OP(psxLHU) { doLoad(regs_, _Rt_, psxMemRead16(_oB_ & ~1)); } | |
799 | OP(psxLW) { doLoad(regs_, _Rt_, psxMemRead32(_oB_ & ~3)); } | |
ef79bbde | 800 | |
6d79a06f | 801 | OP(psxLBe) { if (checkLD(regs_, _oB_, 0)) doLoad(regs_, _Rt_, (s8)psxMemRead8(_oB_)); } |
802 | OP(psxLBUe) { if (checkLD(regs_, _oB_, 0)) doLoad(regs_, _Rt_, psxMemRead8(_oB_)); } | |
803 | OP(psxLHe) { if (checkLD(regs_, _oB_, 1)) doLoad(regs_, _Rt_, (s16)psxMemRead16(_oB_)); } | |
804 | OP(psxLHUe) { if (checkLD(regs_, _oB_, 1)) doLoad(regs_, _Rt_, psxMemRead16(_oB_)); } | |
805 | OP(psxLWe) { if (checkLD(regs_, _oB_, 3)) doLoad(regs_, _Rt_, psxMemRead32(_oB_)); } | |
806 | ||
807 | static void doLWL(psxRegisters *regs, u32 rt, u32 addr) { | |
cab87bf3 | 808 | static const u32 LWL_MASK[4] = { 0xffffff, 0xffff, 0xff, 0 }; |
809 | static const u32 LWL_SHIFT[4] = { 24, 16, 8, 0 }; | |
ef79bbde | 810 | u32 shift = addr & 3; |
6d79a06f | 811 | u32 val, mem; |
812 | u32 oldval = regs->GPR.r[rt]; | |
ef79bbde | 813 | |
633d365e | 814 | #ifdef HANDLE_LOAD_DELAY |
6d79a06f | 815 | int sel = regs->dloadSel; |
816 | if (regs->dloadReg[sel] == rt) | |
817 | oldval = regs->dloadVal[sel]; | |
633d365e | 818 | #endif |
6d79a06f | 819 | mem = psxMemRead32(addr & ~3); |
633d365e | 820 | val = (oldval & LWL_MASK[shift]) | (mem << LWL_SHIFT[shift]); |
6d79a06f | 821 | doLoad(regs, rt, val); |
ef79bbde P |
822 | |
823 | /* | |
824 | Mem = 1234. Reg = abcd | |
825 | ||
826 | 0 4bcd (mem << 24) | (reg & 0x00ffffff) | |
827 | 1 34cd (mem << 16) | (reg & 0x0000ffff) | |
828 | 2 234d (mem << 8) | (reg & 0x000000ff) | |
829 | 3 1234 (mem ) | (reg & 0x00000000) | |
830 | */ | |
831 | } | |
832 | ||
6d79a06f | 833 | static void doLWR(psxRegisters *regs, u32 rt, u32 addr) { |
cab87bf3 | 834 | static const u32 LWR_MASK[4] = { 0, 0xff000000, 0xffff0000, 0xffffff00 }; |
835 | static const u32 LWR_SHIFT[4] = { 0, 8, 16, 24 }; | |
ef79bbde | 836 | u32 shift = addr & 3; |
6d79a06f | 837 | u32 val, mem; |
838 | u32 oldval = regs->GPR.r[rt]; | |
ef79bbde | 839 | |
633d365e | 840 | #ifdef HANDLE_LOAD_DELAY |
6d79a06f | 841 | int sel = regs->dloadSel; |
842 | if (regs->dloadReg[sel] == rt) | |
843 | oldval = regs->dloadVal[sel]; | |
633d365e | 844 | #endif |
6d79a06f | 845 | mem = psxMemRead32(addr & ~3); |
633d365e | 846 | val = (oldval & LWR_MASK[shift]) | (mem >> LWR_SHIFT[shift]); |
6d79a06f | 847 | doLoad(regs, rt, val); |
ef79bbde P |
848 | |
849 | /* | |
850 | Mem = 1234. Reg = abcd | |
851 | ||
852 | 0 1234 (mem ) | (reg & 0x00000000) | |
853 | 1 a123 (mem >> 8) | (reg & 0xff000000) | |
854 | 2 ab12 (mem >> 16) | (reg & 0xffff0000) | |
855 | 3 abc1 (mem >> 24) | (reg & 0xffffff00) | |
856 | */ | |
857 | } | |
858 | ||
6d79a06f | 859 | OP(psxLWL) { doLWL(regs_, _Rt_, _oB_); } |
860 | OP(psxLWR) { doLWR(regs_, _Rt_, _oB_); } | |
ef79bbde | 861 | |
6d79a06f | 862 | OP(psxLWLe) { if (checkLD(regs_, _oB_ & ~3, 0)) doLWL(regs_, _Rt_, _oB_); } |
863 | OP(psxLWRe) { if (checkLD(regs_, _oB_ , 0)) doLWR(regs_, _Rt_, _oB_); } | |
ef79bbde | 864 | |
6d79a06f | 865 | OP(psxSB) { psxMemWrite8 (_oB_, _rRt_ & 0xff); } |
866 | OP(psxSH) { psxMemWrite16(_oB_, _rRt_ & 0xffff); } | |
867 | OP(psxSW) { psxMemWrite32(_oB_, _rRt_); } | |
868 | ||
869 | OP(psxSBe) { if (checkST(regs_, _oB_, 0)) psxMemWrite8 (_oB_, _rRt_ & 0xff); } | |
870 | OP(psxSHe) { if (checkST(regs_, _oB_, 1)) psxMemWrite16(_oB_, _rRt_ & 0xffff); } | |
871 | OP(psxSWe) { if (checkST(regs_, _oB_, 3)) psxMemWrite32(_oB_, _rRt_); } | |
872 | ||
873 | static void doSWL(psxRegisters *regs, u32 rt, u32 addr) { | |
874 | u32 val = regs->GPR.r[rt]; | |
875 | switch (addr & 3) { | |
876 | case 0: psxMemWrite8( addr , val >> 24); break; | |
877 | case 1: psxMemWrite16(addr & ~3, val >> 16); break; | |
878 | case 2: // revisit: should be a single 24bit write | |
879 | psxMemWrite16(addr & ~3, (val >> 8) & 0xffff); | |
880 | psxMemWrite8( addr , val >> 24); break; | |
881 | case 3: psxMemWrite32(addr & ~3, val); break; | |
882 | } | |
ef79bbde P |
883 | /* |
884 | Mem = 1234. Reg = abcd | |
885 | ||
886 | 0 123a (reg >> 24) | (mem & 0xffffff00) | |
887 | 1 12ab (reg >> 16) | (mem & 0xffff0000) | |
888 | 2 1abc (reg >> 8) | (mem & 0xff000000) | |
889 | 3 abcd (reg ) | (mem & 0x00000000) | |
890 | */ | |
891 | } | |
892 | ||
6d79a06f | 893 | static void doSWR(psxRegisters *regs, u32 rt, u32 addr) { |
894 | u32 val = regs->GPR.r[rt]; | |
895 | switch (addr & 3) { | |
896 | case 0: psxMemWrite32(addr , val); break; | |
897 | case 1: // revisit: should be a single 24bit write | |
898 | psxMemWrite8 (addr , val & 0xff); | |
899 | psxMemWrite16(addr + 1, (val >> 8) & 0xffff); break; | |
900 | case 2: psxMemWrite16(addr , val & 0xffff); break; | |
901 | case 3: psxMemWrite8 (addr , val & 0xff); break; | |
902 | } | |
ef79bbde P |
903 | |
904 | /* | |
905 | Mem = 1234. Reg = abcd | |
906 | ||
907 | 0 abcd (reg ) | (mem & 0x00000000) | |
908 | 1 bcd4 (reg << 8) | (mem & 0x000000ff) | |
909 | 2 cd34 (reg << 16) | (mem & 0x0000ffff) | |
910 | 3 d234 (reg << 24) | (mem & 0x00ffffff) | |
911 | */ | |
912 | } | |
913 | ||
6d79a06f | 914 | OP(psxSWL) { doSWL(regs_, _Rt_, _oB_); } |
915 | OP(psxSWR) { doSWR(regs_, _Rt_, _oB_); } | |
916 | ||
917 | OP(psxSWLe) { if (checkST(regs_, _oB_ & ~3, 0)) doSWL(regs_, _Rt_, _oB_); } | |
918 | OP(psxSWRe) { if (checkST(regs_, _oB_ , 0)) doSWR(regs_, _Rt_, _oB_); } | |
919 | ||
ef79bbde P |
920 | /********************************************************* |
921 | * Moves between GPR and COPx * | |
922 | * Format: OP rt, fs * | |
923 | *********************************************************/ | |
dec3c1d7 | 924 | OP(psxMFC0) { |
925 | u32 r = _Rd_; | |
926 | #ifdef DO_EXCEPTION_RESERVEDI | |
6d79a06f | 927 | if (unlikely(0x00000417u & (1u << r))) |
928 | intExceptionInsn(regs_, R3000E_RI << 2); | |
dec3c1d7 | 929 | #endif |
633d365e | 930 | doLoad(regs_, _Rt_, regs_->CP0.r[r]); |
dec3c1d7 | 931 | } |
932 | ||
dec3c1d7 | 933 | static void setupCop(u32 sr); |
934 | ||
cab87bf3 | 935 | void MTC0(psxRegisters *regs_, int reg, u32 val) { |
ef79bbde P |
936 | // SysPrintf("MTC0 %d: %x\n", reg, val); |
937 | switch (reg) { | |
6d79a06f | 938 | case 12: // SR |
939 | if (unlikely((regs_->CP0.n.SR ^ val) & (1 << 16))) | |
c6b7420b | 940 | psxMemOnIsolate((val >> 16) & 1); |
6d79a06f | 941 | if (unlikely((regs_->CP0.n.SR ^ val) & (7 << 29))) |
dec3c1d7 | 942 | setupCop(val); |
6d79a06f | 943 | regs_->CP0.n.SR = val; |
dec3c1d7 | 944 | psxTestSWInts(regs_, 1); |
ef79bbde P |
945 | break; |
946 | ||
947 | case 13: // Cause | |
cab87bf3 | 948 | regs_->CP0.n.Cause &= ~0x0300; |
949 | regs_->CP0.n.Cause |= val & 0x0300; | |
dec3c1d7 | 950 | psxTestSWInts(regs_, 0); |
ef79bbde P |
951 | break; |
952 | ||
6d79a06f | 953 | case 7: |
954 | if ((regs_->CP0.n.DCIC ^ val) & 0xff800000) | |
955 | log_unhandled("DCIC: %08x->%08x\n", regs_->CP0.n.DCIC, val); | |
956 | // fallthrough | |
ef79bbde | 957 | default: |
cab87bf3 | 958 | regs_->CP0.r[reg] = val; |
ef79bbde P |
959 | break; |
960 | } | |
961 | } | |
962 | ||
cab87bf3 | 963 | OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); } |
ef79bbde | 964 | |
6d79a06f | 965 | // no exception |
966 | static inline void psxNULLne(psxRegisters *regs) { | |
967 | log_unhandled("unhandled op %08x @%08x\n", regs->code, regs->pc - 4); | |
968 | } | |
969 | ||
ef79bbde | 970 | /********************************************************* |
dec3c1d7 | 971 | * Unknown instruction (would generate an exception) * |
ef79bbde P |
972 | * Format: ? * |
973 | *********************************************************/ | |
dec3c1d7 | 974 | |
975 | OP(psxNULL) { | |
6d79a06f | 976 | psxNULLne(regs_); |
dec3c1d7 | 977 | #ifdef DO_EXCEPTION_RESERVEDI |
6d79a06f | 978 | intExceptionInsn(regs_, R3000E_RI << 2); |
ef79bbde P |
979 | #endif |
980 | } | |
981 | ||
dec3c1d7 | 982 | void gteNULL(struct psxCP2Regs *regs) { |
6d79a06f | 983 | psxRegisters *regs_ = (psxRegisters *)((u8 *)regs - offsetof(psxRegisters, CP2)); |
984 | psxNULLne(regs_); | |
dec3c1d7 | 985 | } |
ef79bbde | 986 | |
cab87bf3 | 987 | OP(psxSPECIAL) { |
988 | psxSPC[_Funct_](regs_, code); | |
ef79bbde P |
989 | } |
990 | ||
cab87bf3 | 991 | OP(psxCOP0) { |
8659d7fd | 992 | u32 rs = _Rs_; |
993 | if (rs & 0x10) { | |
994 | u32 op2 = code & 0x1f; | |
995 | switch (op2) { | |
996 | case 0x01: | |
997 | case 0x02: | |
998 | case 0x06: | |
999 | case 0x08: psxNULL(regs_, code); break; | |
1000 | case 0x10: psxRFE(regs_, code); break; | |
1001 | default: psxNULLne(regs_); break; | |
1002 | } | |
1003 | return; | |
1004 | } | |
1005 | switch (rs) { | |
cab87bf3 | 1006 | case 0x00: psxMFC0(regs_, code); break; |
cab87bf3 | 1007 | case 0x04: psxMTC0(regs_, code); break; |
8659d7fd | 1008 | case 0x02: // CFC |
1009 | case 0x06: psxNULL(regs_, code); break; // CTC -> exception | |
1010 | case 0x08: | |
1011 | case 0x0c: log_unhandled("BC0 %08x @%08x\n", code, regs_->pc - 4); | |
6d79a06f | 1012 | default: psxNULLne(regs_); break; |
cab87bf3 | 1013 | } |
ef79bbde P |
1014 | } |
1015 | ||
dec3c1d7 | 1016 | OP(psxCOP1) { |
1017 | // ??? what actually happens here? | |
6d79a06f | 1018 | log_unhandled("COP1 %08x @%08x\n", code, regs_->pc - 4); |
dec3c1d7 | 1019 | } |
1020 | ||
cab87bf3 | 1021 | OP(psxCOP2) { |
8659d7fd | 1022 | u32 rt = _Rt_, rd = _Rd_, rs = _Rs_; |
1023 | if (rs & 0x10) { | |
1024 | psxCP2[_Funct_](®s_->CP2); | |
1025 | return; | |
1026 | } | |
1027 | switch (rs) { | |
1028 | case 0x00: doLoad(regs_, rt, MFC2(®s_->CP2, rd)); break; // MFC2 | |
1029 | case 0x02: doLoad(regs_, rt, regs_->CP2C.r[rd]); break; // CFC2 | |
1030 | case 0x04: MTC2(®s_->CP2, regs_->GPR.r[rt], rd); break; // MTC2 | |
1031 | case 0x06: CTC2(®s_->CP2, regs_->GPR.r[rt], rd); break; // CTC2 | |
1032 | case 0x08: | |
1033 | case 0x0c: log_unhandled("BC2 %08x @%08x\n", code, regs_->pc - 4); | |
1034 | default: psxNULLne(regs_); break; | |
1035 | } | |
ef79bbde P |
1036 | } |
1037 | ||
cab87bf3 | 1038 | OP(psxCOP2_stall) { |
630b122b | 1039 | u32 f = _Funct_; |
1040 | gteCheckStall(f); | |
8659d7fd | 1041 | psxCOP2(regs_, code); |
cab87bf3 | 1042 | } |
1043 | ||
1044 | OP(gteLWC2) { | |
1045 | MTC2(®s_->CP2, psxMemRead32(_oB_), _Rt_); | |
1046 | } | |
1047 | ||
cab87bf3 | 1048 | OP(gteLWC2_stall) { |
1049 | gteCheckStall(0); | |
1050 | gteLWC2(regs_, code); | |
db63e60d | 1051 | } |
1052 | ||
6d79a06f | 1053 | OP(gteLWC2e_stall) { |
1054 | gteCheckStall(0); | |
1055 | if (checkLD(regs_, _oB_, 3)) | |
1056 | MTC2(®s_->CP2, psxMemRead32(_oB_), _Rt_); | |
1057 | } | |
1058 | ||
1059 | OP(gteSWC2) { | |
1060 | psxMemWrite32(_oB_, MFC2(®s_->CP2, _Rt_)); | |
1061 | } | |
1062 | ||
cab87bf3 | 1063 | OP(gteSWC2_stall) { |
1064 | gteCheckStall(0); | |
1065 | gteSWC2(regs_, code); | |
1066 | } | |
1067 | ||
6d79a06f | 1068 | OP(gteSWC2e_stall) { |
1069 | gteCheckStall(0); | |
1070 | if (checkST(regs_, _oB_, 3)) | |
1071 | gteSWC2(regs_, code); | |
1072 | } | |
1073 | ||
dec3c1d7 | 1074 | OP(psxCOP3) { |
1075 | // ??? what actually happens here? | |
6d79a06f | 1076 | log_unhandled("COP3 %08x @%08x\n", code, regs_->pc - 4); |
dec3c1d7 | 1077 | } |
1078 | ||
6d79a06f | 1079 | OP(psxCOPd) { |
1080 | log_unhandled("disabled cop%d @%08x\n", (code >> 26) & 3, regs_->pc - 4); | |
dec3c1d7 | 1081 | #ifdef DO_EXCEPTION_RESERVEDI |
6d79a06f | 1082 | intExceptionInsn(regs_, R3000E_CpU << 2); |
dec3c1d7 | 1083 | #endif |
1084 | } | |
1085 | ||
1086 | OP(psxLWCx) { | |
6d79a06f | 1087 | log_unhandled("LWCx %08x @%08x\n", code, regs_->pc - 4); |
1088 | checkLD(regs_, _oB_, 3); | |
dec3c1d7 | 1089 | } |
1090 | ||
1091 | OP(psxSWCx) { | |
1092 | // does this write something to memory? | |
6d79a06f | 1093 | log_unhandled("SWCx %08x @%08x\n", code, regs_->pc - 4); |
1094 | checkST(regs_, _oB_, 3); | |
dec3c1d7 | 1095 | } |
1096 | ||
cab87bf3 | 1097 | OP(psxREGIMM) { |
424e6d52 | 1098 | u32 rt = _Rt_; |
1099 | switch (rt) { | |
cab87bf3 | 1100 | case 0x10: psxBLTZAL(regs_, code); break; |
1101 | case 0x11: psxBGEZAL(regs_, code); break; | |
424e6d52 | 1102 | default: |
1103 | if (rt & 1) | |
1104 | psxBGEZ(regs_, code); | |
1105 | else | |
1106 | psxBLTZ(regs_, code); | |
cab87bf3 | 1107 | } |
ef79bbde P |
1108 | } |
1109 | ||
cab87bf3 | 1110 | OP(psxHLE) { |
dec3c1d7 | 1111 | u32 hleCode; |
1112 | if (unlikely(!Config.HLE)) { | |
1113 | psxSWCx(regs_, code); | |
1114 | return; | |
1115 | } | |
1116 | hleCode = code & 0x03ffffff; | |
1117 | if (hleCode >= (sizeof(psxHLEt) / sizeof(psxHLEt[0]))) { | |
1118 | psxSWCx(regs_, code); | |
1119 | return; | |
1120 | } | |
1121 | psxHLEt[hleCode](); | |
9415f066 | 1122 | branchSeen = 1; |
ef79bbde P |
1123 | } |
1124 | ||
cab87bf3 | 1125 | static void (INT_ATTR *psxBSC[64])(psxRegisters *regs_, u32 code) = { |
ef79bbde P |
1126 | psxSPECIAL, psxREGIMM, psxJ , psxJAL , psxBEQ , psxBNE , psxBLEZ, psxBGTZ, |
1127 | psxADDI , psxADDIU , psxSLTI, psxSLTIU, psxANDI, psxORI , psxXORI, psxLUI , | |
6d79a06f | 1128 | psxCOP0 , psxCOPd , psxCOP2, psxCOPd, psxNULL, psxNULL, psxNULL, psxNULL, |
1129 | psxNULL , psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, | |
1130 | psxLB , psxLH , psxLWL , psxLW , psxLBU , psxLHU , psxLWR , psxNULL, | |
1131 | psxSB , psxSH , psxSWL , psxSW , psxNULL, psxNULL, psxSWR , psxNULL, | |
1132 | psxLWCx , psxLWCx , gteLWC2, psxLWCx , psxNULL, psxNULL, psxNULL, psxNULL, | |
1133 | psxSWCx , psxSWCx , gteSWC2, psxHLE , psxNULL, psxNULL, psxNULL, psxNULL, | |
ef79bbde P |
1134 | }; |
1135 | ||
cab87bf3 | 1136 | static void (INT_ATTR *psxSPC[64])(psxRegisters *regs_, u32 code) = { |
ef79bbde P |
1137 | psxSLL , psxNULL , psxSRL , psxSRA , psxSLLV , psxNULL , psxSRLV, psxSRAV, |
1138 | psxJR , psxJALR , psxNULL, psxNULL, psxSYSCALL, psxBREAK, psxNULL, psxNULL, | |
1139 | psxMFHI, psxMTHI , psxMFLO, psxMTLO, psxNULL , psxNULL , psxNULL, psxNULL, | |
1140 | psxMULT, psxMULTU, psxDIV , psxDIVU, psxNULL , psxNULL , psxNULL, psxNULL, | |
1141 | psxADD , psxADDU , psxSUB , psxSUBU, psxAND , psxOR , psxXOR , psxNOR , | |
1142 | psxNULL, psxNULL , psxSLT , psxSLTU, psxNULL , psxNULL , psxNULL, psxNULL, | |
1143 | psxNULL, psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, psxNULL, | |
1144 | psxNULL, psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, psxNULL | |
1145 | }; | |
1146 | ||
6c0eefaf | 1147 | void (*psxCP2[64])(struct psxCP2Regs *regs) = { |
8659d7fd | 1148 | gteNULL , gteRTPS , gteNULL , gteNULL, gteNULL, gteNULL , gteNCLIP, gteNULL, // 00 |
cab87bf3 | 1149 | gteNULL , gteNULL , gteNULL , gteNULL, gteOP , gteNULL , gteNULL , gteNULL, // 08 |
1150 | gteDPCS , gteINTPL, gteMVMVA, gteNCDS, gteCDP , gteNULL , gteNCDT , gteNULL, // 10 | |
1151 | gteNULL , gteNULL , gteNULL , gteNCCS, gteCC , gteNULL , gteNCS , gteNULL, // 18 | |
1152 | gteNCT , gteNULL , gteNULL , gteNULL, gteNULL, gteNULL , gteNULL , gteNULL, // 20 | |
1153 | gteSQR , gteDCPL , gteDPCT , gteNULL, gteNULL, gteAVSZ3, gteAVSZ4, gteNULL, // 28 | |
1154 | gteRTPT , gteNULL , gteNULL , gteNULL, gteNULL, gteNULL , gteNULL , gteNULL, // 30 | |
1155 | gteNULL , gteNULL , gteNULL , gteNULL, gteNULL, gteGPF , gteGPL , gteNCCT // 38 | |
ef79bbde P |
1156 | }; |
1157 | ||
ef79bbde P |
1158 | /////////////////////////////////////////// |
1159 | ||
1160 | static int intInit() { | |
1161 | return 0; | |
1162 | } | |
1163 | ||
1164 | static void intReset() { | |
633d365e | 1165 | dloadClear(&psxRegs); |
8659d7fd | 1166 | psxRegs.subCycle = 0; |
ef79bbde P |
1167 | } |
1168 | ||
6d79a06f | 1169 | static inline void execI_(u8 **memRLUT, psxRegisters *regs) { |
1170 | u32 pc = regs->pc; | |
dec3c1d7 | 1171 | |
6d79a06f | 1172 | addCycle(regs); |
1173 | dloadStep(regs); | |
cab87bf3 | 1174 | |
6d79a06f | 1175 | regs->pc += 4; |
1176 | regs->code = fetch(regs, memRLUT, pc); | |
1177 | psxBSC[regs->code >> 26](regs, regs->code); | |
1178 | } | |
1179 | ||
1180 | static inline void execIbp(u8 **memRLUT, psxRegisters *regs) { | |
1181 | u32 pc = regs->pc; | |
1182 | ||
1183 | addCycle(regs); | |
1184 | dloadStep(regs); | |
1185 | ||
1186 | if (execBreakCheck(regs, pc)) | |
1187 | return; | |
1188 | ||
1189 | regs->pc += 4; | |
1190 | regs->code = fetch(regs, memRLUT, pc); | |
1191 | psxBSC[regs->code >> 26](regs, regs->code); | |
cab87bf3 | 1192 | } |
1193 | ||
1194 | static void intExecute() { | |
1195 | psxRegisters *regs_ = &psxRegs; | |
1196 | u8 **memRLUT = psxMemRLUT; | |
796a91ef | 1197 | extern int stop; |
cab87bf3 | 1198 | |
1199 | while (!stop) | |
1200 | execI_(memRLUT, regs_); | |
ef79bbde P |
1201 | } |
1202 | ||
6d79a06f | 1203 | static void intExecuteBp() { |
1204 | psxRegisters *regs_ = &psxRegs; | |
1205 | u8 **memRLUT = psxMemRLUT; | |
1206 | extern int stop; | |
1207 | ||
1208 | while (!stop) | |
1209 | execIbp(memRLUT, regs_); | |
1210 | } | |
1211 | ||
f3bc907d | 1212 | void intExecuteBlock(enum blockExecCaller caller) { |
cab87bf3 | 1213 | psxRegisters *regs_ = &psxRegs; |
1214 | u8 **memRLUT = psxMemRLUT; | |
1215 | ||
6d79a06f | 1216 | branchSeen = 0; |
1217 | while (!branchSeen) | |
cab87bf3 | 1218 | execI_(memRLUT, regs_); |
ef79bbde P |
1219 | } |
1220 | ||
1221 | static void intClear(u32 Addr, u32 Size) { | |
1222 | } | |
1223 | ||
20196899 | 1224 | static void intNotify(enum R3000Anote note, void *data) { |
1225 | switch (note) { | |
633d365e | 1226 | case R3000ACPU_NOTIFY_BEFORE_SAVE: |
1227 | dloadFlush(&psxRegs); | |
1228 | break; | |
20196899 | 1229 | case R3000ACPU_NOTIFY_AFTER_LOAD: |
633d365e | 1230 | dloadClear(&psxRegs); |
8659d7fd | 1231 | psxRegs.subCycle = 0; |
6d79a06f | 1232 | setupCop(psxRegs.CP0.n.SR); |
dec3c1d7 | 1233 | // fallthrough |
1234 | case R3000ACPU_NOTIFY_CACHE_ISOLATED: // Armored Core? | |
630b122b | 1235 | memset(&ICache, 0xff, sizeof(ICache)); |
20196899 | 1236 | break; |
1237 | case R3000ACPU_NOTIFY_CACHE_UNISOLATED: | |
20196899 | 1238 | break; |
7a811716 | 1239 | } |
7a811716 | 1240 | } |
1241 | ||
dec3c1d7 | 1242 | static void setupCop(u32 sr) |
1243 | { | |
1244 | if (sr & (1u << 29)) | |
1245 | psxBSC[17] = psxCOP1; | |
1246 | else | |
6d79a06f | 1247 | psxBSC[17] = psxCOPd; |
dec3c1d7 | 1248 | if (sr & (1u << 30)) |
1249 | psxBSC[18] = Config.DisableStalls ? psxCOP2 : psxCOP2_stall; | |
1250 | else | |
6d79a06f | 1251 | psxBSC[18] = psxCOPd; |
dec3c1d7 | 1252 | if (sr & (1u << 31)) |
1253 | psxBSC[19] = psxCOP3; | |
1254 | else | |
6d79a06f | 1255 | psxBSC[19] = psxCOPd; |
dec3c1d7 | 1256 | } |
1257 | ||
630b122b | 1258 | void intApplyConfig() { |
1562ed57 | 1259 | int cycle_mult; |
1260 | ||
630b122b | 1261 | assert(psxSPC[16] == psxMFHI || psxSPC[16] == psxMFHI_stall); |
1262 | assert(psxSPC[18] == psxMFLO || psxSPC[18] == psxMFLO_stall); | |
1263 | assert(psxSPC[24] == psxMULT || psxSPC[24] == psxMULT_stall); | |
1264 | assert(psxSPC[25] == psxMULTU || psxSPC[25] == psxMULTU_stall); | |
1265 | assert(psxSPC[26] == psxDIV || psxSPC[26] == psxDIV_stall); | |
1266 | assert(psxSPC[27] == psxDIVU || psxSPC[27] == psxDIVU_stall); | |
1267 | ||
1268 | if (Config.DisableStalls) { | |
1269 | psxBSC[18] = psxCOP2; | |
1270 | psxBSC[50] = gteLWC2; | |
1271 | psxBSC[58] = gteSWC2; | |
1272 | psxSPC[16] = psxMFHI; | |
1273 | psxSPC[18] = psxMFLO; | |
1274 | psxSPC[24] = psxMULT; | |
1275 | psxSPC[25] = psxMULTU; | |
1276 | psxSPC[26] = psxDIV; | |
1277 | psxSPC[27] = psxDIVU; | |
1278 | } else { | |
1279 | psxBSC[18] = psxCOP2_stall; | |
1280 | psxBSC[50] = gteLWC2_stall; | |
1281 | psxBSC[58] = gteSWC2_stall; | |
1282 | psxSPC[16] = psxMFHI_stall; | |
1283 | psxSPC[18] = psxMFLO_stall; | |
1284 | psxSPC[24] = psxMULT_stall; | |
1285 | psxSPC[25] = psxMULTU_stall; | |
1286 | psxSPC[26] = psxDIV_stall; | |
1287 | psxSPC[27] = psxDIVU_stall; | |
7a811716 | 1288 | } |
6d79a06f | 1289 | setupCop(psxRegs.CP0.n.SR); |
1290 | ||
1291 | if (Config.PreciseExceptions) { | |
1292 | psxBSC[0x20] = psxLBe; | |
1293 | psxBSC[0x21] = psxLHe; | |
1294 | psxBSC[0x22] = psxLWLe; | |
1295 | psxBSC[0x23] = psxLWe; | |
1296 | psxBSC[0x24] = psxLBUe; | |
1297 | psxBSC[0x25] = psxLHUe; | |
1298 | psxBSC[0x26] = psxLWRe; | |
1299 | psxBSC[0x28] = psxSBe; | |
1300 | psxBSC[0x29] = psxSHe; | |
1301 | psxBSC[0x2a] = psxSWLe; | |
1302 | psxBSC[0x2b] = psxSWe; | |
1303 | psxBSC[0x2e] = psxSWRe; | |
1304 | psxBSC[0x32] = gteLWC2e_stall; | |
1305 | psxBSC[0x3a] = gteSWC2e_stall; | |
1306 | psxSPC[0x08] = psxJRe; | |
1307 | psxSPC[0x09] = psxJALRe; | |
1308 | psxInt.Execute = intExecuteBp; | |
1309 | } else { | |
1310 | psxBSC[0x20] = psxLB; | |
1311 | psxBSC[0x21] = psxLH; | |
1312 | psxBSC[0x22] = psxLWL; | |
1313 | psxBSC[0x23] = psxLW; | |
1314 | psxBSC[0x24] = psxLBU; | |
1315 | psxBSC[0x25] = psxLHU; | |
1316 | psxBSC[0x26] = psxLWR; | |
1317 | psxBSC[0x28] = psxSB; | |
1318 | psxBSC[0x29] = psxSH; | |
1319 | psxBSC[0x2a] = psxSWL; | |
1320 | psxBSC[0x2b] = psxSW; | |
1321 | psxBSC[0x2e] = psxSWR; | |
1322 | // LWC2, SWC2 handled by Config.DisableStalls | |
1323 | psxSPC[0x08] = psxJR; | |
1324 | psxSPC[0x09] = psxJALR; | |
1325 | psxInt.Execute = intExecute; | |
1326 | } | |
7a811716 | 1327 | |
6d79a06f | 1328 | // the dynarec may occasionally call the interpreter, in such a case the |
630b122b | 1329 | // cache won't work (cache only works right if all fetches go through it) |
1330 | if (!Config.icache_emulation || psxCpu != &psxInt) | |
1331 | fetch = fetchNoCache; | |
1332 | else | |
1333 | fetch = fetchICache; | |
1562ed57 | 1334 | |
1335 | cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT | |
1336 | ? Config.cycle_multiplier_override : Config.cycle_multiplier; | |
1337 | psxRegs.subCycleStep = 0x10000 * cycle_mult / 100; | |
630b122b | 1338 | } |
1339 | ||
1340 | static void intShutdown() { | |
f2e25348 | 1341 | dloadClear(&psxRegs); |
ef79bbde P |
1342 | } |
1343 | ||
f2e25348 | 1344 | // single step (may do several ops in case of a branch or load delay) |
5753f874 | 1345 | // called by asm/dynarec |
6d79a06f | 1346 | void execI(psxRegisters *regs) { |
f2e25348 | 1347 | do { |
1348 | execIbp(psxMemRLUT, regs); | |
1349 | } while (regs->dloadReg[0] || regs->dloadReg[1]); | |
ef79bbde P |
1350 | } |
1351 | ||
1352 | R3000Acpu psxInt = { | |
1353 | intInit, | |
1354 | intReset, | |
1355 | intExecute, | |
1356 | intExecuteBlock, | |
1357 | intClear, | |
7a811716 | 1358 | intNotify, |
630b122b | 1359 | intApplyConfig, |
ef79bbde P |
1360 | intShutdown |
1361 | }; |