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1 | /*************************************************************************** |
2 | * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team * | |
3 | * * | |
4 | * This program is free software; you can redistribute it and/or modify * | |
5 | * it under the terms of the GNU General Public License as published by * | |
6 | * the Free Software Foundation; either version 2 of the License, or * | |
7 | * (at your option) any later version. * | |
8 | * * | |
9 | * This program is distributed in the hope that it will be useful, * | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
12 | * GNU General Public License for more details. * | |
13 | * * | |
14 | * You should have received a copy of the GNU General Public License * | |
15 | * along with this program; if not, write to the * | |
16 | * Free Software Foundation, Inc., * | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. * | |
18 | ***************************************************************************/ | |
19 | ||
20 | #ifndef __R3000A_H__ | |
21 | #define __R3000A_H__ | |
22 | ||
23 | #ifdef __cplusplus | |
24 | extern "C" { | |
25 | #endif | |
26 | ||
27 | #include "psxcommon.h" | |
28 | #include "psxmem.h" | |
29 | #include "psxcounters.h" | |
30 | #include "psxbios.h" | |
31 | ||
32 | typedef struct { | |
33 | int (*Init)(); | |
34 | void (*Reset)(); | |
35 | void (*Execute)(); /* executes up to a break */ | |
36 | void (*ExecuteBlock)(); /* executes up to a jump */ | |
37 | void (*Clear)(u32 Addr, u32 Size); | |
38 | void (*Shutdown)(); | |
39 | } R3000Acpu; | |
40 | ||
41 | extern R3000Acpu *psxCpu; | |
42 | extern R3000Acpu psxInt; | |
f95a77f7 | 43 | #if (defined(__x86_64__) || defined(__i386__) || defined(__sh__) || defined(__ppc__) || defined(__arm__)) && !defined(NOPSXREC) |
ef79bbde P |
44 | extern R3000Acpu psxRec; |
45 | #define PSXREC | |
46 | #endif | |
47 | ||
48 | typedef union { | |
49 | #if defined(__BIGENDIAN__) | |
50 | struct { u8 h3, h2, h, l; } b; | |
51 | struct { s8 h3, h2, h, l; } sb; | |
52 | struct { u16 h, l; } w; | |
53 | struct { s16 h, l; } sw; | |
54 | #else | |
55 | struct { u8 l, h, h2, h3; } b; | |
56 | struct { u16 l, h; } w; | |
57 | struct { s8 l, h, h2, h3; } sb; | |
58 | struct { s16 l, h; } sw; | |
59 | #endif | |
60 | } PAIR; | |
61 | ||
62 | typedef union { | |
63 | struct { | |
64 | u32 r0, at, v0, v1, a0, a1, a2, a3, | |
65 | t0, t1, t2, t3, t4, t5, t6, t7, | |
66 | s0, s1, s2, s3, s4, s5, s6, s7, | |
67 | t8, t9, k0, k1, gp, sp, s8, ra, lo, hi; | |
68 | } n; | |
69 | u32 r[34]; /* Lo, Hi in r[32] and r[33] */ | |
70 | PAIR p[34]; | |
71 | } psxGPRRegs; | |
72 | ||
73 | typedef union { | |
74 | struct { | |
75 | u32 Index, Random, EntryLo0, EntryLo1, | |
76 | Context, PageMask, Wired, Reserved0, | |
77 | BadVAddr, Count, EntryHi, Compare, | |
78 | Status, Cause, EPC, PRid, | |
79 | Config, LLAddr, WatchLO, WatchHI, | |
80 | XContext, Reserved1, Reserved2, Reserved3, | |
81 | Reserved4, Reserved5, ECC, CacheErr, | |
82 | TagLo, TagHi, ErrorEPC, Reserved6; | |
83 | } n; | |
84 | u32 r[32]; | |
85 | PAIR p[32]; | |
86 | } psxCP0Regs; | |
87 | ||
88 | typedef struct { | |
89 | short x, y; | |
90 | } SVector2D; | |
91 | ||
92 | typedef struct { | |
93 | short z, pad; | |
94 | } SVector2Dz; | |
95 | ||
96 | typedef struct { | |
97 | short x, y, z, pad; | |
98 | } SVector3D; | |
99 | ||
100 | typedef struct { | |
101 | short x, y, z, pad; | |
102 | } LVector3D; | |
103 | ||
104 | typedef struct { | |
105 | unsigned char r, g, b, c; | |
106 | } CBGR; | |
107 | ||
108 | typedef struct { | |
109 | short m11, m12, m13, m21, m22, m23, m31, m32, m33, pad; | |
110 | } SMatrix3D; | |
111 | ||
112 | typedef union { | |
113 | struct { | |
114 | SVector3D v0, v1, v2; | |
115 | CBGR rgb; | |
116 | s32 otz; | |
117 | s32 ir0, ir1, ir2, ir3; | |
118 | SVector2D sxy0, sxy1, sxy2, sxyp; | |
119 | SVector2Dz sz0, sz1, sz2, sz3; | |
120 | CBGR rgb0, rgb1, rgb2; | |
121 | s32 reserved; | |
122 | s32 mac0, mac1, mac2, mac3; | |
123 | u32 irgb, orgb; | |
124 | s32 lzcs, lzcr; | |
125 | } n; | |
126 | u32 r[32]; | |
127 | PAIR p[32]; | |
128 | } psxCP2Data; | |
129 | ||
130 | typedef union { | |
131 | struct { | |
132 | SMatrix3D rMatrix; | |
133 | s32 trX, trY, trZ; | |
134 | SMatrix3D lMatrix; | |
135 | s32 rbk, gbk, bbk; | |
136 | SMatrix3D cMatrix; | |
137 | s32 rfc, gfc, bfc; | |
138 | s32 ofx, ofy; | |
139 | s32 h; | |
140 | s32 dqa, dqb; | |
141 | s32 zsf3, zsf4; | |
142 | s32 flag; | |
143 | } n; | |
144 | u32 r[32]; | |
145 | PAIR p[32]; | |
146 | } psxCP2Ctrl; | |
147 | ||
d28b54b1 | 148 | enum { |
149 | PSXINT_SIO = 0, | |
150 | PSXINT_CDR, | |
151 | PSXINT_CDREAD, | |
152 | PSXINT_GPUDMA, | |
153 | PSXINT_MDECOUTDMA, | |
154 | PSXINT_SPUDMA, | |
528ad661 | 155 | PSXINT_GPUBUSY, |
156 | PSXINT_MDECINDMA, | |
57a757ce | 157 | PSXINT_GPUOTCDMA, |
d28b54b1 | 158 | PSXINT_NEWDRC_CHECK, |
159 | PSXINT_COUNT | |
160 | }; | |
161 | ||
ef79bbde P |
162 | typedef struct { |
163 | psxGPRRegs GPR; /* General Purpose Registers */ | |
164 | psxCP0Regs CP0; /* Coprocessor0 Registers */ | |
165 | psxCP2Data CP2D; /* Cop2 data registers */ | |
166 | psxCP2Ctrl CP2C; /* Cop2 control registers */ | |
167 | u32 pc; /* Program counter */ | |
168 | u32 code; /* The instruction */ | |
169 | u32 cycle; | |
170 | u32 interrupt; | |
d28b54b1 | 171 | struct { u32 sCycle, cycle; } intCycle[32]; |
ef79bbde P |
172 | } psxRegisters; |
173 | ||
174 | extern psxRegisters psxRegs; | |
175 | ||
d28b54b1 | 176 | /* new_dynarec stuff */ |
177 | extern u32 event_cycles[PSXINT_COUNT]; | |
178 | extern u32 next_interupt; | |
179 | ||
52082bc1 | 180 | void new_dyna_save(void); |
181 | void new_dyna_restore(void); | |
182 | ||
d28b54b1 | 183 | #define new_dyna_set_event(e, c) { \ |
184 | s32 c_ = c; \ | |
185 | u32 abs_ = psxRegs.cycle + c_; \ | |
186 | s32 odi_ = next_interupt - psxRegs.cycle; \ | |
187 | event_cycles[e] = abs_; \ | |
188 | if (c_ < odi_) { \ | |
189 | /*printf("%u: next_interupt %d -> %d (%u)\n", psxRegs.cycle, odi_, c_, abs_);*/ \ | |
190 | next_interupt = abs_; \ | |
191 | } \ | |
192 | } | |
193 | ||
ef79bbde P |
194 | #if defined(__BIGENDIAN__) |
195 | ||
196 | #define _i32(x) *(s32 *)&x | |
197 | #define _u32(x) x | |
198 | ||
199 | #define _i16(x) (((short *)&x)[1]) | |
200 | #define _u16(x) (((unsigned short *)&x)[1]) | |
201 | ||
202 | #define _i8(x) (((char *)&x)[3]) | |
203 | #define _u8(x) (((unsigned char *)&x)[3]) | |
204 | ||
205 | #else | |
206 | ||
207 | #define _i32(x) *(s32 *)&x | |
208 | #define _u32(x) x | |
209 | ||
210 | #define _i16(x) *(short *)&x | |
211 | #define _u16(x) *(unsigned short *)&x | |
212 | ||
213 | #define _i8(x) *(char *)&x | |
214 | #define _u8(x) *(unsigned char *)&x | |
215 | ||
216 | #endif | |
217 | ||
218 | /**** R3000A Instruction Macros ****/ | |
219 | #define _PC_ psxRegs.pc // The next PC to be executed | |
220 | ||
221 | #define _fOp_(code) ((code >> 26) ) // The opcode part of the instruction register | |
222 | #define _fFunct_(code) ((code ) & 0x3F) // The funct part of the instruction register | |
223 | #define _fRd_(code) ((code >> 11) & 0x1F) // The rd part of the instruction register | |
224 | #define _fRt_(code) ((code >> 16) & 0x1F) // The rt part of the instruction register | |
225 | #define _fRs_(code) ((code >> 21) & 0x1F) // The rs part of the instruction register | |
226 | #define _fSa_(code) ((code >> 6) & 0x1F) // The sa part of the instruction register | |
227 | #define _fIm_(code) ((u16)code) // The immediate part of the instruction register | |
228 | #define _fTarget_(code) (code & 0x03ffffff) // The target part of the instruction register | |
229 | ||
230 | #define _fImm_(code) ((s16)code) // sign-extended immediate | |
231 | #define _fImmU_(code) (code&0xffff) // zero-extended immediate | |
232 | ||
233 | #define _Op_ _fOp_(psxRegs.code) | |
234 | #define _Funct_ _fFunct_(psxRegs.code) | |
235 | #define _Rd_ _fRd_(psxRegs.code) | |
236 | #define _Rt_ _fRt_(psxRegs.code) | |
237 | #define _Rs_ _fRs_(psxRegs.code) | |
238 | #define _Sa_ _fSa_(psxRegs.code) | |
239 | #define _Im_ _fIm_(psxRegs.code) | |
240 | #define _Target_ _fTarget_(psxRegs.code) | |
241 | ||
242 | #define _Imm_ _fImm_(psxRegs.code) | |
243 | #define _ImmU_ _fImmU_(psxRegs.code) | |
244 | ||
245 | #define _rRs_ psxRegs.GPR.r[_Rs_] // Rs register | |
246 | #define _rRt_ psxRegs.GPR.r[_Rt_] // Rt register | |
247 | #define _rRd_ psxRegs.GPR.r[_Rd_] // Rd register | |
248 | #define _rSa_ psxRegs.GPR.r[_Sa_] // Sa register | |
249 | #define _rFs_ psxRegs.CP0.r[_Rd_] // Fs register | |
250 | ||
251 | #define _c2dRs_ psxRegs.CP2D.r[_Rs_] // Rs cop2 data register | |
252 | #define _c2dRt_ psxRegs.CP2D.r[_Rt_] // Rt cop2 data register | |
253 | #define _c2dRd_ psxRegs.CP2D.r[_Rd_] // Rd cop2 data register | |
254 | #define _c2dSa_ psxRegs.CP2D.r[_Sa_] // Sa cop2 data register | |
255 | ||
256 | #define _rHi_ psxRegs.GPR.n.hi // The HI register | |
257 | #define _rLo_ psxRegs.GPR.n.lo // The LO register | |
258 | ||
259 | #define _JumpTarget_ ((_Target_ * 4) + (_PC_ & 0xf0000000)) // Calculates the target during a jump instruction | |
260 | #define _BranchTarget_ ((s16)_Im_ * 4 + _PC_) // Calculates the target during a branch instruction | |
261 | ||
262 | #define _SetLink(x) psxRegs.GPR.r[x] = _PC_ + 4; // Sets the return address in the link register | |
263 | ||
264 | int psxInit(); | |
265 | void psxReset(); | |
266 | void psxShutdown(); | |
267 | void psxException(u32 code, u32 bd); | |
268 | void psxBranchTest(); | |
269 | void psxExecuteBios(); | |
270 | int psxTestLoadDelay(int reg, u32 tmp); | |
271 | void psxDelayTest(int reg, u32 bpc); | |
272 | void psxTestSWInts(); | |
273 | void psxJumpTest(); | |
274 | ||
275 | #ifdef __cplusplus | |
276 | } | |
277 | #endif | |
278 | #endif |