cff531af |
1 | /* |
2 | * PicoDrive |
6a98f03e |
3 | * (C) notaz, 2009,2010,2013 |
cff531af |
4 | * |
5 | * This work is licensed under the terms of MAME license. |
6 | * See COPYING file in the top-level directory. |
7 | */ |
be2c4208 |
8 | #include "../pico_int.h" |
974fdb5b |
9 | #include "../sound/ym2612.h" |
51d86e55 |
10 | #include "../../cpu/sh2/compiler.h" |
be2c4208 |
11 | |
12 | struct Pico32x Pico32x; |
83ff19ec |
13 | SH2 sh2s[2]; |
be2c4208 |
14 | |
19886062 |
15 | #define SH2_IDLE_STATES (SH2_STATE_CPOLL|SH2_STATE_VPOLL|SH2_STATE_SLEEP) |
16 | |
e05b81fc |
17 | static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level) |
4ea707e1 |
18 | { |
e05b81fc |
19 | if (sh2->pending_irl > sh2->pending_int_irq) { |
20 | elprintf(EL_32X, "%csh2 ack/irl %d @ %08x", |
21 | sh2->is_slave ? 's' : 'm', level, sh2->pc); |
22 | return 64 + sh2->pending_irl / 2; |
23 | } else { |
24 | elprintf(EL_32X, "%csh2 ack/int %d/%d @ %08x", |
25 | sh2->is_slave ? 's' : 'm', level, sh2->pending_int_vector, sh2->pc); |
26 | sh2->pending_int_irq = 0; // auto-clear |
27 | sh2->pending_level = sh2->pending_irl; |
28 | return sh2->pending_int_vector; |
29 | } |
4ea707e1 |
30 | } |
31 | |
c1931173 |
32 | // MUST specify active_sh2 when called from sh2 memhandlers |
4d5dfee8 |
33 | void p32x_update_irls(SH2 *active_sh2, int m68k_cycles) |
4ea707e1 |
34 | { |
35 | int irqs, mlvl = 0, slvl = 0; |
a8fd6e37 |
36 | int mrun, srun; |
4ea707e1 |
37 | |
19886062 |
38 | if (active_sh2 != NULL) |
39 | m68k_cycles = sh2_cycles_done_m68k(active_sh2); |
40 | |
4ea707e1 |
41 | // msh2 |
42 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES); |
43 | while ((irqs >>= 1)) |
44 | mlvl++; |
45 | mlvl *= 2; |
46 | |
47 | // ssh2 |
48 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES); |
49 | while ((irqs >>= 1)) |
50 | slvl++; |
51 | slvl *= 2; |
52 | |
c1931173 |
53 | mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 == &msh2); |
54 | if (mrun) { |
19886062 |
55 | p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles); |
c1931173 |
56 | if (active_sh2 == &msh2) |
57 | sh2_end_run(active_sh2, 1); |
58 | } |
19886062 |
59 | |
c1931173 |
60 | srun = sh2_irl_irq(&ssh2, slvl, active_sh2 == &ssh2); |
61 | if (srun) { |
19886062 |
62 | p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles); |
c1931173 |
63 | if (active_sh2 == &ssh2) |
64 | sh2_end_run(active_sh2, 1); |
65 | } |
19886062 |
66 | |
a8fd6e37 |
67 | elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun); |
4ea707e1 |
68 | } |
69 | |
be2c4208 |
70 | void Pico32xStartup(void) |
71 | { |
72 | elprintf(EL_STATUS|EL_32X, "32X startup"); |
73 | |
679af8a3 |
74 | // TODO: OOM handling |
be2c4208 |
75 | PicoAHW |= PAHW_32X; |
f81107f5 |
76 | sh2_init(&msh2, 0, &ssh2); |
4ea707e1 |
77 | msh2.irq_callback = sh2_irq_cb; |
f81107f5 |
78 | sh2_init(&ssh2, 1, &msh2); |
4ea707e1 |
79 | ssh2.irq_callback = sh2_irq_cb; |
83ff19ec |
80 | |
81 | PicoMemSetup32x(); |
045a4c52 |
82 | p32x_pwm_ctl_changed(); |
a8fd6e37 |
83 | p32x_timers_recalc(); |
acd35d4c |
84 | |
be2c4208 |
85 | if (!Pico.m.pal) |
974fdb5b |
86 | Pico32x.vdp_regs[0] |= P32XV_nPAL; |
be2c4208 |
87 | |
2446536b |
88 | rendstatus_old = -1; |
89 | |
974fdb5b |
90 | emu_32x_startup(); |
be2c4208 |
91 | } |
92 | |
83ff19ec |
93 | #define HWSWAP(x) (((x) << 16) | ((x) >> 16)) |
94 | void p32x_reset_sh2s(void) |
95 | { |
96 | elprintf(EL_32X, "sh2 reset"); |
97 | |
98 | sh2_reset(&msh2); |
99 | sh2_reset(&ssh2); |
cd0ace28 |
100 | sh2_peripheral_reset(&msh2); |
101 | sh2_peripheral_reset(&ssh2); |
83ff19ec |
102 | |
103 | // if we don't have BIOS set, perform it's work here. |
104 | // MSH2 |
105 | if (p32x_bios_m == NULL) { |
106 | unsigned int idl_src, idl_dst, idl_size; // initial data load |
107 | unsigned int vbr; |
108 | |
109 | // initial data |
110 | idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000; |
111 | idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000; |
112 | idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc)); |
113 | if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize || |
114 | idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) { |
115 | elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x", |
116 | idl_src, idl_dst, idl_size); |
117 | } |
118 | else |
119 | memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size); |
120 | |
121 | // GBR/VBR |
122 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8)); |
123 | sh2_set_gbr(0, 0x20004000); |
124 | sh2_set_vbr(0, vbr); |
125 | |
126 | // checksum and M_OK |
127 | Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e); |
128 | // program will set M_OK |
129 | } |
130 | |
131 | // SSH2 |
132 | if (p32x_bios_s == NULL) { |
133 | unsigned int vbr; |
134 | |
135 | // GBR/VBR |
136 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec)); |
137 | sh2_set_gbr(1, 0x20004000); |
138 | sh2_set_vbr(1, vbr); |
139 | // program will set S_OK |
140 | } |
ed4402a7 |
141 | |
142 | msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDoneT(); |
83ff19ec |
143 | } |
144 | |
be2c4208 |
145 | void Pico32xInit(void) |
146 | { |
ed4402a7 |
147 | if (msh2.mult_m68k_to_sh2 == 0 || msh2.mult_sh2_to_m68k == 0) |
148 | Pico32xSetClocks(PICO_MSH2_HZ, 0); |
149 | if (ssh2.mult_m68k_to_sh2 == 0 || ssh2.mult_sh2_to_m68k == 0) |
150 | Pico32xSetClocks(0, PICO_MSH2_HZ); |
974fdb5b |
151 | } |
152 | |
153 | void PicoPower32x(void) |
154 | { |
155 | memset(&Pico32x, 0, sizeof(Pico32x)); |
5e49c3a8 |
156 | |
83ff19ec |
157 | Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified |
4a1fb183 |
158 | Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_PEN; |
87accdf7 |
159 | Pico32x.sh2_regs[0] = P32XS2_ADEN; |
be2c4208 |
160 | } |
161 | |
5e49c3a8 |
162 | void PicoUnload32x(void) |
163 | { |
164 | if (Pico32xMem != NULL) |
b081408f |
165 | plat_munmap(Pico32xMem, sizeof(*Pico32xMem)); |
5e49c3a8 |
166 | Pico32xMem = NULL; |
e898de13 |
167 | sh2_finish(&msh2); |
168 | sh2_finish(&ssh2); |
5e49c3a8 |
169 | |
170 | PicoAHW &= ~PAHW_32X; |
171 | } |
172 | |
be2c4208 |
173 | void PicoReset32x(void) |
174 | { |
83ff19ec |
175 | if (PicoAHW & PAHW_32X) { |
176 | Pico32x.sh2irqs |= P32XI_VRES; |
4d5dfee8 |
177 | p32x_update_irls(NULL, SekCyclesDoneT2()); |
19886062 |
178 | p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0); |
179 | p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0); |
045a4c52 |
180 | p32x_pwm_ctl_changed(); |
a8fd6e37 |
181 | p32x_timers_recalc(); |
83ff19ec |
182 | } |
be2c4208 |
183 | } |
184 | |
974fdb5b |
185 | static void p32x_start_blank(void) |
186 | { |
7a961c19 |
187 | if (Pico32xDrawMode != PDM32X_OFF && !PicoSkipFrame) { |
5aec752d |
188 | int offs, lines; |
189 | |
190 | pprof_start(draw); |
191 | |
192 | offs = 8; lines = 224; |
7a961c19 |
193 | if ((Pico.video.reg[1] & 8) && !(PicoOpt & POPT_ALT_RENDERER)) { |
194 | offs = 0; |
195 | lines = 240; |
196 | } |
197 | |
198 | // XXX: no proper handling of 32col mode.. |
5a681086 |
199 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking |
200 | (Pico.video.reg[12] & 1) && // 40col mode |
201 | (PicoDrawMask & PDRAW_32X_ON)) |
202 | { |
203 | int md_bg = Pico.video.reg[7] & 0x3f; |
5a681086 |
204 | |
205 | // we draw full layer (not line-by-line) |
206 | PicoDraw32xLayer(offs, lines, md_bg); |
207 | } |
7a961c19 |
208 | else if (Pico32xDrawMode != PDM32X_32X_ONLY) |
209 | PicoDraw32xLayerMdOnly(offs, lines); |
5aec752d |
210 | |
211 | pprof_end(draw); |
5a681086 |
212 | } |
213 | |
974fdb5b |
214 | // enter vblank |
215 | Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN; |
216 | |
4ea707e1 |
217 | // FB swap waits until vblank |
974fdb5b |
218 | if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) { |
219 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS; |
220 | Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb; |
221 | Pico32xSwapDRAM(Pico32x.pending_fb ^ 1); |
222 | } |
4ea707e1 |
223 | |
97d3f47f |
224 | Pico32x.sh2irqs |= P32XI_VINT; |
4d5dfee8 |
225 | p32x_update_irls(NULL, SekCyclesDoneT2()); |
19886062 |
226 | p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0); |
227 | p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0); |
974fdb5b |
228 | } |
229 | |
19886062 |
230 | // compare cycles, handling overflows |
231 | // check if a > b |
232 | #define CYCLES_GT(a, b) \ |
233 | ((int)((a) - (b)) > 0) |
234 | // check if a >= b |
235 | #define CYCLES_GE(a, b) \ |
236 | ((int)((a) - (b)) >= 0) |
237 | |
a8fd6e37 |
238 | /* events */ |
a8fd6e37 |
239 | static void fillend_event(unsigned int now) |
240 | { |
241 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_nFEN; |
19886062 |
242 | p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, now); |
243 | p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, now); |
a8fd6e37 |
244 | } |
245 | |
246 | typedef void (event_cb)(unsigned int now); |
247 | |
6a98f03e |
248 | unsigned int event_times[P32X_EVENT_COUNT]; |
a8fd6e37 |
249 | static unsigned int event_time_next; |
250 | static event_cb *event_cbs[] = { |
df63f1a6 |
251 | [P32X_EVENT_PWM] = p32x_pwm_irq_event, |
a8fd6e37 |
252 | [P32X_EVENT_FILLEND] = fillend_event, |
253 | }; |
254 | |
19886062 |
255 | // schedule event at some time 'after', in m68k clocks |
256 | void p32x_event_schedule(unsigned int now, enum p32x_event event, int after) |
a8fd6e37 |
257 | { |
19886062 |
258 | unsigned int when; |
259 | |
260 | when = (now + after) | 1; |
a8fd6e37 |
261 | |
262 | elprintf(EL_32X, "new event #%u %u->%u", event, now, when); |
263 | event_times[event] = when; |
264 | |
19886062 |
265 | if (event_time_next == 0 || CYCLES_GT(event_time_next, when)) |
a8fd6e37 |
266 | event_time_next = when; |
267 | } |
268 | |
19886062 |
269 | void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after) |
270 | { |
271 | unsigned int now = sh2_cycles_done_m68k(sh2); |
272 | int left_to_next; |
273 | |
274 | p32x_event_schedule(now, event, after); |
275 | |
276 | left_to_next = (event_time_next - now) * 3; |
c1931173 |
277 | sh2_end_run(sh2, left_to_next); |
19886062 |
278 | } |
279 | |
a8fd6e37 |
280 | static void run_events(unsigned int until) |
281 | { |
282 | int oldest, oldest_diff, time; |
283 | int i, diff; |
284 | |
285 | while (1) { |
286 | oldest = -1, oldest_diff = 0x7fffffff; |
287 | |
288 | for (i = 0; i < P32X_EVENT_COUNT; i++) { |
289 | if (event_times[i]) { |
290 | diff = event_times[i] - until; |
291 | if (diff < oldest_diff) { |
292 | oldest_diff = diff; |
293 | oldest = i; |
294 | } |
295 | } |
296 | } |
297 | |
298 | if (oldest_diff <= 0) { |
299 | time = event_times[oldest]; |
300 | event_times[oldest] = 0; |
301 | elprintf(EL_32X, "run event #%d %u", oldest, time); |
302 | event_cbs[oldest](time); |
303 | } |
304 | else if (oldest_diff < 0x7fffffff) { |
305 | event_time_next = event_times[oldest]; |
306 | break; |
307 | } |
308 | else { |
309 | event_time_next = 0; |
310 | break; |
311 | } |
312 | } |
313 | |
314 | if (oldest != -1) |
315 | elprintf(EL_32X, "next event #%d at %u", oldest, event_time_next); |
316 | } |
317 | |
19886062 |
318 | static inline void run_sh2(SH2 *sh2, int m68k_cycles) |
319 | { |
320 | int cycles, done; |
321 | |
322 | pevt_log_sh2_o(sh2, EVT_RUN_START); |
323 | sh2->state |= SH2_STATE_RUN; |
324 | cycles = C_M68K_TO_SH2(*sh2, m68k_cycles); |
4a1fb183 |
325 | elprintf(EL_32X, "%csh2 +run %u %d @%08x", |
326 | sh2->is_slave?'s':'m', sh2->m68krcycles_done, cycles, sh2->pc); |
19886062 |
327 | |
328 | done = sh2_execute(sh2, cycles); |
329 | |
330 | sh2->m68krcycles_done += C_SH2_TO_M68K(*sh2, done); |
331 | sh2->state &= ~SH2_STATE_RUN; |
332 | pevt_log_sh2_o(sh2, EVT_RUN_END); |
333 | elprintf(EL_32X, "%csh2 -run %u %d", |
334 | sh2->is_slave?'s':'m', sh2->m68krcycles_done, done); |
335 | } |
336 | |
337 | // sync other sh2 to this one |
338 | // note: recursive call |
339 | void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target) |
340 | { |
f81107f5 |
341 | SH2 *osh2 = sh2->other_sh2; |
19886062 |
342 | int left_to_event; |
343 | int m68k_cycles; |
344 | |
345 | if (osh2->state & SH2_STATE_RUN) |
346 | return; |
347 | |
348 | m68k_cycles = m68k_target - osh2->m68krcycles_done; |
349 | if (m68k_cycles < 200) |
350 | return; |
351 | |
352 | if (osh2->state & SH2_IDLE_STATES) { |
353 | osh2->m68krcycles_done = m68k_target; |
354 | return; |
355 | } |
356 | |
357 | elprintf(EL_32X, "%csh2 sync to %u %d", |
358 | osh2->is_slave?'s':'m', m68k_target, m68k_cycles); |
359 | |
360 | run_sh2(osh2, m68k_cycles); |
361 | |
362 | // there might be new event to schedule current sh2 to |
363 | if (event_time_next) { |
364 | left_to_event = event_time_next - m68k_target; |
365 | left_to_event *= 3; |
366 | if (sh2_cycles_left(sh2) > left_to_event) { |
367 | if (left_to_event < 1) |
368 | left_to_event = 1; |
369 | sh2_end_run(sh2, left_to_event); |
370 | } |
371 | } |
372 | } |
a8fd6e37 |
373 | |
ed4402a7 |
374 | #define sync_sh2s_normal p32x_sync_sh2s |
375 | //#define sync_sh2s_lockstep p32x_sync_sh2s |
974fdb5b |
376 | |
a8fd6e37 |
377 | /* most timing is in 68k clock */ |
ed4402a7 |
378 | void sync_sh2s_normal(unsigned int m68k_target) |
379 | { |
a8fd6e37 |
380 | unsigned int now, target, timer_cycles; |
19886062 |
381 | int cycles; |
ed4402a7 |
382 | |
a8fd6e37 |
383 | elprintf(EL_32X, "sh2 sync to %u", m68k_target); |
ed4402a7 |
384 | |
27e26273 |
385 | if (!(Pico32x.regs[0] & P32XS_nRES)) { |
386 | msh2.m68krcycles_done = ssh2.m68krcycles_done = m68k_target; |
ed4402a7 |
387 | return; // rare |
27e26273 |
388 | } |
ed4402a7 |
389 | |
a8fd6e37 |
390 | now = msh2.m68krcycles_done; |
391 | if (CYCLES_GT(now, ssh2.m68krcycles_done)) |
392 | now = ssh2.m68krcycles_done; |
393 | timer_cycles = now; |
394 | |
395 | while (CYCLES_GT(m68k_target, now)) |
ed4402a7 |
396 | { |
a8fd6e37 |
397 | if (event_time_next && CYCLES_GE(now, event_time_next)) |
398 | run_events(now); |
ed4402a7 |
399 | |
a8fd6e37 |
400 | target = m68k_target; |
401 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
402 | target = event_time_next; |
403 | |
404 | while (CYCLES_GT(target, now)) |
405 | { |
406 | elprintf(EL_32X, "sh2 exec to %u %d,%d/%d, flags %x", target, |
407 | target - msh2.m68krcycles_done, target - ssh2.m68krcycles_done, |
408 | m68k_target - now, Pico32x.emu_flags); |
ed4402a7 |
409 | |
19886062 |
410 | if (!(ssh2.state & SH2_IDLE_STATES)) { |
a8fd6e37 |
411 | cycles = target - ssh2.m68krcycles_done; |
412 | if (cycles > 0) { |
19886062 |
413 | run_sh2(&ssh2, cycles); |
a8fd6e37 |
414 | |
415 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
416 | target = event_time_next; |
417 | } |
ed4402a7 |
418 | } |
419 | |
19886062 |
420 | if (!(msh2.state & SH2_IDLE_STATES)) { |
a8fd6e37 |
421 | cycles = target - msh2.m68krcycles_done; |
422 | if (cycles > 0) { |
19886062 |
423 | run_sh2(&msh2, cycles); |
a8fd6e37 |
424 | |
425 | if (event_time_next && CYCLES_GT(target, event_time_next)) |
426 | target = event_time_next; |
427 | } |
ed4402a7 |
428 | } |
a8fd6e37 |
429 | |
19886062 |
430 | now = target; |
431 | if (!(msh2.state & SH2_IDLE_STATES)) { |
432 | if (CYCLES_GT(now, msh2.m68krcycles_done)) |
433 | now = msh2.m68krcycles_done; |
434 | } |
435 | if (!(ssh2.state & SH2_IDLE_STATES)) { |
436 | if (CYCLES_GT(now, ssh2.m68krcycles_done)) |
437 | now = ssh2.m68krcycles_done; |
438 | } |
ed4402a7 |
439 | } |
a8fd6e37 |
440 | |
045a4c52 |
441 | p32x_timers_do(now - timer_cycles); |
a8fd6e37 |
442 | timer_cycles = now; |
ed4402a7 |
443 | } |
19886062 |
444 | |
445 | // advance idle CPUs |
446 | if (msh2.state & SH2_IDLE_STATES) { |
447 | if (CYCLES_GT(m68k_target, msh2.m68krcycles_done)) |
448 | msh2.m68krcycles_done = m68k_target; |
449 | } |
450 | if (ssh2.state & SH2_IDLE_STATES) { |
451 | if (CYCLES_GT(m68k_target, ssh2.m68krcycles_done)) |
452 | ssh2.m68krcycles_done = m68k_target; |
453 | } |
236990cf |
454 | } |
acd35d4c |
455 | |
c987bb5c |
456 | #define STEP_68K 24 |
ed4402a7 |
457 | |
458 | void sync_sh2s_lockstep(unsigned int m68k_target) |
459 | { |
460 | unsigned int mcycles; |
461 | |
462 | mcycles = msh2.m68krcycles_done; |
463 | if (ssh2.m68krcycles_done < mcycles) |
464 | mcycles = ssh2.m68krcycles_done; |
465 | |
466 | while (mcycles < m68k_target) { |
467 | mcycles += STEP_68K; |
468 | sync_sh2s_normal(mcycles); |
469 | } |
87accdf7 |
470 | } |
471 | |
ed4402a7 |
472 | #define CPUS_RUN(m68k_cycles,s68k_cycles) do { \ |
473 | SekRunM68k(m68k_cycles); \ |
19886062 |
474 | if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \ |
475 | p32x_sync_sh2s(SekCyclesDoneT2()); \ |
ed4402a7 |
476 | } while (0) |
87accdf7 |
477 | |
ed4402a7 |
478 | #define PICO_32X |
974fdb5b |
479 | #include "../pico_cmn.c" |
480 | |
481 | void PicoFrame32x(void) |
482 | { |
4ea707e1 |
483 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank |
db1d3564 |
484 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking |
485 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access |
4ea707e1 |
486 | |
19886062 |
487 | p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0); |
488 | p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0); |
974fdb5b |
489 | |
490 | PicoFrameStart(); |
491 | PicoFrameHints(); |
51d86e55 |
492 | sh2_drc_frame(); |
493 | |
19886062 |
494 | elprintf(EL_32X, "poll: %02x %02x %02x", |
495 | Pico32x.emu_flags & 3, msh2.state, ssh2.state); |
974fdb5b |
496 | } |
db1d3564 |
497 | |
ed4402a7 |
498 | // calculate multipliers against 68k clock (7670442) |
499 | // normally * 3, but effectively slower due to high latencies everywhere |
500 | // however using something lower breaks MK2 animations |
501 | void Pico32xSetClocks(int msh2_hz, int ssh2_hz) |
502 | { |
503 | float m68k_clk = (float)(OSC_NTSC / 7); |
504 | if (msh2_hz > 0) { |
505 | msh2.mult_m68k_to_sh2 = (int)((float)msh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk); |
506 | msh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)msh2_hz); |
507 | } |
508 | if (ssh2_hz > 0) { |
509 | ssh2.mult_m68k_to_sh2 = (int)((float)ssh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk); |
510 | ssh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)ssh2_hz); |
511 | } |
512 | } |
513 | |
27e26273 |
514 | void Pico32xStateLoaded(int is_early) |
515 | { |
516 | if (is_early) { |
517 | Pico32xMemStateLoaded(); |
518 | return; |
519 | } |
520 | |
19886062 |
521 | SekCycleCnt = 0; |
27e26273 |
522 | sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCycleCntT; |
4d5dfee8 |
523 | p32x_update_irls(NULL, SekCycleCntT); |
df63f1a6 |
524 | p32x_pwm_state_loaded(); |
27e26273 |
525 | run_events(SekCycleCntT); |
526 | } |
527 | |
ed4402a7 |
528 | // vim:shiftwidth=2:ts=2:expandtab |