cff531af |
1 | /* |
2 | * PicoDrive |
3 | * (C) notaz, 2009,2010 |
4 | * |
5 | * This work is licensed under the terms of MAME license. |
6 | * See COPYING file in the top-level directory. |
7 | */ |
be2c4208 |
8 | #include "../pico_int.h" |
974fdb5b |
9 | #include "../sound/ym2612.h" |
be2c4208 |
10 | |
11 | struct Pico32x Pico32x; |
83ff19ec |
12 | SH2 sh2s[2]; |
be2c4208 |
13 | |
e05b81fc |
14 | static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level) |
4ea707e1 |
15 | { |
e05b81fc |
16 | if (sh2->pending_irl > sh2->pending_int_irq) { |
17 | elprintf(EL_32X, "%csh2 ack/irl %d @ %08x", |
18 | sh2->is_slave ? 's' : 'm', level, sh2->pc); |
19 | return 64 + sh2->pending_irl / 2; |
20 | } else { |
21 | elprintf(EL_32X, "%csh2 ack/int %d/%d @ %08x", |
22 | sh2->is_slave ? 's' : 'm', level, sh2->pending_int_vector, sh2->pc); |
23 | sh2->pending_int_irq = 0; // auto-clear |
24 | sh2->pending_level = sh2->pending_irl; |
25 | return sh2->pending_int_vector; |
26 | } |
4ea707e1 |
27 | } |
28 | |
1f1ff763 |
29 | void p32x_update_irls(int nested_call) |
4ea707e1 |
30 | { |
31 | int irqs, mlvl = 0, slvl = 0; |
32 | |
33 | // msh2 |
34 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES); |
35 | while ((irqs >>= 1)) |
36 | mlvl++; |
37 | mlvl *= 2; |
38 | |
39 | // ssh2 |
40 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES); |
41 | while ((irqs >>= 1)) |
42 | slvl++; |
43 | slvl *= 2; |
44 | |
45 | elprintf(EL_32X, "update_irls: m %d, s %d", mlvl, slvl); |
1f1ff763 |
46 | sh2_irl_irq(&msh2, mlvl, nested_call); |
47 | sh2_irl_irq(&ssh2, slvl, nested_call); |
87accdf7 |
48 | mlvl = mlvl ? 1 : 0; |
49 | slvl = slvl ? 1 : 0; |
50 | p32x_poll_event(mlvl | (slvl << 1), 0); |
4ea707e1 |
51 | } |
52 | |
be2c4208 |
53 | void Pico32xStartup(void) |
54 | { |
55 | elprintf(EL_STATUS|EL_32X, "32X startup"); |
56 | |
679af8a3 |
57 | // TODO: OOM handling |
be2c4208 |
58 | PicoAHW |= PAHW_32X; |
b78efee2 |
59 | sh2_init(&msh2, 0); |
4ea707e1 |
60 | msh2.irq_callback = sh2_irq_cb; |
b78efee2 |
61 | sh2_init(&ssh2, 1); |
4ea707e1 |
62 | ssh2.irq_callback = sh2_irq_cb; |
83ff19ec |
63 | |
64 | PicoMemSetup32x(); |
acd35d4c |
65 | |
be2c4208 |
66 | if (!Pico.m.pal) |
974fdb5b |
67 | Pico32x.vdp_regs[0] |= P32XV_nPAL; |
be2c4208 |
68 | |
1d7a28a7 |
69 | PREG8(Pico32xMem->sh2_peri_regs[0], 4) = |
70 | PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR |
71 | |
2446536b |
72 | rendstatus_old = -1; |
73 | |
974fdb5b |
74 | emu_32x_startup(); |
be2c4208 |
75 | } |
76 | |
83ff19ec |
77 | #define HWSWAP(x) (((x) << 16) | ((x) >> 16)) |
78 | void p32x_reset_sh2s(void) |
79 | { |
80 | elprintf(EL_32X, "sh2 reset"); |
81 | |
82 | sh2_reset(&msh2); |
83 | sh2_reset(&ssh2); |
84 | |
85 | // if we don't have BIOS set, perform it's work here. |
86 | // MSH2 |
87 | if (p32x_bios_m == NULL) { |
88 | unsigned int idl_src, idl_dst, idl_size; // initial data load |
89 | unsigned int vbr; |
90 | |
91 | // initial data |
92 | idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000; |
93 | idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000; |
94 | idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc)); |
95 | if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize || |
96 | idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) { |
97 | elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x", |
98 | idl_src, idl_dst, idl_size); |
99 | } |
100 | else |
101 | memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size); |
102 | |
103 | // GBR/VBR |
104 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8)); |
105 | sh2_set_gbr(0, 0x20004000); |
106 | sh2_set_vbr(0, vbr); |
107 | |
108 | // checksum and M_OK |
109 | Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e); |
110 | // program will set M_OK |
111 | } |
112 | |
113 | // SSH2 |
114 | if (p32x_bios_s == NULL) { |
115 | unsigned int vbr; |
116 | |
117 | // GBR/VBR |
118 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec)); |
119 | sh2_set_gbr(1, 0x20004000); |
120 | sh2_set_vbr(1, vbr); |
121 | // program will set S_OK |
122 | } |
ed4402a7 |
123 | |
124 | msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDoneT(); |
83ff19ec |
125 | } |
126 | |
be2c4208 |
127 | void Pico32xInit(void) |
128 | { |
ed4402a7 |
129 | if (msh2.mult_m68k_to_sh2 == 0 || msh2.mult_sh2_to_m68k == 0) |
130 | Pico32xSetClocks(PICO_MSH2_HZ, 0); |
131 | if (ssh2.mult_m68k_to_sh2 == 0 || ssh2.mult_sh2_to_m68k == 0) |
132 | Pico32xSetClocks(0, PICO_MSH2_HZ); |
974fdb5b |
133 | } |
134 | |
135 | void PicoPower32x(void) |
136 | { |
137 | memset(&Pico32x, 0, sizeof(Pico32x)); |
5e49c3a8 |
138 | |
83ff19ec |
139 | Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified |
974fdb5b |
140 | Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_HBLK|P32XV_PEN; |
87accdf7 |
141 | Pico32x.sh2_regs[0] = P32XS2_ADEN; |
be2c4208 |
142 | } |
143 | |
5e49c3a8 |
144 | void PicoUnload32x(void) |
145 | { |
146 | if (Pico32xMem != NULL) |
b081408f |
147 | plat_munmap(Pico32xMem, sizeof(*Pico32xMem)); |
5e49c3a8 |
148 | Pico32xMem = NULL; |
e898de13 |
149 | sh2_finish(&msh2); |
150 | sh2_finish(&ssh2); |
5e49c3a8 |
151 | |
152 | PicoAHW &= ~PAHW_32X; |
153 | } |
154 | |
be2c4208 |
155 | void PicoReset32x(void) |
156 | { |
83ff19ec |
157 | if (PicoAHW & PAHW_32X) { |
158 | Pico32x.sh2irqs |= P32XI_VRES; |
1f1ff763 |
159 | p32x_update_irls(0); |
83ff19ec |
160 | p32x_poll_event(3, 0); |
161 | } |
be2c4208 |
162 | } |
163 | |
974fdb5b |
164 | static void p32x_start_blank(void) |
165 | { |
7a961c19 |
166 | if (Pico32xDrawMode != PDM32X_OFF && !PicoSkipFrame) { |
5aec752d |
167 | int offs, lines; |
168 | |
169 | pprof_start(draw); |
170 | |
171 | offs = 8; lines = 224; |
7a961c19 |
172 | if ((Pico.video.reg[1] & 8) && !(PicoOpt & POPT_ALT_RENDERER)) { |
173 | offs = 0; |
174 | lines = 240; |
175 | } |
176 | |
177 | // XXX: no proper handling of 32col mode.. |
5a681086 |
178 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking |
179 | (Pico.video.reg[12] & 1) && // 40col mode |
180 | (PicoDrawMask & PDRAW_32X_ON)) |
181 | { |
182 | int md_bg = Pico.video.reg[7] & 0x3f; |
5a681086 |
183 | |
184 | // we draw full layer (not line-by-line) |
185 | PicoDraw32xLayer(offs, lines, md_bg); |
186 | } |
7a961c19 |
187 | else if (Pico32xDrawMode != PDM32X_32X_ONLY) |
188 | PicoDraw32xLayerMdOnly(offs, lines); |
5aec752d |
189 | |
190 | pprof_end(draw); |
5a681086 |
191 | } |
192 | |
974fdb5b |
193 | // enter vblank |
194 | Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN; |
195 | |
4ea707e1 |
196 | // FB swap waits until vblank |
974fdb5b |
197 | if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) { |
198 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS; |
199 | Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb; |
200 | Pico32xSwapDRAM(Pico32x.pending_fb ^ 1); |
201 | } |
4ea707e1 |
202 | |
97d3f47f |
203 | Pico32x.sh2irqs |= P32XI_VINT; |
1f1ff763 |
204 | p32x_update_irls(0); |
87accdf7 |
205 | p32x_poll_event(3, 1); |
974fdb5b |
206 | } |
207 | |
ed4402a7 |
208 | #define sync_sh2s_normal p32x_sync_sh2s |
209 | //#define sync_sh2s_lockstep p32x_sync_sh2s |
974fdb5b |
210 | |
ed4402a7 |
211 | void sync_sh2s_normal(unsigned int m68k_target) |
212 | { |
213 | unsigned int target = m68k_target; |
214 | int msh2_cycles, ssh2_cycles; |
215 | int done; |
216 | |
217 | elprintf(EL_32X, "sh2 sync to %u (%u)", m68k_target, SekCycleCnt); |
218 | |
219 | if (!(Pico32x.regs[0] & P32XS_nRES)) |
220 | return; // rare |
221 | |
222 | { |
223 | msh2_cycles = C_M68K_TO_SH2(msh2, target - msh2.m68krcycles_done); |
224 | ssh2_cycles = C_M68K_TO_SH2(ssh2, target - ssh2.m68krcycles_done); |
225 | |
226 | while (msh2_cycles > 0 || ssh2_cycles > 0) { |
227 | elprintf(EL_32X, "sh2 exec %u,%u->%u", |
228 | msh2.m68krcycles_done, ssh2.m68krcycles_done, target); |
229 | |
230 | if (Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL)) { |
231 | ssh2.m68krcycles_done = target; |
232 | ssh2_cycles = 0; |
233 | } |
234 | else if (ssh2_cycles > 0) { |
235 | done = sh2_execute(&ssh2, ssh2_cycles); |
236 | ssh2.m68krcycles_done += C_SH2_TO_M68K(ssh2, done); |
237 | |
238 | ssh2_cycles = C_M68K_TO_SH2(ssh2, target - ssh2.m68krcycles_done); |
239 | } |
240 | |
241 | if (Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL)) { |
242 | msh2.m68krcycles_done = target; |
243 | msh2_cycles = 0; |
244 | } |
245 | else if (msh2_cycles > 0) { |
246 | done = sh2_execute(&msh2, msh2_cycles); |
247 | msh2.m68krcycles_done += C_SH2_TO_M68K(msh2, done); |
248 | |
249 | msh2_cycles = C_M68K_TO_SH2(msh2, target - msh2.m68krcycles_done); |
250 | } |
251 | } |
252 | } |
236990cf |
253 | } |
acd35d4c |
254 | |
c987bb5c |
255 | #define STEP_68K 24 |
ed4402a7 |
256 | |
257 | void sync_sh2s_lockstep(unsigned int m68k_target) |
258 | { |
259 | unsigned int mcycles; |
260 | |
261 | mcycles = msh2.m68krcycles_done; |
262 | if (ssh2.m68krcycles_done < mcycles) |
263 | mcycles = ssh2.m68krcycles_done; |
264 | |
265 | while (mcycles < m68k_target) { |
266 | mcycles += STEP_68K; |
267 | sync_sh2s_normal(mcycles); |
268 | } |
87accdf7 |
269 | } |
270 | |
ed4402a7 |
271 | #define CPUS_RUN(m68k_cycles,s68k_cycles) do { \ |
272 | SekRunM68k(m68k_cycles); \ |
273 | if (SekIsStoppedM68k()) \ |
274 | p32x_sync_sh2s(SekCycleCntT + SekCycleCnt); \ |
275 | } while (0) |
87accdf7 |
276 | |
ed4402a7 |
277 | #define PICO_32X |
974fdb5b |
278 | #include "../pico_cmn.c" |
279 | |
280 | void PicoFrame32x(void) |
281 | { |
db1d3564 |
282 | pwm_frame_smp_cnt = 0; |
283 | |
4ea707e1 |
284 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank |
db1d3564 |
285 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking |
286 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access |
4ea707e1 |
287 | |
87accdf7 |
288 | p32x_poll_event(3, 1); |
974fdb5b |
289 | |
290 | PicoFrameStart(); |
291 | PicoFrameHints(); |
be20816c |
292 | elprintf(EL_32X, "poll: %02x", Pico32x.emu_flags); |
974fdb5b |
293 | } |
db1d3564 |
294 | |
ed4402a7 |
295 | // calculate multipliers against 68k clock (7670442) |
296 | // normally * 3, but effectively slower due to high latencies everywhere |
297 | // however using something lower breaks MK2 animations |
298 | void Pico32xSetClocks(int msh2_hz, int ssh2_hz) |
299 | { |
300 | float m68k_clk = (float)(OSC_NTSC / 7); |
301 | if (msh2_hz > 0) { |
302 | msh2.mult_m68k_to_sh2 = (int)((float)msh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk); |
303 | msh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)msh2_hz); |
304 | } |
305 | if (ssh2_hz > 0) { |
306 | ssh2.mult_m68k_to_sh2 = (int)((float)ssh2_hz * (1 << CYCLE_MULT_SHIFT) / m68k_clk); |
307 | ssh2.mult_sh2_to_m68k = (int)(m68k_clk * (1 << CYCLE_MULT_SHIFT) / (float)ssh2_hz); |
308 | } |
309 | } |
310 | |
311 | // vim:shiftwidth=2:ts=2:expandtab |