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1 | #include "../pico_int.h" |
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2 | #include "../sound/ym2612.h" |
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3 | |
4 | struct Pico32x Pico32x; |
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5 | SH2 sh2s[2]; |
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6 | |
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7 | int p32x_msh2_multiplier = MSH2_MULTI_DEFAULT; |
8 | int p32x_ssh2_multiplier = SSH2_MULTI_DEFAULT; |
9 | |
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10 | static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level) |
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11 | { |
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12 | if (sh2->pending_irl > sh2->pending_int_irq) { |
13 | elprintf(EL_32X, "%csh2 ack/irl %d @ %08x", |
14 | sh2->is_slave ? 's' : 'm', level, sh2->pc); |
15 | return 64 + sh2->pending_irl / 2; |
16 | } else { |
17 | elprintf(EL_32X, "%csh2 ack/int %d/%d @ %08x", |
18 | sh2->is_slave ? 's' : 'm', level, sh2->pending_int_vector, sh2->pc); |
19 | sh2->pending_int_irq = 0; // auto-clear |
20 | sh2->pending_level = sh2->pending_irl; |
21 | return sh2->pending_int_vector; |
22 | } |
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23 | } |
24 | |
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25 | void p32x_update_irls(int nested_call) |
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26 | { |
27 | int irqs, mlvl = 0, slvl = 0; |
28 | |
29 | // msh2 |
30 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES); |
31 | while ((irqs >>= 1)) |
32 | mlvl++; |
33 | mlvl *= 2; |
34 | |
35 | // ssh2 |
36 | irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES); |
37 | while ((irqs >>= 1)) |
38 | slvl++; |
39 | slvl *= 2; |
40 | |
41 | elprintf(EL_32X, "update_irls: m %d, s %d", mlvl, slvl); |
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42 | sh2_irl_irq(&msh2, mlvl, nested_call); |
43 | sh2_irl_irq(&ssh2, slvl, nested_call); |
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44 | mlvl = mlvl ? 1 : 0; |
45 | slvl = slvl ? 1 : 0; |
46 | p32x_poll_event(mlvl | (slvl << 1), 0); |
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47 | } |
48 | |
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49 | void Pico32xStartup(void) |
50 | { |
51 | elprintf(EL_STATUS|EL_32X, "32X startup"); |
52 | |
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53 | // TODO: OOM handling |
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54 | PicoAHW |= PAHW_32X; |
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55 | sh2_init(&msh2, 0); |
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56 | msh2.irq_callback = sh2_irq_cb; |
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57 | sh2_init(&ssh2, 1); |
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58 | ssh2.irq_callback = sh2_irq_cb; |
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59 | |
60 | PicoMemSetup32x(); |
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61 | |
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62 | if (!Pico.m.pal) |
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63 | Pico32x.vdp_regs[0] |= P32XV_nPAL; |
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64 | |
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65 | PREG8(Pico32xMem->sh2_peri_regs[0], 4) = |
66 | PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR |
67 | |
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68 | emu_32x_startup(); |
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69 | } |
70 | |
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71 | #define HWSWAP(x) (((x) << 16) | ((x) >> 16)) |
72 | void p32x_reset_sh2s(void) |
73 | { |
74 | elprintf(EL_32X, "sh2 reset"); |
75 | |
76 | sh2_reset(&msh2); |
77 | sh2_reset(&ssh2); |
78 | |
79 | // if we don't have BIOS set, perform it's work here. |
80 | // MSH2 |
81 | if (p32x_bios_m == NULL) { |
82 | unsigned int idl_src, idl_dst, idl_size; // initial data load |
83 | unsigned int vbr; |
84 | |
85 | // initial data |
86 | idl_src = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000; |
87 | idl_dst = HWSWAP(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000; |
88 | idl_size= HWSWAP(*(unsigned int *)(Pico.rom + 0x3dc)); |
89 | if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize || |
90 | idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) { |
91 | elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x", |
92 | idl_src, idl_dst, idl_size); |
93 | } |
94 | else |
95 | memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size); |
96 | |
97 | // GBR/VBR |
98 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3e8)); |
99 | sh2_set_gbr(0, 0x20004000); |
100 | sh2_set_vbr(0, vbr); |
101 | |
102 | // checksum and M_OK |
103 | Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e); |
104 | // program will set M_OK |
105 | } |
106 | |
107 | // SSH2 |
108 | if (p32x_bios_s == NULL) { |
109 | unsigned int vbr; |
110 | |
111 | // GBR/VBR |
112 | vbr = HWSWAP(*(unsigned int *)(Pico.rom + 0x3ec)); |
113 | sh2_set_gbr(1, 0x20004000); |
114 | sh2_set_vbr(1, vbr); |
115 | // program will set S_OK |
116 | } |
117 | } |
118 | |
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119 | void Pico32xInit(void) |
120 | { |
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121 | } |
122 | |
123 | void PicoPower32x(void) |
124 | { |
125 | memset(&Pico32x, 0, sizeof(Pico32x)); |
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126 | |
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127 | Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified |
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128 | Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_HBLK|P32XV_PEN; |
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129 | Pico32x.sh2_regs[0] = P32XS2_ADEN; |
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130 | } |
131 | |
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132 | void PicoUnload32x(void) |
133 | { |
134 | if (Pico32xMem != NULL) |
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135 | plat_munmap(Pico32xMem, sizeof(*Pico32xMem)); |
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136 | Pico32xMem = NULL; |
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137 | sh2_finish(&msh2); |
138 | sh2_finish(&ssh2); |
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139 | |
140 | PicoAHW &= ~PAHW_32X; |
141 | } |
142 | |
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143 | void PicoReset32x(void) |
144 | { |
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145 | if (PicoAHW & PAHW_32X) { |
146 | Pico32x.sh2irqs |= P32XI_VRES; |
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147 | p32x_update_irls(0); |
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148 | p32x_poll_event(3, 0); |
149 | } |
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150 | } |
151 | |
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152 | static void p32x_start_blank(void) |
153 | { |
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154 | if (Pico32xDrawMode != PDM32X_OFF && !PicoSkipFrame) { |
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155 | int offs, lines; |
156 | |
157 | pprof_start(draw); |
158 | |
159 | offs = 8; lines = 224; |
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160 | if ((Pico.video.reg[1] & 8) && !(PicoOpt & POPT_ALT_RENDERER)) { |
161 | offs = 0; |
162 | lines = 240; |
163 | } |
164 | |
165 | // XXX: no proper handling of 32col mode.. |
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166 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0 && // 32x not blanking |
167 | (Pico.video.reg[12] & 1) && // 40col mode |
168 | (PicoDrawMask & PDRAW_32X_ON)) |
169 | { |
170 | int md_bg = Pico.video.reg[7] & 0x3f; |
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171 | |
172 | // we draw full layer (not line-by-line) |
173 | PicoDraw32xLayer(offs, lines, md_bg); |
174 | } |
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175 | else if (Pico32xDrawMode != PDM32X_32X_ONLY) |
176 | PicoDraw32xLayerMdOnly(offs, lines); |
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177 | |
178 | pprof_end(draw); |
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179 | } |
180 | |
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181 | // enter vblank |
182 | Pico32x.vdp_regs[0x0a/2] |= P32XV_VBLK|P32XV_PEN; |
183 | |
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184 | // FB swap waits until vblank |
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185 | if ((Pico32x.vdp_regs[0x0a/2] ^ Pico32x.pending_fb) & P32XV_FS) { |
186 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_FS; |
187 | Pico32x.vdp_regs[0x0a/2] |= Pico32x.pending_fb; |
188 | Pico32xSwapDRAM(Pico32x.pending_fb ^ 1); |
189 | } |
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190 | |
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191 | Pico32x.sh2irqs |= P32XI_VINT; |
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192 | p32x_update_irls(0); |
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193 | p32x_poll_event(3, 1); |
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194 | } |
195 | |
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196 | static __inline void run_m68k(int cyc) |
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197 | { |
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198 | pprof_start(m68k); |
199 | |
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200 | p32x_poll_event(3, 0); |
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201 | #if defined(EMU_C68K) |
202 | PicoCpuCM68k.cycles = cyc; |
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203 | CycloneRun(&PicoCpuCM68k); |
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204 | SekCycleCnt += cyc - PicoCpuCM68k.cycles; |
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205 | #elif defined(EMU_M68K) |
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206 | SekCycleCnt += m68k_execute(cyc); |
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207 | #elif defined(EMU_F68K) |
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208 | SekCycleCnt += fm68k_emulate(cyc+1, 0, 0); |
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209 | #endif |
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210 | |
211 | pprof_end(m68k); |
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212 | } |
213 | |
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214 | // ~1463.8, but due to cache misses and slow mem |
215 | // it's much lower than that |
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216 | //#define SH2_LINE_CYCLES 735 |
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217 | #define CYCLES_M68K2MSH2(x) (((x) * p32x_msh2_multiplier) >> 10) |
218 | #define CYCLES_M68K2SSH2(x) (((x) * p32x_ssh2_multiplier) >> 10) |
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219 | |
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220 | #define PICO_32X |
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221 | #define CPUS_RUN_SIMPLE(m68k_cycles,s68k_cycles) \ |
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222 | { \ |
223 | int slice; \ |
224 | SekCycleAim += m68k_cycles; \ |
225 | while (SekCycleCnt < SekCycleAim) { \ |
226 | slice = SekCycleCnt; \ |
227 | run_m68k(SekCycleAim - SekCycleCnt); \ |
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228 | if (!(Pico32x.regs[0] & P32XS_nRES)) \ |
229 | continue; /* SH2s reseting */ \ |
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230 | slice = SekCycleCnt - slice; /* real count from 68k */ \ |
231 | if (SekCycleCnt < SekCycleAim) \ |
232 | elprintf(EL_32X, "slice %d", slice); \ |
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233 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) { \ |
234 | pprof_start(ssh2); \ |
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235 | sh2_execute(&ssh2, CYCLES_M68K2SSH2(slice)); \ |
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236 | pprof_end(ssh2); \ |
237 | } \ |
238 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) { \ |
239 | pprof_start(msh2); \ |
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240 | sh2_execute(&msh2, CYCLES_M68K2MSH2(slice)); \ |
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241 | pprof_end(msh2); \ |
242 | } \ |
243 | pprof_start(dummy); \ |
244 | pprof_end(dummy); \ |
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245 | } \ |
246 | } |
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247 | |
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248 | #define STEP_68K 24 |
249 | #define CPUS_RUN_LOCKSTEP(m68k_cycles,s68k_cycles) \ |
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250 | { \ |
251 | int i; \ |
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252 | for (i = 0; i <= (m68k_cycles) - STEP_68K; i += STEP_68K) { \ |
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253 | run_m68k(STEP_68K); \ |
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254 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
255 | sh2_execute(&msh2, CYCLES_M68K2SH2(STEP_68K)); \ |
256 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
257 | sh2_execute(&ssh2, CYCLES_M68K2SH2(STEP_68K)); \ |
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258 | } \ |
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259 | /* last step */ \ |
260 | i = (m68k_cycles) - i; \ |
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261 | run_m68k(i); \ |
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262 | if (!(Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL))) \ |
263 | sh2_execute(&msh2, CYCLES_M68K2SH2(i)); \ |
264 | if (!(Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL))) \ |
265 | sh2_execute(&ssh2, CYCLES_M68K2SH2(i)); \ |
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266 | } |
267 | |
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268 | #define CPUS_RUN CPUS_RUN_SIMPLE |
269 | //#define CPUS_RUN CPUS_RUN_LOCKSTEP |
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270 | |
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271 | #include "../pico_cmn.c" |
272 | |
273 | void PicoFrame32x(void) |
274 | { |
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275 | pwm_frame_smp_cnt = 0; |
276 | |
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277 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank |
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278 | if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking |
279 | Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access |
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280 | |
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281 | p32x_poll_event(3, 1); |
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282 | |
283 | PicoFrameStart(); |
284 | PicoFrameHints(); |
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285 | elprintf(EL_32X, "poll: %02x", Pico32x.emu_flags); |
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286 | } |
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287 | |