451ab91e |
1 | /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * |
2 | * Mupen64plus - gcop1.c * |
3 | * Mupen64Plus homepage: http://code.google.com/p/mupen64plus/ * |
4 | * Copyright (C) 2002 Hacktarux * |
5 | * * |
6 | * This program is free software; you can redistribute it and/or modify * |
7 | * it under the terms of the GNU General Public License as published by * |
8 | * the Free Software Foundation; either version 2 of the License, or * |
9 | * (at your option) any later version. * |
10 | * * |
11 | * This program is distributed in the hope that it will be useful, * |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
14 | * GNU General Public License for more details. * |
15 | * * |
16 | * You should have received a copy of the GNU General Public License * |
17 | * along with this program; if not, write to the * |
18 | * Free Software Foundation, Inc., * |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * |
20 | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ |
21 | |
22 | #include <stdio.h> |
23 | |
24 | #include "assemble.h" |
25 | #include "interpret.h" |
26 | |
27 | #include "r4300/recomph.h" |
28 | #include "r4300/recomp.h" |
29 | #include "r4300/r4300.h" |
30 | #include "r4300/ops.h" |
31 | #include "r4300/macros.h" |
32 | |
33 | #include "memory/memory.h" |
34 | |
35 | void genmfc1(void) |
36 | { |
37 | #ifdef INTERPRET_MFC1 |
38 | gencallinterp((unsigned int)cached_interpreter_table.MFC1, 0); |
39 | #else |
40 | gencheck_cop1_unusable(); |
41 | mov_eax_memoffs32((unsigned int*)(®_cop1_simple[dst->f.r.nrd])); |
42 | mov_reg32_preg32(EBX, EAX); |
43 | mov_m32_reg32((unsigned int*)dst->f.r.rt, EBX); |
44 | sar_reg32_imm8(EBX, 31); |
45 | mov_m32_reg32(((unsigned int*)dst->f.r.rt)+1, EBX); |
46 | #endif |
47 | } |
48 | |
49 | void gendmfc1(void) |
50 | { |
51 | #ifdef INTERPRET_DMFC1 |
52 | gencallinterp((unsigned int)cached_interpreter_table.DMFC1, 0); |
53 | #else |
54 | gencheck_cop1_unusable(); |
55 | mov_eax_memoffs32((unsigned int*)(®_cop1_double[dst->f.r.nrd])); |
56 | mov_reg32_preg32(EBX, EAX); |
57 | mov_reg32_preg32pimm32(ECX, EAX, 4); |
58 | mov_m32_reg32((unsigned int*)dst->f.r.rt, EBX); |
59 | mov_m32_reg32(((unsigned int*)dst->f.r.rt)+1, ECX); |
60 | #endif |
61 | } |
62 | |
63 | void gencfc1(void) |
64 | { |
65 | #ifdef INTERPRET_CFC1 |
66 | gencallinterp((unsigned int)cached_interpreter_table.CFC1, 0); |
67 | #else |
68 | gencheck_cop1_unusable(); |
69 | if(dst->f.r.nrd == 31) mov_eax_memoffs32((unsigned int*)&FCR31); |
70 | else mov_eax_memoffs32((unsigned int*)&FCR0); |
71 | mov_memoffs32_eax((unsigned int*)dst->f.r.rt); |
72 | sar_reg32_imm8(EAX, 31); |
73 | mov_memoffs32_eax(((unsigned int*)dst->f.r.rt)+1); |
74 | #endif |
75 | } |
76 | |
77 | void genmtc1(void) |
78 | { |
79 | #ifdef INTERPRET_MTC1 |
80 | gencallinterp((unsigned int)cached_interpreter_table.MTC1, 0); |
81 | #else |
82 | gencheck_cop1_unusable(); |
83 | mov_eax_memoffs32((unsigned int*)dst->f.r.rt); |
84 | mov_reg32_m32(EBX, (unsigned int*)(®_cop1_simple[dst->f.r.nrd])); |
85 | mov_preg32_reg32(EBX, EAX); |
86 | #endif |
87 | } |
88 | |
89 | void gendmtc1(void) |
90 | { |
91 | #ifdef INTERPRET_DMTC1 |
92 | gencallinterp((unsigned int)cached_interpreter_table.DMTC1, 0); |
93 | #else |
94 | gencheck_cop1_unusable(); |
95 | mov_eax_memoffs32((unsigned int*)dst->f.r.rt); |
96 | mov_reg32_m32(EBX, ((unsigned int*)dst->f.r.rt)+1); |
97 | mov_reg32_m32(EDX, (unsigned int*)(®_cop1_double[dst->f.r.nrd])); |
98 | mov_preg32_reg32(EDX, EAX); |
99 | mov_preg32pimm32_reg32(EDX, 4, EBX); |
100 | #endif |
101 | } |
102 | |
103 | void genctc1(void) |
104 | { |
105 | #ifdef INTERPRET_CTC1 |
106 | gencallinterp((unsigned int)cached_interpreter_table.CTC1, 0); |
107 | #else |
108 | gencheck_cop1_unusable(); |
109 | |
110 | if (dst->f.r.nrd != 31) return; |
111 | mov_eax_memoffs32((unsigned int*)dst->f.r.rt); |
112 | mov_memoffs32_eax((unsigned int*)&FCR31); |
113 | and_eax_imm32(3); |
114 | |
115 | cmp_eax_imm32(0); |
116 | jne_rj(12); |
117 | mov_m32_imm32((unsigned int*)&rounding_mode, 0x33F); // 10 |
118 | jmp_imm_short(48); // 2 |
119 | |
120 | cmp_eax_imm32(1); // 5 |
121 | jne_rj(12); // 2 |
122 | mov_m32_imm32((unsigned int*)&rounding_mode, 0xF3F); // 10 |
123 | jmp_imm_short(29); // 2 |
124 | |
125 | cmp_eax_imm32(2); // 5 |
126 | jne_rj(12); // 2 |
127 | mov_m32_imm32((unsigned int*)&rounding_mode, 0xB3F); // 10 |
128 | jmp_imm_short(10); // 2 |
129 | |
130 | mov_m32_imm32((unsigned int*)&rounding_mode, 0x73F); // 10 |
131 | |
132 | fldcw_m16((unsigned short*)&rounding_mode); |
133 | #endif |
134 | } |
135 | |