fc5d46b4 |
1 | /* |
2 | * z64 |
3 | * |
4 | * Copyright (C) 2007 ziggy |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or |
9 | * (at your option) any later version. |
10 | * |
11 | * This program is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
14 | * GNU General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU General Public License along |
17 | * with this program; if not, write to the Free Software Foundation, Inc., |
18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
19 | * |
20 | **/ |
21 | |
22 | /* |
23 | Nintendo/SGI RSP Disassembler |
24 | |
25 | Written by Ville Linde |
26 | */ |
27 | |
28 | //#include "z64.h" |
29 | #include <stdarg.h> |
30 | #include <stdio.h> |
31 | #include "rsp.h" |
32 | |
33 | #define DASMFLAG_SUPPORTED 0x80000000 /* are disassembly flags supported? */ |
34 | #define DASMFLAG_STEP_OUT 0x40000000 /* this instruction should be the end of a step out sequence */ |
35 | #define DASMFLAG_STEP_OVER 0x20000000 /* this instruction should be stepped over by setting a breakpoint afterwards */ |
36 | #define DASMFLAG_OVERINSTMASK 0x18000000 /* number of extra instructions to skip when stepping over */ |
37 | #define DASMFLAG_OVERINSTSHIFT 27 /* bits to shift after masking to get the value */ |
38 | #define DASMFLAG_LENGTHMASK 0x0000ffff /* the low 16-bits contain the actual length */ |
39 | #define DASMFLAG_STEP_OVER_EXTRA(x) ((x) << DASMFLAG_OVERINSTSHIFT) |
40 | |
41 | static const char *reg[32] = |
42 | { |
43 | "0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
44 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
45 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
46 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" |
47 | }; |
48 | |
49 | static const char *vreg[32] = |
50 | { |
51 | " v0", " v1", " v2", " v3", " v4", " v5", " v6", " v7", |
52 | " v8", " v9", "v10", "v11", "v12", "v13", "v14", "v15", |
53 | "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", |
54 | "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" |
55 | }; |
56 | |
57 | static const char *cop0_regs[32] = |
58 | { |
59 | "SP_MEM_ADDR", "SP_DRAM_ADDR", "SP_RD_LEN", "SP_WR_LEN", |
60 | "SP_STATUS", "SP_DMA_FULL", "SP_DMA_BUSY", "SP_SEMAPHORE", |
61 | "DPC_START", "DPC_END", "DPC_CURRENT", "DPC_STATUS", |
62 | "DPC_CLOCK", "DPC_BUFBUSY", "DPC_PIPEBUSY", "DPC_TMEM", |
63 | "???", "???", "???", "???", |
64 | "???", "???", "???", "???", |
65 | "???", "???", "???", "???", |
66 | "???", "???", "???", "???" |
67 | }; |
68 | |
69 | static const char *element[16] = |
70 | { |
71 | "", "[???]", "[00224466]", "[11335577]", "[00004444]", "[11115555]", "[22226666]", "[33337777]", |
72 | "[00000000]", "[11111111]", "[22222222]", "[33333333]", "[44444444]", "[55555555]", "[66666666]", "[77777777]" |
73 | }; |
74 | |
75 | static const char *element2[16] = |
76 | { |
77 | "01234567", "????????", "00224466", "11335577", "00004444", "11115555", "22226666", "33337777", |
78 | "00000000", "11111111", "22222222", "33333333", "44444444", "55555555", "66666666", "77777777" |
79 | }; |
80 | |
81 | #define INLINE inline |
82 | INLINE char *signed_imm16(UINT32 op) |
83 | { |
84 | static char temp[10]; |
85 | INT16 value = op & 0xffff; |
86 | |
87 | if (value < 0) |
88 | { |
89 | sprintf(temp, "-$%04x", -value); |
90 | } |
91 | else |
92 | { |
93 | sprintf(temp, "$%04x", value); |
94 | } |
95 | return temp; |
96 | } |
97 | |
98 | |
99 | static char *output; |
100 | |
101 | static void print(const char *fmt, ...) |
102 | { |
103 | va_list vl; |
104 | |
105 | va_start(vl, fmt); |
106 | output += vsprintf(output, fmt, vl); |
107 | va_end(vl); |
108 | } |
109 | |
110 | static void disasm_cop0(UINT32 op) |
111 | { |
112 | int rt = (op >> 16) & 31; |
113 | int rd = (op >> 11) & 31; |
114 | |
115 | switch ((op >> 21) & 0x1f) |
116 | { |
117 | case 0x00: print("mfc0 %s, %s", reg[rt], cop0_regs[rd]); break; |
118 | case 0x04: print("mtc0 %s, %s", reg[rt], cop0_regs[rd]); break; |
119 | |
120 | default: print("??? (COP0)"); break; |
121 | } |
122 | } |
123 | |
124 | static void disasm_cop2(UINT32 op) |
125 | { |
126 | int rt = (op >> 16) & 31; |
127 | int rd = (op >> 11) & 31; |
128 | int el = (op >> 21) & 0xf; |
129 | int dest = (op >> 6) & 0x1f; |
130 | int s1 = rd; |
131 | int s2 = rt; |
132 | |
133 | switch ((op >> 21) & 0x1f) |
134 | { |
135 | case 0x00: print("mfc2 %s, %s[%d]", reg[rt], vreg[rd], dest); break; |
136 | case 0x02: print("cfc2 %s, FLAG%d", reg[rt], rd); break; |
137 | case 0x04: print("mtc2 %s, %s[%d]", reg[rt], vreg[rd], dest); break; |
138 | case 0x06: print("ctc2 %s, FLAG%d", reg[rt], rd); break; |
139 | |
140 | case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: |
141 | case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: |
142 | { |
143 | switch (op & 0x3f) |
144 | { |
145 | case 0x00: print("vmulf %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
146 | case 0x01: print("vmulu %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
147 | case 0x02: print("vrndp %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
148 | case 0x03: print("vmulq %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
149 | case 0x04: print("vmudl %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
150 | case 0x05: print("vmudm %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
151 | case 0x06: print("vmudn %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
152 | case 0x07: print("vmudh %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
153 | case 0x08: print("vmacf %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
154 | case 0x09: print("vmacu %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
155 | case 0x0a: print("vrndn %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
156 | case 0x0b: print("vmacq %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
157 | case 0x0c: print("vmadl %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
158 | case 0x0d: print("vmadm %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
159 | case 0x0e: print("vmadn %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
160 | case 0x0f: print("vmadh %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
161 | case 0x10: print("vadd %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
162 | case 0x11: print("vsub %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
163 | case 0x12: print("vsut???"); break; |
164 | case 0x13: print("vabs %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
165 | case 0x14: print("vaddc %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
166 | case 0x15: print("vsubc %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
167 | |
168 | case 0x1d: |
169 | { |
170 | switch (el) |
171 | { |
172 | case 8: print("vsaw %s, ACCUM_H", vreg[dest]); break; |
173 | case 9: print("vsaw %s, ACCUM_M", vreg[dest]); break; |
174 | case 10: print("vsaw %s, ACCUM_L", vreg[dest]); break; |
175 | default: print("vsaw %s, ???", vreg[dest]); break; |
176 | } |
177 | break; |
178 | } |
179 | |
180 | case 0x20: print("vlt %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
181 | case 0x21: print("veq %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
182 | case 0x22: print("vne %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
183 | case 0x23: print("vge %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
184 | case 0x24: print("vcl %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
185 | case 0x25: print("vch %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
186 | case 0x26: print("vcr %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
187 | case 0x27: print("vmrg %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
188 | case 0x28: print("vand %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
189 | case 0x29: print("vnand %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
190 | case 0x2a: print("vor %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
191 | case 0x2b: print("vnor %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
192 | case 0x2c: print("vxor %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
193 | case 0x2d: print("vnxor %s, %s, %s%s", vreg[dest], vreg[s1], vreg[s2], element[el]); break; |
194 | case 0x30: print("vrcp %s[%d], %s[%c]", vreg[dest], s1 & 7, vreg[s2], element2[el][7-(s1 & 7)]); break; |
195 | case 0x31: print("vrcpl %s[%d], %s[%c]", vreg[dest], s1 & 7, vreg[s2], element2[el][7-(s1 & 7)]); break; |
196 | case 0x32: print("vrcph %s[%d], %s[%c]", vreg[dest], s1 & 7, vreg[s2], element2[el][7-(s1 & 7)]); break; |
197 | case 0x33: print("vmov %s[%d], %s[%c]", vreg[dest], s1 & 7, vreg[s2], element2[el][7-(s1 & 7)]); break; |
198 | case 0x34: print("vrsq %s[%d], %s[%c]", vreg[dest], s1 & 7, vreg[s2], element2[el][7-(s1 & 7)]); break; |
199 | case 0x35: print("vrsql %s[%d], %s[%c]", vreg[dest], s1 & 7, vreg[s2], element2[el][7-(s1 & 7)]); break; |
200 | case 0x36: print("vrsqh %s[%d], %s[%c]", vreg[dest], s1 & 7, vreg[s2], element2[el][7-(s1 & 7)]); break; |
201 | case 0x37: print("vnop"); break; |
202 | default: print("??? (VECTOR OP)"); break; |
203 | } |
204 | break; |
205 | } |
206 | |
207 | default: print("??? (COP2)"); break; |
208 | } |
209 | } |
210 | |
211 | static void disasm_lwc2(UINT32 op) |
212 | { |
213 | int dest = (op >> 16) & 0x1f; |
214 | int base = (op >> 21) & 0x1f; |
215 | int del = (op >> 7) & 0xf; |
216 | int offset = (op & 0x7f); |
217 | if (offset & 0x40) |
218 | offset |= 0xffffff80; |
219 | |
220 | switch ((op >> 11) & 0x1f) |
221 | { |
222 | case 0x00: print("lbv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 1), reg[base]); break; |
223 | case 0x01: print("lsv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 2), reg[base]); break; |
224 | case 0x02: print("llv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 4), reg[base]); break; |
225 | case 0x03: print("ldv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 8), reg[base]); break; |
226 | case 0x04: print("lqv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 16), reg[base]); break; |
227 | case 0x05: print("lrv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 16), reg[base]); break; |
228 | case 0x06: print("lpv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 8), reg[base]); break; |
229 | case 0x07: print("luv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 8), reg[base]); break; |
230 | case 0x08: print("lhv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 16), reg[base]); break; |
231 | case 0x09: print("lfv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 16), reg[base]); break; |
232 | case 0x0a: print("lwv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 16), reg[base]); break; |
233 | case 0x0b: print("ltv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 16), reg[base]); break; |
234 | default: print("??? (LWC2)"); break; |
235 | } |
236 | } |
237 | |
238 | static void disasm_swc2(UINT32 op) |
239 | { |
240 | int dest = (op >> 16) & 0x1f; |
241 | int base = (op >> 21) & 0x1f; |
242 | int del = (op >> 7) & 0xf; |
243 | int offset = (op & 0x7f); |
244 | if (offset & 0x40) |
245 | offset |= 0xffffff80; |
246 | |
247 | switch ((op >> 11) & 0x1f) |
248 | { |
249 | case 0x00: print("sbv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 1), reg[base]); break; |
250 | case 0x01: print("ssv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 2), reg[base]); break; |
251 | case 0x02: print("slv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 4), reg[base]); break; |
252 | case 0x03: print("sdv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 8), reg[base]); break; |
253 | case 0x04: print("sqv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 16), reg[base]); break; |
254 | case 0x05: print("srv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 16), reg[base]); break; |
255 | case 0x06: print("spv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 8), reg[base]); break; |
256 | case 0x07: print("suv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 8), reg[base]); break; |
257 | case 0x08: print("shv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 16), reg[base]); break; |
258 | case 0x09: print("sfv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 16), reg[base]); break; |
259 | case 0x0a: print("swv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 16), reg[base]); break; |
260 | case 0x0b: print("stv %s[%d], %s(%s)", vreg[dest], del, signed_imm16(offset * 16), reg[base]); break; |
261 | default: print("??? (SWC2)"); break; |
262 | } |
263 | } |
264 | |
265 | offs_t rsp_dasm_one(char *buffer, offs_t pc, UINT32 op) |
266 | { |
267 | int rs = (op >> 21) & 31; |
268 | int rt = (op >> 16) & 31; |
269 | int rd = (op >> 11) & 31; |
270 | int shift = (op >> 6) & 31; |
271 | UINT32 flags = 0; |
272 | |
273 | output = buffer; |
274 | |
275 | switch (op >> 26) |
276 | { |
277 | case 0x00: // SPECIAL |
278 | { |
279 | switch (op & 0x3f) |
280 | { |
281 | case 0x00: |
282 | { |
283 | if (op == 0) |
284 | { |
285 | print("nop"); |
286 | } |
287 | else |
288 | { |
289 | print("sll %s, %s, %d", reg[rd], reg[rt], shift); |
290 | } |
291 | break; |
292 | } |
293 | case 0x02: print("srl %s, %s, %d", reg[rd], reg[rt], shift); break; |
294 | case 0x03: print("sra %s, %s, %d", reg[rd], reg[rt], shift); break; |
295 | case 0x04: print("sllv %s, %s, %s", reg[rd], reg[rt], reg[rs]); break; |
296 | case 0x06: print("srlv %s, %s, %s", reg[rd], reg[rt], reg[rs]); break; |
297 | case 0x07: print("srav %s, %s, %s", reg[rd], reg[rt], reg[rs]); break; |
298 | case 0x08: print("jr %s", reg[rs]); if (rs == 31) flags = DASMFLAG_STEP_OUT; break; |
299 | case 0x09: |
300 | { |
301 | if (rd == 31) |
302 | { |
303 | print("jalr %s", reg[rs]); |
304 | } |
305 | else |
306 | { |
307 | print("jalr %s, %s", reg[rs], reg[rd]); |
308 | } |
309 | flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA(1); |
310 | break; |
311 | } |
312 | case 0x0d: print("break"); flags = DASMFLAG_STEP_OVER; break; |
313 | case 0x20: print("add %s, %s, %s", reg[rd], reg[rs], reg[rt]); break; |
314 | case 0x21: print("addu %s, %s, %s", reg[rd], reg[rs], reg[rt]); break; |
315 | case 0x22: print("sub %s, %s, %s", reg[rd], reg[rs], reg[rt]); break; |
316 | case 0x23: print("subu %s, %s, %s", reg[rd], reg[rs], reg[rt]); break; |
317 | case 0x24: print("and %s, %s, %s", reg[rd], reg[rs], reg[rt]); break; |
318 | case 0x25: print("or %s, %s, %s", reg[rd], reg[rs], reg[rt]); break; |
319 | case 0x26: print("xor %s, %s, %s", reg[rd], reg[rs], reg[rt]); break; |
320 | case 0x27: print("nor %s, %s, %s", reg[rd], reg[rs], reg[rt]); break; |
321 | case 0x2a: print("slt %s, %s, %s", reg[rd], reg[rs], reg[rt]); break; |
322 | case 0x2b: print("sltu %s, %s, %s", reg[rd], reg[rs], reg[rt]); break; |
323 | |
324 | default: print("???"); break; |
325 | } |
326 | break; |
327 | } |
328 | |
329 | case 0x01: // REGIMM |
330 | { |
331 | switch ((op >> 16) & 0x1f) |
332 | { |
333 | case 0x00: print("bltz %s, $%08X", reg[rs], pc + 4 + ((INT16)op << 2)); break; |
334 | case 0x01: print("bgez %s, $%08X", reg[rs], pc + 4 + ((INT16)op << 2)); break; |
335 | case 0x10: print("bltzal %s, $%08X", reg[rs], pc + 4 + ((INT16)op << 2)); break; |
336 | case 0x11: print("bgezal %s, $%08X", reg[rs], pc + 4 + ((INT16)op << 2)); break; |
337 | |
338 | default: print("???"); break; |
339 | } |
340 | break; |
341 | } |
342 | |
343 | case 0x02: print("j $%08X", (op & 0x03ffffff) << 2); break; |
344 | case 0x03: print("jal $%08X", (op & 0x03ffffff) << 2); break; |
345 | case 0x04: print("beq %s, %s, $%08X", reg[rs], reg[rt], pc + 4 + ((INT16)(op) << 2)); break; |
346 | case 0x05: print("bne %s, %s, $%08X", reg[rs], reg[rt], pc + 4 + ((INT16)(op) << 2)); break; |
347 | case 0x06: print("blez %s, $%08X", reg[rs], pc + 4 + ((INT16)(op) << 2)); break; |
348 | case 0x07: print("bgtz %s, $%08X", reg[rs], pc + 4 + ((INT16)(op) << 2)); break; |
349 | case 0x08: print("addi %s, %s, %s", reg[rt], reg[rs], signed_imm16(op)); break; |
350 | case 0x09: print("addiu %s, %s, %s", reg[rt], reg[rs], signed_imm16(op)); break; |
351 | case 0x0a: print("slti %s, %s, %s", reg[rt], reg[rs], signed_imm16(op)); break; |
352 | case 0x0b: print("sltiu %s, %s, %s", reg[rt], reg[rs], signed_imm16(op)); break; |
353 | case 0x0c: print("andi %s, %s, $%04X", reg[rt], reg[rs], (UINT16)(op)); break; |
354 | case 0x0d: print("ori %s, %s, $%04X", reg[rt], reg[rs], (UINT16)(op)); break; |
355 | case 0x0e: print("xori %s, %s, $%04X", reg[rt], reg[rs], (UINT16)(op)); break; |
356 | case 0x0f: print("lui %s, %s, $%04X", reg[rt], reg[rs], (UINT16)(op)); break; |
357 | |
358 | case 0x10: disasm_cop0(op); break; |
359 | case 0x12: disasm_cop2(op); break; |
360 | |
361 | case 0x20: print("lb %s, %s(%s)", reg[rt], signed_imm16(op), reg[rs]); break; |
362 | case 0x21: print("lh %s, %s(%s)", reg[rt], signed_imm16(op), reg[rs]); break; |
363 | case 0x23: print("lw %s, %s(%s)", reg[rt], signed_imm16(op), reg[rs]); break; |
364 | case 0x24: print("lbu %s, %s(%s)", reg[rt], signed_imm16(op), reg[rs]); break; |
365 | case 0x25: print("lhu %s, %s(%s)", reg[rt], signed_imm16(op), reg[rs]); break; |
366 | case 0x28: print("sb %s, %s(%s)", reg[rt], signed_imm16(op), reg[rs]); break; |
367 | case 0x29: print("sh %s, %s(%s)", reg[rt], signed_imm16(op), reg[rs]); break; |
368 | case 0x2b: print("sw %s, %s(%s)", reg[rt], signed_imm16(op), reg[rs]); break; |
369 | |
370 | case 0x32: disasm_lwc2(op); break; |
371 | case 0x3a: disasm_swc2(op); break; |
372 | |
373 | default: print("???"); break; |
374 | } |
375 | |
376 | return 4 | flags | DASMFLAG_SUPPORTED; |
377 | } |