| 1 | Delta modulation channel tutorial 1.0 |
| 2 | Written by Brad Taylor |
| 3 | |
| 4 | Last updated: August 20th, 2000. |
| 5 | |
| 6 | All results were obtained by studying prior information available (from |
| 7 | nestech 1.00, and postings on NESDev from miscellanious people), and through |
| 8 | a series of experiments conducted by me. Results aquired by individuals |
| 9 | prior to my reverse-engineering have been double checked, and final results |
| 10 | have been confirmed. Credit is due to those individual(s) who contributed |
| 11 | any information in regards to the DMC. |
| 12 | |
| 13 | Description |
| 14 | ----------- |
| 15 | |
| 16 | The delta modulation channel (DMC) is a complex digital network of counters |
| 17 | and registers used to produce analog sound. It's primary function is to play |
| 18 | "samples" from memory, and have an internal counter connected to a digital |
| 19 | to analog converter (DAC) updated accordingly. The channel is able to be |
| 20 | assigned a pointer to a chunk of memory to be played. At timed intervals, |
| 21 | the DMC will halt the 2A03 (NES's CPU) for 1 clock cycle to retrieve the |
| 22 | sample to pe played. This method of playback will be refered to here on as |
| 23 | direct memory access (DMA). Another method of playback known as pulse code |
| 24 | modulation (PCM) is available by the channel, which requires the constant |
| 25 | updating of one of the DMC's memory-mapped registers. |
| 26 | |
| 27 | Registers |
| 28 | --------- |
| 29 | |
| 30 | The DMC has 5 registers assigned to it. They are as follows: |
| 31 | |
| 32 | $4010: play mode and DMA frequency |
| 33 | $4011: delta counter |
| 34 | $4012: play code's starting address |
| 35 | $4013: length of play code |
| 36 | $4015: DMC/IRQ status |
| 37 | |
| 38 | Note that $4015 is the only R/W register. All others are write only (attempt |
| 39 | to read them will most likely result in a returned 040H, due to heavy |
| 40 | capacitance on the NES's data bus). |
| 41 | |
| 42 | $4010 - Play mode and DMA frequency |
| 43 | ----------------------------------- |
| 44 | This register is used to control the frequency of the DMA fetches, and to |
| 45 | control the playback mode. |
| 46 | |
| 47 | Bits |
| 48 | ---- |
| 49 | 6-7 this is the playback mode. |
| 50 | |
| 51 | 00 - play DMC sample until length counter reaches 0 (see $4013) |
| 52 | x1 - loop the DMC sample (x = immaterial) |
| 53 | 10 - play DMC sample until length counter reaches 0, then generate a CPU |
| 54 | IRQ |
| 55 | |
| 56 | Looping (playback mode "x1") will have the chunk of memory played over and |
| 57 | over, until the channel is disabled (via $4015). In this case, after the |
| 58 | length counter reaches 0, it will be reloaded with the calculated length |
| 59 | value of $4013. |
| 60 | |
| 61 | If playback mode "10" is chosen, an interrupt will be dispached when the |
| 62 | length counter reaches 0 (after the sample is done playing). There are 2 |
| 63 | ways to acknowledge the DMC's interrupt request upon recieving it. The first |
| 64 | is a write to this register ($4010), with the MSB (bit 7) cleared (0). The |
| 65 | second is any write to $4015 (see the $4015 register description for more |
| 66 | details). |
| 67 | |
| 68 | If playback mode "00" is chosen, the sample plays until the length counter |
| 69 | reaches 0. No interrupt is generated. |
| 70 | |
| 71 | 5-4 appear to be unused |
| 72 | |
| 73 | 3-0 this is the DMC frequency control. Valid values are from 0 - F. The |
| 74 | value of this register determines how many CPU clocks to wait before the DMA |
| 75 | will fetch another byte from memory. The # of clocks to wait -1 is initially |
| 76 | loaded into an internal 12-bit down counter. The down counter is then |
| 77 | decremented at the frequency of the CPU (1.79MHz). The channel fetches the |
| 78 | next DMC sample byte when the count reaches 0, and then reloads the count. |
| 79 | This process repeats until the channel is disabled by $4015, or when the |
| 80 | length counter has reached 0 (if not in the looping playback mode). The |
| 81 | exact number of CPU clock cycles is as follows: |
| 82 | |
| 83 | value CPU |
| 84 | written clocks octave scale |
| 85 | ------- ------ ------ ----- |
| 86 | F 1B0 8 C |
| 87 | E 240 7 G |
| 88 | D 2A0 7 E |
| 89 | C 350 7 C |
| 90 | B 400 6 A |
| 91 | A 470 6 G |
| 92 | 9 500 6 F |
| 93 | 8 5F0 6 D |
| 94 | 7 6B0 6 C |
| 95 | 6 710 5 B |
| 96 | 5 7F0 5 A |
| 97 | 4 8F0 5 G |
| 98 | 3 A00 5 F |
| 99 | 2 AA0 5 E |
| 100 | 1 BE0 5 D |
| 101 | 0 D60 5 C |
| 102 | |
| 103 | The octave and scale values shown represent the DMC DMA clock cycle rate |
| 104 | equivelant. These values are merely shown for the music enthusiast |
| 105 | programmer, who is more familiar with notes than clock cycles. |
| 106 | |
| 107 | Every fetched byte is loaded into a internal 8-bit shift register. The shift |
| 108 | register is then clocked at 8x the DMA frequency (which means that the CPU |
| 109 | clock count would be 1/8th that of the DMA clock count), or shifted at +3 |
| 110 | the octave of the DMA (same scale). The data shifted out of the register is |
| 111 | in serial form, and the least significant bit (LSB, or bit 0) of the fetched |
| 112 | byte is the first one to be shifted out (then bit 1, bit 2, etc.). |
| 113 | |
| 114 | The bits shifted out are then fed to the UP/DOWN control pin of the internal |
| 115 | delta counter, which will effectively have the counter increment it's |
| 116 | retained value by one on "1" bit samples, and decrement it's value by one on |
| 117 | "0" bit samples. This counter is clocked at the same frequency of the shift |
| 118 | register's. |
| 119 | |
| 120 | The counter is only 6 bits in size, and has it's 6 outputs tied to the 6 MSB |
| 121 | inputs of a 7 bit DAC. The analog output of the DAC is then what you hear |
| 122 | being played by the DMC. |
| 123 | |
| 124 | Wrap around counting is not allowed on this counter. Instead, a "clipping" |
| 125 | behaviour is exhibited. If the internal value of the counter has reached 0, |
| 126 | and the next bit sample is a 0 (instructing a decrement), the counter will |
| 127 | take no action. Likewise, if the counter's value is currently at -1 |
| 128 | (111111B, or 03FH), and the bit sample to be played is a 1, the counter will |
| 129 | not increment. |
| 130 | |
| 131 | |
| 132 | $4011 - Delta counter load register |
| 133 | ----------------------------------- |
| 134 | |
| 135 | bits |
| 136 | ---- |
| 137 | 7 appears to be unused |
| 138 | 1-6 the load inputs of the internal delta counter |
| 139 | 0 LSB of the DAC |
| 140 | |
| 141 | A write to this register effectively loads the internal delta counter with a |
| 142 | 6 bit value, but can be used for 7 bit PCM playback. Bit 0 is connected |
| 143 | directly to the LSB (bit 0) of the DAC, and has no effect on the internal |
| 144 | delta counter. Bit 7 appears to be unused. |
| 145 | |
| 146 | This register can be used to output direct 7-bit digital PCM data to the |
| 147 | DMC's audio output. To use this register for PCM playback, the programmer |
| 148 | would be responsible for making sure that this register is updated at a |
| 149 | constant rate. The rate is completely user-definable. For the regular CD |
| 150 | quality 44100 Hz playback sample rate, this register would have to be |
| 151 | written to approximately every 40 CPU cycles (assuming the 2A03 is running @ |
| 152 | 1.79 MHz). |
| 153 | |
| 154 | |
| 155 | $4012 - DMA address load register |
| 156 | ---------------------------- |
| 157 | |
| 158 | This register contains the initial address where the DMC is to fetch samples |
| 159 | from memory for playback. The effective address value is $4012 shl 6 or |
| 160 | 0C000H. This register is connected to the load pins of the internal DMA |
| 161 | address pointer register (counter). The counter is incremented after every |
| 162 | DMA byte fetch. The counter is 15 bits in size, and has addresses wrap |
| 163 | around from $FFFF to $8000 (not $C000, as you might have guessed). The DMA |
| 164 | address pointer register is reloaded with the initial calculated address, |
| 165 | when the DMC is activated from an inactive state, or when the length counter |
| 166 | has arrived at terminal count (count=0), if in the looping playback mode. |
| 167 | |
| 168 | |
| 169 | $4013 - DMA length register |
| 170 | --------------------------- |
| 171 | |
| 172 | This register contains the length of the chunk of memory to be played by the |
| 173 | DMC, and it's size is measured in bytes. The value of $4013 shl 4 is loaded |
| 174 | into a 12 bit internal down counter, dubbed the length counter. The length |
| 175 | counter is decremented after every DMA fetch, and when it arrives at 0, the |
| 176 | DMC will take action(s) based on the 2 MSB of $4010. This counter will be |
| 177 | loaded with the current calculated address value of $4013 when the DMC is |
| 178 | activated from an inactive state. Because the value that is loaded by the |
| 179 | length counter is $4013 shl 4, this effectively produces a calculated byte |
| 180 | sample length of $4013 shl 4 + 1 (i.e. if $4013=0, sample length is 1 byte |
| 181 | long; if $4013=FF, sample length is $FF1 bytes long). |
| 182 | |
| 183 | |
| 184 | $4015 - DMC status |
| 185 | ------------------ |
| 186 | |
| 187 | This contains the current status of the DMC channel. There are 2 read bits, |
| 188 | and 1 write bit. |
| 189 | |
| 190 | bits |
| 191 | ---- |
| 192 | 7(R) DMC's IRQ status (1=CPU IRQ being caused by DMC) |
| 193 | 4(R) DMC is currently enabled (playing a stream of samples) |
| 194 | 4(W) enable/disable DMC (1=start/continue playing a sample;0=stop playing) |
| 195 | |
| 196 | When an IRQ goes off inside the 2A03, Bit 7 of $4015 can tell the interrupt |
| 197 | handler if it was caused by the DMC hardware or not. This bit will be set |
| 198 | (1) if the DMC is responsible for the IRQ. Of course, if your program has no |
| 199 | other IRQ-generating hardware going while it's using the DMC, then reading |
| 200 | this register is not neccessary upon IRQ generation. Note that reading this |
| 201 | register will NOT clear bit 7 (meaning that the DMC's IRQ will still NOT be |
| 202 | acknowledged). Also note that if the 2 MSB of $4010 were set to 10, no IRQ |
| 203 | will be generated, and bit 7 will always be 0. |
| 204 | |
| 205 | Upon generation of a IRQ, to let the DMC know that the software has |
| 206 | acknowledged the /IRQ (and to reset the DMC's internal IRQ flag), any write |
| 207 | out to $4015 will reset the flag, or a write out to $4010 with the MSB set |
| 208 | to 0 will do. These practices should be performed inside the IRQ handler |
| 209 | routine. To replay the same sample that just finished, all you need to do is |
| 210 | just write a 1 out to bit 4 of $4015. |
| 211 | |
| 212 | Bit 4 of $4015 reports the real-time status of the DMC. A returned value of |
| 213 | 1 denotes that the channel is currently playing a stream of samples. A |
| 214 | returned value of 0 indicates that the channel is inactive. If the |
| 215 | programmer needed to know when a stream of samples was finished playing, but |
| 216 | didn't want to use the IRQ generation feature of the DMC, then polling this |
| 217 | bit would be a valid option. |
| 218 | |
| 219 | Writing a value to $4015's 4th bit has the effect of enabling the channel |
| 220 | (start, or continue playing a stream of samples), or disabling the channel |
| 221 | (stop all DMC activity). Note that writing a 1 to this bit while the channel |
| 222 | is currently enabled, will have no effect on counters or registers internal |
| 223 | to the DMC. |
| 224 | |
| 225 | The conditions that control the time the DMC will stay enabled are |
| 226 | determined by the 2 MSB of $4010, and register $4013 (if applicable). |
| 227 | |
| 228 | |
| 229 | System Reset |
| 230 | ------------ |
| 231 | |
| 232 | On system reset, all 7 used bits of $4011 are reset to 0, the IRQ flag is |
| 233 | cleared (disabled), and the channel is disabled. All other registers will |
| 234 | remain unmodified. |
| 235 | |